Multilayer ceramic capacitors

Abstract

To provide a multilayer ceramic capacitor having enhanced reliability in which strength at a side margin can be enhanced, even if the dimension of the side margin is small in the width direction.SOLUTION: A multilayer ceramic capacitor 10 is constituted of a laminate 12, and first and second external electrodes 40, 42 formed on the opposite end faces of the laminate 12, respectively. Assuming the regions of the cross section of the laminate 12 viewed from the lamination direction, where first internal electrode 22 and second internal electrode 24 do not exist, are side margins 32, 34, the side margins 32, 34 have a plurality of side margin layers, and the content of Si of the side margin layers other than that on the internal electrode side is higher than the content of the side margin layer on the innermost electrode side.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a multilayer ceramic capacitor. [Background technology]

[0002] In recent years, there has been a demand for large-capacity, compact multilayer ceramic capacitors. Such multilayer ceramic capacitors have, for example, a rectangular parallelepiped laminate formed by alternately laminating inner dielectric layers on which the internal electrodes are printed and the internal electrodes, and then laminating outer ceramic layers on the top and bottom surfaces of the laminate. External electrodes are formed on both end surfaces of the laminate. Some such multilayer ceramic capacitors have dielectric layers called side margins formed on the side surfaces of the laminate to prevent the internal electrodes from connecting to the external electrodes on the side surfaces of the laminate.

[0003] Patent Document 1 discloses a method for manufacturing a multilayer ceramic capacitor having the above-mentioned side margin portion. In the method for manufacturing a multilayer ceramic capacitor described in Patent Document 1, ceramic green sheets having conductive films formed on their surfaces to become internal electrodes are first stacked. Next, a mother laminate is formed, and the mother laminate is cut so that the conductive films are exposed on the sides where no external electrodes are formed. This results in a laminate chip. Then, ceramic slurry that becomes the side margin portion is applied to the internal electrodes exposed on both sides of the cut laminate chip. This allows the internal electrodes to be formed across the entire width of the laminate chip, thereby improving the efficiency of capacitance acquisition and reducing capacitance variation. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 61-248413 Summary of the Invention [Problem to be solved by the invention]

[0005] However, in the multilayer ceramic capacitor of Patent Document 1, for example, if the thickness of the side margins, i.e., the dimension along the width direction of the laminate, is reduced in order to obtain a larger capacitance with a smaller size of the multilayer ceramic capacitor, the side margins do not have sufficient strength. As a result, the multilayer ceramic capacitor of Patent Document 1 has the problem of not being able to obtain sufficient flexural strength. Furthermore, cracks and chips are likely to occur in the side margins, allowing moisture to penetrate through the cracks and chips. This causes the problem of a decrease in the insulation properties of the multilayer ceramic capacitor of Patent Document 1.

[0006] A primary object of the present invention is to provide a multilayer ceramic capacitor having improved reliability by improving the strength of the side margins even when the width of the side margins is small. [Means for solving the problem]

[0007] The multilayer ceramic capacitor according to the present invention is a multilayer ceramic capacitor comprising a laminate including dielectric layers and internal electrodes stacked in a stacking direction, and external electrodes connected to the internal electrodes, wherein the laminate is formed in a shape including a first main surface and a second main surface opposing each other in the stacking direction, a first side surface and a second side surface opposing each other in a width direction intersecting the stacking direction, and a first end face and a second end face opposing each other in a length direction intersecting the stacking direction and the width direction, and the laminate is formed in a shape including an inner layer portion formed by stacking the dielectric layers and the internal electrodes in the stacking direction, and external electrodes sandwiching the inner layer portion from the stacking direction. and side ceramic layers arranged so as to sandwich the inner layer portion and the outer layer portion in the width direction, the inner electrodes include a first inner electrode exposed at the first end face and a second inner electrode exposed at the second end face, the outer electrodes include a first outer electrode provided on the first end face and connected to the first inner electrode, and a second outer electrode provided on the second end face and connected to the second inner electrode, the side ceramic layers include an inner layer located on the inner layer portion side and outer layers located on the first side face side and the second side face side, and the Si content of the outer layer is higher than the Si content of the inner layer. Ku , The number of moles of Si / the number of moles of Ti in the outer layer is 3.0 or more and 7.0 or less, and the number of moles of Si / the number of moles of Ti in the inner layer is 1.0 or more and 4.0 or less, It is a multilayer ceramic capacitor. In addition, in the multilayer ceramic capacitor according to the present invention, it is preferable that the exposed surfaces of the first internal electrode and the second internal electrode on the first side surface and the second side surface of the laminate contain more Si than the central portions of the first internal electrode and the second internal electrode. Furthermore, in the multilayer ceramic capacitor according to the present invention, the ratio of the number of moles of Si / the number of moles of Ti in the side ceramic layers is preferably 1.0 or more and 7.0 or less. Furthermore, the dimension along the width direction of the side ceramic layer is preferably 5 μm or more and 40 μm or less. The multilayer ceramic capacitor according to the present invention is a multilayer ceramic capacitor comprising a laminate including dielectric layers and internal electrodes stacked in a stacking direction, and external electrodes connected to the internal electrodes, wherein the laminate is formed in a shape including a first main surface and a second main surface opposing each other in the stacking direction, a first side surface and a second side surface opposing each other in a width direction intersecting the stacking direction, and a first end face and a second end face opposing each other in a length direction intersecting the stacking direction and the width direction, and the laminate is formed in a shape including an inner layer portion formed by stacking the dielectric layers and the internal electrodes in the stacking direction, and external electrodes sandwiching the inner layer portion from the stacking direction. and side ceramic layers including voids arranged so as to sandwich the inner layer portion and the outer layer portion in the width direction, the inner electrodes include a first inner electrode exposed at the first end face and a second inner electrode exposed at the second end face, the outer electrodes include a first outer electrode formed on the first end face and connected to the first inner electrode, and a second outer electrode formed on the second end face and connected to the second inner electrode, the side ceramic layers have an inner layer located on the inner layer portion side and outer layers located on the first side face side and the second side face side, and the voids in the outer layer are larger than the voids in the inner layer. Few It is a multilayer ceramic capacitor.

[0008] The multilayer ceramic capacitor according to the present invention includes an inner layer portion formed by stacking dielectric layers and internal electrodes in the stacking direction, outer layer portions arranged to sandwich the inner layer portion in the stacking direction, and side ceramic layers arranged to sandwich the inner layer portion and the outer layer portion in the width direction. The internal electrodes include a first internal electrode exposed at a first end face and a second internal electrode exposed at a second end face. The external electrodes include a first external electrode provided on the first end face and connected to the first internal electrode, and a second external electrode provided on the second end face and connected to the second internal electrode. The side ceramic layers include an inner layer located on the inner layer portion side and outer layers located on the first side face and the second side face. The Si content of the outer layer is higher than that of the inner layer, thereby improving the strength of the side margin portion and improving the flexural strength of the multilayer ceramic capacitor. Furthermore, cracks and chips are less likely to occur in the side margin portion and moisture intrusion is prevented, thereby ensuring the insulation of the multilayer ceramic capacitor. As a result, a multilayer ceramic capacitor with improved reliability can be provided. [Effects of the Invention]

[0009] According to the present invention, even if the width dimension of the side margin portion is small, the strength of the side margin portion can be improved, and a multilayer ceramic capacitor with improved reliability can be provided.

[0010] The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description of the preferred embodiments of the present invention, which proceeds with reference to the accompanying drawings. [Brief explanation of the drawings]

[0011] [Figure 1] 1 is an external perspective view of a multilayer ceramic capacitor according to an embodiment; [Figure 2] 2 is a cross-sectional view taken along line AA in FIG. 1 showing the multilayer ceramic capacitor according to the embodiment. [Figure 3] 2 is a cross-sectional view taken along line BB in FIG. 1 showing the multilayer ceramic capacitor according to the embodiment. [Figure 4]4 is an enlarged view of a portion C in FIG. 3 showing the multilayer ceramic capacitor according to the embodiment. [Figure 5] 10 is a diagram showing an image of a Si segregation portion of a side margin portion of the multilayer ceramic capacitor according to the embodiment, taken by WDX. [Figure 6] 1 is a diagram showing an image of a Mg segregation portion near the surface of a side margin portion of a multilayer ceramic capacitor according to an embodiment, taken by WDS. [Figure 7] 1 is a diagram showing an image of a Ni segregation portion near the surface of a side margin portion of a multilayer ceramic capacitor according to an embodiment, taken by WDS. [Figure 8] 1 is a diagram showing an image of a Si segregation portion near the surface of a side margin portion of a multilayer ceramic capacitor according to an embodiment, taken by WDS. [Figure 9] 1A and 1B are diagrams for explaining a method for manufacturing a multilayer ceramic capacitor according to the present invention, in which FIG. 1A is a schematic diagram showing ceramic green sheets on which conductive films have been formed, and FIG. 1B is a schematic diagram showing how the ceramic green sheets on which conductive films have been formed are stacked. [Figure 10] 1 is a perspective view showing an example of the appearance of a laminate chip obtained by a method for manufacturing a multilayer ceramic capacitor according to the present invention. [Figure 11] FIG. 10 is a diagram showing the relationship between the pore area ratio near the surface of the side margin portion and the Vickers hardness of the surface of the side margin portion. DETAILED DESCRIPTION OF THE INVENTION

[0012] 1. Multilayer ceramic capacitors An embodiment of the multilayer ceramic capacitor according to the present invention will be described with reference to Figs. 1 to 4. Fig. 1 is an external perspective view showing the multilayer ceramic capacitor according to the embodiment. Fig. 2 is a cross-sectional view taken along line AA in Fig. 1 showing the multilayer ceramic capacitor according to the embodiment. Fig. 3 is a cross-sectional view taken along line BB in Fig. 1 showing the multilayer ceramic capacitor according to the embodiment. Fig. 4 is an enlarged view of part C in Fig. 3 showing the multilayer ceramic capacitor according to the embodiment.

[0013] As shown in FIG. 1, the multilayer ceramic capacitor 10 of this embodiment is generally composed of a laminate 12 and first and second external electrodes 40, 42 formed on both end surfaces of the laminate 12, respectively.

[0014] When the size of the multilayer ceramic capacitor 10 according to the present invention is described as "length (L) direction dimension × width (W) direction dimension × lamination (T) direction dimension," it is generally expected to be, for example, "1.6 mm × 0.8 mm × 0.8 mm," "1.0 mm × 0.5 mm × 0.5 mm," "0.6 mm × 0.3 mm × 0.3 mm," "0.4 mm × 0.2 mm × 0.2 mm," or "0.2 mm × 0.1 mm × 0.1 mm."

[0015] As shown in FIG. 1 , the laminate 12 is formed in a substantially rectangular parallelepiped shape. The laminate 12 has a first end face 13 and a second end face 14 extending along the width (W) direction and the stacking (T) direction, a first side face 15 and a second side face 16 extending along the length (L) direction and the stacking (T) direction, and a first main face 17 and a second main face 18 extending along the length (L) direction and the width (W) direction. The first end face 13 and the second end face 14 face each other, the first side face 15 and the second side face 16 face each other, and the first main face 17 and the second main face 18 face each other. The first side face 15 and the second side face 16 are perpendicular to the first end face 13 and the second end face 14, and the first main face 17 and the second main face 18 are perpendicular to the first end face 13 and the first side face 15. If the laminate 12 has a substantially rectangular parallelepiped shape, it is preferable that the corners and edges are rounded.

[0016] As shown in FIG. 2 , the laminate 12 has a first internal electrode 22 disposed at the interface between the inner layer ceramic layers 20, and a second internal electrode 24 disposed opposite the first internal electrode 22, sandwiching the inner layer ceramic layer 20. A plurality of such combinations of inner layer ceramic layers 20, first internal electrodes 22, and second internal electrodes 24 are stacked to form an inner layer portion 26. Outer layer portions 28 and 30 are provided to sandwich the inner layer portion 26 in the stacking (T) direction. The outer layer portion 28 has a plurality of outer layer ceramic layers 46, and the outer layer portion 30 has a plurality of outer layer ceramic layers 48. Side margin portions 32 and 34 are provided to sandwich the inner layer portion 26 and the outer layer portions 28 and 30 in the width (W) direction. These side margin portions 32 and 34 are formed by a plurality of side margin ceramic layers. In other words, the inner layer portion 26 is a region sandwiched along the stacking (T) direction between the first inner electrode 22b closest to the first main surface 17 and the second inner electrode 24b closest to the second main surface 18. The side margin portions 32, 34 are regions where the first inner electrode 22 and the second inner electrode 24 are not present in a cross section of the laminate 12 viewed from the stacking (T) direction.

[0017] Each of the multiple inner ceramic layers 20 is formed so as to be sandwiched between a first internal electrode 22 and a second internal electrode 24. The inner ceramic layers 20 are composed of dielectric ceramic particles having a perovskite structure, with a perovskite-type compound containing, for example, Ba and Ti as the main component. At least one of Si, Mg, and Ba may also be added as an additive to these main components. The additive is present between the ceramic particles. The thickness of the inner ceramic layers 20 after firing is 0.2 μm or more and 10 μm or less.

[0018] In the laminate 12, the outer layer ceramic layers 46, 48 constituting the upper and lower outer layer portions 28, 30 are formed of the same dielectric ceramic material as the inner layer ceramic layers 20. The outer layer ceramic layers 46, 48 may be formed of a material different from that of the inner layer ceramic layers 20. When the outer layer ceramic layers 46, 48 each have a multi-layer structure, it is preferable that the Si segregation portion of the outer layer ceramic layers 46, 48 closest to the first and second internal electrodes 22b, 24b be greater than the Si segregation portion of the other outer layer ceramic layers 46, 48. This improves the flexural strength of the multilayer ceramic capacitor 10 from the stacking (T) direction. The thickness of the outer layer portions 28, 30 after firing is 15 μm or more and 40 μm or less. Each of the outer layer ceramic layers 46, 48 may have a single-layer structure rather than a multiple-layer structure.

[0019] The first internal electrode 22 and the second internal electrode 24 face each other in the stacking (T) direction via the inner layer ceramic layer 20. A capacitance is generated by the portion where the first internal electrode 22 and the second internal electrode 24 face each other via the inner layer ceramic layer 20.

[0020] The inner layer ceramic layers 20 extend in the width (W) and length (L) directions, and each of the plurality of first internal electrodes 22 extends in a flat plate shape along the inner layer ceramic layers 20. Each of the plurality of first internal electrodes 22 is extended to a first end face 13 of the laminate 12 and electrically connected to a first external electrode 40. Each of the plurality of second internal electrodes 24 extends in a flat plate shape so as to face the first internal electrode 22 with the inner layer ceramic layer 20 interposed therebetween. Each of the plurality of second internal electrodes 24 is extended to a second end face 14 of the laminate 12 and electrically connected to a second external electrode 42.

[0021] The thickness of each of the first and second internal electrodes 22, 24 is, for example, 0.3 μm or more and 2.0 μm or less. The first and second internal electrodes 22, 24 preferably contain Ni. In addition to Ni, metals such as Cu, Ag, Pd, Ag-Pd alloy, and Au may be contained. The first and second internal electrodes 22, 24 may contain the same dielectric particles as the inner ceramic layer 20.

[0022] As shown in Fig. 4, Si is segregated in the portions of the first and second internal electrodes 22, 24 including the surfaces that are most exposed toward the side margin portions 32, 34. Si has segregated regions in the internal electrodes within a range of at least 0.5 µm from the side margin portions toward the center in the width (W) direction, forming segregation portions 22a, 24a. In other words, the segregation portion 22a is formed on the side margin portions 32, 34 side of the first internal electrode 22, and the segregation portion 24a is formed on the side margin portions 32, 34 side of the second internal electrode 24. These segregation portions 22a, 24a improve the flexural strength of the multilayer ceramic capacitor 10.

[0023] When the cross section of the laminate 12 is viewed from the stacking (T) direction, and the regions where the first internal electrode 22 and the second internal electrode 24 are not present are defined as side margin portions 32, 34, the side margin portions 32, 34 have multiple side margin layers, and the Si content of the other side margin layers is higher than that of the side margin layer closest to the internal electrodes 22, 24, thereby increasing the strength of the side margin portions 32, 34. This improves the flexural strength of the multilayer ceramic capacitor 10. Furthermore, cracks and chips are less likely to occur in the side margin portions 32, 34, preventing moisture penetration. This ensures the insulation of the multilayer ceramic capacitor 10. As a result, a sufficiently reliable multilayer ceramic capacitor 10 can be obtained.

[0024] Furthermore, in the laminate 12, the first internal electrode 22 and the second internal electrode 24 include segregation portions 22a, 24a on the side margin portions 32, 34 side, and when the segregation portions 22a, 24a contain Si, the flexural strength of the multilayer ceramic capacitor can be further improved. The side margin portions 32, 34 each have a multilayer structure including outer layers 32a, 34a located on the first and second side surfaces 15, 16 side of the laminate 12, and inner layers 32b, 34b located on the first and second internal electrodes 22, 24 side. The fact that the side margin portions 32, 34 have a multilayer structure can be easily confirmed by observation with an optical microscope due to the difference in sinterability between the outer layers 32a, 34a and the inner layers 32b, 34b.

[0025] The width (W) dimension of the side margin portions 32, 34 after firing is, for example, 5 μm or more and 40 μm or less, and more preferably 20 μm or less. Furthermore, the width (W) dimension of the outer layers 32a, 34a is larger than the width (W) dimension of the inner layers 32b, 34b. Specifically, the width (W) dimension of the outer layers 32a, 34a is 5 μm or more and 20 μm or less. The width (W) dimension of the inner layers 32b, 34b is 0.1 μm or more and 20 μm or less.

[0026] In this invention, the width (W) direction dimension of the side margins 32, 34 refers to the average dimension calculated from the measurement results of measuring the dimensions of the side margins 32, 34 at multiple locations along the stacking (T) direction. The measurement method is as follows: First, a surface including the width (W) direction and the stacking (T) direction of the multilayer ceramic capacitor 10 (hereinafter referred to as the "WT cross section") is exposed. Next, an image of the WT cross section is taken using an optical microscope so that the width (W) direction ends of the first and second internal electrodes 22, 24 and one of the side margins 32, 34 are within the same field of view. Images are taken at three locations in the stacking (T) direction: the top, center, and bottom. Then, at the top, center, and bottom, multiple line segments parallel to the width (W) direction are drawn from the width (W) direction ends of the first and second internal electrodes 22, 24 toward the first and second side surfaces 15, 16, and the length of each line segment is measured. The average length of the line segments measured in this way is calculated for each of the upper, middle, and lower portions, and the thickness of the side margin portions 32, 34 is obtained by further averaging these average values.

[0027] The side margin portions 32, 34 are made of a dielectric ceramic material with a perovskite structure, primarily composed of BaTiO3 or another such material. Si is added to these primary components as an additive, and portions where the additive segregates exist between ceramic particles are present. The presence of the segregated Si portions improves the flexural strength of the side margin portions 32, 34. Si is added to the outer layers 32a, 34a in a ratio of 3.0 to 7.0 moles of Si / Ti moles, and to the inner layers 32b, 34b in a ratio of 1.0 to 4.0 moles of Si / Ti moles. In particular, the segregated Si portions in the outer layers 32a, 34a are greater than the segregated Si portions in the inner layers 32b, 34b.

[0028] FIG. 5 is a diagram of Si segregation in the side margins of the multilayer ceramic capacitor 10, imaged using a wavelength dispersive X-ray analyzer (hereinafter referred to as WDX). The Si segregation in the side margins 32, 34 can be confirmed by exposing a WT cross section at approximately the center of the laminate 12 in the length (L) direction and then observing it using WDX. Furthermore, it can be confirmed that Si segregation 22a, 24a is formed on the first and second internal electrodes 22, 24 closest to the side margins 32, 34. Segregation of not only Si but also Mg was also confirmed. FIGS. 6 to 8 are WDS images of the same location (near the surface of the side margins) of the multilayer ceramic capacitor 10, with FIG. 6 being an image of the Mg segregation, FIG. 7 being an image of the Ni segregation, and FIG. 8 being an image of the Si segregation.

[0029] The amount of Ba, which is an additive, between the ceramic particles in each of the inner ceramic layer 20, the outer layers 32a and 34a, and the inner layers 32b and 34b is as follows: Ceramic layer 20 for inner layer<outer layers 32a, 34a<inner layers 32b, 34b, is. Thus, the Ba content differs between the ceramic particles in the inner ceramic layer 20, the outer layers 32a, 34a, and the inner layers 32b, 34b. The difference in Ba content can be detected by TEM analysis.

[0030] The content of Ba in the outer layers 32a, 34a and the inner layers 32b, 34b of the inner layer portion 26 and the side margin portions 32, 34 is such that the molar ratio of Ba to 1 mol of Ti is, at the center value, The outer layers 32a and 34a are greater than 1.01 and less than or equal to 1.020. The inner layers 32b and 34b are greater than 1.020 and less than 1.040; The inner layer 26 is greater than 0.99 and less than 1.01; It is formulated so that

[0031] The method for confirming the above-mentioned molar ratio is as follows. First, the outer layers 32a, 34a and the inner layers 32b, 34b in the side margins 32, 34 of the laminate 12 are polished from the side margins 32, 34. Next, the powders of the outer layers 32a, 34a and the inner layers 32b, 34b obtained by polishing are dissolved in acid. Then, ICP emission spectroscopy is performed to confirm whether the outer layers 32a, 34a and the inner layers 32b, 34b each have the above-mentioned molar ratio.

[0032] The content of Ba between the ceramic particles of the inner layers 32b, 34b is greater than the content of Ba between the ceramic particles of the outer layers 32a, 34a by more than 100% and less than 140%.

[0033] The side margins 32, 34 are formed so that the voids decrease from the internal electrode side toward the side surface. That is, the voids in the outer layers 32a, 34a are smaller than the voids in the inner layers 32b, 34b. This prevents moisture from penetrating into the laminate 12 from the side margins 32, 34, thereby improving the moisture resistance of the multilayer ceramic capacitor 10. Furthermore, the insulation properties of the multilayer ceramic capacitor 10 can be ensured.

[0034] (First and second external electrodes 40, 42) The first external electrode 40 is formed so as to cover the first end face 13 of the laminate 12, and is electrically connected to the first internal electrode 22 extended to the first end face 13 of the laminate 12. The second external electrode 42 is formed so as to cover the second end face 14 of the laminate 12, and is electrically connected to the second internal electrode 24 extended to the second end face 14 of the laminate 12.

[0035] 1 and 2, the first external electrode 40 has a three-layer structure including a base electrode layer 40a, an underlayer plating 40b formed on the surface of the base electrode layer 40a, and an upper layer plating 40c formed on the surface of the underlayer plating 40b. The base electrode layer 40a is provided so as to cover the entire first end face 13 of the laminate 12, and is provided so as to cover from the portion covering the end face 13 to portions of each of the first side face 15 and the second side face 16 and each of the first main face 17 and the second main face 18.

[0036] 1 and 2, the second external electrode 42 has a three-layer structure including a base electrode layer 42a, an underlayer plating 42b formed on the surface of the base electrode layer 42a, and an upper layer plating 42c formed on the surface of the underlayer plating 42b. The base electrode layer 42a is provided so as to cover the entire second end face 14 of the laminate 12, and is provided so as to cover from the portion covering the end face 14 to portions of each of the first side face 15 and the second side face 16 and each of the first main face 17 and the second main face 18.

[0037] The base electrode layers 40a, 42a preferably contain Cu formed by baking. In addition to Cu, they may contain, for example, Ni, Ag, Pd, an Ag-Pd alloy, or Au. The base electrode layers 40a, 42a may be multi-layered. The base electrode layers 40a, 42a may be formed by co-firing with the first internal electrode 22 and the second internal electrode 24, or by post-firing, in which a conductive paste is applied and baked. The base electrode layers 40a, 42a may be formed by direct plating, or by curing a resin layer containing conductive particles and a thermosetting resin.

[0038] The lower layer plating 40b, 42b preferably contains Ni to prevent solder leaching. The upper layer plating 40c, 42c preferably contains Sn to improve mountability. The lower layer plating 40b, 42b, or the upper layer plating 40c, 42c, may contain, in addition to Ni, Cu, Ag, Pd, an Ag-Pd alloy, or Au, for example, in addition to Sn. A conductive resin layer for stress relief may be formed between the base electrode layer 40a and the lower layer plating 40b, and between the base electrode layer 42a and the lower layer plating 42b. The first and second external electrodes 40, 42 may be formed by plating directly on the laminate 12.

[0039] When direct plating is used for the external electrodes 40, 42, and Ni is used for the first and second internal electrodes 22, 24, it is preferable to use Cu, which has good bonding properties with Ni, for the underlayer plating 40b, 42b. Furthermore, it is preferable that the upper layer plating 40c, 42c has a two-layer structure including a first upper layer plating layer formed on the surface of the underlayer plating 40b, 42b and a second upper layer plating layer formed on the surface of the first upper layer plating. It is preferable that the first upper layer plating layer contains Ni, which has the function of preventing solder leaching. It is preferable that the second upper layer plating layer contains Sn or Au, which have good solder wettability.

[0040] As shown in FIG. 3 , the multilayer ceramic capacitor 10 of this embodiment has side margin portions 32, 34 that are composed of multiple layers. The side margin portion 32 has an outer layer 32a and an inner layer 32b. The inner layer 32b is disposed between the first and second internal electrodes 22, 24 and the outer layer 32a. The outer layer 32a, which is a side margin layer other than the inner layer 32b, has a higher Si content than the inner layer 32b, which is disposed closest to the first and second internal electrodes 22, 24. The side margin portion 34 has an outer layer 34a and an inner layer 34b. The inner layer 34b is disposed between the first and second internal electrodes 22, 24 and the outer layer. The outer layer 34a, which is a side margin layer other than the inner layer 34b, has a higher Si content than the inner layer 34b, which is disposed closest to the first and second internal electrodes 22, 24. This improves the strength of the side margins 32, 34, thereby improving the flexural strength of the multilayer ceramic capacitor 10. Furthermore, cracks and chips are less likely to occur in the side margins 32, 34, and moisture penetration can be prevented, ensuring the insulation of the multilayer ceramic capacitor 10. As a result, it is possible to provide a multilayer ceramic capacitor 10 with improved reliability. In addition, interfaces exist between the outer layers 32a, 34a and the inner layers 32b, 34b, and these interfaces can relieve stress applied to the multilayer ceramic capacitor 10.

[0041] Furthermore, the multilayer ceramic capacitor 10 of this embodiment contains more Si on the surfaces closest to the side margin portions 32, 34 than on the central portions of the first and second internal electrodes 22, 24. As a result, the strength of the side margin portions 32, 34 can be further improved.

[0042] Furthermore, in the multilayer ceramic capacitor 10 of this embodiment, the Si content of the side margin portions 32, 34 is 1.0 or more and 7.0 or less, calculated as the ratio of moles of Si to moles of Ti. If the ratio of moles of Si to moles of Ti is less than 1.0, the side margin portions 32, 34 will not be sintered sufficiently, resulting in increased porosity and insufficient improvement in flexural strength. On the other hand, if the ratio of moles of Si to moles of Ti exceeds 7.0, excessive Si will diffuse into the internal electrodes, resulting in over-sintering and reduced reliability in terms of insulation resistance and the like.

[0043] Furthermore, in the multilayer ceramic capacitor 10 of this embodiment, the dimension of the side margins 32, 34 in the width direction of the laminate 10 is 5 μm or more and 40 μm or less. If the side margins 32, 34 exceed 40 μm, the required capacitance cannot be ensured. If they are less than 5 μm, the sintering of the side margins 32, 34 does not proceed sufficiently, and dense side margins 32, 34 cannot be obtained. If the side margins are not dense, moisture can easily penetrate from the outside.

[0044] 2. Manufacturing method of multilayer ceramic capacitors Next, a method for manufacturing a multilayer ceramic capacitor will be described. Fig. 9 is a diagram for explaining the method for manufacturing a multilayer ceramic capacitor according to this embodiment, where (a) is a schematic diagram showing ceramic green sheets on which conductive films have been formed, and (b) is a schematic diagram showing how the ceramic green sheets on which conductive films have been formed are stacked. Fig. 10 is a perspective view showing an example of the appearance of a laminate chip obtained by the method for manufacturing a multilayer ceramic capacitor according to this embodiment.

[0045] (1) Formation of stacked chips First, a perovskite compound containing Ba and Ti is prepared as a dielectric ceramic material. A ceramic powder obtained from this dielectric ceramic material is mixed with additives, such as at least one of Si, Mg, and Ba, as well as an organic binder, an organic solvent, a plasticizer, and a dispersant, in predetermined proportions to produce a ceramic slurry. The ceramic slurry is then molded into ceramic green sheets 50a and 50b on the surfaces of multiple resin films (not shown). The ceramic green sheets 50b are laminated alternately with the ceramic green sheets 50a. The ceramic green sheets 50a (50b) are molded using, for example, a die coater, a gravure coater, or a microgravure coater.

[0046] Next, as shown in FIG. 9(a), the conductive paste for the internal electrodes is printed in stripes in the X direction on the surface of the ceramic green sheet 50a (50b) and dried. Hereinafter, the direction in which the conductive paste for the internal electrodes extends in stripes is referred to as the X direction. The width direction of the conductive films 52a, 52b is referred to as the Y direction. In this manner, the conductive films 52a (52b) that will become the first internal electrodes 22 (second internal electrodes 24) are formed. Various printing methods, such as screen printing, inkjet printing, and gravure printing, can be used. The thickness of the conductive films 52a, 52b is, for example, 1.5 μm or less.

[0047] First, a predetermined number of ceramic green sheets that do not have a conductive film formed thereon and that will become outer layer portions 28 are stacked, and then, as shown in Fig. 9(b), multiple ceramic green sheets 50a, 50b that have conductive films 52a, 52b printed thereon are shifted in the Y direction and stacked to become inner layer portions 26. Furthermore, a predetermined number of ceramic green sheets that do not have a conductive film formed thereon and that will become outer layer portions 30 are stacked on top of inner layer portions 26 to obtain a mother laminate.

[0048] Next, the mother laminate obtained is pressed. The method for pressing the mother laminate can be a rigid press, a hydrostatic press, or the like.

[0049] Next, the pressed mother laminate is cut into a chip shape to obtain a laminate chip 60 shown in Fig. 10. The mother laminate can be cut by various methods such as press cutting, dicing, laser, etc.

[0050] 10, only the conductive film 52a of the ceramic green sheet 50a is exposed on one end surface of the laminate chip 60 obtained by the above steps, and only the conductive film 52b of the ceramic green sheet 50b is exposed on the other end surface. Furthermore, on both side surfaces of the laminate chip 60, the conductive film 52a of the ceramic green sheet 50a and the conductive film 52b of the ceramic green sheet 50b are exposed.

[0051] (2) Formation of side margins Next, a procedure for producing ceramic green sheets for the side margins 32 and 34 will be described.

[0052] First, a perovskite compound containing Ba and Ti is prepared as a dielectric ceramic material. Dielectric powder obtained from this dielectric ceramic material is mixed with at least one of Si, Mg, and Ba as additives, as well as a binder resin, an organic solvent, a plasticizer, and a dispersant in predetermined proportions to produce a ceramic slurry.

[0053] Here, Si is added to the ceramic slurry that will become the outer layer 32a of the side margin portion 32 (and the outer layer 34a of the side margin portion 34). Specifically, Si is added so that the ratio of moles of Si / moles of Ti is 1.0 or more and 7.0 or less. Si is also added to the ceramic slurry that will become the inner layer 32b of the side margin portion 32 (and the outer layer 34b of the side margin portion 34). Specifically, Si is added so that the ratio of moles of Si / moles of Ti is 1.0 or more and 4.0 or less.

[0054] Ba is also added to the ceramic slurry that will become the outer layer 32a of the side margin portion 32 (and the outer layer 34a of the side margin portion 34). Specifically, Ba is added so that the ratio of moles of Ba / moles of Ti is 0.00 or more and less than 0.02. Ba is also added to the ceramic slurry that will become the inner layer 32b of the side margin portion 32 (and the outer layer 34b of the side margin portion 34). Specifically, Ba is added so that the ratio of moles of Ba / moles of Ti is 0.02 or more and less than 0.04.

[0055] Furthermore, the amount of polyvinyl chloride (PVC) contained in the ceramic slurry that will form the outer layers 32a, 34a of the side margin portions 32, 34 is greater than the amount of polyvinyl chloride (PVC) contained in the ceramic slurry that will form the inner portions 32b, 34b of the side margin portions 32, 34.

[0056] Furthermore, the solvent contained in the ceramic slurry that will form the inner layers 32b, 34b of the side margin portions 32, 34 is appropriately selected to prevent dissolution of the outer layer ceramic green sheets. The inner layer ceramic green sheets also serve to adhere to the laminate chip 60.

[0057] Then, the ceramic slurry that will become the outer layers 32a, 34a is applied to the surface of the resin film and dried to obtain ceramic green sheets for the outer layers.

[0058] Next, the ceramic slurry for the inner layers 32b and 34b is applied to the surface of the outer layer ceramic green sheet and dried to form the inner layer ceramic green sheet. In this way, a two-layer structure side margin ceramic green sheet is obtained.

[0059] Here, the widthwise dimension of the ceramic green sheets for the inner layer is preferably smaller than the widthwise dimension of the ceramic green sheets for the outer layer. Specifically, for example, the thickness of the ceramic green sheets for the outer layer after firing is formed to be 5 μm or more and 20 μm or less, and the thickness of the ceramic green sheets for the inner layer is formed to be 0.1 μm or more and 20 μm or less.

[0060] In the above, the two-layered side margin ceramic green sheet has been described as being obtained by applying an inner layer ceramic green sheet to the surface of an outer layer ceramic green sheet and drying the applied sheet. However, this is not limited to this case, and the outer layer ceramic green sheet and the inner layer ceramic green sheet may be formed in advance, and then the two-layered side margin ceramic green sheet may be obtained by laminating them together. The side margin ceramic green sheet is not limited to two layers, and may be three or more layers.

[0061] Next, the side margin ceramic green sheets are peeled off from the resin film.

[0062] Next, the inner layer ceramic green sheet of the peeled side margin ceramic green sheet is placed opposite the side surface of the laminate chip 60 where the conductive films 52a, 52b are exposed, and the sheets are pressed together and punched out to form a layer that will become the side margin portion 32. Furthermore, for the side surface of the laminate chip 60 where the layer that will become the side margin portion 32 is not formed, the inner layer ceramic green sheet is placed opposite the side surface of the laminate chip 60 where the conductive films 52a, 52b are exposed, and the sheets are pressed together and punched out to form a layer that will become the side margin portion 34. At this time, it is preferable to apply an organic solvent that will serve as an adhesive to the side surface of the laminate chip 60 in advance.

[0063] Next, the laminate chip 60 on which the layers that will become the side margin portions 32, 34 are formed is degreased under specified conditions in a nitrogen atmosphere, and then sintered at a specified temperature in a nitrogen-hydrogen-water vapor mixed atmosphere to obtain the sintered laminate 12.

[0064] Next, an external electrode paste mainly composed of Cu is applied to each of the two end faces of the sintered laminate 12 and baked to form a base electrode 40a connected to the first internal electrode 22 and a base electrode 42a connected to the second internal electrode 22. Furthermore, lower layer platings 40b, 42b made of Ni plating are formed on the surfaces of the base electrode layers 40a, 42a, and upper layer platings 40c, 42c made of Sn plating are formed on the surfaces of the lower layer platings 40b, 42b, thereby forming the first and second external electrodes 40, 42.

[0065] In this manner, the multilayer ceramic capacitor 10 shown in FIG. 1 is manufactured.

[0066] The side margins 32 and 34 may be formed by applying a ceramic slurry for the side margins to both side surfaces of the laminated chip 60 where the conductive films 52a and 52b are exposed.

[0067] That is, ceramic slurry that will become the inner layers 32b and 34b is applied and dried to both side surfaces of the laminate chip 60 where the conductive films 52a and 52b are exposed. Furthermore, ceramic slurry that will become the outer layers 32a and 34a is applied to the surfaces of the inner layers 32b and 34b.

[0068] In this case, the thickness of each of the ceramic slurries that will become the outer layers 32a, 34a and the inner layers 32b, 34b can be adjusted by changing the amount of resin contained in each ceramic slurry.

[0069] Alternatively, the side margins 32, 34 may be formed by masking both end surfaces of the laminate chip 60 with resin or the like, dipping the entire laminate chip 60 in a ceramic slurry that will form the inner layers 32b, 34b, drying it, and then dipping it again in a ceramic slurry that will form the outer layers 32a, 34a. In this case, the inner and outer layers are formed on the outer layer portions 28, 30, forming a three-layer structure.

[0070] 3. Experimental Example The following describes experimental examples conducted by the inventors to confirm the effects of the present invention. In the experimental examples, samples of multilayer ceramic capacitors according to the following examples and comparative examples were manufactured, and the hardness of the surfaces of the side margins of the multilayer ceramic capacitors was measured and evaluated using a Vickers hardness tester.

[0071] (Example) First, in the example, a sample of the multilayer ceramic capacitor shown in FIG. 1 was manufactured using the method described above. In this case, the outer dimensions of the multilayer ceramic capacitor were 1.0 mm in length, 0.5 mm in width, and 0.5 mm in height. In the example, a multilayer ceramic capacitor was prepared having a two-layer side margin portion consisting of an inner layer containing Si relative to Ti such that the ratio of the number of moles of Si to the number of moles of Ti was 3.5, and an outer layer containing Si relative to Ti such that the ratio of the number of moles of Si to the number of moles of Ti was 5. The thickness of the side margin portion was 20 μm. In the example, the thickness of the outer layer was 16 μm, and the thickness of the inner layer was 4 μm.

[0072] (Comparative Example) In the comparative example, a multilayer ceramic capacitor was manufactured under the same conditions as in the example, except that a side margin portion consisting of two layers, an inner layer and an outer layer, was not provided, and instead a single-layer side margin portion was used in which Si was contained relative to Ti such that the number of moles of Si / the number of moles of Ti was 3.5.

[0073] (Evaluation method) Five samples of each of the multilayer ceramic capacitors of the examples and comparative examples were prepared, and the hardness of the surface of the side margins on both sides of the multilayer ceramic capacitors was measured using a Vickers hardness tester. The Vickers hardness measurement conditions were a measurement load of 200 gf and a bottom dead center holding time of 10 s. The pore area ratio near the surface of the side margins of each sample of the multilayer ceramic capacitors of the examples and comparative examples was also calculated. This pore area ratio was determined by exposing the surface including the side margins and imaging it with an SEM. The image was then processed to measure the pore area. The pore area ratio was calculated by dividing the pore area by the area of ​​the multilayer ceramic capacitor shown in the image.

[0074] FIG. 11 is a diagram showing the relationship between the pore area ratio in the vicinity of the surface of the side margin portion and the Vickers hardness of the surface of the side margin portion. As a result of the experiment, as shown in FIG. 11, in the multilayer ceramic capacitor of the example, the pore area ratio near the surface of the side margin portion was 0.3%, and the Vickers hardness of the surface of the side margin portion was 1470 MPa or more and 1680 MPa or less. On the other hand, as shown in FIG. 11, in the comparative multilayer ceramic capacitor, the pore area ratio near the surface of the side margin portion was 1.9%, and the Vickers hardness of the surface of the side margin portion was 1140 MPa or more and 1270 MPa or less. From the above, it is clear that the multilayer ceramic capacitor of the example has improved bending strength compared to the multilayer ceramic capacitor of the comparative example.

[0075] The present invention is not limited to the above-described embodiment, but may be modified in various ways within the scope of the invention. [Explanation of symbols]

[0076] 10 Multilayer ceramic capacitors 12 Laminate 13 First end face 14 Second end face 15 First Aspect 16 The Second Aspect 17 First principal surface 18 Second main surface 20. Ceramic layer for inner layer 22 First internal electrode 22a, 24a Segregation part 22b: First inner electrode closest to the first main surface 24 Second internal electrode 24b: second internal electrode closest to the second main surface 26 Inner layer 28, 30 outer layer 32, 34 Side margin 32a, 34a outer layer 32b, 34b inner layer 40 First external electrode 42 Second external electrode 40a, 42a base electrode layer 40b, 42b Underlayer plating 40c, 42c top layer plating 46, 48 Ceramic outer layer 50a, 50b Ceramic green sheets 52a, 52b conductive film 60 stacked chips

Claims

1. A multilayer ceramic capacitor comprising a laminate including dielectric layers and internal electrodes stacked in a stacking direction, and external electrodes connected to the internal electrodes, The laminate is the laminate is formed in a shape including a first main surface and a second main surface that face each other in a stacking direction, a first side surface and a second side surface that face each other in a width direction that intersects with the stacking direction, and a first end surface and a second end surface that face each other in a length direction that intersects with the stacking direction and the width direction; an inner layer portion formed by laminating the dielectric layers and the internal electrodes in the lamination direction; outer layer portions arranged to sandwich the inner layer portion in the lamination direction; and side ceramic layers arranged to sandwich the inner layer portion and the outer layer portion in the width direction, the internal electrodes include a first internal electrode exposed at the first end surface and a second internal electrode exposed at the second end surface, the external electrodes include a first external electrode provided on the first end face and connected to the first internal electrode, and a second external electrode provided on the second end face and connected to the second internal electrode, the side ceramic layer has an inner layer located on the inner layer portion side and outer layers located on the first side surface side and the second side surface side, and the Si content of the outer layer is higher than the Si content of the inner layer; the mole number of Si / mol number of Ti in the outer layer is 3.0 or more and 7.0 or less, the molar ratio of Si to Ti in the inner layer is 1.0 or more and 4.0 or less; Multilayer ceramic capacitor.

2. the exposed surfaces of the first internal electrodes and the second internal electrodes on the first side surface and the second side surface of the laminate contain more Si than central portions of the first internal electrodes and the second internal electrodes; The multilayer ceramic capacitor according to claim 1 .

3. the ratio of the mole number of Si to the mole number of Ti in the side ceramic layer is 1.0 or more and 7.0 or less; 3. The multilayer ceramic capacitor according to claim 1.

4. 4. The multilayer ceramic capacitor according to claim 1, wherein the dimension of said side ceramic layers along said width direction is 5 [mu]m or more and 40 [mu]m or less.

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