Semiconductor Devices

Abstract

To reduce warpage caused by heat.SOLUTION: The difference in thermal expansion coefficients between a base plate 5, a resin layer 4 and a circuit pattern 3 in an insulated circuit board 2 is small, and warpage of the insulated circuit board 2 due to heat can be reduced. Semiconductor chips 6a,6b are bonded to the circuit surface of the circuit pattern 3 with the side edges spaced inward from the outer edge of the circuit pattern 3 by a predetermined distance D1 or more. Therefore, heat diffusion portions 7a, 7b of the circuit pattern 3 are not interfered with the semiconductor chips 6a, 6b, and the reduction in heat dissipation of the circuit pattern 3 with respect to the semiconductor chips 6a, 6b can be suppressed. Therefore, the long-term reliability of a semiconductor device 1 can be suppressed along with the reduction in heat dissipation of the semiconductor device.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] The semiconductor device includes a power device. The power device is, for example, a semiconductor chip including an IGBT (Insulated Gate Bipolar Transistor) or a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The semiconductor device includes an insulating circuit board on which the semiconductor chip is disposed. The insulating circuit board includes a ceramic plate, a circuit pattern formed on the front surface of the ceramic plate, and a metal plate formed on the back surface of the ceramic plate. The semiconductor chip is bonded onto the circuit pattern. Furthermore, the semiconductor device has a case bonded to the insulating circuit board with an adhesive, surrounding the outer peripheral edge of the insulating circuit board. A lead frame for input and output is insert-molded into the case. Inside the case, the semiconductor chip and the lead frame are electrically connected by wires (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2017-139406 Summary of the Invention [Problem to be solved by the invention]

[0004] However, in the above-mentioned insulated circuit board, there is a difference in the thermal expansion coefficient between the ceramic plate and the circuit pattern and metal plate. Therefore, the insulated circuit board undergoes significant warping due to heat generation from the semiconductor chip. Furthermore, when the insulated circuit board repeatedly warps due to the heat cycle of the semiconductor device, cracks may occur in the ceramic plate, and these cracks may further propagate. When the ceramic plate is damaged in this way, the thermal conductivity and insulating properties of the insulated circuit board decrease, reducing the long-term reliability of the semiconductor device.

[0005] The present invention has been made in view of the above points, and has as its object to provide a semiconductor device in which the occurrence of warping due to heat is reduced. [Means for solving the problem]

[0006] According to one aspect of the present invention, there is provided an insulating circuit board including a base plate, a resin layer provided on a front surface of the base plate, and a first circuit pattern provided on the front surface of the resin layer; a first semiconductor chip bonded to the circuit front surface of the first circuit pattern; and a second semiconductor chip bonded to the circuit front surface with a gap from the first semiconductor chip, wherein a thickness of the first circuit pattern is 0.1 times or more a first length of one side of the first semiconductor chip and 0.1 times or more a second length of one side of the second semiconductor chip, and the gap is 0.2 times or more a combined length of the first length and the second length. the law of nature , The device further includes a case having a frame body with an opening at the center, the back surface of the frame body being joined to an outer peripheral edge of the resin layer, and the first circuit pattern being provided in the opening in a plan view. A semiconductor device is provided.

[0007] According to another aspect of the present invention, there is provided a semiconductor device including: an insulating circuit board having a base plate, a resin layer provided on an upper surface of the base plate, and a first circuit pattern provided on the upper surface of the resin layer; a first semiconductor chip bonded to the circuit upper surface of the first circuit pattern; a second semiconductor chip bonded to the circuit upper surface; and a case having a frame body portion with an opening at its center, the back surface of the frame body portion being bonded to an outer peripheral edge of the resin layer, and the first circuit pattern being provided in the opening in a planar view, wherein a thickness of the first circuit pattern is at least 0.1 times a first length of one side of the first semiconductor chip and is at least 0.1 times a second length of one side of the second semiconductor chip, and further, a side edge of the first semiconductor chip is spaced inward from the outer peripheral edge of the first circuit pattern by at least 0.1 times the first length, and a side edge of the second semiconductor chip is spaced inward from the outer peripheral edge of the first circuit pattern by at least 0.1 times the second length. [Effects of the Invention]

[0008] According to the disclosed technology, it is possible to reduce the occurrence of warpage and prevent a decrease in the long-term reliability of the semiconductor device. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a diagram for explaining a semiconductor device according to a first embodiment. [Figure 2] FIG. 10 is a cross-sectional view of a semiconductor device according to a second embodiment. [Figure 3] FIG. 10 is a plan view of a semiconductor device according to a second embodiment. [Figure 4] FIG. 10 is a diagram for explaining a circuit pattern according to a second embodiment. [Figure 5] 10 is a cross-sectional view (part 1) of a main part of a semiconductor device according to a second embodiment; FIG. [Figure 6] FIG. 10 is a cross-sectional view (part 2) of a main part of the semiconductor device according to the second embodiment. [Figure 7] FIG. 10 is a cross-sectional view of a main part of a semiconductor device according to a third embodiment. [Figure 8]FIG. 10 is a cross-sectional view (part 1) of a main part of a semiconductor device according to a fourth embodiment. [Figure 9] FIG. 10 is a cross-sectional view (part 2) of a main part of the semiconductor device according to the fourth embodiment. [Figure 10] FIG. 10 is a cross-sectional view of a main part of a semiconductor device according to a fifth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, embodiments will be described with reference to the drawings. In the following description, the terms "front surface" and "upper surface" refer to the surface facing upward in the semiconductor device 10 of FIG. 2. Similarly, "up" refers to the upward direction in the semiconductor device 10 of FIG. 2. The terms "back surface" and "lower surface" refer to the surface facing downward in the semiconductor device 10 of FIG. 2. Similarly, "lower" refers to the downward direction in the semiconductor device 10 of FIG. 2. Similar orientations will be used in other drawings as necessary. The terms "front surface," "upper surface," "upper," "back surface," "lower surface," "lower," and "side surface" are merely convenient expressions for specifying relative positional relationships and do not limit the technical concept of the present invention. For example, "upper" and "lower" do not necessarily refer to the vertical direction relative to the ground. In other words, the "upper" and "lower" directions are not limited to the direction of gravity. In the following description, the term "main component" refers to a component containing 80 vol% or more of a component.

[0011] [First embodiment] A semiconductor device according to a first embodiment will be described with reference to Fig. 1. Fig. 1 is a diagram for explaining the semiconductor device according to the first embodiment. Fig. 1(A) is an enlarged plan view of a main part of the semiconductor device 1. Fig. 1(B) is a cross-sectional view taken along dashed line XX in Fig. 1(A).

[0012] The semiconductor device 1 includes an insulating circuit board 2 and semiconductor chips 6a and 6b. The insulating circuit board 2 includes a circuit pattern 3, a resin layer 4 having the circuit pattern 3 formed on its front surface (resin front surface), and a base plate 5 having the resin layer 4 formed on its front surface. The circuit pattern 3 and the base plate 5 are made of conductive metal. The resin layer 4 is made of a resin with low thermal resistance and high insulating properties. The semiconductor chips 6a and 6b are power devices having a rectangular shape in a planar view. The semiconductor chips 6a and 6b are bonded to the front surface (circuit front surface) of the circuit pattern 3. Furthermore, the semiconductor chips 6a and 6b are bonded such that their side edges are spaced inward from the outer periphery of the circuit pattern 3 by a predetermined distance D1 or more. In this case, the predetermined distance D1 corresponds to the thickness T of the circuit pattern 3. The thickness T of the circuit pattern 3 is 0.1 times or more the length of one side of the semiconductor chips 6a and 6b. That is, the predetermined distance D1 and the thickness T of the circuit pattern 3 are both 0.1 times or more the length (Da1, Db1) of one side of the semiconductor chips 6a, 6b. The distance D2 between the opposing side ends of the semiconductor chips 6a, 6b in a side view is at least twice the predetermined distance D1. That is, the distance D2 between the opposing side ends of the semiconductor chips 6a, 6b in a side view is at least 0.2 times the length of one side of the semiconductor chips 6a, 6b. Here, the length of one side of the semiconductor chips 6a, 6b may be the length of the short side if the semiconductor chips 6a, 6b are rectangular in a plan view.

[0013] In such an insulating circuit board 2, the difference in thermal expansion coefficient between the circuit pattern 3 and base plate 5 and the resin layer 4 is smaller than the difference in thermal expansion coefficient between the circuit pattern 3 and base plate 5 and the ceramic plate. This makes it possible to reduce warpage that occurs in the insulating circuit board 2 due to the heat from the semiconductor chips 6a and 6b.

[0014] Furthermore, as the semiconductor chips 6a and 6b arranged on the circuit pattern 3 are driven, the heat generated from the semiconductor chips 6a and 6b diffuses through the area indicated by the dashed lines (thermal diffusion sections 7a and 7b) of the circuit pattern 3 and is conducted to the resin layer 4. That is, the heat generated from the semiconductor chips 6a and 6b diffuses so as to spread as it advances toward the resin layer 4 in a side view of the circuit pattern 3. At this time, the thermal diffusion sections 7a and 7b in the circuit pattern 3 are not interfered with by others, so that the heat from the semiconductor chips 6a and 6b can be reliably conducted to the resin layer 4. Furthermore, if the conduction of heat from the semiconductor chips 6a and 6b is, for example, a 45° diffusion, the thermal diffusion outermost regions 7a1 and 7b1, which are the boundaries between the thermal diffusion sections 7a and 7b and the circuit pattern 3, form a 45° angle with a vertical line perpendicular to the rear surfaces of the semiconductor chips 6a and 6b. Therefore, in order for the thermal diffusion units 7a and 7b to fit within the circuit pattern 3 as shown in FIG. 1B, the predetermined distance D1 from the outer peripheral edge of the circuit pattern 3 must be equal to or greater than the thickness T of the circuit pattern 3. If the predetermined distance D1 were less than the thickness T of the circuit pattern 3, the end portions of the thermal diffusion units 7a and 7b would not fit within the circuit pattern 3. This would reduce the thermal conductivity of the semiconductor chips 6a and 6b to the circuit pattern 3. Furthermore, the semiconductor chips 6a and 6b must be spaced apart by a distance D2 or greater so that the thermal diffusion units 7a and 7b do not interfere with each other within the circuit pattern 3. This distance D2 must be at least D1 + D1.

[0015] In this case, the thickness T of the circuit pattern 3 must be at least 0.1 times the length of one side of the semiconductor chips 6a, 6b. As the chip area of ​​the semiconductor chips 6a, 6b increases, the thermal conductivity of the circuit pattern 3 is less affected by the thickness T of the circuit pattern 3. In view of this, when the chip area of ​​the semiconductor chips 6a, 6b is large, it is necessary to maintain a certain degree of thickness T of the circuit pattern 3 in order to conduct heat from the semiconductor chips 6a, 6b to the resin layer 4. For this reason, the thickness T of the circuit pattern 3 must be at least 0.1 times, and more preferably at least 0.3 times, the chip area (length of one side; if rectangular, length of the short side) of the semiconductor chips 6a, 6b.

[0016] The semiconductor device 1 includes an insulating circuit board 2 and semiconductor chips 6a and 6b. The insulating circuit board 2 includes a base plate 5, a resin layer 4 formed on the front surface of the base plate 5, and a circuit pattern 3 formed on the resin front surface of the resin layer 4. The semiconductor chips 6a and 6b are bonded to the front circuit surface of the circuit pattern 3 with their side edges spaced inward from the outer peripheral edge of the circuit pattern 3 by a predetermined distance D1 or more, and are rectangular in plan view. Furthermore, the predetermined distance D1 must be 0.1 times or more, and more preferably 0.3 times or more, the length of one side of each of the semiconductor chips 6a and 6b (the length of the short side if rectangular).

[0017] In this semiconductor device 1, the difference in thermal expansion coefficients between the base plate 5, resin layer 4, and circuit pattern 3 included in the insulating circuit board 2 is small, thereby reducing warping of the insulating circuit board 2 due to heat. Furthermore, the semiconductor chips 6a, 6b are bonded to the front circuit surface of the circuit pattern 3 with their side edges spaced inward from the outer periphery of the circuit pattern 3 by a predetermined distance D1 or more. This prevents interference with the thermal diffusion sections 7a, 7b within the circuit pattern 3 caused by the semiconductor chips 6a, 6b, thereby preventing a decrease in the heat dissipation performance of the circuit pattern 3 relative to the semiconductor chips 6a, 6b. This prevents a decrease in the heat dissipation performance of the semiconductor device 1 as well as a decrease in its long-term reliability.

[0018] [Second embodiment] The second embodiment is a more specific example of the first embodiment. The semiconductor device of the second embodiment will be described with reference to FIGS. 2 to 6. FIG. 2 is a cross-sectional view of the semiconductor device of the second embodiment, and FIG. 3 is a plan view of the semiconductor device of the second embodiment. FIG. 4 is a diagram for explaining a circuit pattern of the second embodiment. FIGS. 5 and 6 are cross-sectional views of essential parts of the semiconductor device of the second embodiment. FIG. 2 shows a cross-sectional view taken along dashed line XX in FIG. 3. Also, FIG. 3 omits the illustration of the case 60 and sealing member 66 of the semiconductor device 10. FIG. 4 is an enlarged cross-sectional view of an arbitrary circuit pattern. FIG. 5 shows a cross-sectional view taken along dashed line YY in FIG. 3. FIG. 6 illustrates a case where a wire 50 is connected instead of a slit 22c1 in the case of FIG. 5.

[0019] The semiconductor device 10 includes an insulating circuit board 20, semiconductor chips 30a, 40a, 30b, and 40b, and a case 60 that houses the insulating circuit board 20 and the semiconductor chips 30a, 40a, 30b, and 40b. The insulating circuit board 20 includes a resin layer 21, circuit patterns 22a and 22b, and a base plate 23. Note that the circuit patterns 22a and 22b are generic names for the circuit patterns 22a1 to 22a3 and 22b1 to 22b3. Hereinafter, when there is no need to distinguish between the circuit patterns 22a1 to 22a3 and 22b1 to 22b3, they will be referred to as the circuit patterns 22a and 22b.

[0020] The resin layer 21 is made of a resin with low thermal resistance and high insulating properties. Such a resin is, for example, a thermosetting resin. The thermosetting resin may contain a thermally conductive filler. This reduces the thermal resistance of the resin layer 21 and reduces the difference in thermal expansion coefficient between the resin layer 21 and the base plate 23. Examples of such a thermosetting resin include at least one of epoxy resin, cyanate resin, benzoxazine resin, unsaturated polyester resin, phenolic resin, melamine resin, silicone resin, maleimide resin, acrylic resin, and polyamide resin. The thermally conductive filler is made of at least one of an oxide and a nitride. Examples of oxides include silicon oxide and aluminum oxide. Examples of nitrides include silicon nitride, aluminum nitride, and boron nitride. Hexagonal boron nitride may also be used as the thermally conductive filler. The thickness of the resin layer 21 depends on the rated voltage of the semiconductor device 10. That is, the higher the rated voltage of the semiconductor device 10, the greater the thickness of the resin layer 21. On the other hand, it is also desirable to reduce the thermal resistance by making the resin layer 21 as thin as possible. The thickness of such a resin layer 21 is, for example, not less than 0.05 mm and not more than 0.50 mm.

[0021] The circuit patterns 22a and 22b are made of a material with excellent conductivity. Examples of such materials include copper, aluminum, or an alloy containing at least one of these. The thickness of the circuit patterns 22a and 22b is preferably 0.1 mm or more and 5.0 mm or less, and more preferably 0.2 mm or more and 2.0 mm or less. Details of the thickness of each of the circuit patterns 22a and 22b will be described later.

[0022] The circuit patterns 22a and 22b are obtained by punching a single conductive plate into the desired pattern shape. The circuit patterns 22a and 22b thus obtained have burrs on the outer peripheral edge of the main surface and sagging on the outer peripheral edge of the main surface opposite the main surface, depending on the punching direction. For example, as shown in FIG. 4, the circuit pattern 22a is disposed on the resin layer 21 so that sagging 22d2 is located on the back surface facing the resin layer 21 and burr 22d1 is located on the front surface. Suppose the circuit pattern 22a is disposed so that the burr 22d1 is located on the back surface of the resin layer 21. In this case, depending on the thickness of the resin layer 21, there is a risk that the burr 22d1 will break through the resin layer 21. This would prevent the resin layer 21 from maintaining insulation between the circuit pattern 22a and the base plate 23. Furthermore, the circuit pattern 22a is disposed so that the sagging 22d2 is located on the back surface of the circuit pattern 22a. In this case, the sags 22d2 are more likely to adhere to the resin layer 21. This ensures that the circuit pattern 22a is securely fixed to the resin layer 21, and prevents the circuit pattern 22a from peeling off from the resin layer 21. The circuit pattern 22b on which the burrs 22d1 and the sags 22d2 are generated is also disposed on the resin layer 21 in the same manner as described above.

[0023] The semiconductor chips 30a, 40a and the semiconductor chips 30b, 40b are soldered onto the circuit patterns 22a2, 22b2. In addition to the semiconductor chips 30a, 40a and the semiconductor chips 30b, 40b, wiring members and electronic components such as wires, lead frames, and connection terminals can be arranged on the circuit patterns 22a, 22b as needed. The squares on the circuit patterns 22a2, 22a3, and 22b2 represent the bonding locations of the lead frames 62 to 64. These circuit patterns 22a, 22b can also be plated with a material that has excellent corrosion resistance. Such a material is, for example, nickel or a nickel-containing alloy.

[0024] Furthermore, in the circuit pattern 22a2, slits 22c1 are formed between the semiconductor chips 30a and between the semiconductor chips 40a. Note that FIG. 5 shows the case where the slits 22c1 are formed between the semiconductor chips 30a. In the circuit pattern 22b2, slits 22c2 are also formed between the semiconductor chips 30b and between the semiconductor chips 40b. These slits 22c1 can reduce thermal interference between the semiconductor chips 30a and 40a. The slits 22c2 can also reduce thermal interference between the semiconductor chips 30b and 40b.

[0025] The number, arrangement position and shape of the circuit patterns 22a, 22b shown in FIGS. 2 and 3 are merely examples, and the number, arrangement position and shape can be selected appropriately by design without being limited to this case.

[0026] The base plate 23 is made of a material with excellent thermal conductivity. Examples of such materials include aluminum, iron, silver, copper, or an alloy containing at least one of these. Such a material may also be a metal composite. Examples of metal composites include aluminum-silicon carbide (Al-SiC) and magnesium-silicon carbide (Mg-SiC). To improve corrosion resistance, the surface of the base plate 23 may be plated. Examples of plating materials include nickel, nickel-phosphorus alloys, and nickel-boron alloys. The thickness of the plating film is preferably 1 μm or more, more preferably 5 μm or more. Furthermore, as described below, a cooling unit (not shown) can be attached to the back surface of the base plate 23 via solder, silver brazing, or the like. This improves the heat dissipation performance of the semiconductor device 10. In this case, the cooling unit is made of a metal with excellent thermal conductivity. The metal may be aluminum, iron, silver, copper, or an alloy containing at least one of these. The cooling unit may be a heat sink with one or more fins or a water-cooled cooling device. The base plate 23 may be integrated with such a cooling unit. In this case, the base plate 23 may be made of aluminum, iron, silver, copper, or an alloy containing at least one of these materials, which have excellent thermal conductivity. To improve corrosion resistance, the surface of the base plate 23 integrated with the cooling unit may be plated. Examples of plating materials include nickel, nickel-phosphorus alloy, and nickel-boron alloy. The thickness of the base plate 23 is preferably 2 mm or more and 10 mm or less.

[0027] Therefore, such an insulating circuit board 20 can reduce the difference in thermal expansion coefficient between the circuit patterns 22a, 22b and the base plate 23, and the resin layer 21. As a result, even if the semiconductor chips 30a, 40a, 30b, 40b generate heat, the occurrence of warping of the insulating circuit board 20 can be reduced.

[0028] Incidentally, the thermal resistance of the circuit patterns 22a2 and 22b2 (both with constant thickness) on which the semiconductor chips 30a and 40a and the semiconductor chips 30b and 40b are arranged is related to the chip area of ​​the semiconductor chips 30a and 40a and the semiconductor chips 30b and 40b. That is, as the chip area of ​​each increases, the thermal resistance of the circuit patterns 22a2 and 22b2 decreases. Also, the thermal resistance of the circuit patterns 22a2 and 22b2 (with constant chip area) is related to the thickness of the circuit patterns 22a2 and 22b2. That is, as the thickness of the circuit patterns 22a2 and 22b2 increases, the thermal resistance of the circuit patterns 22a2 and 22b2 decreases. Therefore, we measured the thermal resistance of circuit patterns 22a2 and 22b2 when the thicknesses of circuit patterns 22a2 and 22b2 were 0.1 mm, 0.3 mm, 0.4 mm, 0.5 mm, 0.8 mm, and 1.0 mm, respectively, and varied the chip area. We found that, for all thicknesses of circuit patterns 22a2 and 22b2, the thermal resistance of circuit patterns 22a2 and 22b2 decreased with increasing chip area. The results showed that, compared to the thermal resistance for the reference thickness of circuit patterns 22a2 and 22b2, a decrease in thermal resistance was observed when the thickness of circuit patterns 22a2 and 22b2 was 0.5 mm or greater. Therefore, it is preferable that the thickness of circuit patterns 22a2 and 22b2 be 0.5 mm or greater. Furthermore, circuit patterns 22a3 and 22b3 require a certain thickness because they receive output current from semiconductor chips 30a and 30b. Therefore, in consideration of reducing manufacturing costs, it is preferable that the thickness of the circuit patterns 22a3 and 22b3 is also 0.5 mm or more, similar to the circuit patterns 22a2 and 22b2. On the other hand, the circuit patterns 22a1 and 22b1 conduct control signals to the semiconductor chips 30a and 30b. Therefore, the circuit patterns 22a1 and 22b1 do not require high heat dissipation. Therefore, the circuit patterns 22a1 and 22b1 do not need to be as thick as the other circuit patterns 22a2, 22a3, 22b2, and 22b3.

[0029] Such an insulated circuit board 20 is formed, for example, as follows: First, circuit patterns 22a and 22b are obtained in advance by punching from a conductive plate. The thus-obtained circuit patterns 22a and 22b, resin layer 21, and base plate 23 are stacked, and then heated and pressed in the stacking direction to compress and bond them together. This compression bonding is performed in an activated gas atmosphere or in a vacuum. In this way, the insulated circuit board 20 is obtained. Alternatively, the following method may be used: First, base plate 23, resin layer 21, and conductive plate are stacked in this order, and then heated and pressed in the stacking direction to compress and bond them together in the same manner as above. Then, the conductive plate is masked with a photosensitive resist mask to match a predetermined pattern, and the pattern is formed by etching. The photosensitive resist mask is then removed to form the circuit patterns 22a and 22b. The product thus formed is then singulated to obtain the insulated circuit board 20.

[0030] The semiconductor chips 30a, 40a, 30b, and 40b are power devices primarily composed of silicon or a wide bandgap semiconductor. Examples of wide bandgap semiconductors include silicon nitride and gallium nitride. The chip areas of the semiconductor chips 30a, 40a, 30b, and 40b (the side lengths (Da1) of the semiconductor chips 30a and 30b and the side lengths (Db1) of the semiconductor chips 40a and 40b) are 5.5 mm or less. The semiconductor chips 30a and 30b include switching elements. The switching elements are power MOSFETs and IGBTs. The semiconductor chips 30a and 30b each include, for example, a drain electrode (positive electrode, or collector electrode in an IGBT) as a main electrode on the back surface and a gate electrode (control electrode) and a source electrode (negative electrode, or emitter electrode in an IGBT) as main electrodes on the front surface. The semiconductor chips 40a and 40b also include diode elements. The diode elements are free-wheeling diodes (FWDs) such as Schottky barrier diodes (SBDs) and P-intrinsic-N (PiN) diodes. Each of the semiconductor chips 40a and 40b has a cathode electrode as a main electrode on its back surface and an anode electrode as a main electrode on its front surface. The back surfaces of the semiconductor chips 30a and 40a and the semiconductor chips 30b and 40b are bonded to the circuit patterns 22a2 and 22b2 with solder 31 (see FIG. 5, etc.). The solder 31 is made of lead-free solder containing a predetermined alloy as a main component. The predetermined alloy may be, for example, at least one of a tin-silver-copper alloy, a tin-zinc-bismuth alloy, a tin-copper alloy, and a tin-silver-indium-bismuth alloy. The solder 31 may contain an additive, such as nickel, germanium, cobalt, or silicon. Instead of using solder 31, bonding may be performed by sintering using a sintering material. In this case, the sintering material is, for example, a powder containing copper and aluminum as its main components. The thickness of the semiconductor chips 30a, 40a, 30b, and 40b is, for example, 80 μm or more and 500 μm or less, with an average thickness of approximately 200 μm. Electronic components may be arranged on the circuit patterns 22a and 22b as needed.The electronic components are, for example, capacitors, resistors, thermistors, current sensors, and control ICs (Integrated Circuits). Furthermore, instead of the semiconductor chips 30a, 40a and the semiconductor chips 30b, 40b, semiconductor chips including RC (Reverse Conducting)-IGBT switching elements in which an IGBT and an FWD are configured on a single chip may be disposed. Note that FIG. 3 illustrates an example in which two sets of semiconductor chips 30a, 40a and semiconductor chips 30b, 40b are disposed on the circuit patterns 22a2 and 22b2. However, this example is not limiting, and one set, or three or more sets may be disposed depending on the appropriate design.

[0031] The semiconductor chips 30a and 40a are spaced inward from the outer peripheral edge of the circuit pattern 22a2 by a distance equal to or greater than the thickness of the circuit pattern 22a2. The semiconductor chips 30b and 40b are also spaced inward from the outer peripheral edge of the circuit pattern 22b2 by a distance equal to or greater than the thickness of the circuit pattern 22b2. This prevents the heat diffusion units for the circuit patterns 22a2 and 22b2 from the semiconductor chips 30a and 40a and the semiconductor chips 30b and 40b from being interfered with by the outside or by each other. This prevents a decrease in the heat dissipation performance of the circuit patterns 22a2 and 22b2 for the semiconductor chips 30a and 40a and the semiconductor chips 30b and 40b.

[0032] 5, the thermal diffusion units 22d are provided in the circuit pattern 22a2 at intervals between the semiconductor chips 30a so as not to interfere with each other within the circuit pattern 22a2. In this case, the slits 22c1 formed between the semiconductor chips 30a are formed in the circuit pattern 22a2 with a depth that does not interfere with the two thermal diffusion units 22d. This prevents the slits 22c1 from hindering the suppression of a decrease in the heat dissipation performance of the circuit pattern 22a2 relative to the semiconductor chip 30a. The same applies to the slits 22c1 and 22c2 formed between the semiconductor chips 40a, 30b, and 40b, respectively.

[0033] Furthermore, depending on the design, wires 50 may be connected between the semiconductor chips 30a, as shown in Fig. 6, for example. Even in this case, the wires 50 do not hinder the suppression of a decrease in the heat dissipation performance of the circuit pattern 22a2 for the semiconductor chip 30a. The same applies when wires 50 are connected between the semiconductor chips 40a, between the semiconductor chips 30b, and between the semiconductor chips 40b. Details of the wires 50 will be described below.

[0034] The wires 50 electrically and mechanically connect the main electrodes of the semiconductor chips 30a, 40a and 30b, 40b to the circuit patterns 22a and 22b, the main electrodes of the semiconductor chips 30a, 40a, and the main electrodes of the semiconductor chips 30b, 40b, respectively. The wires 51a, 51b electrically and mechanically connect the circuit patterns 22a1, 22b1 to the control electrodes of the semiconductor chips 30a, 30b. The wires 50, 51a, 51b are made of a material with excellent conductivity, such as gold, silver, copper, aluminum, or an alloy containing at least one of these metals. The diameter of the wire 50 is, for example, 390 μm or more and 410 μm or less. The diameter of the wires 51a, 51b is, for example, 120 μm or more and 130 μm or less.

[0035] The case 60 has a frame body 61 and a lid body 65 provided above the opening of the frame body 61. The frame body 61 has an opening formed in the center that penetrates from the front surface to the back surface, forming a frame shape in a plan view. The frame body 61 also includes lead frames 62 to 64. The frame body 61 is integrally formed with the lead frames 62 to 64 by insert molding. In insert molding, a thermoplastic resin that can be bonded to the lead frames 62 to 64 is used. Examples of such resins include polyphenylene sulfide resin, polybutylene terephthalate resin, polybutylene succinate resin, polyamide resin, and acrylonitrile butadiene styrene resin. The lid body 65 is also made of the same material as the frame body 61.

[0036] The lead frames 62 to 64 are, for example, crank-shaped in side view as shown in FIG. 2. Terminals 62a to 64a at one end of the lead frames 62 to 64 protrude from the upper surface of the lid 65 of the case 60 and are disposed in the frame 61. The other end of the lead frames 62 to 64 is electrically and mechanically joined to the circuit patterns 22a2, 22a3, and 22b2 within the frame 61 by soldering (not shown). The lead frames 62 to 64 are made of a material with excellent conductivity. Examples of such materials include copper, aluminum, and alloys containing at least one of these. The thickness of the lead frames 62 to 64 is preferably 1.00 mm to 2.00 mm, and more preferably 1.20 mm to 1.50 mm. The lead frames 62 to 64 can also be plated with a material with excellent corrosion resistance. Examples of such materials include nickel and alloys containing nickel.

[0037] The back surface of the frame portion 61 of the case 60 is fixed to the outer peripheral edge of the insulating circuit board 20 (resin layer 21) with an adhesive member 67. The adhesive member 67 may be, for example, a thermosetting resin adhesive member or an organic adhesive member. The thermosetting resin adhesive member is primarily composed of, for example, epoxy resin or phenolic resin. The organic adhesive member is, for example, an elastomer adhesive primarily composed of silicone rubber or chloroprene rubber. In this manner, the semiconductor chips 30a, 40a, 30b, 40b, etc. are housed in the opening of the frame portion 61, and the opening is sealed with a sealing member 66. It is sufficient for the sealing member 66 to seal the insulating circuit board 20, the semiconductor chips 30a, 40a, 30b, 40b, and the wires 50, 51a, 51b in the opening of the frame portion 61. It is not necessary for the sealing member 66 to fill the entire opening of the frame portion 61.

[0038] The sealing member 66 contains a thermosetting resin and a filler contained in the thermosetting resin. Examples of thermosetting resins include epoxy resin, phenol resin, maleimide resin, and polyester resin. One example of the sealing member 66 is an epoxy resin containing a filler. Examples of the filler include silicon oxide, aluminum oxide, boron nitride, and aluminum nitride. Alternatively, the sealing member 66 may be a thermoplastic resin. Examples of the thermoplastic resin include polyphenylene sulfide resin, polybutylene terephthalate resin, polybutylene succinate resin, polyamide resin, and acrylonitrile butadiene styrene resin.

[0039] To seal the case 60 with the sealing member 66, the molten sealing member 66 is injected into the case 60. At this time, to maintain the viscosity of the molten sealing member 66, the sealing member 66, the case 60, and the semiconductor chips 30a, 40a, 30b, and 40b are heated to maintain a predetermined temperature. Injecting the sealing member 66 in a vacuum ensures that the sealing member 66 reaches every corner of the case 60 without creating voids. Before injection, the sealing member 66 is degassed in a vacuum to remove voids. After degassing, the molten sealing member 66 is stirred in a vacuum to completely degas, thereby preventing further voids from forming. Alternatively, ultrasonic vibrations may be applied to the case 60, the insulating circuit board 20, and the like when injecting the molten sealing member 66. This more reliably prevents voids from forming in the sealing member 66.

[0040] In this semiconductor device 10, the difference in thermal expansion coefficients between the base plate 23, resin layer 21, and circuit patterns 22a and 22b included in the insulating circuit substrate 20 is small, thereby reducing warping of the insulating circuit substrate 20 due to heat. Furthermore, the semiconductor chips 30a and 40a and the semiconductor chips 30b and 40b are bonded to the front surfaces of the circuit patterns 22a2 and 22b2 with their side edges spaced inward from the outer peripheral edges of the circuit patterns 22a2 and 22b2 by a predetermined distance or more. This prevents interference with the thermal diffusion of the circuit patterns 22a2 and 22b2 by the semiconductor chips 30a and 40a and the semiconductor chips 30b and 40b, thereby suppressing a decrease in the heat dissipation performance of the circuit patterns 22a2 and 22b2 relative to the semiconductor chips 30a and 40a and the semiconductor chips 30b and 40b. This suppresses a decrease in the heat dissipation performance of the semiconductor device 10 as well as a decrease in its long-term reliability.

[0041] [Third embodiment] In the third embodiment, in the insulating circuit board 20 included in the semiconductor device 10 of the second embodiment, portions of the lower portions of the circuit patterns 22a and 22b are embedded in the resin layer 21. This case will be described below with reference to FIG. 7. FIG. 7 is a cross-sectional view of a main portion of the semiconductor device of the third embodiment. Note that FIG. 7 corresponds to the cross-sectional view of the semiconductor device 10 taken along the dashed-dotted line XX in FIG. 3, and shows the periphery of the semiconductor chip 40a in this cross-sectional view. Also, FIG. 7 shows the cross sections of the circuit patterns 22a2 and 22a3 as rectangular. As shown in FIG. 4, the circuit patterns 22a2 and 22a3 may have burrs on the front surface side and sagging on the back surface side.

[0042] In this case, in the insulating circuit board 20, approximately half of the lower portions of the circuit patterns 22a2 and 22a3 are embedded in the resin layer 21. A sealing member 66 is inserted between the circuit patterns 22a2 and 22a3, pressing the circuit patterns 22a2 and 22a3 toward the base plate 23. This prevents the circuit patterns 22a2 and 22a3 from peeling off from the resin layer 21. Even if the sides of the circuit patterns 22a2 and 22a3 peel off from the resin layer 21, this does not significantly affect the heat dissipation performance of the insulating circuit board 20. However, if the back surfaces of the circuit patterns 22a2 and 22a3 peel off from the resin layer 21, the heat dissipation performance of the insulating circuit board 20 will be reduced. As shown in FIG. 7 , preventing the circuit patterns 22a2 and 22a3 from peeling off from the resin layer 21 prevents a reduction in the heat dissipation performance of the insulating circuit board 20. This applies not only to the circuit patterns 22a2 and 22a3, but also to the other circuit patterns 22a and 22b. Therefore, it is possible to suppress a decrease in the heat dissipation performance of the semiconductor device 10 as well as a decrease in the long-term reliability.

[0043] [Fourth embodiment] In the fourth embodiment, the entire circuit patterns 22a and 22b are embedded in the resin layer 21 in the insulating circuit board 20 included in the semiconductor device 10 of the second embodiment. This case will be described below with reference to FIGS. 8 and 9. FIGS. 8 and 9 are cross-sectional views of a main portion of the semiconductor device of the fourth embodiment. Note that FIGS. 8 and 9 correspond to the cross-sectional view of the semiconductor device 10 taken along the dashed-dotted line XX in FIG. 3, and show the periphery of the semiconductor chip 40a in this cross-sectional view. Also, FIGS. 8 and 9 show rectangular cross sections of the circuit patterns 22a2 and 22a3. As shown in FIG. 4, the circuit patterns 22a2 and 22a3 may have burrs on the front surface side and sagging on the back surface side.

[0044] In this case, in insulating circuit board 20, circuit patterns 22a2 and 22a3 are embedded in resin layer 21 so that the front surfaces of circuit patterns 22a2 and 22a3 are flush with the front surface of resin layer 21. As described in the second embodiment, insulating circuit board 20 is obtained by pressure-bonding circuit patterns 22a and 22b to resin layer 21. During this pressure-bonding, circuit patterns 22a and 22b are pressed against resin layer 21 with greater pressure. As a result, circuit patterns 22a and 22b are embedded in resin layer 21. At this time, a portion of resin layer 21 pressed against circuit patterns 22a and 22b (resin insulating portion) protrudes from the gap between circuit patterns 22a2 and 22a3, as shown in FIG. 8, for example. Then, resin layer 21 between circuit patterns 22a2 and 22a3 is sealed with sealing member 66 and pressed toward base plate 23. Therefore, as in the third embodiment, peeling of circuit patterns 22a2 and 22a3 from resin layer 21 is prevented, and a decrease in the heat dissipation performance of insulating circuit board 20 can be prevented. Furthermore, resin layer 21 protrudes from between circuit patterns 22a2 and 22a3. This increases the length (creepage distance) of the interface between sealing member 66 and resin layer 21, improving the insulation performance between circuit patterns 22a2 and 22a3 and base plate 23. This is true not only for circuit patterns 22a2 and 22a3, but also for the other circuit patterns 22a and 22b. Therefore, a decrease in the heat dissipation performance of semiconductor device 10 as well as a decrease in long-term reliability can be suppressed.

[0045] Furthermore, when circuit patterns 22a and 22b are pressed against resin layer 21 with greater pressure, as shown in FIG. 9, a portion of resin layer 21 (resin insulating portion) may protrude from the gap between circuit patterns 22a2 and 22a3 and wrap around to the front surface side of circuit patterns 22a2 and 22a3. Even in this case, as in FIG. 8, the length (creepage distance) of the interface between sealing member 66 and resin layer 21 becomes longer, improving the insulation between circuit patterns 22a2 and 22a3 and base plate 23. Furthermore, resin layer 21 wrapping around to the front surface side of circuit patterns 22a2 and 22a3 presses circuit patterns 22a2 and 22a3 toward base plate 23. This further prevents peeling of circuit patterns 22a2 and 22a3. This applies not only to circuit patterns 22a2 and 22a3 but also to other circuit patterns 22a and 22b.

[0046] [Fifth embodiment] In the fifth embodiment, the corners of circuit patterns 22a, 22b are chamfered in insulating circuit substrate 20 included in semiconductor device 10 of the second embodiment. This case will be described below with reference to FIG. 10. FIG. 10 is a cross-sectional view of a main part of the semiconductor device of the fifth embodiment. Note that FIG. 10 corresponds to the cross-sectional view of semiconductor device 10 taken along dashed line XX in FIG. 3, and shows the periphery of semiconductor chip 40a in this cross-sectional view.

[0047] In this case, the corners of the circuit patterns 22a2 and 22a3 included in the insulating circuit board 20 are chamfered along the outer periphery on the front surface. The chamfering angle is, for example, an angle that does not interfere with the thermal diffusion portion for the circuit pattern 22a2 of the semiconductor chip 40a. Such circuit patterns 22a2 and 22a3 are sealed with a sealing member 66. For example, if the corners of the circuit patterns 22a2 and 22a3 are not chamfered as in the case of FIG. 7, the corners of the circuit patterns 22a2 and 22a3 may become the starting point for cracks in the sealing member 66. If a crack propagates into the sealing member 66, moisture may penetrate the crack, reducing the insulating properties of the sealing member 66. In contrast, in this embodiment, the corners of the circuit patterns 22a2 and 22a3 are chamfered, preventing the starting point for cracks in the sealing member 66 and suppressing crack occurrence. This applies not only to the circuit patterns 22a2 and 22a3 but also to the other circuit patterns 22a and 22b. Therefore, the insulating properties of the semiconductor device 10 are maintained, and the deterioration of the heat dissipation properties of the semiconductor device 10 as well as the deterioration of the long-term reliability can be suppressed. [Explanation of symbols]

[0048] 1,10 Semiconductor devices 2,20 Insulated circuit board 3, 22a, 22a1 to 22a3, 22b, 22b1 to 22b3 Circuit pattern 4,21 Resin layer 5,23 Base plate 6a, 6b, 30a, 30b, 40a, 40b Semiconductor chips 7a,7b,22d Heat diffusion section 7a1, 7b1 Outermost thermal diffusion region 22c1,22c2 slit 22d1 Bali 22d2 Dare 31 Solder 50, 51a, 51b Wire 60 cases 61 Frame body part 62, 63, 64 Lead frame 62a, 63a, 64a terminals 65 Lid 66 Sealing member 67 Adhesive materials D1 Distance D2 interval T Thickness

Claims

1. an insulating circuit board including a base plate, a resin layer provided on a front surface of the base plate, and a first circuit pattern provided on the front surface of the resin layer; a first semiconductor chip bonded to a front circuit surface of the first circuit pattern; a second semiconductor chip bonded to the front surface of the circuit with a gap between the first semiconductor chip and the second semiconductor chip; Including, a thickness of the first circuit pattern is 0.1 times or more a first length of one side of the first semiconductor chip and 0.1 times or more a second length of one side of the second semiconductor chip; the gap is equal to or greater than 0.2 times the combined length of the first length and the second length, The device further includes a case having a frame body with an opening at the center, The rear surface of the frame body is joined to the outer peripheral end of the resin layer, the first circuit pattern is provided in the opening in a plan view; Semiconductor device.

2. a side edge of the first semiconductor chip is spaced inward from an outer peripheral edge of the first circuit pattern by at least 0.1 times the first length; a side edge of the second semiconductor chip is spaced inward from an outer peripheral edge of the first circuit pattern by 0.1 times or more of the second length; The semiconductor device according to claim 1 .

3. the second semiconductor chip is arranged next to the side of the first semiconductor chip in the first direction in a plan view; 3. The semiconductor device according to claim 1.

4. another first semiconductor chip bonded to the circuit front surface of the first circuit pattern alongside a side portion of the first semiconductor chip in a second direction perpendicular to the first direction in a plan view; another second semiconductor chip joined to the circuit front surface of the first circuit pattern alongside a side portion of the second semiconductor chip in the second direction in a plan view; further comprising the first circuit pattern has a slit at least either between the first semiconductor chip and the another first semiconductor chip or between the second semiconductor chip and the another second semiconductor chip; The semiconductor device according to claim 3 .

5. an insulating circuit board having a base plate, a resin layer provided on a front surface of the base plate, and a first circuit pattern provided on the front surface of the resin layer; a first semiconductor chip bonded to a front circuit surface of the first circuit pattern; a second semiconductor chip bonded to the circuit front surface; a case having a frame body portion with an opening provided at the center, a back surface of the frame body portion being joined to an outer peripheral edge of the resin layer, and the first circuit pattern being provided in the opening in a plan view; Including, a thickness of the first circuit pattern is 0.1 times or more a first length of one side of the first semiconductor chip and 0.1 times or more a second length of one side of the second semiconductor chip; and a side edge of the first semiconductor chip is spaced inward from an outer peripheral edge of the first circuit pattern by at least 0.1 times the first length; a side edge of the second semiconductor chip is spaced inward from an outer peripheral edge of the first circuit pattern by 0.1 times or more of the second length; Semiconductor device.

6. the frame body portion includes a lead frame having one end connected to the first circuit pattern; The semiconductor device according to claim 5 .

7. a second circuit pattern, through which a control signal is conducted, is provided between the frame portion and the first circuit pattern on the front surface of the resin layer in a plan view of the insulating circuit board; 7. The semiconductor device according to claim 5.

8. the insulating circuit board has a third circuit pattern provided on the front surface of the resin layer on an opposite side of the second circuit pattern with respect to the first circuit pattern in a plan view; The semiconductor device according to claim 7 .

9. a resin insulating portion provided on the front surface of the circuit of the first circuit pattern on the third circuit pattern side; a sealing member provided inside the opening; Including, the resin insulating portion is provided adjacent to the first semiconductor chip or the second semiconductor chip; The semiconductor device according to claim 8 .

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