Semiconductor Devices

Abstract

This semiconductor device comprises a substrate, a first wiring part, a second wiring part, and a semiconductor element. The first wiring part includes a first through-electrode, first main-surface wiring, and a first wiring electrode. The second wiring section includes a second through-electrode, second main-surface wiring, and a second wiring electrode. An upper surface is depressed toward the interior of the first through-electrode. The first wiring electrode is joined to a first element electrode of the semiconductor element by a first joining member. The second wiring electrode is joined to a second element electrode of the semiconductor element by a second joining member. The first wiring electrode, which is formed on an upper surface of the first main-surface wiring, is larger than the second wiring electrode, which is formed on an upper surface of the second main-surface wiring, as seen from the thickness direction.

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] Conventionally, electronic components including elements such as resistors and semiconductor chips include a substrate on which the elements are mounted and a sealing resin that covers the elements. For example, Patent Document 1 discloses a semiconductor device that includes a wiring body having external connection terminals on one side and a semiconductor element mounted on the other side, and a sealing resin formed on the other side of the wiring body so as to seal the semiconductor element. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2013-197263 Summary of the Invention [Problem to be solved by the invention]

[0004] The semiconductor element is connected to the conductive layer of the wiring body by solder, and depending on the condition of the wiring body, there is a risk of poor connection between the semiconductor element and the wiring body, i.e., poor mounting of the semiconductor element. [Means for solving the problem]

[0005] A semiconductor device according to one aspect of the present disclosure includes a substrate having a substrate main surface facing a thickness direction, a semiconductor element having a device main surface opposite the substrate main surface and first and second device electrodes formed on the device main surface, a first through-hole electrode penetrating the substrate and having a first electrode upper surface facing the same side as the substrate main surface, a second through-hole electrode penetrating the substrate and having a second electrode upper surface facing the same side as the substrate main surface, a first main surface wiring in contact with the substrate main surface and the first electrode upper surface and having a first wiring upper surface facing the same side as the substrate main surface, and a first electrode in contact with the second electrode upper surface and having a first wiring upper surface facing the same side as the substrate main surface. The semiconductor device comprises second main surface wiring having a second wiring main surface facing the same side as the substrate main surface, a first wiring electrode formed on the first wiring main surface, a second wiring electrode formed on the second wiring main surface, a first bonding member bonding the first element electrode and the first wiring electrode, and a second bonding member bonding the second element electrode and the second wiring electrode, wherein an upper surface of the first electrode is recessed toward the inside of the first through electrode, and an upper surface of the second electrode is recessed toward the inside of the second through electrode, and when viewed in the thickness direction, the first wiring electrode is larger than the second wiring electrode.

[0006] A semiconductor device according to another aspect of the present disclosure includes a substrate having a substrate main surface facing a thickness direction, a semiconductor element having an element main surface opposite the substrate main surface, and a first element electrode and a second element electrode formed on the element main surface, a first through-hole electrode penetrating the substrate and having a first electrode upper surface facing the same side as the substrate main surface, a second through-hole electrode penetrating the substrate and having a second electrode upper surface facing the same side as the substrate main surface, a first main surface wiring in contact with the substrate main surface and the first electrode upper surface and having a first wiring upper surface facing the same side as the substrate main surface, and in contact with the second electrode upper surface, The semiconductor device comprises second main surface wiring having a second wiring upper surface facing the same side as the substrate main surface, a first wiring electrode formed on the first wiring upper surface, a second wiring electrode formed on the second wiring upper surface, a first bonding member bonding the first element electrode and the first wiring electrode, and a second bonding member bonding the second element electrode and the second wiring electrode, wherein the first electrode upper surface is recessed toward the inside of the first through electrode, and the second electrode upper surface is recessed toward the inside of the second through electrode, and when viewed from the thickness direction, the first element electrode is larger than the second element electrode. [Effects of the Invention]

[0007] According to one aspect of the present disclosure, it is possible to provide a semiconductor device that can reduce mounting defects of semiconductor elements. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a perspective view of a semiconductor device according to an embodiment, viewed from above. [Figure 2] FIG. 2 is a perspective view of the semiconductor device of the embodiment as viewed from the bottom side. [Figure 3] FIG. 3 is a schematic cross-sectional view showing a semiconductor device according to an embodiment. [Figure 4] FIG. 4 is a schematic plan view showing a semiconductor device according to an embodiment. [Figure 5] FIG. 5 is an enlarged cross-sectional view of a portion of the semiconductor device according to the embodiment. [Figure 6] FIG. 6 is a schematic cross-sectional view for explaining a manufacturing process of a semiconductor device according to one embodiment. [Figure 7] FIG. 7 is a schematic cross-sectional view for explaining a manufacturing process of a semiconductor device according to one embodiment. [Figure 8] FIG. 8 is a schematic cross-sectional view for explaining a manufacturing process of a semiconductor device according to one embodiment. [Figure 9] FIG. 9 is a schematic cross-sectional view illustrating a manufacturing process of a semiconductor device according to one embodiment. [Figure 10] FIG. 10 is a schematic cross-sectional view for explaining a manufacturing process of a semiconductor device according to one embodiment. [Figure 11] FIG. 11 is a schematic cross-sectional view for explaining a manufacturing process of a semiconductor device according to one embodiment. [Figure 12] FIG. 12 is a cross-sectional view showing the state of the solder layer of the substrate and the semiconductor element according to one embodiment. [Figure 13] FIG. 13 is an enlarged cross-sectional view showing the state of the wiring electrodes and solder layers of one embodiment. [Figure 14]FIG. 14 is a cross-sectional view showing a bonded state of a substrate and a semiconductor element according to one embodiment. [Figure 15] FIG. 15 is a schematic cross-sectional view for explaining a manufacturing process of a semiconductor device according to one embodiment. [Figure 16] FIG. 16 is a cross-sectional view showing the state of the solder layer of the substrate and the semiconductor element of the comparative example. [Figure 17] FIG. 17 is a cross-sectional view showing a bonding state of a substrate and a semiconductor element of a comparative example. [Figure 18] FIG. 18 is a schematic cross-sectional view for explaining a manufacturing process of a semiconductor device according to one embodiment. [Figure 19] FIG. 19 is a schematic cross-sectional view for explaining a manufacturing process of a semiconductor device according to one embodiment. [Figure 20] FIG. 20 is a schematic cross-sectional view for explaining a manufacturing process of a semiconductor device according to one embodiment. [Figure 21] FIG. 21 is a schematic cross-sectional view for explaining a manufacturing process of a semiconductor device according to one embodiment. [Figure 22] FIG. 22 is a schematic cross-sectional view for explaining a manufacturing process of a semiconductor device according to one embodiment. [Figure 23] FIG. 23 is a schematic cross-sectional view for explaining a manufacturing process of a semiconductor device according to one embodiment. [Figure 24] FIG. 24 is a partially enlarged cross-sectional view showing a semiconductor device according to a modified example. [Figure 25] FIG. 25 is a partially enlarged cross-sectional view showing a semiconductor device according to a modified example. [Figure 26] FIG. 26 is a cross-sectional view showing a semiconductor device according to a modified example. [Figure 27] FIG. 27 is a cross-sectional view showing the state of the wiring electrodes and the solder layers. [Figure 28] FIG. 28 is a cross-sectional view showing a semiconductor device according to a modified example. [Figure 29] FIG. 29 is a cross-sectional view showing the state of the wiring electrodes and the solder layers. [Figure 30] FIG. 30 is a cross-sectional view showing a semiconductor device according to a modified example. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, embodiments and modified examples will be described with reference to the drawings. The embodiments and modified examples shown below are merely examples of configurations and methods for embodying the technical ideas, and are not intended to limit the materials, shapes, structures, arrangements, dimensions, etc. of the components to those described below. Various modifications can be made to the following embodiments and modified examples. Furthermore, the following embodiments and modified examples can be combined with each other within the scope of technical compatibility.

[0010] In this specification, unless otherwise specified, "A is formed above B" includes a configuration in which A is formed directly on B, and a configuration in which A is formed above B via an intervening object provided between A and B. Similarly, "a state in which a component C is provided between components A and B" includes a case in which components A and C, or components B and C, are directly connected, as well as a case in which components A and C, or components B and C, are indirectly connected via another component that does not affect the electrical connection state.

[0011] The statement "at least one of A and B" in this specification should be understood to mean "A only, or B only, or both A and B." (Configuration of semiconductor device) A semiconductor device 1A according to one embodiment will be described with reference to FIGS.

[0012] 1 and 2 are perspective views showing the appearance of semiconductor device 1A, where FIG. 1 is a perspective view of semiconductor device 1A viewed from the top side and FIG. 2 is a perspective view of semiconductor device 1A viewed from the bottom side. FIG. 3 is a cross-sectional view of semiconductor device 1A. FIG. 4 is a schematic plan view of semiconductor device 1A viewed from the bottom side. FIG. 5 is an enlarged cross-sectional view of a portion of semiconductor device 1A. FIGS. 6 to 15 and 18 to 23 are cross-sectional views showing an example of a manufacturing process of a semiconductor device. FIGS. 16 and 17 are cross-sectional views showing a step in a manufacturing process of a semiconductor device that is a comparative example to semiconductor device 1A of one embodiment.

[0013] The semiconductor device 1A shown in these figures is a device that is surface-mounted on the circuit board of various electronic devices. For ease of explanation, the thickness direction of the semiconductor device 1A will be referred to as the thickness direction Z. Also, the direction along one side of the semiconductor device 1A that is perpendicular to the thickness direction Z (the left-right direction in the plan view) will be referred to as the first direction X. Also, the direction that is perpendicular to both the thickness direction Z and the first direction X of the semiconductor device 1A (the up-down direction in the plan view) will be referred to as the second direction Y.

[0014] 1 and 2, the semiconductor device 1A has a rectangular plate shape. The semiconductor device 1A has a substrate 10, a sealing resin 70, a first external conductive film 81, and a second external conductive film 82. As shown in FIGS. 3 to 5, the semiconductor device 1A has a first wiring portion 21, a second wiring portion 31, a semiconductor element 40, a first bonding member 61, and a second bonding member 62. The semiconductor element 40 is connected to the first wiring portion 21 and the second wiring portion 31 by the first bonding member 61 and the second bonding member 62.

[0015] As shown in Fig. 3, the substrate 10 is a support member that serves as the base of the semiconductor device 1A. The semiconductor element 40 is mounted on the substrate 10. As shown in Fig. 4, the shape of the substrate 10 is rectangular when viewed in the thickness direction Z, with the length of the side in the first direction X being equal to the length of the side in the second direction Y. Note that the shape of the substrate 10 and the length of each side may be changed as appropriate.

[0016] The substrate 10 has a substrate main surface 101, a substrate back surface 102, and multiple substrate side surfaces 103. The substrate main surface 101 and the substrate back surface 102 face in opposite directions in the thickness direction Z. The substrate main surface 101 is flat. The substrate back surface 102 is flat. Each substrate side surface 103 intersects with the substrate main surface 101 and the substrate back surface 102. The substrate side surface 103 faces either the first direction X or the second direction Y. Each substrate side surface 103 is flat. Each substrate side surface 103 intersects with the substrate main surface 101 and the substrate back surface 102, and in this embodiment, is perpendicular to them.

[0017] The substrate 10 is made of, for example, an electrically insulating material. For example, a synthetic resin containing an epoxy resin as a main component can be used as this material. The synthetic resin according to this embodiment is an epoxy resin containing a filler. The filler is made of, for example, SiO2. The material constituting the substrate 10 is colored, for example, black. Cutting marks are formed on the surfaces of the substrate 10, namely, the main surface 101, the back surface 102, and the side surface 103. The filler contained in the material of the substrate 10 is exposed on the surfaces of the substrate 10, namely, the main surface 101, the back surface 102, and the side surface 103.

[0018] The substrate 10 has a plurality of first through holes 11 penetrating the substrate 10 in the thickness direction Z from the substrate main surface 101 to the substrate back surface 102. As shown in FIG. 4 , in this embodiment, the substrate 10 has four first through holes 11 on each side of the substrate 10. The first through holes 11 are, for example, rectangular when viewed from the thickness direction Z. The shape of the first through holes 11 may be circular or polygonal. Each first through hole 11 extends to the substrate side surface 103. That is, each first through hole 11 opens at the substrate side surface 103.

[0019] The substrate 10 also has one second through hole 12 that penetrates the substrate 10 in the thickness direction Z from the substrate main surface 101 to the substrate back surface 102. As shown in FIGS. 3 and 4, the second through hole 12 is formed in the center of the substrate 10. The second through hole 12 is also formed at a position that overlaps with the semiconductor element 40 when viewed from the thickness direction Z. The second through hole 12 has, for example, a rectangular shape when viewed from the thickness direction Z.

[0020] 3 to 5, the semiconductor device 1A of this embodiment has a plurality of first wiring portions 21 and one second wiring portion 31. As shown in FIGS. 3 and 4, the first wiring portion 21 of this embodiment is formed so as to extend from a portion overlapping the semiconductor element 40 in the thickness direction Z to the substrate side surface 103 of the substrate 10. The second wiring portion 31 of this embodiment is arranged so as to overlap the semiconductor element 40 in the thickness direction Z.

[0021] The first wiring portion 21 includes a first through electrode 22, a first main surface wiring 23, and a first wiring electrode 24. The first through electrode 22 is disposed in the first through hole 11. As shown in Fig. 5 , the first through electrode 22 has an upper surface 221, a lower surface 222, and side surfaces 223 and 224. The upper surface 221 and the lower surface 222 face opposite each other in the thickness direction Z. The side surfaces 223 and 224 intersect with the upper surface 221 and the lower surface 222.

[0022] The upper surface 221 of the first through electrode 22 is recessed toward the inside of the first through electrode 22. As shown in FIG. 5, the upper surface 221 has an edge portion adjacent to the inner wall surface 113 of the first through hole 11 and an inner portion closer to the center of the upper surface 221 than the edge portion. The inner portion is a generally flat surface. The inner portion extends to the substrate side surface 103 of the substrate 10. The edge portion is formed to recess toward the inside of the first through electrode 22 so as to be located closer to the substrate back surface 102 than the substrate main surface 101 as it moves away from the inner wall surface 113 of the first through hole 11. Note that the upper surface 221 may be formed so that the entire upper surface 221 is a flat surface, that is, so that the position from the inner portion to the edge portion 221a is the same in the thickness direction Z. The depth of the upper surface 221 of the first through electrode 22 with respect to the substrate main surface 101 is, for example, 1 μm.

[0023] A lower surface 222 of the first through electrode 22 is flush with the rear surface 102 of the substrate 10. This lower surface 222 is an exposed surface exposed from the rear surface 102 of the substrate 10. The lower surface 222 of the first through electrode 22 may not be flush with the rear surface 102 of the substrate 10. A side surface 223 of the first through electrode 22 is in contact with the inner wall surface 113 of the first through hole 11. A side surface 224 of the first through electrode 22 is exposed from the side surface 103 of the substrate 10. The first through electrode 22 is made of an electrically conductive material. Examples of materials that can be used for the first through electrode 22 include Cu (copper) and a Cu alloy.

[0024] The first main surface wiring 23 extends from the upper surface 221 of the first through electrode 22 to the substrate main surface 101 of the substrate 10. More specifically, as shown in FIGS. 3 to 5 , the first main surface wiring 23 extends to the substrate main surface 101 that overlaps with the semiconductor element 40 when viewed from the thickness direction Z. The first main surface wiring 23 includes a connection wiring portion 23A connected to the upper surface 221 of the first through electrode 22, and an on-substrate wiring portion 23B that contacts the substrate main surface 101 of the substrate 10.

[0025] The first main surface wiring 23 is made of an electrically conductive material and is electrically connected to the first through electrode 22. The first main surface wiring 23 has an upper surface 231, a lower surface 232, and side surfaces 233 and 234. The upper surface 231 and the lower surface 232 face opposite each other in the thickness direction Z. The side surfaces 233 and 234 face in a direction perpendicular to the thickness direction Z. The upper surface 231 of the first main surface wiring 23 faces the same direction as the substrate main surface 101 of the substrate 10. The lower surface 232 of the first main surface wiring 23 faces the same direction as the substrate rear surface 102 of the substrate 10. A portion of the lower surface 232 contacts the substrate main surface 101 of the substrate 10, and another portion of the lower surface 232 is connected to the upper surface 221 of the first through electrode 22. The multiple side surfaces 233 contact the sealing resin 70. 5, the side surface 234 facing the first direction X is an exposed side surface exposed from the resin side surface 703 of the sealing resin 70. The thickness of the first main surface wiring 23 is, for example, not less than 5 μm and not more than 30 μm.

[0026] As shown in FIG. 5, the first main surface wiring 23 has a metal layer 25 and a conductive layer 26. The metal layer 25 and the conductive layer 26 are stacked in this order on the substrate main surface 101 of the substrate 10. The metal layer 25 is composed of a first layer, which is mainly composed of Ti (titanium) and is in contact with the substrate main surface 101 of the substrate 10 and the upper surface 221 of the first through electrode 22, and a second layer, which is mainly composed of Cu and is in contact with the first layer. The metal layer 25 is formed as a seed layer for forming the conductive layer 26. The conductive layer 26 is mainly composed of Cu, for example.

[0027] 3 and 5, the first wiring electrode 24 is formed on the upper surface 231 of the first main surface wiring 23. The first main surface wiring 23 has a connection wiring portion 23A connected to the first through electrode 22, and an on-substrate wiring portion 23B in contact with the substrate main surface 101. The first wiring electrode 24 is formed on the upper surface 231 of the on-substrate wiring portion 23B.

[0028] 3 and 4, the first wiring electrode 24 is formed in a region overlapping with the semiconductor element 40 in the thickness direction Z. The first wiring electrode 24 is also formed in a portion of the first main surface wiring 23 overlapping with the substrate main surface 101 of the substrate 10 in the thickness direction Z. As shown in Fig. 4, the first wiring electrode 24 is formed in a circular shape when viewed from the thickness direction Z. The first wiring electrode 24 is made of, for example, Ni.

[0029] The second wiring portion 31 is disposed in the second through hole 12 that overlaps with the semiconductor element 40 when viewed from the thickness direction Z. That is, the second wiring portion 31 penetrates the substrate 10. The second wiring portion 31 is used, for example, to dissipate heat from the semiconductor element 40. The second wiring portion 31 dissipates heat generated from the semiconductor element 40 to the rear surface 102 side of the substrate 10.

[0030] As shown in FIG. 4 , the second wiring portion 31 is disposed so as to overlap the central portion of the semiconductor element 40. The substrate 10 has a second through hole 12 that overlaps the central portion of the semiconductor element 40. The position of the second wiring portion 31 can be changed as appropriate. For example, it is preferable to dispose the second through hole 12, i.e., the second wiring portion 31, so that the second through hole 12 and the second wiring portion 31 overlap a region of the semiconductor element 40 that includes a portion that generates the highest heat. For example, the amount of heat generated in the semiconductor element 40 is large in a portion where a power transistor is formed. It is preferable to dispose the second through hole 12 and the second wiring portion 31 so that the second through hole 12 and the second wiring portion 31 overlap a region of the semiconductor element 40 that includes a portion of the element that generates the largest amount of heat.

[0031] As shown in FIG. 3, the second wiring portion 31 includes a second through electrode 32, a second main surface wiring 33, and a second wiring electrode . The second through electrode 32 is disposed in the second through hole 12. The second through electrode 32 has an upper surface 321, a lower surface 322, and a plurality of side surfaces 323. The upper surface 321 and the lower surface 322 face opposite each other in the thickness direction Z. The side surfaces 323 face in a direction intersecting the thickness direction Z and intersect with the upper surface 321 and the lower surface 322.

[0032] The upper surface 321 of the second through electrode 32 is recessed toward the inside of the second through electrode 32. As shown in FIG. 5, the upper surface 321 has an edge portion 321a adjacent to the inner wall surface 123 of the second through hole 12 and an inner portion 321b located closer to the center of the upper surface 321 than the edge portion 321a. The inner portion 321b is a generally flat surface. The edge portion 321a is recessed toward the inside of the second through electrode 32 as it moves away from the inner wall surface 123 of the second through hole 12, so that it is positioned closer to the substrate back surface 102 than the substrate main surface 101. Note that the entire upper surface 321 may be a flat surface, that is, the upper surface 321 may be formed so that the position from the inner portion 321b to the edge portion 321a is the same in the thickness direction Z. The depth of the upper surface 321 of the second through electrode 32 with respect to the substrate main surface 101 is, for example, 1 μm.

[0033] The lower surface 322 of the second through electrode 32 is flush with the rear surface 102 of the substrate 10. This lower surface 322 is an exposed surface exposed from the rear surface 102 of the substrate 10. The lower surface 322 of the second through electrode 32 may not be flush with the rear surface 102 of the substrate 10. Furthermore, the side surface 323 of the second through electrode 32 is in contact with the inner wall surface 123 of the second through hole 12. The second through electrode 32 is made of an electrically conductive material. The second through electrode 32 is formed, for example, of a plated metal. The second through electrode 32 is made, for example, of the same material as the first through electrode 22. The second through electrode 32 can be made of, for example, Cu, a Cu alloy, or the like.

[0034] The second main surface wiring 33 is connected to the upper surface 321 of the second through electrode 32. The second main surface wiring 33 has a rectangular shape when viewed in the thickness direction Z. The second main surface wiring 33 has an upper surface 331, a lower surface 332, and multiple side surfaces 333. The upper surface 331 and the lower surface 332 face opposite each other in the thickness direction Z. The side surfaces 333 intersect with the upper surface 331 and the lower surface 332. The upper surface 331 of the second main surface wiring 33 faces the same direction as the upper surface 321 of the second through electrode 32. The lower surface 332 of the second main surface wiring 33 faces the upper surface 321 of the second through electrode 32 and is in contact with the upper surface 321.

[0035] The thickness of the second main surface wiring 33 is the same as the thickness of the first main surface wiring 23. The second main surface wiring 33 is formed to be larger than the second through electrode 32 when viewed in the thickness direction Z. The second main surface wiring 33 has a connection wiring portion 33A connected to the upper surface 321 of the second through electrode 32, and an extension portion 33B extending outward beyond the side surface 323 of the second through electrode 32. The extension portion 33B is a portion that does not overlap with the second through electrode 32 in the thickness direction Z. In this embodiment, the extension portion 33B is annular. A lower surface 332 of the extension portion 33B contacts the substrate main surface 101.

[0036] As shown in FIG. 5 , the second main surface wiring 33 has a metal layer 35 and a conductive layer 36. The metal layer 35 and the conductive layer 36 are stacked in this order on the upper surface 321 of the second through electrode 32. The metal layer 35 is made up of a first layer in contact with the upper surface 321 of the second through electrode 32 and a second layer in contact with the first layer. The first layer is a layer containing, for example, Ti as its main component, and the second layer is a layer containing, for example, Cu as its main component. The metal layer 35 is formed as a seed layer for forming the conductive layer 36. The conductive layer 36 is containing, for example, Cu as its main component. The configuration of this second main surface wiring 33 is the same as the configuration of the first main surface wiring 23. The second main surface wiring 33 is formed simultaneously with the first main surface wiring 23.

[0037] As shown in FIG. 3, the second wiring electrode 34 is formed on the upper surface 331 of the second main surface wiring 33. As shown in FIG. 4, the semiconductor device 1A of this embodiment has two second wiring electrodes 34. The number of second wiring electrodes 34 may be one or three or more. As shown in FIGS. 3 and 4, the second wiring electrode 34 is formed in a region overlapping with the semiconductor element 40 in the thickness direction Z. As shown in FIG. 3, the second wiring electrode 34 is formed on the upper surface 331 of the second main surface wiring 33 that overlaps with the second through electrode 32 in the thickness direction Z. That is, the second wiring electrode 34 is formed on the upper surface 331 of the connection wiring portion 33A of the second main surface wiring 33 that is connected to the upper surface 321 of the second through electrode 32.

[0038] 4, the second wiring electrode 34 is formed in a circular shape when viewed from the thickness direction Z. The thickness of the second wiring electrode 34 is the same as the thickness of the first wiring electrode 24. For example, the first wiring electrode 24 and the second wiring electrode 34 are formed in the same process. The second wiring electrode 34 is made of, for example, Ni.

[0039] 3 to 5, the first wiring electrode 24 and the second wiring electrode 34 have different sizes when viewed in the thickness direction Z. In this embodiment, the first wiring electrode 24 is formed to be larger than the second wiring electrode 34. As shown in FIG. 5, when the diameter of the first wiring electrode 24 is D1 and the diameter of the second wiring electrode 34 is D2, the diameter D2 of the second wiring electrode 34 is smaller than the diameter D1 of the first wiring electrode 24.

[0040] As shown in Fig. 4, the semiconductor element 40 has a rectangular shape when viewed in the thickness direction Z. As shown in Figs. 3 and 4, the semiconductor element 40 has an element main surface 401 and an element back surface 402 facing opposite each other in the thickness direction Z, and a plurality of element side surfaces 403 facing in a direction perpendicular to the thickness direction Z. The element side surfaces 403 intersect with the element main surface 401 and the element back surface 402. The element main surface 401 faces the substrate main surface 101 of the substrate 10. The element back surface 402 faces in the same direction as the substrate main surface 101 of the substrate 10.

[0041] The semiconductor element 40 is an integrated circuit (IC) such as an LSI (Large Scale Integration). The semiconductor element 40 may also be a voltage control element such as an LDO (Low Drop Out), an amplifying element such as an operational amplifier, or a discrete semiconductor element such as a diode or various sensors. For example, in the case of an LSI, the element main surface 401 is the surface on which components required for the function of the semiconductor element 40 are formed. The semiconductor element 40 is not limited to an element having multiple components formed thereon, but may also be an element having a single component formed thereon, such as a chip capacitor or a chip inductor, or an element having components formed on a substrate other than a semiconductor. In this embodiment, the semiconductor element 40 is an LSI.

[0042] The semiconductor element 40 has first connection pads 41 and second connection pads 51 for mounting on the element main surface 401 side. As shown in FIG. 4, the first connection pads 41 are arranged along each element side surface 403. The second connection pads 51 are arranged inside the multiple first connection pads 41. The multiple first connection pads 41 are terminals for inputting and outputting signals related to the operation of the semiconductor element 40. The second connection pads 51 are, for example, terminals that do not affect the electrical characteristics of the semiconductor element 40. These terminals may be terminals insulated from the first connection pads 41, ground terminals, etc.

[0043] As shown in FIG. 3 , the semiconductor element 40 is disposed with its element principal surface 401 facing the substrate principal surface 101 of the substrate 10. The first connection pads 41 of the semiconductor element 40 are disposed opposite the first wiring electrodes 24 on the upper surface 231 of the first main surface wiring 23. The second connection pads 51 of the semiconductor element 40 are disposed opposite the second wiring electrodes 34 on the upper surface 331 of the second main surface wiring 33. The first connection pads 41 are connected to the first wiring electrodes 24 by first bonding members 61. The second connection pads 51 are connected to the second wiring electrodes 34 by second bonding members 62. In this way, the semiconductor element 40 is flip-chip mounted with the element principal surface 401 facing the substrate principal surface 101 of the substrate 10. Therefore, the element principal surface 401 can be said to be an element mounting surface for mounting the semiconductor element 40.

[0044] As shown in FIG. 5, the first connection pad 41 includes a first electrode pad 42 and a first element electrode 43. The first electrode pad 42 is exposed through openings 451 and 452 in a protective film 45 covering the element principal surface 401 of the semiconductor element 40. The first electrode pad 42 is made of, for example, Al (aluminum). The first element electrode 43 is connected to the first electrode pad 42. The first element electrode 43 includes a conductive layer 43A and a barrier layer 43B. The conductive layer 43A is made of, for example, Cu or a Cu alloy. The conductive layer 43A may include a seed layer. The seed layer is made of, for example, Ti / Cu. The barrier layer 43B is made of Ni, an alloy containing Ni, or multiple metal layers containing Ni. The barrier layer 43B can be made of, for example, Ni, Pd, Au, or an alloy containing two or more of these metals. The protective film 45 is made of, for example, polyimide resin.

[0045] The second connection pad 51 has the same configuration as the first connection pad 41. More specifically, the second connection pad 51 has a second electrode pad 52 and a second element electrode 53. The second electrode pad 52 is exposed through an opening in the protective film 45 that covers the element principal surface 401 of the semiconductor element 40. The second electrode pad 52 is made of, for example, Al. The second element electrode 53 is connected to the second electrode pad 52. The second element electrode 53 includes a conductive layer 53A and a barrier layer 53B. The conductive layer 53A is made of, for example, Cu or a Cu alloy. The conductive layer 53A may include a seed layer. The seed layer is made of, for example, Ti / Cu. The barrier layer 53B is made of Ni, an alloy containing Ni, or multiple metal layers containing Ni. The barrier layer 53B can be made of, for example, Ni, Pd, Au, or an alloy containing two or more of these metals.

[0046] The first element electrode 43 is formed, for example, in a circular shape when viewed from the thickness direction. The second element electrode 53 is formed, for example, in a circular shape when viewed from the thickness direction. As shown in FIG. 5 , the diameter D3 of the first element electrode 43 is the same as the diameter D4 of the second element electrode 53. In this embodiment, the diameter D1 of the first wiring electrode 24 is larger than the diameter D3 of the first element electrode 43. The diameter D2 of the second wiring electrode 34 is the same as the diameter D4 of the second element electrode 53. The shapes of the first element electrode 43 and the second element electrode 53 when viewed from the thickness direction may be changed to any shape, such as a rectangle, a polygon with pentagons or more sides, or an ellipse. Furthermore, the first element electrode 43 and the second element electrode 53 may have different shapes.

[0047] The first bonding member 61 and the second bonding member 62 bond the semiconductor element 40 to the first wiring portion 21 and the second wiring portion 31. The first bonding member 61 bonds the first wiring electrode 24 of the first main surface wiring 23 to the first element electrode 43 of the semiconductor element 40. The second bonding member 62 bonds the second wiring electrode 34 of the second main surface wiring 33 to the second element electrode 53 of the semiconductor element 40.

[0048] 5, the first bonding members 61 are formed in a generally trapezoidal shape in a cross section along the thickness direction Z, i.e., in a cross section perpendicular to the substrate main surface 101. The second bonding members 62 are formed in a generally rectangular shape (parallelogram shape) in a cross section perpendicular to the substrate main surface 101. The first bonding members 61 and the second bonding members 62 are made of Sn or an alloy containing Sn. This alloy is, for example, a Sn—Ag (silver)-based alloy, a Sn—Sb (antimony)-based alloy, or the like.

[0049] 3, the sealing resin 70 is formed to contact the substrate main surface 101 of the substrate 10 and cover the semiconductor element 40. The sealing resin 70 is filled between the substrate 10 and the semiconductor element 40. As a result, the sealing resin 70 covers the substrate main surface 101 of the substrate 10, the first wiring portion 21, and the second wiring portion 31. The sealing resin 70 also covers the element main surface 401, element side surface 403, and element back surface 402 of the semiconductor element 40. Furthermore, the sealing resin 70 covers the first bonding members 61 and second bonding members 62 that bond the semiconductor element 40 to the first wiring portion 21 and the second wiring portion 31.

[0050] The sealing resin 70 overlaps the substrate 10 when viewed from the thickness direction Z. The sealing resin 70 has a resin upper surface 701 facing in the same direction as the substrate main surface 101 of the substrate 10, and a resin side surface 703 facing in the same direction as the substrate side surface 103.

[0051] The sealing resin 70 has a first resin portion 70A, which is a portion on the substrate 10 side in the thickness direction Z, and a second resin portion 70B, which is a portion on the resin upper surface 701 side. The first resin portion 70A has a first resin side surface 703a that constitutes a part of the resin side surface 703, and the second resin portion 70B has a second resin side surface 703b that constitutes a part of the resin side surface 703. When viewed from the thickness direction Z, the first resin portion 70A is the same size as the substrate 10. When viewed from the thickness direction Z, the second resin portion 70B is formed to be larger than the first resin portion 70A. The second resin side surface 703b is located further outward than the first resin side surface 703a. Thus, the sealing resin 70 has a step 71 recessed inward of the sealing resin 70 due to the difference in size between the first resin portion 70A and the second resin portion 70B. As shown in FIG. 2, the step 71 is provided throughout the entire circumferential direction of the sealing resin 70.

[0052] The sealing resin 70 is made of, for example, a resin having electrical insulating properties. As this resin, for example, a synthetic resin containing epoxy resin as a main component can be used. The sealing resin 70 is colored, for example, black. The material and shape of the sealing resin 70 are not limited.

[0053] The first external conductive film 81 has a first conductive film 81A and a second conductive film 81B. The first conductive film 81A covers the lower surface 222 of the first through electrode 22. The second conductive film 81B covers the side surface 224 of the first through electrode 22 and the side surface 234 of the first main surface wiring 23. The first external conductive film 81, which has the first conductive film 81A and the second conductive film 81B, serves as an external connection terminal of the semiconductor device 1A. The first external conductive film 81 is composed of, for example, a plurality of metal layers stacked on top of each other. The metal layers are, for example, Ni layers and Au layers. The material of the first external conductive film 81 is not limited, but may be, for example, a stack of Ni layers, Pd layers, and Au layers, or Sn.

[0054] When this semiconductor device 1A is mounted on a circuit board, the solder connecting the first external conductive film 81 to the connection pad of the circuit board is interposed between the first conductive film 81A and the connection pad, and also adheres to the second conductive film 81B. In other words, the solder that has become liquid through the reflow process creeps up the second conductive film 81B and forms a solder fillet between the second conductive film 81B and the connection pad. In this way, the semiconductor device 1A makes it easier to form solder fillets. These solder fillets increase the solder joint area, further improving connection strength. Furthermore, the solder fillets allow the soldering condition of the semiconductor device 1A to be confirmed from the outside.

[0055] The second external conductive film 82 is formed so as to cover the lower surface 322 of the second through electrode 32 exposed from the substrate 10. The second external conductive film 82 serves as a terminal for dissipating heat generated in the semiconductor device 1A to the outside. The second external conductive film 82 is made of, for example, the same material as the first external conductive film 81. The second external conductive film 82 is made of, for example, a plurality of metal layers stacked on top of each other. The metal layers are, for example, Ni layers and Au layers. The material of the second external conductive film 82 is not limited, but may be, for example, a stack of Ni layers, Pd layers, and Au layers, or Sn.

[0056] (Semiconductor device manufacturing process) An example of a method for manufacturing a semiconductor device 1A according to this embodiment of the present disclosure will be described with reference to Figures 6 to 14 and Figures 17 to 23. Each referenced figure shows the area in which one semiconductor device 1A is formed. The definitions of the directions shown in each figure are the same as those shown in Figures 1 to 5.

[0057] First, as shown in FIG. 6, the manufacturing method of the semiconductor device 1A includes a step of preparing a support substrate 900. The support substrate 900 is made of, for example, a single crystal Si material. The support substrate 900 has a main surface 900s and a bottom surface 900r that face opposite each other in the thickness direction Z. Note that the support substrate 900 may also be made of a synthetic resin material such as epoxy resin.

[0058] Next, terminal pillars 922, 932 are formed on the main surface 900s of the support substrate 900. The terminal pillars 922, 932 are made of, for example, Cu or an alloy containing Cu as a main component. The terminal pillars 922, 932 are formed by, for example, electrolytic plating. The terminal pillar 922 will become the first through electrode 22 in the semiconductor device 1A described above, and the terminal pillar 932 will become the second through electrode 32 in the semiconductor device 1A described above.

[0059] The terminal pillars 922, 932 are formed, for example, through a process of forming a seed layer, a process of forming a mask on the seed layer by photolithography, and a process of forming a plating layer in contact with the seed layer. For example, a seed layer is formed on the main surface 900s of the support substrate 900 by sputtering. Next, the seed layer is covered with a photosensitive resist layer, which is then exposed and developed to form a mask with openings. Next, the terminal pillars 922, 932 are formed by depositing a plating metal on the surface of the seed layer exposed from the mask by electrolytic plating using the seed layer as a conductive path. After the terminal pillars 922, 932 are formed, the mask is removed. The terminal pillars 922, 932 may also be formed using Cu columnar materials.

[0060] 7, the manufacturing method of the semiconductor device 1A includes a step of forming a base material 910 that contacts a main surface 900s of a support substrate 900 and covers the terminal pillars 922, 932. The base material 910 is formed so as to cover the top and side surfaces of the terminal pillars 922, 932. The material of the base material 910 may be the material that constitutes the substrate 10 shown in FIGS. 1 to 3 and 5. In this embodiment, the material of the base material 910 may be a synthetic resin that contains an epoxy resin or the like as a main component.

[0061] As shown in FIG. 8 , the manufacturing method of the semiconductor device 1A includes a step of grinding a portion of the base material 910 and the terminal pillars 922 and 932 to form the first through-hole electrode 22 and the second through-hole electrode 32. In grinding the base material 910, the base material 910 is formed to have a thickness greater than that of the substrate 10 shown in FIGS. 3 and 5 . By this grinding, the upper surfaces 221 and 321 of the first through-hole electrode 22 and the second through-hole electrode 32 are exposed on the base material main surface 9101 of the base material 910. Then, burrs on the terminal pillars 922 and 932 caused by grinding are removed from the base material main surface 9101 of the base material 910 by etching, for example, wet etching. By this etching, the upper surfaces 221 and 321 of the first through-hole electrode 22 and the second through-hole electrode 32 are recessed from the base material main surface 9101 of the base material 910 toward the inside of the first through-hole electrode 22 and the second through-hole electrode 32.

[0062] As shown in FIG. 9, the method for manufacturing the semiconductor device 1A includes a step of forming first main surface wiring 23 and second main surface wiring 33. The process of forming the first main surface wiring 23 and the second main surface wiring includes a process of forming a seed layer and a process of forming a conductive layer. The seed layer, for example, forms the metal layer 25 of the first main surface wiring 23 and the metal layer 35 of the second main surface wiring 33 shown in FIG. 5. The conductive layer, for example, forms the conductive layer 26 of the first main surface wiring 23 and the conductive layer 36 of the second main surface wiring 33 shown in FIG. 5.

[0063] First, a seed layer that will become the metal layers 25 and 35 is formed by, for example, sputtering. The seed layer includes, for example, a first layer primarily composed of Ti and a second layer primarily composed of Cu. The seed layer is formed so as to cover the substrate main surface 9101 of the substrate 910 and the upper surfaces 221 and 321 of the first through-hole electrode 22 and the second through-hole electrode 32. Next, a mask with openings is formed by, for example, photolithography using a photosensitive resist layer. Next, a plating metal is deposited on the surface of the seed layer exposed through the openings in the mask by, for example, electrolytic plating using the seed layer as a conductive path, to form a conductive layer. The seed layer is removed at an appropriate time.

[0064] As shown in FIG. 10 , the manufacturing method of the semiconductor device 1A includes the steps of forming the first wiring electrodes 24 and the second wiring electrodes 34, and the first-substrate-side solder layer 27 and the second-substrate-side solder layer 37. The first wiring electrodes 24 and the second wiring electrodes 34 are formed, for example, by electrolytic plating. A mask 902 is formed on a substrate main surface 9101 of a substrate 910. The mask 902 is formed, for example, by photolithography using a photosensitive resist layer. The mask 902 has an opening 9021 that exposes a portion of the upper surface 231 of the first main-surface wiring 23 and an opening 9022 that exposes a portion of the upper surface 331 of the second main-surface wiring 33. The opening 9021 for forming the first wiring electrodes 24 is larger than the opening 9022 for forming the second wiring electrodes 34. Then, Ni is deposited as a plating metal on the upper surface 231 of the first main surface wiring 23 and the upper surface 331 of the second main surface wiring 33 to form the first wiring electrode 24 and the second wiring electrode 34.

[0065] Next, a first-substrate-side solder layer 27 is formed on the first wiring electrode 24, and a second-substrate-side solder layer 37 is formed on the second wiring electrode 34. The first-substrate-side solder layer 27 and the second-substrate-side solder layer 37 become part of the first bonding member 61 and the second bonding member 62 shown in Figures 3 and 5. The first-substrate-side solder layer 27 and the second-substrate-side solder layer 37 are formed by, for example, electrolytic plating.

[0066] The first-substrate-side solder layer 27 is formed by depositing an alloy containing Sn and Ag as a plating metal on the first wiring electrode 24. The second-substrate-side solder layer 37 is formed by depositing an alloy containing Sn and Ag as a plating metal on the second wiring electrode 34. In this process, the current density of the electrolytic plating differs depending on the opening diameters of the openings 9021 and 9022 in the mask 902, and the height of the second wiring electrode 34 and the second-substrate-side solder layer 37 formed in the opening 9022 can be made higher than the height of the first wiring electrode 24 and the first-substrate-side solder layer 27 formed in the opening 9021.

[0067] 11, the manufacturing method of semiconductor device 1A includes a step of performing a flow treatment. The flow treatment flattens the surfaces of first substrate side solder layer 27 and second substrate side solder layer 37. The flow treatment makes the surfaces of first substrate side solder layer 27 and second substrate side solder layer 37 arc-shaped in cross section along thickness direction Z.

[0068] 11 and 12 show the states of the first-substrate-side solder layer 27 and the second-substrate-side solder layer 37 after flow processing. As shown in Fig. 12, the uppermost point (vertex) P27 of the first-substrate-side solder layer 27 and the uppermost point (vertex) P37 of the second-substrate-side solder layer 37 are at the same position in the thickness direction Z. As shown in Fig. 12, the diameters of the first wiring electrode 24 and the second wiring electrode 34, i.e., the sizes of the openings 9021 and 9022 in the mask 902, are set so that the position of the vertex P27 of the first-substrate-side solder layer 27 and the position of the uppermost point P37 of the second-substrate-side solder layer 37 are at the same position in the thickness direction Z after flow processing.

[0069] More specifically, the upper surface 221 of the first through electrode 22 is recessed toward the inside of the first through electrode 22 from the substrate main surface 101 of the substrate 10. The thickness of the first wiring electrode 24 and the thickness of the second wiring electrode 34 are the same. Therefore, the difference DT1 in the thickness direction Z between the upper surface 241 of the first wiring electrode 24 and the upper surface 341 of the second wiring electrode 34 is the same as the difference DT2 between the upper surface 221 of the first through electrode 22 and the substrate main surface 101 of the substrate 10.

[0070] A height T12 of the second wiring electrode 34 and the second-substrate-side solder layer 37 is greater than a height T11 of the first wiring electrode 24 and the first-substrate-side solder layer 27. The height T11 of the first wiring electrode 24 and the first-substrate-side solder layer 27 is the distance along the thickness direction Z from the upper surface 231 of the first main-side wiring 23 to the apex P27 of the first-substrate-side solder layer 27. The height T11 of the second wiring electrode 34 and the second-substrate-side solder layer 37 is the distance from the upper surface 331 of the second main-side wiring 33 to the apex P37 of the second-substrate-side solder layer 37.

[0071] The first wiring electrode 24 and the first-substrate-side solder layer 27, and the second wiring electrode 34 and the second-substrate-side solder layer 37 are formed so as to absorb the difference DT1 between the upper surface 231 of the first main-surface wiring 23 and the upper surface 331 of the second main-surface wiring 33. In other words, the difference between the height T11 of the first wiring electrode 24 and the first-substrate-side solder layer 27 and the height T12 of the second wiring electrode 34 and the second-substrate-side solder layer 37 is made equal to the difference DT1 between the upper surface 231 of the first main-surface wiring 23 and the upper surface 331 of the second main-surface wiring 33, i.e., the difference DT2 between the substrate main surface 101 of the substrate 10 and the upper surface 321 of the second through electrode 32.

[0072] 13 to 15, the method for manufacturing the semiconductor device 1A includes a step of mounting a semiconductor element 40. The step of mounting the semiconductor element 40 includes a step of flip-chip mounting the semiconductor element 40 shown in FIGS. 13 and 14, and a reflow step shown in FIG.

[0073] 13, the semiconductor element 40 is placed with the element main surface 401 facing the base material 910. The semiconductor element 40 has a first element-side solder layer 44 and a second element-side solder layer 54 formed on the first element electrode 43 and the second element electrode 53. The first element-side solder layer 44 and the second element-side solder layer 54 become part of the first bonding member 61 and the second bonding member 62 shown in FIGS.

[0074] The first element-side solder layer 44 and the second element-side solder layer 54 are formed by electroplating and flow treatment. The first element-side solder layer 44 is formed by depositing an alloy containing Sn and Ag as a plating metal on the lower surface 431 of the first element electrode 43. The second element-side solder layer 54 is formed by depositing an alloy containing Sn and Ag as a plating metal on the lower surface 531 of the second element electrode 53. Then, flow treatment is performed to smooth the surfaces of the first element-side solder layer 44 and the second element-side solder layer 54. This flow treatment causes the surfaces of the first element-side solder layer 44 and the second element-side solder layer 54 to have an arc-like shape in cross section along the thickness direction Z.

[0075] The first element electrode 43 and the second element electrode 53 have the same size when viewed from the thickness direction Z. Therefore, the height T41 of the first element-side solder layer 44 and the height T42 of the second element-side solder layer 54 are the same. The height T41 of the first element-side solder layer 44 is the distance along the thickness direction Z from the first element electrode 43 to the lowest point (vertex) P44 of the first element-side solder layer 44. The height T42 of the second element-side solder layer 54 is the distance along the thickness direction Z from the second element electrode 53 to the lowest point (vertex) P54 of the second element-side solder layer 54. Therefore, the vertex P44 of the first element-side solder layer 44 and the vertex P54 of the second element-side solder layer 54 are at the same position in the thickness direction Z.

[0076] As shown in FIG. 14, the semiconductor element 40 is flip-chip mounted by applying flux to the first element side solder layer 44 and the second element side solder layer 54 using, for example, a flip-chip bonder.

[0077] At this time, the apex P27 of the first-board-side solder layer 27 and the apex P37 of the second-board-side solder layer 37 are at the same position in the thickness direction Z. On the other hand, the apex P44 of the first-element-side solder layer 44 and the apex P54 of the second-element-side solder layer 54 are at the same position in the thickness direction Z. Therefore, the first-element-side solder layer 44 and the second-element-side solder layer 54 are in contact with the first-board-side solder layer 27 and the second-board-side solder layer 37, respectively.

[0078] Next, as shown in Fig. 15, a first bonding member 61 and a second bonding member 62 are formed by a reflow process. The first bonding member 61 is formed from the first substrate side solder layer 27 and the first element side solder layer 44 shown in Fig. 14. The second bonding member 62 is formed from the second substrate side solder layer 37 and the second element side solder layer 54 shown in Fig. 14.

[0079] As shown in Fig. 14, the first-board-side solder layer 27 and the first-element-side solder layer 44 are in contact with each other. Therefore, the first-board-side solder layer 27 and the first-element-side solder layer 44 that have been melted by the reflow process are joined to each other, forming a first bonding member 61 shown in Fig. 15. Similarly, as shown in Fig. 14, the second-board-side solder layer 37 and the second-element-side solder layer 54 are in contact with each other. Therefore, the second-board-side solder layer 37 and the second-element-side solder layer 54 that have been melted by the reflow process are joined to each other, forming a second bonding member 62 shown in Fig. 15.

[0080] Here, a comparative example of this embodiment will be described. Figures 16 and 17 show a step of flip-chip mounting a semiconductor element 40 in a manufacturing process of a semiconductor device of this comparative example of this embodiment. Note that in the comparative example, the same components as those in the semiconductor device 1A of this embodiment are given the same reference numerals and will not be described again. The semiconductor device of the comparative example differs from the semiconductor device 1A of this embodiment and its components involved in the manufacturing process thereof in the first wiring electrodes 24, second wiring electrodes 34, first substrate side solder layer 27, and second substrate side solder layer 37.

[0081] 16 and 17 , in the comparative example, the first wiring electrode 24 and the second wiring electrode 34 are equal in size when viewed from the thickness direction Z, and the first-substrate-side solder layer 27 and the second-substrate-side solder layer 37 are equal in shape. Therefore, the apex P37 of the second-substrate-side solder layer 37 is located closer to the base material 910 than the apex P27 of the first-substrate-side solder layer 27. Therefore, as shown in FIG. 17 , when the semiconductor element 40 is flip-chip mounted, the first-element-side solder layer 44 contacts the first-substrate-side solder layer 27, while the second-element-side solder layer 54 does not contact the second-substrate-side solder layer 37. Therefore, during the reflow process, it is difficult for the second-element-side solder layer 54 and the second-substrate-side solder layer 37 to bond to each other, resulting in a mounting defect in which some of the element electrodes of the semiconductor element 40 are not connected to the wiring electrodes.

[0082] In contrast, in the semiconductor device 1A and its manufacturing method of the present embodiment, all of the first element electrodes 43 and second element electrodes 53 of the semiconductor element 40 are bonded to the first wiring electrodes 24 and second wiring electrodes 34 on the base material 910 side. This reduces mounting defects of the semiconductor element 40.

[0083] Returning to the manufacturing method of the semiconductor device 1A of this embodiment, the steps after mounting will be described. As shown in FIG. 18 , the manufacturing method of the semiconductor device 1A includes a step of forming a resin layer 970 that covers the substrate main surface 9101 of the substrate 910 and the semiconductor element 40. The resin layer 970 is a member that becomes the sealing resin 70 shown in FIGS. 1 to 5 . The resin layer 970 is a synthetic resin whose main material is, for example, epoxy resin. The resin layer 970 is formed by, for example, compression molding. The resin layer 970 is filled between the element main surface 401 of the semiconductor element 40 and the substrate main surface 9101 of the substrate 910.

[0084] As shown in FIGS. 19 and 20, the method for manufacturing the semiconductor device 1A includes a step of removing the support substrate 900. A dicing tape (not shown) is attached to the lower surface 972 of the resin layer 970, and the support substrate 900 shown in FIG. 19 is removed. Note that FIG. 19 is shown upside down compared to FIG. 18. For example, the support substrate 900 is removed by grinding, and the base material 910, the first terminal pillar 922, and the second terminal pillar 932 are partially ground. The base material 910, the first terminal pillar 922, and the second terminal pillar 932 are ground from the support substrate 900 side up to the dashed line shown in FIG. Note that the base material 910, the first terminal pillar 922, and the second terminal pillar 932 may be ground after the support substrate 900 is peeled off. As a result, the substrate 10 and the first through electrode 22 and the second through electrode 32 penetrating the substrate 10 are formed.

[0085] As shown in FIG. 21 , the manufacturing method of the semiconductor device 1A includes a step of cutting the base material 910 and cutting (half-cutting) a portion of the resin layer 970 in the thickness direction Z. When cutting the base material 910 and half-cutting the resin layer 970, a dicing blade is used, for example, to make a cut along the cutting line (dashed line) shown in FIG. 21 from the base material 910 side toward the lower surface 972 of the resin layer 970. By half-cutting the resin layer 970 in this manner, a separation groove 971 is formed in the resin layer 970. Then, by cutting the base material 910 and half-cutting the resin layer 970 with the dicing blade, the first main surface wiring 23 is cut. As a result, the substrate 10 and the first main surface wiring 23 are formed. More specifically, a side surface 224 of the first through electrode 22 and a side surface 234 of the first main surface wiring 23 are formed. The side surface 224 of the first through electrode 22 and the side surface 234 of the first main surface wiring 23 are exposed in the separation groove 971. The first through electrodes 22 and the first main surface wiring 23 thus formed constitute the first wiring section 21.

[0086] 22 , the manufacturing method of the semiconductor device 1A includes the steps of forming a first external conductive film 81 and a second external conductive film 82. The first external conductive film 81 has a first conductive film 81A that covers the lower surfaces 222 of the first through-hole electrodes 22, and a second conductive film 81B that covers the side surfaces 224, 234 of the first through-hole electrodes 22 and the first main-surface wiring 23. The second conductive film 81B is formed in the separation trench 971. The second external conductive film 82 is formed to cover the lower surfaces 322 of the second through-hole electrodes 32.

[0087] The first outer conductive film 81 and the second outer conductive film 82 are each made of a plated metal. For example, the first outer conductive film 81 and the second outer conductive film 82 are formed by depositing plated metals, such as Ni, Pd, and Au, in this order, by electroless plating. Note that the structures and formation methods of the first outer conductive film 81 and the second outer conductive film 82 are not limited.

[0088] As shown in FIG. 23, the method for manufacturing the semiconductor device 1A includes a step of dividing the semiconductor device 1A into individual pieces. The resin layer 970 is cut to separate the semiconductor elements 40 into individual pieces. For example, a dicing blade narrower than the dicing blade that half-cut the resin layer 970 is used to cut the resin layer 970 along the cutting lines (dashed lines) from the separation grooves 971 to the bottom surface 972. The individual pieces are semiconductor devices 1A including the substrate 10 and the sealing resin 70. In other words, a dicing blade narrower than the dicing blade that half-cut the resin layer 970 is used to cut the resin layer 970 down to the bottom surface 972, thereby forming the step 71 in the resin layer 970. This forms the sealing resin 70. More specifically, the sealing resin 70 includes a resin side surface 703, a first resin portion 70A, and a second resin portion 70B. The semiconductor device 1A is manufactured through the above steps.

[0089] (action) Next, the operation of the semiconductor device 1A of this embodiment will be described. The semiconductor device 1A includes a substrate 10, a first wiring portion 21, a second wiring portion 31, and a semiconductor element 40. The substrate 10 has a substrate main surface 101 facing in the thickness direction. The semiconductor element 40 has an element main surface 401 facing the substrate main surface 101, and a first element electrode 43 and a second element electrode 53 formed on the element main surface 401.

[0090] The first wiring portion 21 has a first through electrode 22, a first main surface wiring 23, and a first wiring electrode 24. The first through electrode 22 penetrates the substrate 10 and has an upper surface 221 facing the same side as the substrate main surface 101. The first main surface wiring 23 is in contact with the substrate main surface 101 and the upper surface 221 and has an upper surface 231 facing the same side as the substrate main surface 101. The first wiring electrode 24 is formed on the upper surface 231.

[0091] The second wiring portion 31 has a second through electrode 32, a second main surface wiring 33, and a second wiring electrode 34. The second through electrode 32 penetrates the substrate 10 and has an upper surface 321 facing the same side as the substrate main surface 101. The second main surface wiring 33 is in contact with the substrate main surface 101 and the upper surface 321 and has an upper surface 331 facing the same side as the substrate main surface 101. The second wiring electrode 34 is formed on the upper surface 331. The upper surface 221 is recessed toward the inside of the first through electrode 22. The upper surface 321 is recessed toward the inside of the second through electrode 32. The first wiring electrode 24 formed on the upper surface 231 of the first main surface wiring 23 is larger than the second wiring electrode 34 formed on the upper surface 331 of the second main surface wiring 33 when viewed from the thickness direction Z.

[0092] The first wiring electrode 24 is joined to the first element electrode 43 of the semiconductor element 40 by a first bonding member 61. The second wiring electrode 34 is joined to the second element electrode 53 of the semiconductor element 40 by a second bonding member 62. The first bonding member 61 is formed by bonding the first-substrate-side solder layer 27 formed on the upper surface 241 of the first wiring electrode 24 to the first-element-side solder layer 44 formed on the lower surface 431 of the first element electrode 43 of the semiconductor element 40. The second bonding member 62 is formed by bonding the second-substrate-side solder layer 37 formed on the upper surface 341 of the second wiring electrode 34 to the second-element-side solder layer 54 formed on the lower surface 531 of the second element electrode 53 of the semiconductor element 40.

[0093] The first wiring electrode 24 is formed on an upper surface 231 of the first main surface wiring 23 in contact with the substrate main surface 101 of the substrate 10. The second wiring electrode 34 is formed on an upper surface 331 of the second main surface wiring 33 in contact with an upper surface 321 of the second through electrode 32.

[0094] When the first wiring electrode 24 and the second wiring electrode 34 are formed to have the same size as viewed from the thickness direction Z, the height of the first wiring electrode 24 and the first-substrate-side solder layer 27 is equal to the height of the second wiring electrode 34 and the second-substrate-side solder layer 37, so that the apex P37 of the second-substrate-side solder layer 37 is lower than the apex P27 of the first-substrate-side solder layer 27. When the first-substrate-side solder layer 27 and the first-element-side solder layer 44 come into contact with each other during mounting of the semiconductor element 40, the second-substrate-side solder layer 37 and the second-element-side solder layer 54 may become separated from each other. As a result, the second-substrate-side solder layer 37 and the second-element-side solder layer 54 are not bonded to each other, resulting in a mounting defect of the semiconductor element 40.

[0095] In this embodiment, the first wiring electrodes 24 formed on the upper surfaces 231 of the first main-surface wiring 23 are larger than the second wiring electrodes 34 formed on the upper surfaces 331 of the second main-surface wiring 33 when viewed in the thickness direction Z. Therefore, the heights of the second wiring electrodes 34 and the second-substrate-side solder layers 37 are greater than the heights of the first wiring electrodes 24 and the first-substrate-side solder layers 27, so that the apex P37 of the second-substrate-side solder layer 37 and the apex P27 of the first-substrate-side solder layer 27 are at the same position in the thickness direction Z. When mounting the semiconductor element 40, when the first-substrate-side solder layer 27 and the first-element-side solder layer 44 come into contact, the second-substrate-side solder layer 37 and the second-element-side solder layer 54 come into contact. Therefore, the second-substrate-side solder layer 37 and the second-element-side solder layer 54 can be joined, thereby suppressing mounting defects of the semiconductor element 40.

[0096] 3, the semiconductor device 1A has a second wiring portion 31 that overlaps at least a portion of the semiconductor element 40 when viewed from the thickness direction Z, penetrates the substrate 10 from the substrate main surface 101 to the substrate back surface 102, and has a higher thermal conductivity than the substrate 10. Therefore, the semiconductor device 1A can dissipate heat generated in the semiconductor element 40 toward the substrate back surface 102 of the substrate 10 to the outside of the semiconductor device 1A.

[0097] The second wiring portion 31 has one second through electrode 32 that penetrates the substrate 10. The second through electrode 32 is a rectangular flat plate when viewed from the thickness direction Z. Therefore, the second wiring portion 31 of this embodiment has a small heat capacity and can easily dissipate heat from the semiconductor element 40.

[0098] The second through electrode 32 of the second wiring portion 31 is a rectangular flat plate when viewed from the thickness direction Z. The second through electrode 32 transfers heat in a first direction X and a second direction Y that are perpendicular to the thickness direction Z. Therefore, the second wiring portion 31 can dissipate heat more efficiently by diffusing heat that is locally generated on the element main surface 401 of the semiconductor element 40, such as a power transistor, in the first direction X and the second direction Y that are perpendicular to the thickness direction Z.

[0099] The semiconductor element 40 includes a first connection pad 41 and a second connection pad 51. The first connection pad 41 is a terminal for inputting and outputting signals and the like used for the operation of the semiconductor element 40. The second connection pad 51 is a terminal that is insulated from the first connection pad or does not affect the electrical characteristics of the semiconductor element 40. The second connection pad 51 is connected to the second wiring portion 31. As described above, the second wiring portion 31 is used for heat dissipation of the semiconductor element 40. Therefore, heat from the semiconductor element 40 can be efficiently dissipated without affecting the electrical characteristics of the semiconductor element 40.

[0100] The second external conductive film 82 is formed so as to cover the lower surfaces 322 of the second through electrodes 32 exposed on the rear surface 102 of the substrate 10. The second external conductive film 82 increases the surface area for heat dissipation, enabling more efficient heat dissipation.

[0101] The second through electrode 32 is made of plated metal. The first wiring portion 21 of the semiconductor device 1A has a first through electrode 22 that penetrates the substrate 10. The first through electrode 22 is made of plated metal. The second through electrode 32 of the second wiring portion 31 is formed simultaneously with the first through electrode 22 of the first wiring portion 21. Therefore, in the manufacturing process of the semiconductor device 1A, the second through electrode 32 can be formed efficiently in the process of forming the first through electrode 22.

[0102] The semiconductor device 1A has a first external conductive film 81 and a second external conductive film 82. The first external conductive film 81 and the second external conductive film 82 are made of plated metal. The second external conductive film 82 of the second wiring portion 31 is formed simultaneously with the first external conductive film 81 that covers the first wiring portion 21. Therefore, in the manufacturing process of the semiconductor device 1A, the second external conductive film 82 can be formed efficiently in the process of forming the first external conductive film 81.

[0103] The second external conductive film 82 can also be connected to, for example, a circuit board. The circuit board on which the semiconductor device 1A is mounted has pads to which the first external conductive film 81 of the semiconductor device 1A is connected. The first external conductive film 81 is connected to the pads of the circuit board by, for example, solder. A pad facing the second external conductive film 82 is provided on this circuit board, and the second external conductive film 82 is connected to the pad by, for example, solder. This allows heat transferred from the semiconductor element 40 to the second wiring portion 31 to be dissipated from the second external conductive film 82 of the second wiring portion 31 to the circuit board. Note that a heat sink made of, for example, a metal such as Al can be connected to the second external conductive film 82.

[0104] As described above, according to this embodiment, the following effects are achieved. (1) The semiconductor device 1A includes a substrate 10, a first wiring portion 21, a second wiring portion 31, and a semiconductor element 40. The substrate 10 has a substrate main surface 101 facing in the thickness direction. The semiconductor element 40 has an element main surface 401 facing the substrate main surface 101, and a first element electrode 43 and a second element electrode 53 formed on the element main surface 401. The first wiring portion 21 has a first through electrode 22, a first main surface wiring 23, and a first wiring electrode 24.

[0105] The first through-electrode 22 penetrates the substrate 10 and has an upper surface 221 facing the same side as the substrate main surface 101. The first main surface wiring 23 is in contact with the substrate main surface 101 and the upper surface 221 and has an upper surface 231 facing the same side as the substrate main surface 101. The first wiring electrode 24 is formed on the upper surface 231. The second wiring part 31 has a second through-electrode 32, a second main surface wiring 33, and a second wiring electrode 34. The second through-electrode 32 penetrates the substrate 10 and has an upper surface 321 facing the same side as the substrate main surface 101. The second main surface wiring 33 is in contact with the substrate main surface 101 and the upper surface 321 and has an upper surface 331 facing the same side as the substrate main surface 101. The second wiring electrode 34 is formed on the upper surface 331. The upper surface 221 is recessed toward the inside of the first through-electrode 22. The upper surface 321 is recessed toward the inside of the second through electrode 32. The first wiring electrode 24 formed on the upper surface 231 of the first main surface wiring 23 is larger than the second wiring electrode 34 formed on the upper surface 331 of the second main surface wiring 33 when viewed from the thickness direction Z.

[0106] The first wiring electrode 24 is joined to the first element electrode 43 of the semiconductor element 40 by a first bonding member 61. The second wiring electrode 34 is joined to the second element electrode 53 of the semiconductor element 40 by a second bonding member 62.

[0107] The first bonding member 61 is formed by bonding the first-substrate-side solder layer 27 formed on the upper surface 241 of the first wiring electrode 24 to the first-element-side solder layer 44 formed on the lower surface 431 of the first element electrode 43 of the semiconductor element 40. The second bonding member 62 is formed by bonding the second-substrate-side solder layer 37 formed on the upper surface 341 of the second wiring electrode 34 to the second-element-side solder layer 54 formed on the lower surface 531 of the second element electrode 53 of the semiconductor element 40. When the first-substrate-side solder layer 27 and the first-element-side solder layer 44 come into contact with each other during mounting of the semiconductor element 40, the second-substrate-side solder layer 37 and the second-element-side solder layer 54 also come into contact with each other. This allows the second-substrate-side solder layer 37 and the second-element-side solder layer 54 to be bonded together, thereby preventing mounting defects of the semiconductor element 40.

[0108] (2) The second through electrode 32 of the second wiring portion 31 overlaps at least a portion of the semiconductor element 40 when viewed from the thickness direction Z, and penetrates the substrate 10 from the substrate main surface 101 to the substrate back surface 102. The thermal conductivity of the second through electrode 32 is higher than that of the substrate 10. Therefore, the semiconductor device 1A can transfer heat generated in the semiconductor element 40 toward the substrate back surface 102 of the substrate 10 and dissipate the heat to the outside of the semiconductor device 1A.

[0109] (3) The second wiring portion 31 has one second through electrode 32 that penetrates the substrate 10. The second through electrode 32 is a rectangular flat plate when viewed in the thickness direction Z. Therefore, the second wiring portion 31 of this embodiment has a small heat capacity and can easily dissipate heat from the semiconductor element 40.

[0110] (4) The second through electrode 32 of the second wiring portion 31 is a rectangular flat plate when viewed in the thickness direction Z. The second through electrode 32 transfers heat in the first direction X and the second direction Y that are perpendicular to the thickness direction Z. Therefore, the second wiring portion 31 can dissipate heat more efficiently by diffusing heat that is locally generated on the element main surface 401 of the semiconductor element 40, such as a power transistor, in the first direction X and the second direction Y that are perpendicular to the thickness direction Z.

[0111] (5) The second wiring portion 31 is electrically insulated from the first wiring portion 21 of the semiconductor element 40 or is connected to a portion of wiring that does not electrically affect the first wiring portion 21. Therefore, the heat of the semiconductor element 40 can be dissipated without affecting the electrical characteristics of the semiconductor element 40.

[0112] (6) The second through electrode 32 is made of a plated metal. The first wiring portion 21 of the semiconductor device 1A has a first through electrode 22 that penetrates the substrate 10. The first through electrode 22 is made of a plated metal. The second through electrode 32 of the second wiring portion 31 is formed simultaneously with the first through electrode 22 of the first wiring portion 21. Therefore, in the manufacturing process of the semiconductor device 1A, the second through electrode 32 can be formed efficiently in the process of forming the first through electrode 22.

[0113] (7) The semiconductor device 1A has a first external conductive film 81 that covers the first wiring portion 21 and a second external conductive film 82 that covers the second wiring portion 31. The first external conductive film 81 and the second external conductive film 82 are made of plated metal. The second external conductive film 82 of the second wiring portion 31 is formed simultaneously with the first external conductive film 81 that covers the first wiring portion 21. Therefore, in the manufacturing process of the semiconductor device 1A, the second external conductive film 82 can be formed efficiently in the process of forming the first external conductive film 81.

[0114] (8) The second wiring portion 31 has a second external conductive film 82. The second external conductive film 82 is formed so as to cover the lower surface 322 of the second through electrode 32 exposed on the rear surface 102 of the substrate 10. This second external conductive film 82 enables more efficient heat dissipation.

[0115] (9) The second external conductive film 82 can also be connected to, for example, a circuit board. This allows heat transferred from the semiconductor element 40 to the second wiring portion 31 to be dissipated from the second external conductive film 82 of the second wiring portion 31 to the circuit board.

[0116] (10) When the semiconductor device 1A is mounted on a circuit board, the solder connecting the first external conductive film 81 to the connection pad of the circuit board is interposed between the first conductive film 81A and the connection pad, and also adheres to the second conductive film 81B. In other words, the solder that has become liquid through the reflow process creeps up the second conductive film 81B and forms a solder fillet between the second conductive film 81B and the connection pad. This solder fillet increases the solder joint area, further improving connection strength. Furthermore, the solder fillet allows the state of the soldering of the semiconductor device 1A to be confirmed from the outside.

[0117] (11) The semiconductor device 1A has second main surface wiring 33 connected to the upper surface 321 of the second through electrode 32. The second main surface wiring 33 has an extending portion 33B that extends outward beyond the side surface 323 of the second through electrode 32. The extending portion 33B contacts the substrate main surface 101 around the second through electrode 32. This prevents the second through electrode 32 from falling off the substrate 10.

[0118] (12) When viewed from the thickness direction Z, the size of the second wiring electrode 34 is equal to the size of the second element electrode 53. This reduces the stress applied to the second joint member 62 that connects the second wiring electrode 34 and the second element electrode 53. Large stress applied to the second joint member 62 may cause cracks in the second joint member 62. Therefore, by reducing the stress, it is possible to prevent cracks from occurring in the second joint member 62.

[0119] (Example of change) The above-described embodiments are examples of possible forms of the semiconductor device and semiconductor device manufacturing method according to the present disclosure, and are not intended to limit the forms. The semiconductor device and semiconductor device manufacturing method according to the present disclosure may take forms different from those exemplified in the above-described embodiments. Examples include forms in which part of the configuration of the above-described embodiments is replaced, modified, or omitted, or forms in which new configurations are added to the above-described embodiments. The following modified examples can be combined with each other as long as no technical contradictions arise. Note that, for convenience of explanation, the following modified examples will basically be described using the above-described embodiment, but can also be applied to other embodiments as long as no technical contradictions arise.

[0120] In the above embodiment, the size of the second wiring electrode 34 may be larger than the size of the second element electrode 53. In this case, the margin for misalignment when bonding the semiconductor element 40 to the substrate 10 becomes wider. This makes it easier to bond the semiconductor element 40 to the substrate 10.

[0121] A semiconductor device 1B shown in FIG. 24 differs from the above-described embodiment in the configuration of a semiconductor element 40B. The semiconductor element 40B includes an insulating film 46 and a rewiring layer 47. The insulating film 46 covers the surface of the element substrate and also covers the peripheral portions of the first electrode pads 42 and the second electrode pads 52. The insulating film 46 is made of, for example, SiN. The rewiring layer 47 covers the surfaces of the first electrode pads 42 and the second electrode pads 52, extends to the insulating film 46, and is in contact with the surface of the insulating film 46. The rewiring layer 47 is made of, for example, Cu or a Cu alloy. The protective film 45 covers the surface of the insulating film 46 and a portion of the rewiring layer 47. Openings 451 and 452 in the protective film 45 expose portions of the surface of the rewiring layer 47 as connection terminals. The first opening 451 is formed so as to expose, as connection terminals, portions of the rewiring layer 47 that do not overlap with the first electrode pads 42 in the thickness direction Z. The second opening 452 is formed so as to expose, as connection terminals, portions of the rewiring layer 47 that do not overlap with the second electrode pads 52 in the thickness direction Z.

[0122] The first element electrode 43 is connected to the redistribution layer 47 exposed from the first opening 451. The second element electrode 53 is connected to the redistribution layer 47 exposed from the second opening 452. The first electrode pad 42 and the first element electrode 43 do not overlap in the thickness direction Z. In other words, the first electrode pad 42 and the first element electrode 43 are offset in a direction intersecting the thickness direction Z. The second electrode pad 52 and the second element electrode 53 do not overlap in the thickness direction Z. In other words, the second electrode pad 52 and the second element electrode 53 are offset in a direction intersecting the thickness direction Z.

[0123] The first external conductive film 81 and the second external conductive film 82 of the semiconductor device 1B are connected to a circuit board on which the semiconductor device 1B is mounted. Temperature changes in the environment in which the semiconductor device 1B and the circuit board are used can cause stress due to hard metal members such as the second through electrode 32. With respect to such stress, the second electrode pad 52 is offset in a direction intersecting the thickness direction Z with respect to the second element electrodes 53 arranged in the thickness direction Z via the second through electrode 32, the second main surface wiring 33, the second wiring electrode 34, and the second bonding member 62. Therefore, stress caused by temperature changes and the like is less likely to be applied to the second electrode pad 52, that is, the stress is alleviated. Therefore, the stress applied to the semiconductor element 40B can be alleviated.

[0124] A semiconductor device 1C shown in FIG. 25 differs from the above-described embodiment in the configuration of a semiconductor element 40C. In this modified semiconductor device 1C, the first element electrode 43 and the second element electrode 53 constituting the first connection pad 41 and the second connection pad 51 are made of barrier layers 43B and 53B, and do not have the conductive layers 43A and 53A shown in Fig. 5. With this semiconductor device 1C, the same effects as those of the above embodiment can be obtained.

[0125] In the semiconductor device 1D shown in FIG. 26 , the first wiring electrodes 24 and the second wiring electrodes 34 are the same size when viewed from the thickness direction Z. The second element electrodes 53 of the semiconductor element 40D are equal in size to the second wiring electrodes 34. Meanwhile, in the semiconductor element 40D, the first element electrodes 43 are larger than the second element electrodes 53. Therefore, as shown in FIG. 27 , the height of the first element-side solder layer 44 is lower than the height of the second element-side solder layer 54. By making this height difference equal to the height difference in the thickness direction Z of the upper surface 331 of the second main-surface wiring 33 relative to the substrate main surface 101 of the substrate 10, the first substrate-side solder layer 27 and the first element-side solder layer 44 can be brought into contact with each other, and the second substrate-side solder layer 37 and the second element-side solder layer 54 can be brought into contact with each other. This allows the element electrodes 43, 53 of the semiconductor element 40D to be joined to the wiring electrodes 24, 34, reducing mounting defects of the semiconductor element 40D.

[0126] In the semiconductor device 1E shown in FIG. 28 , the first wiring electrode 24 and the first element electrode 43 are the same size when viewed from the thickness direction Z. The size of the first element electrode 43 is equal to the size of the second element electrode 53. Meanwhile, the size of the first wiring electrode 24 is larger than the size of the second wiring electrode 34. Therefore, as shown in FIG. 29 , the height T12 of the second wiring electrode 34 and the second-substrate-side solder layer 37 can be made higher than the height T11 of the first wiring electrode 24 and the first-substrate-side solder layer 27, and the position of the apex P27 of the first-substrate-side solder layer 27 can be made the same as the position of the apex P37 of the second-substrate-side solder layer 37. This allows the first-substrate-side solder layer 27 to be in contact with the first-element-side solder layer 44, and the second-substrate-side solder layer 37 to be in contact with the second-element-side solder layer 54, as in the above embodiment. This allows the element electrodes 43 and 53 of the semiconductor element 40 to be joined to the wiring electrodes 24 and 34, thereby reducing mounting defects of the semiconductor element 40.

[0127] In the case of the semiconductor device 1E, the size of the first wiring electrode 24 is equal to the size of the first element electrode 43 when viewed in the thickness direction Z. This reduces the stress applied to the first joint member 61 that connects the first wiring electrode 24 and the first element electrode 43. This also reduces the occurrence of cracks in the first joint member 61.

[0128] The semiconductor device 1F shown in FIG. 30 includes two second wiring portions 31. It is also possible to configure the semiconductor device 1F to include three or more second wiring portions 31. The second wiring electrodes 34 of each second wiring portion 31 are connected to the second element electrodes 53 of the semiconductor element 40 via second bonding members 62. The semiconductor device 1F configured in this manner can also achieve the same effects as the above-described embodiment. The two second wiring portions 31 may be connected to the same signal wiring that does not affect the electrical characteristics of the semiconductor element 40, or may be connected to different signal wirings. At least one of the two second wiring portions 31 may be left unconnected. [Explanation of symbols]

[0129] 1A~1F Semiconductor equipment 10 Substrate 101 Main surface of substrate 102 Back of the board 103 Side of the board 11 Through hole 12 Through holes 21 1st wiring section 22 1st through electrode 221 Top surface (first electrode top surface) 23 First main surface wiring 23A Connection Wiring 23B Wiring section on board 231 Top surface (first wiring top surface) 24 1st wiring electrode 25 metal layer 26 Conductive layer 27 First board side solder layer 31 2nd wiring section 32 2nd through electrode 321 Top surface (second electrode top surface) 33 Second main surface wiring 33A Connection Wiring Section 33B Extension part 331 Top surface (second wiring top surface) 34 2nd wiring electrode 35 Metal layer 36 Conductive layer 37 Second board side solder layer 40, 40B~40D Semiconductor elements 401 Element main surface 402 Back side of element 403 Element side 41 First connection pad 42 First electrode pad 43 First element electrode 44 Solder layer on the first element side 45 Protective film 46 insulating film 47 Redistribution layer 51 Second connection pad 52 Second electrode pad 53 Second element electrode 54 Second element side solder layer 61 First joining member 62 Second joining member 70 Sealing resin 81 First outer conductive film 82 Second outer conductive film

Claims

1. a substrate having a substrate main surface facing in a thickness direction; a semiconductor element having a main element surface facing the substrate main surface and a first element electrode and a second element electrode formed on the main element surface; a first through electrode that penetrates the substrate and has a first electrode upper surface facing the same side as the main surface of the substrate; a second through electrode that penetrates the substrate and has a second electrode upper surface facing the same side as the main surface of the substrate; a first main surface wiring having a first wiring upper surface that is in contact with the substrate main surface and the first electrode upper surface and faces the same side as the substrate main surface; a second main surface wiring having a second wiring upper surface that is in contact with the second electrode upper surface and faces the same side as the substrate main surface; a first wiring electrode formed on an upper surface of the first wiring; a second wiring electrode formed on an upper surface of the second wiring; a first bonding member that bonds the first element electrode and the first wiring electrode; a second bonding member that bonds the second element electrode and the second wiring electrode; Equipped with an upper surface of the first electrode is recessed toward the inside of the first through-electrode; an upper surface of the second electrode is recessed toward the inside of the second through-electrode; When viewed from the thickness direction, the first wiring electrode is larger than the second wiring electrode. Semiconductor device.

2. The semiconductor device according to claim 1 , wherein the first element electrode and the second element electrode are equal in size when viewed from the thickness direction.

3. 3. The semiconductor device according to claim 1, wherein a size of the second wiring electrode is equal to a size of the second element electrode when viewed from the thickness direction.

4. 3. The semiconductor device according to claim 1, wherein the second wiring electrode is larger than the second element electrode when viewed in the thickness direction.

5. 3. The semiconductor device according to claim 1, wherein a size of the first wiring electrode is equal to a size of the first element electrode when viewed from the thickness direction.

6. 3. The semiconductor device according to claim 1, wherein the first wiring electrode is larger than the first element electrode when viewed in the thickness direction.

7. a substrate having a substrate main surface facing in a thickness direction; a semiconductor element having a main element surface facing the substrate main surface and a first element electrode and a second element electrode formed on the main element surface; a first through electrode that penetrates the substrate and has a first electrode upper surface facing the same side as the main surface of the substrate; a second through electrode that penetrates the substrate and has a second electrode upper surface facing the same side as the main surface of the substrate; a first main surface wiring having a first wiring upper surface that is in contact with the substrate main surface and the first electrode upper surface and faces the same side as the substrate main surface; a second main surface wiring having a second wiring upper surface that is in contact with the second electrode upper surface and faces the same side as the substrate main surface; a first wiring electrode formed on an upper surface of the first wiring; a second wiring electrode formed on an upper surface of the second wiring; a first bonding member that bonds the first element electrode and the first wiring electrode; a second bonding member that bonds the second element electrode and the second wiring electrode; Equipped with an upper surface of the first electrode is recessed toward the inside of the first through-electrode; an upper surface of the second electrode is recessed toward the inside of the second through-electrode; When viewed from the thickness direction, the first element electrode is larger than the second element electrode. Semiconductor device.

8. The semiconductor device according to claim 7 , wherein the first wiring electrode and the second wiring electrode are equal in size when viewed from the thickness direction.

9. 9. The semiconductor device according to claim 7, wherein a size of the second wiring electrode is equal to a size of the second element electrode when viewed from the thickness direction.

10. 9. The semiconductor device according to claim 7, wherein the second wiring electrode is larger than the second element electrode when viewed in the thickness direction.

11. 9. The semiconductor device according to claim 7, wherein a size of the first wiring electrode is equal to a size of the first element electrode when viewed from the thickness direction.

12. 9. The semiconductor device according to claim 7, wherein the first wiring electrode is larger than the first element electrode when viewed in the thickness direction.

13. The semiconductor device according to claim 1 , wherein the first wiring electrode is formed on an upper surface of the first wiring that overlaps with the main surface of the substrate when viewed in the thickness direction.

14. 14. The semiconductor device according to claim 1, wherein a thickness of the first main surface wiring and a thickness of the second main surface wiring are equal to each other.

15. 15. The semiconductor device according to claim 1, wherein the second through electrode, the second main surface wiring, and the second wiring electrode are provided in a plurality of regions overlapping the semiconductor element when viewed from the thickness direction.

16. 16. The semiconductor device according to claim 1, wherein the second main surface wiring has an extension portion that is located outside the second through electrode when viewed in the thickness direction, and the extension portion contacts the substrate main surface.

17. The semiconductor device according to claim 1 , further comprising a sealing resin that covers the main surface of the substrate and the semiconductor element.

18. 18. The semiconductor device according to claim 17, wherein the sealing resin is filled between the main surface of the substrate and the semiconductor element.

19. the substrate has a substrate back surface facing the opposite side to the substrate main surface in the thickness direction, a first external conductive film covering the first through electrode exposed from the rear surface of the substrate; a second external conductive film covering the second through electrode exposed from the rear surface of the substrate; The semiconductor device according to claim 1 , comprising:

20. the substrate has a substrate side surface that intersects with the substrate main surface, the first through electrode has an electrode side surface exposed from a side surface of the substrate, the first external conductive film covers the electrode side surface of the first through electrode; 20. The semiconductor device according to claim 19.

21. the first main surface wiring has a wiring side surface exposed from a side surface of the substrate, the first external conductive film covers the wiring side surface of the first main surface wiring; The semiconductor device according to claim 20.

22. the semiconductor element includes an electrode pad; the first element electrode and the second element electrode are disposed at positions overlapping the electrode pads in the thickness direction and are connected to the electrode pads. The semiconductor device according to any one of claims 1 to 21.

23. the semiconductor element includes an electrode pad and a rewiring layer connected to the electrode pad; the first element electrode and the second element electrode are disposed at positions not overlapping the electrode pads in the thickness direction and are connected to the rewiring layer. The semiconductor device according to any one of claims 1 to 21.

Images