Scalable Space-Based Directory

Abstract

A cache directory is disclosed that includes one or more cache directories that are configurable to swap at least one bit between a first field and a second field within each cache directory entry to change the size of the represented memory region and the number of cache lines tracked within the cache subsystem.

Description

[Background technology]

[0001] Modern computing systems have multiple central processing units (CPUs), which typically include and rely on multiple caches in a cache hierarchy to improve processor and memory performance. Compared to main memory, caches are smaller, faster memory devices that store frequently accessed data so that the data can be accessed with low latency. Such cache devices are often implemented in static random access memory (SRAM) and typically reside between the processing unit issuing the memory request and the main memory device. A memory-side cache is a dedicated cache attached to a specific memory device or partition of memory that caches data written to and read from the memory device by other devices.

[0002] In multi-node computer systems, special precautions must be taken to maintain coherency of data being used by different processing nodes. For example, when a processor attempts to access data at a memory address, the processor must first determine whether the memory is stored and modified in another cache. To implement this cache coherency protocol, caches typically include several status bits that indicate the status of a cache line to maintain data coherency across the system. For example, one common coherency protocol is the "MOESI" protocol, where each letter represents a state of a cache line. These states are: the cache line is modified (M); the cache line is exclusive (E) or shared (S); or the cache line is invalid (I). The owned (O) state indicates that the line has been modified in one cache, that a shared copy may exist in another cache, and that the data in memory is stale. Each cache line includes a status bit in a cache directory that tracks cache lines currently being used by the system to indicate which MOESI state the line is in.

[0003] Managing a cache directory scheme in a multiprocessor system becomes difficult due to the increasing demands on various types of processing and the increasing size of caches and main memory.

[0004] The embodiments illustrated in the accompanying drawings herein are shown by way of example and not by way of limitation. [Brief explanation of the drawings]

[0005] [Figure 1] FIG. 1 is a block diagram of one embodiment of a computing system. [Figure 2] FIG. 1 is a block diagram of one embodiment of a core complex. [Figure 3] FIG. 1 is a block diagram of one embodiment of a multi-CPU processor system. [Figure 4] FIG. 2 is a block diagram of one embodiment of a cache directory. [Figure 5] FIG. 1 is a process flow diagram illustrating one embodiment of a method for changing the region size of tracked cache lines in a processor system. [Figure 6] FIG. 1 is a process flow diagram illustrating one embodiment of a method for increasing or decreasing region size and reallocating regions as needed. DETAILED DESCRIPTION OF THE INVENTION

[0006] In the following description, numerous specific details are set forth, such as examples of specific systems, components, methods, etc., to provide a thorough understanding of the embodiments. However, it will be apparent to those skilled in the art that at least some embodiments may be practiced without these specific details. In other instances, well-known components or methods are not described in detail or are presented in simplified block diagram form to avoid unnecessarily obscuring the embodiments. Thus, the specific details set forth are for illustrative purposes only. Particular embodiments may vary from these example details and still be considered within the scope of the embodiments.

[0007] As the number of CPUs, their respective caches, and cache sizes increase, cache directories also grow to cover a larger number of entries. Typically, a cache directory is accessed cache line by cache line to know exactly where that line is cached in the system and the current state of that line to accurately filter snoops when a request is received. In one embodiment, to reduce the amount of chip area, the directory consumes cache directory track space in memory that corresponds to a group of cache lines in the system instead of a single cache line. In this way, decisions can be made collectively for an entire group of cache lines.

[0008] An embodiment of a cache directory scheme may statically or dynamically reconfigure the size of memory regions and the number of cache lines tracked in each cache directory entry. Figure 1 is a block diagram of an embodiment of a computing system 100 including multiple core complexes 105A-105N and multiple home nodes 130A-130N that may be configured to change the size of memory regions and the number of cache lines tracked per cache directory entry. Computing system 100 also includes an input / output (I / O) interface 120, a data fabric / bus 125, and a network interface 135. In other embodiments, computing system 100 may include other components and / or be arranged in other configurations.

[0009] In one embodiment, each core complex 105A-105N includes a processing component, such as one or more processor cores or other dedicated processing components. Each processor core within a core complex 105A-105N includes a cache subsystem having one or more levels of cache. In one embodiment, the cache subsystem includes a shared cache connected to each core complex 105A-105N (e.g., L3 cache 230 in FIG. 2 ). In some embodiments, one or more core complexes 105A-105N may include a data-parallel processor with a highly parallel architecture, such as one or more of a graphics processing unit (GPU), a digital signal processor (DSP), a field programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc. As used herein, a “core complex” may also be referred to as a “processing node,” a “CPU,” or a “CPU complex.”

[0010] In one embodiment, home node 130 may include one or more of a coherent slave, a cache directory, and a memory controller coupled to any number and types of memory devices (not shown). For example, the memory device(s) coupled to home node(s) 130 may include dynamic random access memory (DRAM), static random access memory (SRAM), NAND flash memory, NOR flash memory, ferroelectric random access memory (FeRAM), etc.

[0011] I / O (input / output) interface 120 represents any number and type of I / O interfaces, such as, but not limited to, various types of Peripheral Component Interconnect (PCI) buses, Gigabit Ethernet (GBE) buses, Universal Serial Buses (USB), specialized processors (e.g., platform security processors, graphics processors), and system management logic. Various types of peripheral devices can be coupled to I / O interface 120. Such peripheral devices include (but are not limited to) displays, keyboards, mice, printers, scanners, joysticks, other types of game controllers, media recording devices, external storage devices, network interface cards, etc.

[0012] In various embodiments, computing system 100 is a server, a desktop computer, a laptop, a mobile device, a game console, a streaming device, a wearable device, or any of a variety of other types of computing systems or devices. The number, orientation, and types of components shown in computing system 100 are merely examples and may vary from embodiment to embodiment based on the application and system architecture.

[0013] FIG. 2 is a block diagram of one embodiment of a core complex 200, such as core complexes 105A-105N of FIG. 1. In one embodiment, core complex 200 may include four processor cores 210A-210D and a cache subsystem including L1 caches 215A-215D, L2 caches 220A-220D, and L3 cache 230. The cache subsystem may include high-speed cache memory (e.g., L1 caches 215A-215D, L2 caches 220A-220D, and L3 cache 230) configured to store blocks of data (not shown). As used herein, a "block" is a set of bytes stored in contiguous memory locations within a cache memory that is treated as a unit for coherency purposes. Furthermore, the terms "cache block," "block," "cache line," and "line" are each interchangeable herein. In some embodiments, a block may be a unit of allocation and deallocation within a cache. The block can be retrieved from other caches in the system, such as from other core complexes (e.g., core complexes 105A-105N in FIG. 1), or from main memory, such as via home node 130A in FIG. 1.

[0014] Additionally, in one embodiment, L3 cache 230 is shared by each of processor cores 210A-210D. L3 cache 230 is coupled to a coherent master for access to a data fabric (e.g., data fabric / bus 125 of FIG. 1) and a memory subsystem (not shown). In other embodiments, core complex 200 may include fewer or more processor cores (e.g., processor core 210A) and corresponding L2 caches (e.g., L2 cache 220A). In still other embodiments, core complex 200 may include other types of addressable cache subsystems that may include different numbers, types, and levels of cache memory without departing from the scope of this disclosure.

[0015] FIG. 3 is a block diagram of one embodiment of a processor system 300. In one embodiment, the processor system 300 includes multiple core complexes, as represented by CPUs 305A-305N. In various embodiments, the number of CPUs (e.g., CPU 305A) and the number of cores per CPU (e.g., cores 308A-308N) may vary according to design choice. Additionally, each CPU 305A-305N includes a corresponding one of cache subsystems 310A-310N. In various embodiments, the cache subsystems 310A-310N may vary in size and structure, as described above with reference to FIG. 2.

[0016] In one embodiment, each CPU 305A-305N is connected to a corresponding coherent master 315A-315N, which are further connected to data fabric / bus 318. As used herein, a "coherent master" is defined as an agent that handles traffic flowing over the interconnect (e.g., data fabric / bus 318) and manages cache coherency, and includes each coherent master (e.g., coherent masters 315A-315N) operating in concert to generate, receive, and process coherency-related messages and probes to synchronize copies of shared cache data within processor system 300.

[0017] In various embodiments, each CPU 305A-305N may be connected to one or more coherent slaves by a corresponding coherent master 315A-315N and data fabric / bus 318. For example, CPU 305A may be connected to multiple coherent slaves with access to each other's cache directories, such as coherent slaves (CS) 320A-320D and coherent slaves 321A-321D, each connected via coherent master 315A and data fabric / bus 318. Coherent slave 320A is connected to memory controller (MC) 330A and cache directory (CD) 325A, and coherent slave 321A is coupled to memory controller 331A and cache directory 326A. Each memory controller 330A-330N and 331A-331N is connected to a respective one of memory devices 340A-340N and 341A-341N. One function of each memory controller, such as memory controller 330A, is to provide elements of processor system 300 with access to memory devices 340A-340N and 341A-341N. Although shown as a single block in various embodiments, each of memory devices 340A-340N and 341A-341N may be comprised of one or more physical memories, and may be of any type suitable for storing data, such as dynamic random access memory (DRAM), static random access memory (SRAM), etc.

[0018] In one embodiment, each cache directory, e.g., cache directory 325A, includes one or more entries, each corresponding to a region in memory 340A. Each entry includes information (e.g., see FIG. 4) for tracking cached data in processor system 300 that corresponds to data in the region in memory 340A. The region size, sometimes referred to as the page size, is defined by a block of addresses in memory 340A, which addresses may vary between embodiments depending on how the memory is organized, e.g., whether the memory is interleaved across channels and memory address map bases. In one embodiment, one or more fields of an entry are configurable to change the page size of the region in memory 340A being tracked by the cache directory.

[0019] In one embodiment, the memory in devices 340A-340N and 341A-341N is divided equally among each of memory controllers 330A-330N and 331A-331N, with each coherent slave (e.g., coherent slaves 320A-320N and 321A-321N) and their respective cache directories (e.g., cache directories 325A-325N and 326A-326N) managing a respective equal and contiguous portion of the memory. Alternatively, some or all of memory devices 340A-340N and 341A-341N may have different memory capacities. In various embodiments, a coherent slave may access the cache directories of one or more other coherent slaves. For example, coherent slave 320A may access multiple other cache directories (e.g., 326A-326N and 325B-325N) within processor system 300.

[0020] In one embodiment, when coherent slave 320A receives a memory request targeted to its corresponding memory controller 330A, coherent slave 320A performs a lookup in its corresponding cache directory 325A to determine whether the request targets data in a memory location encompassed within a region of memory 340A tracked by an entry in cache directory 325A, and whether the memory request results in a cache hit, meaning that the requested data can be found in a cache line stored in a cache subsystem 310A-310N associated with the region. In one embodiment, if the lookup results in a hit, coherent slave 320A sends a probe to the CPU(s) (e.g., CPUs 305A-305N) identified in the hit entry in the cache directory. The type of probe generated by coherent slave 320A depends on the coherency state specified by the hit entry.

[0021] In one embodiment, coherent slave 320A may reconfigure cache directory 325A to change the region size, and therefore the number of cache lines, tracked within cache subsystems 310A-310N by swapping at least one bit between the tag field and reference count field of each entry in cache directory 325A.

[0022] Increasing the region size, and therefore the number of cache lines tracked per cache directory entry, reduces the granularity of cache line tracking in a processing system, allowing the cache directory to accommodate larger cache system sizes.

[0023] 3, in other embodiments, there may be other connections from data fabric / bus 318 to other components not shown to avoid obscuring the figure. For example, in another embodiment, data fabric / bus 318 includes one or more I / O interfaces and connections to one or more I / O devices, as shown in FIG.

[0024] 4 is a block diagram of one embodiment of a cache directory 400. In one embodiment, cache directory 400 includes a cache directory controller 402 and a cache directory array 404 that includes cache directory entry 406 and cache directory entry 408. Cache directory 400 also includes a cache directory array 410 that includes cache directory entry 412, and is shown after programmed bit reallocation to increase region size, as described further below. In one embodiment, each entry in array 404 and array 410 includes a status field 415, a sector valid field 420, a cluster valid field 425, a reference count field 430, and a tag field 435. In other embodiments, the entries in array 404 and array 410 may include other fields and may be arranged according to design choice.

[0025] In one embodiment indicating a change in region size, a bit reallocation is initiated to increase the region size of each cache directory entry, thereby increasing the cache line usage tracking capacity of reference count field 430 for each CPU complex in the processor system (e.g., CPUs 305A-305N in processor system 300 of FIG. 3). In various embodiments, the width of reference count field 430 depends on the number of CPU complexes in the processor system, as each CPU complex contains tracked cache lines.

[0026] The reference count field 430 is used to track the number of cache lines for the region that are cached somewhere in the processor system. For each new subscription to a cache line from this region, the reference count field 430 is incremented. For each cache line from this region that is evicted from the cache, the reference count field 430 is decremented. Eventually, when the reference count field 430 reaches zero, the cache directory entry (e.g., entry 406) is marked invalid and the entry may be reused for another region in memory. Utilizing the reference count field 430 can reduce the incidence of region invalidation probes. The reference count field 430 allows a cache directory entry to be reused if it is associated with a region that no longer has active cache lines in the processor system's cache.

[0027] For example, returning to FIG. 4 , assuming the bit width of each entry is fixed, tag bits from tag field 435 are shifted into reference count field 430 to double the region size of each cache directory entry. For a 2K region and a 48-bit address width, the first 11 [10-0] bits are used for the offset, defining the region size (2^11 = 2048 (2K)). Assuming a 64-byte cache line size and a 2 kilobyte (K) region size, the number of cache lines per region is 2K / 64, or 32 cache lines per region. Tag field 435 is the most significant 36 bits from [47-11] of the address, and the least significant 11 bits of the address correspond to the 2K region size as described above. Thus, reference count field 430 will have Z bits corresponding to the total number of cache lines to track, determined by the number of cache lines per CPU cluster and the total number of CPU clusters, as shown in cache directory entries 406 and 408.

[0028] Here, to increase the region size to 4k, according to one embodiment, one bit is reallocated from tag field 435 to reference count field 430, so that tag field 435 contains the most significant 35 bits from [47-12], with the least significant bits [11-0] being the offset for the 4k (2^12) region size. Now, for the same 64-byte cache line size, a 4k region would contain 4k / 64 or 64 cache lines per region. The reference count field 430 shown in cache entry 412 is Z+1 bits after shifting bits from tag field 435, which, in binary, doubles the number of lines being tracked. In other embodiments, the region may be decreased by reallocating bits from reference count field 430 to tag field 435, or two or more bits may be reallocated to and from tag field 435 and reference count field 430 to create larger or smaller region sizes.

[0029] The cluster valid field 425 contains a bit vector for tracking the presence of cache lines within a core complex (e.g., CPUs 305A-305N in FIG. 3 ) associated with the defined region represented by the cache directory entry. For example, there may be eight CPU cores grouped together into four CPU clusters of two CPU cores each. In this example, the cluster valid field 425 has four bits, each bit representing two of the eight CPU cores in the processor system. For example, if the cluster valid field 425 vector is 1001, only the first and fourth CPU clusters are interacting with any of the cache lines represented by the region. In one embodiment, the sector valid field 420 stores a bit vector corresponding to a subgroup or sector of cache lines within the region, providing fine-grained tracking within the region. For example, as described above, for a 64-byte cache line and a 2 kilobyte (K) region size, the number of cache lines per region would be 2K / 64, or 32 cache lines per region. For an 8-bit sector valid field 420, each bit must track 32 / 8, or 4 cache lines per sector. For example, with the same 64-byte cache line size, if the region size is increased to 4K as described above, the number of cache lines tracked will be 4K / 64, or 64 lines per region. Then, for the same 8-bit sector valid field 420, each bit must track 64 / 8, or 8 cache lines per sector. The reduction in granularity may be acceptable in certain applications, for example, where the benefit of additional cache system coverage gained by increasing the region size is not widely shared across multiple cache complexes.

[0030] In one embodiment, the state field 415 includes state bits that specify the aggregate state of multiple cache lines in the cache line subsystem associated with the region. The aggregate state of the cache lines is defined by the most restrictive cache line state of each region. For example, the state field 415 of a cache directory entry associated with a region is set to "dirty" if at least one cache line in the entire region of multiple cache lines is dirty. Similarly, if at least one cache line in the entire given region is shared, the state of the given region is set to "shared." In various embodiments, there may be other states for a single cache line entry in the region that belongs to the entire region as well.

[0031] The organization of subgroups or sectors and the number of bits in sector valid field 420 may vary among different embodiments. In one embodiment described above, the sector valid field had 8 bits, but in other embodiments, the sector valid field may have additional bits to increase granularity or fewer bits to decrease granularity. Furthermore, in one embodiment, partitions may be identified using offsets stored in sector valid field 420. Each offset identifies the location of a given partition within a given region. In another embodiment, sector valid field 420 may indicate a separate owner and a separate status for each partition within a given region.

[0032] 5 is a flow diagram of a process 500 illustrating one embodiment of a method for changing the size of a region of memory and the number of cache lines tracked in each cache directory entry in a processor system. In one embodiment, process 500 is initiated at system startup by reading and executing configuration settings and instructions. In other embodiments, one or more programs or applications may be configured to automatically monitor cache utilization and dynamically initiate process 500, or may be configured to accept input, such as user input, to initiate process 500. In other embodiments, cache utilization may be monitored remotely for one or more computing systems, and each system may be configured to initiate process 500 based on a remote command.

[0033] At block 502, the processor system reconfigures the cache directory from tracking a first region size to a second region size, where the region size is defined by a starting address in memory (memories 340A-340N and 341A-341N in FIG. 3) and a number of offset bits removed from an address in a tag field (e.g., tag field 435 in FIG. 4) corresponding to the page size. The process continues at block 504, where the cache directory entry array fields are reconfigured by swapping at least one bit between the tag field and the reference count field (see FIG. 4). As described above, this reassignment increases or decreases the region corresponding to the memory page size and the number of cache lines tracked in the processor system, depending on the direction of the bit reassignment. Once the reconfiguration is complete, at block 506, the cache directory may track cache lines in the cache subsystem based on the reconfigured region size based on the bit reassignment.

[0034] 6 is a flow diagram of a process 600 illustrating one embodiment of a method for increasing or decreasing region size and reallocating regions based on utilization. Beginning at block 602, a home node in a processor system (e.g., processor system 300 of FIG. 3) receives a signal to reconfigure one or more cache directories from a first region size to a second region size as defined by a starting address in memory and a number of offset bits removed from an address in a tag field corresponding to a page size.

[0035] At decision block 604, the region size is increased or decreased based on the signal received at block 602. If increased, at block 606, in one embodiment, a cache directory controller in the cache directory (e.g., cache directory controller 402 in FIG. 4) configures the cache directory entry array (e.g., cache directory array 404 in FIG. 4) by reallocating one or more bits from the least significant bits of the tag field to the reference count field. Each reallocated bit doubles the region size defined by the address offset in the tag field, and each bit added to the reference field doubles the number of cache lines that the field can track in one or more cache subsystems of the processor system (e.g., cache subsystems 310A-310N in FIG. 3). In one embodiment, at block 608, the increased cache lines tracked means that each bit in the sector valid field tracks more cache lines based on the larger region size and the extended reference count field (see the 2K / 4K example described above with reference to sector valid field 420 in FIG. 4).

[0036] Similarly, to decrease the region size, in block 610, a cache directory controller in the cache directory configures the cache directory entry array by reallocating one or more bits from the reference count field to the tag field. Each reallocated bit halves the region size defined by the address offset in the tag field, and each bit taken from the reference field halves the number of cache lines that the field can track in one or more cache subsystems of the processor system. In one embodiment, in block 612, decreasing the tracked cache lines means that each bit in the sector valid field tracks fewer cache lines based on the smaller region size and reduced reference count field.

[0037] In one embodiment, in block 614, a reference count may be monitored to determine how many cache lines in the cache subsystem(s) of the processor system are subscribed to or utilized. For example, the reference count may be decremented for each cache line associated with the region that is evicted or incremented for each cache line that is added. In one embodiment, a change in region size is triggered when the reference count decrements below a threshold. While the blocks in FIG. 6 are shown as executing serially, in other embodiments, the blocks, e.g., blocks 606-614 or blocks 610-614, may execute in parallel or concurrently with one another.

[0038] A method is disclosed for maintaining a cache directory including one or more cache directory entries for tracking cache lines for a first region size and configuring one or more cache directory entries for tracking cache lines for a second region size, wherein each of the one or more cache directory entries includes a first field and a second field, the first field corresponding to a first region in a memory having a first page size, and the second field tracking a first number of cache lines stored in a cache subsystem associated with the first region.

[0039] Configuring one or more cache directory entries to track cache lines for a second region size includes swapping at least one bit between a first field and a second field in the cache directory to change the first region to a second region corresponding to a second page size in memory and to change a maximum number of cache lines tracked by each of the one or more cache directory entries. The swapping of at least one bit includes reallocating at least one bit from the least significant bits of the first field to the second field to increase the region size by increasing the number of offset bits. In one embodiment, the second region size is larger than the first region size, and reallocating at least one bit to the second field increases the maximum number of cache lines tracked in the cache subsystem to correspond to the increased region size.

[0040] Depending on the region size, the first page size may contain an amount of data equal to a multiple of two or more cache lines cached in the cache subsystem. In another embodiment, the process includes configuring a second cache directory from tracking cache lines for the first region size to tracking cache lines for a second region size, the second cache directory coupled to the home node by a data fabric. In yet another embodiment, the process includes changing the number of cache lines tracked per bit in a third field of the one or more cache entries based on configuring one or more cache directory entries to track cache lines of the second region size. The process may include, for each entry of the one or more cache directory entries, reallocating the entry to track another portion of memory if a value of the second field in the entry reaches a threshold.

[0041] In one embodiment, the processing system includes one or more home nodes coupled to one or more cache directories, each cache directory capable of changing from tracking cache lines for a first region size per cache line entry to tracking cache lines for a second region size per cache line entry, the first region size associated with a first page size of memory and the second region size associated with a second page size of memory. The processing system further includes a plurality of processing nodes coupled to the one or more home nodes, each processing node including one or more processors and a cache subsystem containing cache lines tracked by the one or more cache directories.

[0042] A processing system for changing from tracking cache lines from a first region size per cache line entry to tracking cache lines for a second region size per cache line entry may include one or more cache directories for exchanging at least one bit between a first field and a second field of each cache line entry. In one embodiment, each of the one or more home nodes may receive a signal to initiate an exchange in the one or more cache directories of at least one bit between the first field and the second field. The processing system for exchanging at least one bit may reallocate at least one bit from a least significant bit of the first field to the second field, wherein the loss of the at least one bit in the first field increases the second region size compared to the first region size and the addition of the at least one bit in the second field increases the maximum number of cache lines tracked by each of the one or more cache directory entries.

[0043] In one embodiment, the second page size comprises an even multiple of two or more cache lines cached in the cache subsystem. In another embodiment, at least one of the one or more home nodes may configure a second cache directory from tracking cache lines for the first region size to tracking cache lines for the second region size, the second cache directory being coupled to the coherent slave by a data fabric. At least one of the one or more home nodes may change, in at least one of the one or more cache directories, the number of cache lines tracked per bit in a third field of one or more cache directory entries for tracking cache lines of the second region size.

[0044] In one embodiment, the cache directory includes one or more cache entries and may change from tracking cache lines for a first region size per cache line entry to tracking cache lines for a second region size per cache line entry. The first region size is associated with a first page size of the memory, and the second region size is associated with a second page size of the memory. A cache directory controller may be coupled to the cache directory and may swap at least one bit between a first field and a second field of each cache entry in one or more cache entries to change from the first region size to the second region size. In one embodiment, for the cache directory controller to swap at least one bit, there is a reallocation of at least one bit from a least significant bit of the first field to the second field, wherein the loss of at least one bit in the first field increases the second region size compared to the first region size and the addition of at least one bit in the second field increases the maximum number of cache lines tracked by each of the one or more cache directory entries. In one embodiment, the second page size includes an even multiple of two or more cache lines cached in the cache subsystem.

[0045] The embodiments described herein may include various operations. These operations may be performed by hardware components, software, firmware, or a combination thereof. As used herein, the term "coupled to" may mean directly or indirectly coupled through one or more intervening components. Any of the signals provided via the various buses described herein may be time-shared with other signals and provided via one or more common buses. Furthermore, interconnections between circuit components and blocks may be depicted as buses or single signal lines. Each of the buses may alternatively be one or more single signal lines, and each of the single signal lines may alternatively be a bus.

[0046] Certain embodiments may be implemented as a computer program product, which may include instructions stored on a non-transitory computer-readable storage medium. These instructions may be used to program a general-purpose or special-purpose processor to perform the described operations. A computer-readable storage medium includes any mechanism for storing or transmitting information in a form (e.g., software, processing application) readable by a machine (e.g., a computer). Non-transitory computer-readable storage media may include, but are not limited to, magnetic storage media (e.g., floppy diskettes), optical storage media (e.g., CD-ROMs), magneto-optical storage media, read-only memory (ROM), random access memory (RAM), erasable programmable memory (e.g., EPROM and EEPROM), flash memory, or another type of medium suitable for storing electronic instructions.

[0047] Additionally, some embodiments may be implemented in a distributed computing environment where a computer-readable storage medium is stored on and / or executed by more than one computer system. Further, information transferred between computer systems may be pulled or pushed through a transmission medium connecting the computer systems.

[0048] Although the operations of the method(s) herein are shown and described in a particular order, the order of the operations of each method may be changed such that certain operations may be performed in the reverse order or such that certain operations may be performed at least in part concurrently with other operations. In alternative embodiments, instructions or sub-operations of individual operations may be performed intermittently and / or alternately.

[0049] In the foregoing specification, the embodiments have been described with reference to specific exemplary embodiments thereof. It will be apparent, however, that various modifications and changes can be made thereto without departing from the broader scope of the embodiments as set forth in the appended claims. The specification and drawings are therefore to be regarded in an illustrative rather than a restrictive sense.

Claims

1. 1. A method comprising: maintaining a cache directory including one or more cache directory entries each tracking a cache line of the first region size using a number of bits; reconfiguring the one or more cache directory entries to use the number of bits to respectively track cache lines of a second region size different from the first region size, wherein the reconfiguring includes changing a number of cache lines tracked for each bit of the number of bits. method.

2. each of the one or more cache directory entries comprising a first field and a second field, the first field corresponding to a first region in memory having a first page size, and the second field tracking a first number of cache lines stored in a cache subsystem associated with the first region; 10. The method of claim 1.

3. reconfiguring the one or more cache directory entries to track cache lines of a second region size includes changing the first region to a second region corresponding to a second page size in the memory and swapping at least one bit of the number of bits between the first field and the second field of the one or more cache directory entries to change a maximum number of cache lines tracked by each of the one or more cache directory entries. The method of claim 2.

4. and exchanging at least one bit of the number of bits includes reallocating the at least one bit from a least significant bit of the first field to the second field to increase the region size by increasing the number of offset bits. The method of claim 3.

5. the second region size is larger than the first region size; reallocating at least one bit of the number of bits to the second field increases the maximum number of cache lines tracked within the cache subsystem to correspond to the second region size. The method of claim 4.

6. the first page size includes an amount of data equal to a multiple of two or more cache lines cached in the cache subsystem; The method of claim 2.

7. and reconfiguring a second cache directory from tracking cache lines of the first region size to tracking cache lines of the second region size, the second cache directory being coupled to a home node.

10. The method of claim 1.

8. Changing the number of cache lines tracked for each bit of the number of bits includes changing a value in a third field of each of the one or more cache directory entries to specify the number of cache lines tracked for each bit of the number of bits.

10. The method of claim 1.

9. and reallocating the cache directory entry to track another portion of memory when, for each of the one or more cache directory entries, a value of a second field in the cache directory entry reaches a threshold.

10. The method of claim 1.

10. 1. A system comprising: one or more home nodes coupled to one or more cache directories, each of the one or more home nodes configured to reconfigure cache directory entries of at least one of the one or more cache directories from tracking cache lines of a first region size per cache directory entry to tracking cache lines of a second region size per cache directory entry while maintaining a number of bits included in each of the one or more cache directory entries, the first region size being associated with a first page size of memory and the second region size being associated with a second page size of memory that is different from the first page size of memory; at least one of the one or more home nodes is configured to modify, in at least one of the one or more cache directories, a number of cache lines tracked per bit in a field of a cache directory entry of at least one of the one or more cache directories of the second region size; system.

11. a plurality of processing nodes coupled to the one or more home nodes; each processing node comprising one or more processors and a cache subsystem containing cache lines tracked by said one or more cache directories; The system of claim 10.

12. each of the one or more home nodes is configured to reconfigure cache directory entries of the one or more cache directories from tracking cache lines of the first region size to tracking cache lines of the second region size by swapping at least one bit of the number of bits between a first field and a second field of each cache directory entry; The system of claim 10.

13. each of the one or more home nodes configured to receive a signal to initiate an exchange of at least one bit of the number of bits of each cache directory entry of the one or more cache directories; The system of claim 12.

14. exchanging the at least one bit includes reallocating at least one bit from a least significant bit of the first field to the second field, the loss of the at least one bit in the first field increasing the second region size compared to the first region size, and the reallocation of the at least one bit in the second field increasing a maximum number of cache lines tracked by each of the cache directory entries. The system of claim 12.

15. the second page size comprises an even multiple of two or more cache lines cached in the cache subsystem; The system of claim 11.

16. at least one of the one or more home nodes is configured to reconfigure a second cache directory from tracking cache lines of the first region size to tracking cache lines of the second region size; the second cache directory is coupled to a coherent slave; The system of claim 10.

17. 1. A computing device comprising: a cache directory including one or more cache directory entries, the cache directory configured to change from tracking cache lines of a first region size per cache directory entry to tracking cache lines of a second region size per cache directory entry while maintaining a number of bits included in each of the one or more cache directory entries; the first region size is associated with a first page size of memory, and the second region size is associated with a second page size of memory that is different from the first page size of memory; the computing device is configured to change to tracking cache lines of the second region size by changing a number of cache lines tracked per bit of the number of bits. Computing devices.

18. a cache directory controller coupled to the cache directory and configured to swap at least one bit of the number of bits between a first field and a second field of each cache directory entry in the one or more cache directory entries to change from tracking the first region size to tracking the second region size; 20. The computing device of claim 17.

19. the cache directory controller is configured to swap the at least one bit by reallocating the at least one bit from a least significant bit of the first field to the second field, wherein the loss of the at least one bit in the first field increases the second region size compared to the first region size and the addition of the at least one bit in the second field increases a maximum number of cache lines tracked by each of the one or more cache directory entries.

20. The computing device of claim 18.

20. the second page size comprises an even multiple of two or more cache lines cached in a cache subsystem; 20. The computing device of claim 17.

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