semiconductor integrated circuit device

Abstract

In a semiconductor integrated circuit device (100), a first semiconductor chip (101) comprises: an embedded power supply wiring line (21) supplied with a first power supply; and a power supply wiring line (41) that is provided in a layer above the embedded power supply wiring line (21) and that is supplied with a second power supply. The embedded power supply wiring line (21) is supplied with the first power supply from a back surface of the first semiconductor chip (101) via a first via electrode (31), and the power supply wiring line (41) is supplied with the second power supply from the back surface of the first semiconductor chip (101) via a second via electrode (32). The cross-section area of the second via electrode (32) is larger than the cross-section area of the first via electrode (31).

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor integrated circuit device having a buried power rail (BPR). [Background technology]

[0002] Due to the trend toward higher integration and lower voltages associated with miniaturization of semiconductor integrated circuits, designs must pay more attention to power supply voltage drop (IR-Drop) and power supply noise. For this reason, the design of the power delivery network (PDN) that supplies power to semiconductor integrated circuits becomes important.

[0003] Patent Document 1 discloses the structure of a power supply network in which buried power rails are provided in a buried interconnect layer embedded in the substrate of a semiconductor integrated circuit, and power is supplied from the back of the semiconductor integrated circuit via TSVs (Through Silicon Vias). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] U.S. Patent No. 10,636,739 (Fig. 7) Summary of the Invention [Problem to be solved by the invention]

[0005] However, in the configuration of Patent Document 1, power is supplied to the buried wiring layer, so if power is supplied to a wiring layer above the buried wiring layer, the resistance of the power supply network increases, causing a problem of a large power supply voltage drop. Also, if power is supplied to a transistor from the buried wiring layer, power supply noise generated in the transistor is likely to be transmitted to the upper wiring layer.

[0006] In particular, in a semiconductor integrated circuit device constructed by stacking semiconductor chips, when power is supplied from a lower semiconductor chip to an upper semiconductor chip, the problems of power supply voltage drop and power supply noise described above become prominent with respect to the power supplied to the upper semiconductor chip.

[0007] An object of the present disclosure is to make it possible to suppress power supply voltage drops and power supply noise in a semiconductor integrated circuit device that includes embedded power supply wiring. [Means for solving the problem]

[0008] In an aspect of the present disclosure, in a semiconductor integrated circuit device including a first semiconductor chip, the first semiconductor chip includes a substrate, a first embedded power wiring formed in an embedded wiring layer within the substrate and supplying a first power supply, and a first power wiring provided in a layer above the first embedded power wiring and supplying a second power supply, wherein the first embedded power wiring receives the first power supply from a back surface of the first semiconductor chip via a first through electrode, and the first power wiring receives the second power supply from the back surface of the first semiconductor chip via a second through electrode, and the cross-sectional area of ​​the second through electrode is larger than the cross-sectional area of ​​the first through electrode.

[0009] According to this aspect, the first power supply is supplied to the first embedded power wiring via the first through-electrode from the back surface of the first semiconductor chip, while the second power supply is supplied to the first power wiring provided in a layer above the first embedded power wiring via the second through-electrode from the back surface of the first semiconductor chip. That is, the supply of the first power supply to the first embedded power wiring and the supply of the second power supply to the first power wiring are realized by separate configurations. This reduces power supply noise for the second power supply due to transistors and the like associated with the first power supply. Furthermore, because the cross-sectional area of ​​the second through-electrode is larger than the cross-sectional area of ​​the first through-electrode, the resistance value in the supply path of the second power supply can be reduced, thereby suppressing power supply voltage drops for the second power supply. [Effects of the Invention]

[0010] According to the present disclosure, in a semiconductor integrated circuit device having embedded power wiring, it is possible to suppress power supply voltage drops and power supply noise. [Brief explanation of the drawings]

[0011] [Figure 1] Overall configuration of a semiconductor integrated circuit device according to an embodiment [Figure 2] Cross-sectional structure of the semiconductor integrated circuit device of FIG. [Figure 3] 1A and 1B are plan views of a first semiconductor chip, in which FIG. 1A shows the back surface and FIG. 1B shows the main surface. [Figure 4] Cross-sectional structure of the semiconductor integrated circuit device according to Modification 1 of FIG. [Figure 5] Cross-sectional structure of the semiconductor integrated circuit device according to Modification 2 of FIG. DETAILED DESCRIPTION OF THE INVENTION

[0012] Hereinafter, embodiments will be described with reference to the drawings.

[0013] (Embodiment) Fig. 1 is a diagram showing the overall configuration of a semiconductor integrated circuit device according to an embodiment. As shown in Fig. 1, a semiconductor integrated circuit device 100 is configured by stacking a first semiconductor chip 101 (chip A) and a second semiconductor chip 102 (chip B). In the stacked portion, the main surface of the first semiconductor chip 101 and the main surface of the second semiconductor chip 102 face each other.

[0014] The first semiconductor chip 101 is configured with a circuit including a transistor. The first semiconductor chip 101 is also configured with embedded power wiring that supplies a first power supply. The first power supply is supplied from the back surface of the first semiconductor chip 101. The second semiconductor chip 102 is configured with power wiring that supplies a second power supply. The second power supply is supplied from the back surface of the first semiconductor chip 101 to the second semiconductor chip 102 via the first semiconductor chip 101. For example, the first semiconductor chip 101 is a chip on which a logic circuit is mounted, and the second semiconductor chip 102 is a chip on which a memory is mounted.

[0015] Fig. 2 is a diagram showing a cross-sectional structure of the semiconductor integrated circuit device 100 of Fig. 1. Fig. 2 schematically shows a cross-sectional structure relating to the power supply terminals and signal terminals of the semiconductor integrated circuit device 100.

[0016] A first power supply and a second power supply are supplied to the first semiconductor chip 101 from the back surface. In the first semiconductor chip 101, embedded power supply wiring 21 that supplies the first power supply is provided in an embedded wiring layer in the substrate 10. One end of a first TSV 31 (corresponding to a first through electrode) is connected to the embedded power supply wiring 21, and the other end is exposed on the back surface of the first semiconductor chip 101. The embedded power supply wiring 21 receives the first power supply from the back surface of the first semiconductor chip 101 via the first TSV 31. The first power supply is supplied from the embedded power supply wiring 21 to a transistor or the like (not shown).

[0017] Furthermore, in the first semiconductor chip 101, a power supply terminal 41 (corresponding to the first power supply wiring) is formed on the uppermost wiring layer. One end of the second TSV 32 (corresponding to the second through-electrode) is connected to the power supply terminal 41, and the other end is exposed on the back surface of the first semiconductor chip 101. The power supply terminal 41 receives the second power supply from the back surface of the first semiconductor chip 101 via the second TSV 32. That is, the power supply terminal 41 is supplied with the second power supply without going through the embedded power supply wiring. The power supply terminal 41 and the second TSV 32 have the same central position in a planar view. Note that the central positions of the power supply terminal 41 and the second TSV 32 need only be approximately the same, and do not have to be exactly the same. Furthermore, the cross-sectional area of ​​the second TSV 32 is larger than that of the first TSV 31.

[0018] Signal terminals 42 are provided on the main surface of the first semiconductor chip 101. The signal terminals 42 are connected to transistors and the like (not shown) through vias 43 and 45, signal wiring 44 and the like.

[0019] The second semiconductor chip 102 has power terminals 51 and signal terminals 52 on its main surface. The power terminals 41 of the first semiconductor chip 101 and the power terminals 51 of the second semiconductor chip 102, and the signal terminals 42 of the first semiconductor chip 101 and the signal terminals 52 of the second semiconductor chip 102 are bonded together, for example, by hybrid bonding. Hybrid bonding is a technique for simultaneously bonding electrodes and insulating films together using a structure in which an insulating film is formed around the electrodes on the bonding surfaces of the chips. However, the method for bonding the terminals is not limited to this, and bonding using bumps or the like may also be used. In the second semiconductor chip 102, the second power supplied to the second power terminals 51 is supplied to transistors and the like (not shown) via wiring and vias.

[0020] 3A and 3B are plan views showing the configuration of the first semiconductor chip 101, where (a) is the back surface and (b) is the main surface.

[0021] As shown in Fig. 3(a), openings for supplying the first power supply and the second power supply are provided on the back surface of the first semiconductor chip 101, and the first TSV 31 and the second TSV 32 are formed in the openings, respectively. The second TSV 32 is larger in size than the first TSV 31 in a plan view. Note that, although the planar shapes of the first TSV 31 and the second TSV 32 are circular in Fig. 3(a), the present invention is not limited to this.

[0022] As shown in FIG. 3(b), power supply terminals 41 and signal terminals 42 are arranged on the main surface of the first semiconductor chip 101. The power supply terminals 41 are arranged in the same positions as the second TSVs 32 formed on the back surface in a plan view. The power supply terminals 41 are connected to power supply terminals 51 of the second semiconductor chip 102 arranged in opposing positions. The signal terminals 42 are connected to signal terminals 52 of the second semiconductor chip 102 arranged in opposing positions. Note that, although the planar shapes of the second power supply terminals 41 and the signal terminals 42 are rectangular in FIG. 3(b), the present invention is not limited to this.

[0023] Furthermore, the numbers and positions of the first and second TSVs 31, 32, power supply terminals 41 and signal terminals 42 shown in FIG. 3 are merely examples, and are not limited to those shown in FIG.

[0024] According to this embodiment, the following effect can be obtained. In first semiconductor chip 101, power supply to embedded power wiring 21 and power supply to power terminal 41 in the upper wiring layer are realized by separate configurations. That is, the first power supply is supplied to embedded power wiring 21 from the back surface of first semiconductor chip 101 via first TSV 31, while the second power supply is supplied to power terminal 41 from the back surface of first semiconductor chip 101 via second TSV 32. This makes it possible to reduce power supply noise caused by transistors and the like related to the first power supply with respect to the second power supply supplied to power terminal 41.

[0025] Furthermore, the cross-sectional area of ​​second TSV 32 that directly connects power supply terminal 41 and the back surface of first semiconductor chip 101 is larger than the cross-sectional area of ​​first TSV 31 that directly connects embedded power wiring 21 and the back surface of first semiconductor chip 101. This reduces the resistance value in the supply path of the second power supply, thereby suppressing a power supply voltage drop for the second power supply.

[0026] Furthermore, the effects of reducing power supply noise and suppressing power supply voltage drop of the second power supply described above are more pronounced in the configuration shown in this embodiment, i.e., in a configuration in which the first and second semiconductor chips 101, 102 are stacked and the second power supply is supplied from the first semiconductor chip 101 to the second semiconductor chip 102.

[0027] The configuration of this embodiment can be easily applied to the case where the power supplies to the first and second semiconductor chips 101 and 102 are separate power supplies.

[0028] (Variation 1) Fig. 4 is a diagram showing a cross-sectional structure according to Modification 1 of the semiconductor integrated circuit device 100 of Fig. 1. Like Fig. 2, Fig. 4 also shows a schematic cross-sectional structure of the power supply terminals and signal terminals of the semiconductor integrated circuit device 100.

[0029] The cross-sectional structure shown in Fig. 4 is substantially the same as the cross-sectional structure shown in Fig. 2. However, in the first semiconductor chip 101, the second TSV 32A is not directly connected to the second power supply terminal 41 (corresponding to the second power supply wiring), but is connected to the second power supply terminal 41 via the power supply wiring 45 (corresponding to the first power supply wiring) and the via 46. The power supply wiring 45 is located in a layer above the embedded power supply wiring 21.

[0030] An insulating film 61 is formed on the rear surface of the first semiconductor chip 101, and a wiring layer is provided in the insulating film 61, and power supply terminals 62 and 63 are formed in the wiring layer. The first TSV 31 is connected to the power supply terminal 62, and the second TSV 32A is connected to the power supply terminal 63. The wiring layer forming the power supply terminals 62 and 63 may be a single wiring layer or multiple wiring layers.

[0031] This modification also provides the same effects as the above-described embodiment, that is, it is possible to reduce power supply noise and suppress power supply voltage effects with respect to the second power supply supplied to the power supply terminal 41.

[0032] (Variation 2) Fig. 5 is a diagram showing a cross-sectional structure according to Modification 2 of the semiconductor integrated circuit device 100 of Fig. 1. Like Fig. 2, Fig. 5 also shows a schematic cross-sectional structure of the power supply terminals and signal terminals of the semiconductor integrated circuit device 100.

[0033] The cross-sectional structure shown in Fig. 5 is substantially the same as the cross-sectional structure shown in Fig. 4. However, in this modification, the first power supply and the second power supply are power supplies of the same voltage. Furthermore, power supply wiring 45A (corresponding to the first power supply wiring) connected to second TSV 32A is electrically connected to embedded power supply wiring 21 via power supply wiring 71 and vias 72 and 73.

[0034] Furthermore, embedded power supply wiring 22 is formed in an embedded wiring layer in substrate 10. Embedded power supply wiring 22 is connected to embedded power supply wiring 21 via power supply wiring 71 and vias 73 and 74. Embedded power supply wiring 22 is not connected to first TSV 31, and does not receive the first power supply from the back surface of first semiconductor chip 101.

[0035] According to this modification, power is strengthened by supplying power to embedded power wiring 21 both via first TSV 31 and via second TSV 32A. Furthermore, the second power supply from the back surface to the main surface of first semiconductor chip 101 does not pass through embedded power wiring, so power noise can be reduced and power supply voltage drops can be suppressed. [Industrial Applicability]

[0036] The present disclosure is useful for improving the performance of system LSIs, for example, because it can suppress power supply voltage drops and power supply noise in semiconductor integrated circuit devices equipped with embedded power supply wiring. [Explanation of symbols]

[0037] 10 Substrate 21 Buried power wiring 22 Embedded power wiring 31 1st TSV 32 2nd TSV 41 Power terminal 45,45A power wiring 100 Semiconductor integrated circuit device 101 First semiconductor chip 102 Second semiconductor chip

Claims

1. A semiconductor integrated circuit device including a first semiconductor chip, The first semiconductor chip A substrate; a first buried power supply wiring formed in a buried wiring layer in the substrate and supplying a first power supply; a first power supply wiring provided in a layer above the first embedded power supply wiring and supplying a second power supply; the first embedded power supply wiring receives the first power supply from a back surface of the first semiconductor chip via a first through electrode; the first power supply wiring receives the second power supply from a back surface of the first semiconductor chip via a second through electrode; The cross-sectional area of ​​the second through electrode is larger than the cross-sectional area of ​​the first through electrode. Semiconductor integrated circuit device.

2. 2. The semiconductor integrated circuit device according to claim 1, a second semiconductor chip stacked on the first semiconductor chip, the second semiconductor chip having a main surface facing the main surface of the first semiconductor chip; The second semiconductor chip receives the second power supply from the first semiconductor chip via the first power supply wiring. Semiconductor integrated circuit device.

3. 2. The semiconductor integrated circuit device according to claim 1, The first semiconductor chip a second power supply wiring provided in a layer above the first power supply wiring and electrically connected to the first power supply wiring; Semiconductor integrated circuit device.

4. 2. The semiconductor integrated circuit device according to claim 1, the first power supply and the second power supply are power supplies of the same voltage, In the first semiconductor chip, The first buried power supply wiring and the first power supply wiring are electrically connected to each other. Semiconductor integrated circuit device.

5. 2. The semiconductor integrated circuit device according to claim 1, The first semiconductor chip a second embedded power supply wiring formed in a buried wiring layer in the substrate, not receiving the first power supply from the back surface of the first semiconductor chip, and electrically connected to the first embedded power supply wiring; Semiconductor integrated circuit device.

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