Class D amplifier circuit

Abstract

To suppress a mounting area and reduce power consumption, in a capacitive load drive application.SOLUTION: A class-D amplifier circuit comprises a PWM modulation circuit, a first output driver, and a second output driver. The PWM modulation circuit has an output logic of N values (N is an odd number equal to or more than three). Each of the first and second output drivers has an output voltage level of (N-1) / 2+1 steps according to the output logic of the PWM modulation circuit. In a case where the output voltage levels of the first and second output drivers are equivalent to each other, output resistances by the first and second output drivers are a first output resistance, respectively. In a case where the output voltage levels of the first and second output drivers are different from each other, an output resistance by at least one of the first and second output drivers is a second output resistance larger than the first output resistance.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The embodiments herein relate to a class D amplifier circuit. [Background technology]

[0002] In recent years, high power efficiency is desirable for amplifier circuits such as audio amplifiers in order to reduce environmental impact. For example, Class D amplifier circuits are known to have lower losses and higher efficiency than other amplifier circuits.

[0003] For example, there is a capacitive load driving application of a class D amplifier circuit that aims to reduce power consumption by using a capacitive load such as a piezoelectric speaker or piezoelectric actuator instead of an inductive dynamic speaker or actuator. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] U.S. Patent No. 6,614,297 Summary of the Invention [Problem to be solved by the invention]

[0005] However, in capacitive load driving applications involving large-capacitance loads, when the applied voltage and input frequency are high, components with large rated currents and allowable losses must be installed to suppress resonance in the output LC filter, resulting in problems such as a large mounting area and difficulty in reducing power consumption due to the power consumption of these components.

[0006] SUMMARY OF THE INVENTION In view of the above, an object of the present invention is to reduce the mounting area and power consumption in capacitive load driving applications. [Means for solving the problem]

[0007] In order to solve the above-mentioned problems and achieve the object, a class D amplifier circuit according to an embodiment includes a PWM modulation circuit, a first output driver, and a second output driver. 3 values The first output driver and the second output driver have an output logic corresponding to the output logic of the PWM modulation circuit. 2 When the output voltage levels of the first output driver and the second output driver are equal, the output resistances of the first output driver and the second output driver are each a first output resistance. When the output voltage levels of the first output driver and the second output driver are different, the output resistance of at least one of the first output driver and the second output driver is a second output resistance greater than the first output resistance. [Effects of the Invention]

[0008] According to the present invention, in capacitive load driving applications, it is possible to reduce the mounting area and power consumption. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a diagram showing an example of the configuration of a class-D amplifier circuit according to the first embodiment. [Figure 2] FIG. 2 is a diagram showing an example of the operating waveforms of each part of the class-D amplifier circuit of FIG. [Figure 3] FIG. 3 is a diagram showing an example of the configuration of a general class D amplifier circuit in which the on-resistance state does not change according to the output logic of a PWM signal, unlike the class D amplifier circuit according to the embodiment. [Figure 4] FIG. 4 is a diagram showing an example of an operational waveform of each part of the class-D amplifier circuit of FIG. [Figure 5] FIG. 5 is a diagram illustrating an example of the frequency characteristics of the LC filter of the class D amplifier circuit of FIG. [Figure 6] FIG. 6 is a diagram illustrating an example of the configuration of a class-D amplifier circuit according to the second embodiment. [Figure 7]FIG. 7 is a diagram showing an example of the configuration of a gate control circuit on the high side in the class-D amplifier circuit of FIG. [Figure 8] FIG. 8 is a diagram illustrating an example of the configuration of a class-D amplifier circuit according to the third embodiment. [Figure 9] FIG. 9 is a diagram illustrating an example of the configuration of a class-D amplifier circuit according to the fourth embodiment. [Figure 10] FIG. 10 is a diagram showing an example of the operating waveforms of each part of the class-D amplifier circuit of FIG. [Figure 11] FIG. 11 is a diagram illustrating an example of the configuration of a class-D amplifier circuit according to the fifth embodiment. [Figure 12] FIG. 12 is a diagram illustrating an example of the configuration of a class-D amplifier circuit according to the sixth embodiment. [Figure 13] FIG. 13 is a diagram showing an example of the operating waveforms of each part of the class-D amplifier circuit of FIG. [Figure 14] FIG. 14 is a diagram illustrating an example of the configuration of a class-D amplifier circuit according to the seventh embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, embodiments of a class-D amplifier circuit will be described in detail with reference to the drawings. In the following embodiments, parts with the same reference numerals perform similar operations, and duplicated descriptions will be omitted as appropriate. In the following embodiments, "connection" means "electrical connection."

[0011] (First embodiment) FIG. 1 is a diagram showing an example of the configuration of a class-D amplifier circuit 101 according to the first embodiment.

[0012] 1, an input terminal IN of the class D amplifier circuit 101 is connected to the ground potential via an input signal source V101. An input signal, such as an audio signal, is input to the input terminal IN from the input signal source V101.

[0013] As shown in Fig. 1, an LC filter is connected to the output terminals OUTP and OUTN of the class-D amplifier circuit 101. The LC filter is configured to filter the signals output from the output terminals OUTP and OUTN and smooth them into analog signals. Specifically, the LC filter has an inductor L101P and a capacitive load CLOAD. One end of the capacitive load CLOAD is connected to the positive output terminal OUTP via the inductor L101P, and the other end is connected to the negative output terminal OUTN.

[0014] The class-D amplifier circuit 101 is configured to amplify an input signal from an input signal source V101 using a power supply voltage from an external power supply (not shown) and output the amplified pulse signal from output terminals OUTP and OUTN. In the following description, the potential of the positive power supply terminal connected to the external power supply (not shown) may be referred to as VDD. Similarly, the potential of the negative power supply terminal may be referred to as VSS or ground.

[0015] 1, the class-D amplifier circuit 101 includes a ternary PWM modulation circuit X102, an XOR gate X105, inverters X103, X104, and X106, OR gates X107 and X109, AND gates X108 and X110, PMOS transistors M101, M103, M105, and M107, and NMOS transistors M102, M104, M106, and M108. Here, the XOR gate X105, the inverters X103 and X106, the OR gate X107, the AND gate X108, the PMOS transistors M101 and M103, and the NMOS transistors M102 and M104 are an example of a first output driver. Furthermore, the XOR gate X105, the inverters X104 and X106, the OR gate X109, the AND gate X110, the PMOS transistors M105 and M107, and the NMOS transistors M106 and M108 are an example of a second output driver.

[0016] The input terminal of the ternary PWM modulation circuit X102 is connected to the input terminal IN. The ternary PWM modulation circuit X102 is a PWM modulation circuit having a ternary output logic. In response to an input signal from an input signal source V101, the ternary PWM modulation circuit X102 outputs a PWM (Pulse Width Modulation) signal having a pulse width according to the amplitude of the input signal. In this embodiment, the PWM signal output from the positive output terminal and the PWM signal output from the negative output terminal are referred to as output signals PWMP and PWMN, respectively.

[0017] A pair of input terminals of the XOR gate X105 are connected to a pair of output terminals of the ternary PWM modulation circuit X102, respectively.

[0018] The input terminal of the inverter X103 is connected to the high-side output terminal of the ternary PWM modulation circuit X102. The input terminal of the inverter X104 is connected to the low-side output terminal of the ternary PWM modulation circuit X102. The input terminal of the inverter X106 is connected to the output terminal of the XOR gate X105.

[0019] A pair of input terminals of the OR gate X107 is connected to the output terminal of the XOR gate X105 and the output terminal of the inverter X103. A pair of input terminals of the OR gate X109 is connected to the output terminal of the XOR gate X105 and the output terminal of the inverter X104.

[0020] A pair of input terminals of the AND gate X108 is connected to the output terminals of the inverters X103 and X106, and a pair of input terminals of the AND gate X110 is connected to the output terminals of the inverters X104 and X106.

[0021] The PMOS transistor M101 and the NMOS transistor M102 are each a high-side power transistor. The gates of the PMOS transistor M101 and the NMOS transistor M102 are connected to the output terminal (N101) of the inverter X103. The source of the PMOS transistor M101 is connected to a positive power supply terminal of an external power supply (not shown). The source of the NMOS transistor M102 is connected to a negative power supply terminal of the external power supply (not shown). The connection point of the drains of the PMOS transistor M101 and the NMOS transistor M102 is connected to a positive output terminal OUTP.

[0022] The PMOS transistor M105 and the NMOS transistor M106 are low-side power transistors. The gates of the PMOS transistor M105 and the NMOS transistor M106 are connected to the output terminal (N104) of the inverter X104. The source of the PMOS transistor M105 is connected to a positive power supply terminal of an external power supply (not shown). The source of the NMOS transistor M106 is connected to a negative power supply terminal of the external power supply (not shown). The connection point of the drains of the PMOS transistor M105 and the NMOS transistor M106 is connected to a negative output terminal OUTN.

[0023] The PMOS transistor M103 has a source connected to a positive power supply terminal of an external power supply (not shown) and a gate connected to the output terminal (N102) of the OR gate X107. The NMOS transistor M104 has a source connected to a negative power supply terminal of the external power supply (not shown) and a gate connected to the output terminal (N103) of the AND gate X108. The connection point of the drains of the PMOS transistor M103 and the NMOS transistor M104 is connected to the positive output terminal OUTP.

[0024] The PMOS transistor M107 has a source connected to a positive power supply terminal of an external power supply (not shown) and a gate connected to the output terminal (N105) of the OR gate X109. The NMOS transistor M108 has a source connected to a negative power supply terminal of the external power supply (not shown) and a gate connected to the output terminal (N106) of the AND gate X110. The connection point of the drains of the PMOS transistor M107 and the NMOS transistor M108 is connected to the negative output terminal OUTN.

[0025] The PMOS transistors M101 and M105 and the NMOS transistors M102 and M106 are each set to a high on-resistance.

[0026] An example of the operation of the class-D amplifier circuit 101 according to the embodiment will now be described with reference to the drawings. Fig. 2 is a diagram showing an example of the operating waveforms of the various parts of the class-D amplifier circuit 101 shown in Fig. 1.

[0027] The ternary PWM modulation circuit X102 outputs a positive output signal PWMP and a negative output signal PWMN in response to an input signal from an input terminal IN.

[0028] The inverter X103 outputs a logically inverted signal (N101) of the positive output signal PWMP, and drives the gates of the PMOS transistor M101 and NMOS transistor M102, which are high-side power transistors.

[0029] The OR gate X107 outputs a logical OR signal (N102) of the exclusive OR signal of the output signals PWMP, PWMN from the ternary PWM modulation circuit X102 and the logical inversion signal (N101) of the positive output signal PWMP from the inverter X103, and drives the gate of the PMOS transistor M103.

[0030] The AND gate X108 outputs a logical product signal (N103) of the logical inversion signal of the exclusive OR signal of the output signals PWMP and PWMN from the inverter X106 and the logical inversion signal (N101) of the positive output signal PWMP from the inverter X103, and drives the gate of the NMOS transistor M104.

[0031] The inverter X104 outputs a logically inverted signal (N104) of the negative output signal PWMN, and drives the gates of the PMOS transistor M105 and NMOS transistor M106, which are power transistors on the low side.

[0032] The OR gate X109 outputs a logical OR signal (N105) of the exclusive OR signal of the output signals PWMP, PWMN from the ternary PWM modulation circuit X102 and the logical inversion signal (N104) of the negative output signal PWMP from the inverter X104, and drives the gate of the PMOS transistor M107.

[0033] The AND gate X110 outputs a logical product signal (N106) of the logical inversion signal of the exclusive OR signal of the output signals PWMP and PWMN from the inverter X106 and the logical inversion signal (N104) of the negative output signal PWMP from the inverter X104, and drives the gate of the NMOS transistor M108.

[0034] The positive output terminal OUTP outputs a binary output voltage level according to the potential at the connection point of the PMOS transistor M101 and the NMOS transistor M102 and the potential at the connection point of the PMOS transistor M103 and the NMOS transistor M104.

[0035] The negative output terminal OUTN outputs a binary output voltage level according to the potential at the connection point of the PMOS transistor M105 and the NMOS transistor M106 and the potential at the connection point of the PMOS transistor M107 and the NMOS transistor M108.

[0036] The output signals from the output terminals OUTP and OUTN of the class D amplifier circuit 101 drive the capacitive load CLOAD in a BTL (Bridged Transformer Less) manner via the inductor L101P.

[0037] Generally, in amplifier circuits such as audio amplifiers, high power efficiency is desirable from the viewpoint of reducing environmental impact. For example, Class D amplifier circuits are known to have low loss and high efficiency compared to other amplifier circuits.

[0038] For example, there is a capacitive load driving application of a class-D amplifier circuit that uses a capacitive load such as a piezoelectric speaker or piezoelectric actuator instead of an inductive dynamic speaker or actuator to reduce power consumption. Here, as an example of a capacitive load driving application, a general class-D amplifier circuit 1201 will be described with reference to FIGS. 3 to 5. Here, differences from the class-D amplifier circuit 101 of FIG. 1 will be mainly described. FIG. 3 is a diagram showing an example of the configuration of a general class-D amplifier circuit 1201 that, unlike the class-D amplifier circuit 101 according to the embodiment, does not change its on-resistance state according to the output logic of the output signals PWMP and PWMN from the ternary PWM modulation circuit X1202. FIG. 4 is a diagram showing an example of the operating waveforms of each component of the class-D amplifier circuit 1201 of FIG. 3. FIG. 5 is a diagram showing an example of the frequency characteristics of an LC filter of the class-D amplifier circuit 1201 of FIG. 3.

[0039] Similar to the class D amplifier circuit 101 according to the embodiment of FIG. 1, the class D amplifier circuit 1201 of FIG. 3 includes a ternary PWM modulation circuit X1202, inverters X1203 and X1204, PMOS transistors M1201 and M1203, and NMOS transistors M1202 and M1204.

[0040] Here, the ternary PWM modulation circuit X1202 in Fig. 3 corresponds to the ternary PWM modulation circuit X102 in Fig. 1. The inverters X1203 and X1204 in Fig. 3 correspond to the inverters X103 and X104 in Fig. 1, respectively. The PMOS transistors M1201 and M1203 in Fig. 3 correspond to the PMOS transistors M101 and M105 in Fig. 1, respectively. The NMOS transistors M1202 and M1204 in Fig. 3 correspond to the NMOS transistors M102 and M106 in Fig. 1, respectively.

[0041] However, in the class D amplifier circuit 1201 of FIG. 3, the PMOS transistors M1201 and M1203 and the NMOS transistors M1202 and M1204 are each set to a low on-resistance, unlike the class D amplifier circuit 101 according to the embodiment of FIG. 1. As an example, the on-resistance of the PMOS transistor M1201 of FIG. 3 corresponds to the on-resistance when the PMOS transistors M101 and M103 of FIG. 1 are both on. The on-resistance of the NMOS transistor M1202 of FIG. 3 corresponds to the on-resistance when the NMOS transistors M102 and M104 of FIG. 1 are both on. The on-resistance of the PMOS transistor M1203 of FIG. 3 corresponds to the on-resistance when the PMOS transistors M105 and M107 of FIG. 1 are both on. The on-resistance of the NMOS transistor M1204 of FIG. 3 corresponds to the on-resistance when the NMOS transistors M106 and M108 of FIG. 1 are both on. That is, the output resistance (on-resistance state) of the first output driver does not change because only the PMOS transistors M101 and M103 or the NMOS transistors M102 and M104, which are power transistors in the class-D amplifier circuit 101 according to the embodiment of Fig. 1, are controlled to be either on or off. Similarly, the output resistance (on-resistance state) of the second output driver does not change because only the PMOS transistors M105 and M107 or the NMOS transistors M106 and M108, which are power transistors, are controlled to be either on or off.

[0042] As shown in Fig. 3, an LC filter is connected to the output terminals OUTP and OUTN of the class D amplifier circuit 1201. The LC filter is configured to filter the signals output from the output terminals OUTP and OUTN and smooth them into analog signals. Specifically, the LC filter has inductors L1201 and L1202 and a capacitive load CLOAD. One end of the capacitive load CLOAD is connected to the positive output terminal OUTP via inductor L1201, and the other end is connected to the negative output terminal OUTN via inductor L1202.

[0043] 3, external resistors R1201 and R1202 for suppressing resonance of the LC filter on the output side are connected to the output terminals OUTP and OUTN of the class D amplifier circuit 1201 in FIG.

[0044] In the class D amplifier circuit 1201 of FIG. 3, the gates of the PMOS transistor M1201 and the NMOS transistor M1202 are connected to the output terminal (N1201 in FIG. 4) of the inverter X1203. The input terminal of the inverter X1203 is connected to the positive output terminal of the ternary PWM modulation circuit X1202. The gates of the PMOS transistor M1203 and the NMOS transistor M1204 are connected to the output terminal (N1202 in FIG. 4) of the inverter X1204. The input terminal of the inverter X1204 is connected to the negative output terminal of the ternary PWM modulation circuit X1202. The sources of the PMOS transistors M1201 and M1203 are connected to the positive power supply terminal of an external power supply (not shown). The sources of the NMOS transistors M1202 and M1204 are connected to the negative power supply terminal of the external power supply (not shown). The connection point of the drains of the PMOS transistor M1201 and the NMOS transistor M1202 is connected to the positive output terminal OUTP, and the connection point of the drains of the PMOS transistor M1203 and the NMOS transistor M1204 is connected to the negative output terminal OUTN.

[0045] In the class-D amplifier circuit 1201 of Fig. 3, the ternary PWM modulation circuit X1202 outputs a positive-side output signal PWMP and a negative-side output signal PWMN in response to an input signal from the input terminal IN. The inverter X1203 outputs a logically inverted signal (N1201 in Fig. 4) of the positive-side output signal PWMP to drive the gates of the PMOS transistor M1201 and NMOS transistor M1202, which are high-side power transistors. The inverter X1204 outputs a logically inverted signal (N1202 in Fig. 4) of the negative-side output signal PWMN to drive the gates of the PMOS transistor M1203 and NMOS transistor M1204, which are low-side power transistors.

[0046] The output signals from the output terminals OUTP and OUTN drive the capacitive load CLOAD via BTL via inductors L1201 and L1202 and external resistors R1201 and R1202. At this time, since the output signals from the output terminals OUTP and OUTN are square waves, a large current would flow if the capacitive load CLOAD were driven directly. For this reason, the class-D amplifier circuit 1201 in FIG. 3 is configured to remove harmonic components using an LC filter including inductors L1201 and L1202 and the capacitive load CLOAD. Furthermore, in the LC filter, a resonance peak occurs at the LC resonance frequency, as shown in FIG. 5. For this reason, the class-D amplifier circuit 1201 in FIG. 3 is configured to reduce the Q value of the resonance peak by connecting external resistors R1201 and R1202 in series with the LC filter. Here, the inductance of the external inductors L1201 and L1202 is defined as L, the load capacitance of the capacitive load CLOAD is defined as C, and the resistance of the external resistor is defined as R. OUT The on-resistance of each of the power transistors, PMOS transistors M1201 and M1203 and NMOS transistors M1202 and M1204, is R ON Then, the Q value of the resonant frequency at the BTL output is expressed by the following equation:

[0047]

number

[0048] The on-resistance of each of the PMOS transistors M1201 and M1203 and the NMOS transistors M1202 and M1204 is R ON As mentioned above, is a sufficiently small value, so in adjusting the Q value, R OUT The value of V is dominant. SUP When the angular frequency is ω, the power consumption P when driving a capacitive load when the peak value of the output voltage is equal to the power supply voltage is SUP can be expressed by the following formula:

[0049]

number

[0050] However, in capacitive load driving applications incorporating a large-capacitance capacitive load, when the applied voltage and input frequency are high, components with large rated currents and allowable losses must be mounted to suppress resonance of the output-side LC filter, resulting in a problem of a large mounting area. For example, the above-described class-D amplifier circuit 1201 is mounted with external resistors R1201 and R1202. Furthermore, there is a problem in that it is difficult to reduce power consumption due to the power consumption of components for suppressing resonance of the output-side LC filter, such as the power consumption of the external resistors R1201 and R1202.

[0051] Therefore, the class D amplifier circuit 101 according to this embodiment is configured to transition the output resistance from the output terminals OUTP and OUTN of the class D amplifier circuit 101 between a high on-resistance state HS (second output resistance) and a low on-resistance state LS (first output resistance) according to the logic of each output signal PWMP and PWMN from the ternary PWM modulation circuit X102.

[0052] For example, if the logic levels of the output signals PWMP, PWMN from the ternary PWM modulation circuit X102 are different, the output signal of the XOR gate X105 will be "H." Therefore, regardless of the "H" ("L") output signals from the inverters X103 (N101) and X104 (N104), the OR gates X107 (N102) and X109 (N105) each output "H." Furthermore, because the output signal of the inverter X106 is "L," the AND gates X108 (N103) and X110 (N106) each output "L" regardless of the "H" ("L") output signals from the inverters X103 (N101) and X104 (N104). As a result, the PMOS transistors M103, M107 and NMOS transistors M104, M108, which are connected in parallel to the PMOS transistors M101, M105 and NMOS transistors M102, M106, respectively, are all turned off. As described above, the PMOS transistors M101, M105 and the NMOS transistors M102, M106 are each set to a high on-resistance. In other words, when the logics of the output signals PWMP, PWMN from the ternary PWM modulation circuit X102 are different, the output resistance from the output terminals OUTP, OUTN of the class D amplifier circuit 101 is in the high on-resistance state HS.

[0053] On the other hand, when the logic levels of the output signals PWMP and PWMN from the ternary PWM modulation circuit X102 are equal, the output signal of the XOR gate X105 becomes low level "L."

[0054] Therefore, when the output signals PWMP and PWMN from the ternary PWM modulation circuit X102 are both at high level "H," OR gates X107 (N102) and X109 (N105) each output an "L" output signal in response to the "L" output signals from inverters X103 (N101) and X104 (N104). Also, because the output signal of inverter X106 is "H," AND gates X108 (N103) and X110 (N106) each output an "L" output signal in response to the "L" output signals from inverters X103 (N101) and X104 (N104). As a result, PMOS transistors M103 and M107, which are connected in parallel to the on-state PMOS transistors M101 and M105, respectively, are turned on. That is, the PMOS transistors M101, M103, M105, and M107 are turned on, so that the output resistance from the output terminals OUTP and OUTN of the class D amplifier circuit 101 can be transitioned to the low on-resistance state LS.

[0055] Similarly, when the output signals PWMP and PWMN from the ternary PWM modulation circuit X102 are both "L," OR gates X107 (N102) and X109 (N105) each output an "H" output signal in response to the "H" output signals from inverters X103 (N101) and X104 (N104). Furthermore, because the output signal of inverter X106 is "H," AND gates X108 (N103) and X110 (N106) each output an "H" output signal in response to the "H" output signals from inverters X103 (N101) and X104 (N104). This causes the NMOS transistors M104 and M108, which are connected in parallel to the on-state NMOS transistors M102 and M106, respectively, to turn on. That is, the NMOS transistors M102, M104, M106, and M108 are turned on, so that the output resistance from the output terminals OUTP and OUTN of the class D amplifier circuit 101 can be transitioned to the low on-resistance state LS.

[0056] In this way, the class-D amplifier circuit 101 according to the embodiment is configured to transition the output resistance from the output terminals OUTP and OUTN in accordance with the logic of the output signals PWMP and PWMN from the ternary PWM modulation circuit X102. In other words, because a low on-resistance state and a high on-resistance state appear within one cycle of the PWM signal, the resonant current is reduced in the high on-resistance state, and the Q value of the LC filter can be equivalently reduced without providing an external resistor. Therefore, the class-D amplifier circuit 101 according to the embodiment does not require an external resistor, and therefore the mounting area can be reduced.

[0057] Here, the on-resistance in the high on-resistance state is R ON0 , the on-resistance in the low on-resistance state is R ON1 , the load capacitance of the capacitive load CLOAD is C, and the power supply voltage is V SUP When the capacitive load CLOAD is driven, the power consumption P D can be expressed by the following formula:

[0058]

number

[0059] In this way, the power consumption P of the class D amplifier circuit 101 of FIG. 1 shown in equation (3) D is the power consumption P of the class D amplifier circuit 1201 shown in FIG. 3, as shown in equation (2). SUP This is because, in the case of a capacitive load, the output voltage and the output current are out of phase with each other by 90 degrees, and therefore, in the class-D amplifier circuit 101 according to the embodiment, when the load current is large, the on-resistance is R ON1 That is, according to the class-D amplifier circuit 101 according to the embodiment, the power consumption P SUP This allows for lower power consumption compared to the conventional method.

[0060] (Second embodiment) 6 is a diagram showing an example of the configuration of a class-D amplifier circuit 301 according to the second embodiment. Here, differences from the class-D amplifier circuit 101 according to the first embodiment shown in FIG. 1 will be mainly described.

[0061] For example, in a high on-resistance state, the MOS transistor generates a large amount of heat, causing the junction temperature to rise. When the junction temperature rises, the on-resistance of a normal MOS transistor also increases. This further increases the junction temperature, which can lead to burnout of the MOS transistor. Therefore, in the second embodiment, a class-D amplifier circuit 301 capable of controlling the output resistance from the output terminals OUTP and OUTN in accordance with the junction temperature will be described.

[0062] As shown in FIG. 6, the class D amplifier circuit 301 according to this embodiment is similar to the class D amplifier circuit 101 according to the first embodiment shown in FIG. 1, except that it includes gate control circuits X301 to X304. Specifically, the high-side gate control circuit X301 is connected to the gate of the PMOS transistor M101 and the output terminal of the inverter X103. The high-side gate control circuit X302 is connected to the gate of the NMOS transistor M102 and the output terminal of the inverter X103. The low-side gate control circuit X303 is connected to the gate of the PMOS transistor M105 and the output terminal of the inverter X104. The low-side gate control circuit X304 is connected to the gate of the NMOS transistor M106 and the output terminal of the inverter X104. Here, the gate control circuits X301 to X304 are each an example of an output resistance control circuit.

[0063] Fig. 7 is a diagram showing an example of the configuration of the high-side gate control circuit X301 in the class-D amplifier circuit 301 of Fig. 6. The configuration of the high-side gate control circuit X303 is not shown, but is the same as the configuration in Fig. 7. The low-side gate control circuits X302 and X304 are not shown, but may be configured with only the polarity changed from the configuration in Fig. 7. For simplicity of the following explanation, the explanation will be continued using the high-side gate control circuit X301 as an example.

[0064] As shown in FIG. 7, the high-side gate control circuit X301 has current sources I401 and I402, a bipolar transistor Q401, an amplifier X401, NMOS transistors M401, M402, and M403, PMOS transistors M404 and M405, and resistors R401 and R402.

[0065] The current sources I401 and I402 are each connected to the positive power supply terminal of an external power supply (not shown). The bipolar transistor Q401 has an emitter connected to the output terminal of the current source I401, and a collector and base connected to ground. The non-inverting input terminal (+) of the amplifier X401 is connected to the connection point between the emitter of the bipolar transistor Q401 and the output terminal of the current source I401. The inverting input terminal (-) of the amplifier X401 is connected to ground via a resistor R401. The NMOS transistor M401 has a gate connected to the output terminal of the amplifier X401, a drain connected to the output terminal of the current source I402, and a source connected to the connection point between the inverting input terminal (-) of the amplifier X401 and the resistor R401.

[0066] The NMOS transistors M402 and M403 form a current mirror circuit. Specifically, the gate of the NMOS transistor M402 is connected to the gate of the NMOS transistor M403, the drain is connected to the output terminal of the current source I402, and the source is connected to ground. The connection point of the gates of the NMOS transistors M402 and M403 is connected to the drain of the NMOS transistor M402. The source of the NMOS transistor M403 is connected to ground.

[0067] The PMOS transistors M404 and M405 configure a source follower circuit. Specifically, the PMOS transistor M404 has a gate connected to the gate of the PMOS transistor M405, a drain connected to the drain of the NMOS transistor M403, and a source connected to the positive power supply terminal of an external power supply (not shown) via a resistor R402. The connection point between the gates of the PMOS transistors M404 and M405 is connected to the drain of the PMOS transistor M404. The PMOS transistor M405 has a source connected to the gate of the PMOS transistor M101, and a drain connected to ground.

[0068] In the class-D amplifier circuit 301 according to this embodiment, the gate control circuit X301 monitors the junction temperature using a bipolar transistor Q401 and generates a current inversely proportional to the rise in junction temperature using a resistor R401. The current mirror circuit mirrors the difference between the current generated in the resistor R401 and the current from a current source I402 (a constant current source), and generates a voltage proportional to the junction temperature using a resistor R402. The source follower circuit inputs the voltage generated in the resistor R402 to the gate of the PMOS transistor M101. Similarly to the gate control circuit X301, the gate control circuits X302 to X304 also control the voltage output to the gate of each MOS transistor in accordance with the junction temperature. Therefore, for each of the PMOS transistors M101 and M105 and the NMOS transistors M102 and M106, the gate-source voltage increases as the junction temperature rises, and therefore the on-resistance can be reduced as the junction temperature rises.

[0069] As described above, the class-D amplifier circuit 301 according to this embodiment is configured to control the output resistance from the output terminals OUTP and OUTN in accordance with the junction temperature. Specifically, the class-D amplifier circuit 301 according to this embodiment is configured to increase the gate-source voltage of the MOS transistor in accordance with the rise in junction temperature when the on-resistance increases with the rise in junction temperature. This configuration makes it possible to reduce the on-resistance that increases with the rise in junction temperature and realize control that maintains the on-resistance constant.

[0070] (Third embodiment) 8 is a diagram showing an example of the configuration of a class-D amplifier circuit 501 according to the third embodiment. Here, differences from the class-D amplifier circuit 101 according to the first embodiment shown in FIG. 1 will be mainly described.

[0071] In the first embodiment, the class-D amplifier circuit 101 transitions to a high on-resistance state when the logic levels of the output signals PWMP and PWMN are different, but this is not limiting. For example, even when the logic levels of the output signals PWMP and PWMN are different, the output resistance may transition to a low on-resistance state as long as the resonant current is suppressed and the Q value of the LC filter can be reduced.

[0072] As shown in Fig. 8, a class D amplifier circuit 501 according to this embodiment is similar to the class D amplifier circuit 101 according to the first embodiment shown in Fig. 1, except that it has a logic circuit configuration including a counter X501 and an AND gate X502. The logic circuit configuration including the counter X501 and the AND gate X502 is connected to the output terminal of the XOR gate X105. Specifically, one of a pair of input terminals of the AND gate X502 is connected to the output terminal of the XOR gate X105 via the counter X501. The output terminal of the AND gate X502 is connected to the inverter X106 and OR gates X107 and X109, similar to the output terminal of the XOR gate X105 in the class D amplifier circuit 101 according to the first embodiment shown in Fig. 1.

[0073] In the class-D amplifier circuit 501 according to this embodiment, the counter X501 counts the number of pulses when the logic of each output signal PWMP, PWMN is different, i.e., counts the number of "H" outputs from the XOR gate X105. The counter X501 is configured to output "H" when the count of "H" from the XOR gate X105 has not reached a predetermined count number, and to output "L" when the count reaches the predetermined count number. In other words, in the class-D amplifier circuit 501 according to this embodiment, the output resistance from the output terminals OUTP, OUTN can be transitioned to a low on-resistance state with a predetermined frequency when the logic of each output signal PWMP, PWMN is different.

[0074] The number of "H" counts by the counter X501 is determined in advance so as to reduce the frequency of occurrence of the high on-resistance state within a range in which the resonant current can be suppressed. In other words, the number of "H" counts by the counter X501 can be set arbitrarily while taking into consideration the balance between suppressing the resonant current due to the high on-resistance state and reducing the power consumption due to the low on-resistance state. For example, when the frequency of occurrence of the high on-resistance state is reduced to 1 / M, the power consumption P when driving the capacitive load CLOAD is reduced to 1 / M. D can be expressed by the following formula:

[0075]

number

[0076] In this way, the class D amplifier circuit 501 according to this embodiment is configured to transition the output resistance to a low on-resistance state for a predetermined period when the logic levels of the output signals PWMP and PWMN are different, within a range in which the resonant current can be suppressed and the Q value of the LC filter can be suppressed. With this configuration, the power consumption P of the class D amplifier circuit 101 in FIG. 1, as shown in equation (3), D This allows for even lower power consumption compared to the conventional method.

[0077] The technology according to the third embodiment can be appropriately combined with the technology according to each of the above-described embodiments.

[0078] (Fourth embodiment) Fig. 9 is a diagram showing an example of the configuration of a class D amplifier circuit 601 according to the fourth embodiment. Fig. 10 is a diagram showing an example of the operating waveforms of each part of the class D amplifier circuit 601 of Fig. 9. Here, differences from the class D amplifier circuit 101 according to the first embodiment of Fig. 1 will be mainly described.

[0079] In the first embodiment, the class-D amplifier circuit 101 is illustrated in which the PMOS transistors M101 and M105 and the NMOS transistors M102 and M106 are set to high on-resistance, and the PMOS transistors M103 and M107 and the NMOS transistors M104 and M108 are controlled to be on or off in accordance with the logic of the output signals PWMP and PWMN, thereby transitioning the on-resistance state. However, the present embodiment describes another configuration in which the on-resistance state transitions in accordance with the logic of the output signals PWMP and PWMN.

[0080] 9, the class-D amplifier circuit 601 according to this embodiment includes a ternary PWM modulation circuit X102, an XOR gate X601, inverters X602, X603, and X606, OR gates X604 and X605, PMOS transistors M601 and M603, and NMOS transistors M602 and M604. The XOR gate X601, the inverters X602 and X606, the OR gate X604, the PMOS transistor M601, and the NMOS transistor M602 are an example of a first output driver. The XOR gate X601, the inverters X603 and X606, the OR gate X605, the PMOS transistor M603, and the NMOS transistor M604 are an example of a second output driver.

[0081] Here, the XOR gate X601 in FIG. 9 corresponds to the XOR gate X105 in FIG. 1. The inverters X602 and X603 in FIG. 9 correspond to the inverters X103 and X104 in FIG. 1, respectively. The OR gates X604 and X605 in FIG. 9 correspond to the OR gates X107 and X109 in FIG. 1, respectively. The inverter X606 in FIG. 9 corresponds to the inverter X106 in FIG. 1. The PMOS transistor M601 in FIG. 9 corresponds to the pair of PMOS transistors M101 and M103 in FIG. 1. The NMOS transistor M602 in FIG. 9 corresponds to the pair of NMOS transistors M102 and M104 in FIG. 1. The PMOS transistor M603 in FIG. 9 corresponds to the pair of PMOS transistors M105 and M107 in FIG. 1. The NMOS transistor M604 in FIG. 9 corresponds to the pair of NMOS transistors M106 and M108 in FIG. 1. On the other hand, the class D amplifier circuit 601 in FIG. 9 does not have a configuration equivalent to the AND gates X108 and X110 in FIG.

[0082] In the class-D amplifier circuit 601 according to this embodiment, the PMOS transistors M601 and M603 are each set to a high on-resistance, while the NMOS transistors M602 and M604 are each set to a low on-resistance.

[0083] In the class D amplifier circuit 601 of Fig. 9, the output terminal of the XOR gate X601 is connected via an inverter X606 to one of the input terminals of each of the OR gates X604 and X605, similar to the output terminal of the XOR gate X105 of Fig. 1. The output terminal (N601) of the OR gate X604 is connected to the gates of the PMOS transistor M601 and the NMOS transistor M602. The connection point of the drains of the PMOS transistor M601 and the NMOS transistor M602 is connected to the positive output terminal OUTP. The output terminal (N602) of the OR gate X605 is connected to the gates of the PMOS transistor M603 and the NMOS transistor M604. The connection point of the drains of the PMOS transistor M603 and the NMOS transistor M604 is connected to the negative output terminal OUTN.

[0084] In the class-D amplifier circuit 601 according to this embodiment, when the logic of each output signal PWMP, PWMN from the ternary PWM modulation circuit X102 is different, the output signal of the XOR gate X601 is "H" and therefore the output signal of the inverter X606 is "L." Depending on the logic of each output signal PWMP, PWMN from the ternary PWM modulation circuit X102, one output signal of the OR gates X604 (N601) and X605 (N602) becomes "H" and the other output signal becomes "L."

[0085] For example, when the output signal PWMP is "H" and the output signal PWMN is "L", the output signal (N601) of the OR gate X604 becomes "H" and the output signal (N602) of the OR gate X605 becomes "L". At this time, with respect to the positive output terminal OUTP, the PMOS transistor M601 is in the OFF state and the NMOS transistor M602 is in the ON state. Also, with respect to the negative output terminal OUTN, the PMOS transistor M603 is in the ON state and the NMOS transistor M604 is in the OFF state.

[0086] Furthermore, for example, when the output signal PWMP is "L" and the output signal PWMN is "H", the output signal (N601) of the OR gate X604 becomes "L" and the output signal (N602) of the OR gate X605 becomes "H". At this time, with respect to the positive output terminal OUTP, the PMOS transistor M601 is in the ON state and the NMOS transistor M602 is in the OFF state. With respect to the negative output terminal OUTN, the PMOS transistor M603 is in the OFF state and the NMOS transistor M604 is in the ON state.

[0087] Therefore, in the class D amplifier circuit 601 according to the embodiment, when the logics of the output signals PWMP, PWMN from the ternary PWM modulation circuit X102 are different, the PMOS transistor set to a high on-resistance for either the output terminal OUTP or OUTN is turned on.

[0088] On the other hand, in the class-D amplifier circuit 601 according to this embodiment, when the logic levels of the output signals PWMP and PWMN from the ternary PWM modulation circuit X102 are equal, the output signal of the XOR gate X601 is “L” and the output signal of the inverter X606 is “H.” Therefore, the output signals of the OR gates X604 (N601) and X605 (N602) are both “H” regardless of the logic levels of the output signals PWMP and PWMN from the ternary PWM modulation circuit X102. Therefore, when the logic levels of the output signals PWMP and PWMN from the ternary PWM modulation circuit X102 are equal, the low-side MOS transistors set to low on-resistance for both the output terminals OUTP and OUTN are turned on. In other words, when the logic levels of the output signals PWMP and PWMN from the ternary PWM modulation circuit X102 are equal, the output voltage levels from the output terminals OUTP and OUTN are each at their minimum voltage levels.

[0089] In this way, the class-D amplifier circuit 601 according to the embodiment is configured to control the driving of the PMOS transistor set to a high on-resistance and the NMOS transistor set to a low on-resistance in accordance with the logic of each output signal PWMP, PWMN from the ternary PWM modulation circuit X102. In this configuration, the PMOS transistors M601, M603 are used only in the high on-resistance state, so the PMOS power transistors can be designed to be small enough to achieve the high on-resistance state, resulting in an effect of further reducing the mounting area.

[0090] (Fifth embodiment) 11 is a diagram showing an example of the configuration of a class-D amplifier circuit 801 according to the fifth embodiment. Here, differences from the class-D amplifier circuit 101 according to the first embodiment shown in FIG. 1 will be mainly described.

[0091] When handling a signal with a low input frequency while driving a capacitive load, the drive current is small and the switching current of the power transistor may become the dominant factor in the current consumption. Therefore, in this embodiment, a class-D amplifier circuit 801 configured to control the output resistance from the output terminals OUTP and OUTN in accordance with the switching current of the power transistor will be described.

[0092] As shown in FIG. 11 , a class-D amplifier circuit 801 according to this embodiment is similar to the class-D amplifier circuit 101 according to the first embodiment shown in FIG. 1 , except that it further includes a load current detection circuit X801 and an OR gate X802. The load current detection circuit X801 is configured to detect the drive current at the output terminals OUTP and OUTN. Specifically, the load current detection circuit X801 is configured to output “H” when it detects that the drive current is low for a predetermined period of time, i.e., when it detects a drive current equal to or lower than a predetermined threshold. One of a pair of input terminals of the OR gate X802 is connected to the output terminal of the XOR gate X105, and the other is connected to the output terminal of the load current detection circuit X801. The output terminal of the OR gate X802 is connected to the inverter X106 and OR gates X107 and X109, similar to the output terminal of the XOR gate X105 in the class-D amplifier circuit 101 according to the first embodiment shown in FIG. 1 .

[0093] In the class D amplifier circuit 501 according to this embodiment, if the load current detection circuit X801 does not detect a low drive current state for a certain period of time, the signal output from the load current detection circuit X801 to the OR gate X802 is "L." Therefore, if the load current detection circuit X801 does not detect a low drive current state for a certain period of time, the output of the OR gate X802 is the same as the output of the XOR gate X105. In other words, if the load current detection circuit X801 does not detect a low drive current state for a certain period of time, the class D amplifier circuit 501 according to this embodiment operates in the same manner as the class D amplifier circuit 101 according to the first embodiment of FIG. 1.

[0094] On the other hand, in the class-D amplifier circuit 501 according to this embodiment, when the load current detection circuit X801 detects that the drive current is low for a certain period of time, the load current detection circuit X801 outputs "H" to the OR gate X802. At this time, the output of the OR gate X802 is "H" regardless of the output of the XOR gate X105. In other words, when the load current detection circuit X801 detects that the drive current is low for a certain period of time, the class-D amplifier circuit 501 according to this embodiment turns off the PMOS transistors M103 and M107 and the NMOS transistors M104 and M108 regardless of the logic of the output signals PWMP and PWMN. As a result, the output resistance from the output terminals OUTP and OUTN transitions to a high on-resistance state.

[0095] In this way, the class-D amplifier circuit 801 according to this embodiment transitions the output resistance from the output terminals OUTP and OUTN to a high on-resistance state when the drive current is small, such as when handling a signal with a low input frequency. With this configuration, when there is little need to transition to a low on-resistance state, such as when the impedance of the class-D amplifier circuit 801 as seen from the capacitive load CLOAD is small, the output resistance from the output terminals OUTP and OUTN can be transitioned to a high on-resistance state. Furthermore, by turning off the PMOS transistors M103 and M107 and the NMOS transistors M104 and M108, the switching current of the power transistors can be reduced.

[0096] The technology according to the fifth embodiment can be combined with the technology according to each of the first to third embodiments as appropriate.

[0097] (Sixth embodiment) Fig. 12 is a diagram showing an example of the configuration of a class D amplifier circuit 901 according to the sixth embodiment. Fig. 13 is a diagram showing an example of the operating waveforms of each part of the class D amplifier circuit 901 of Fig. 12. Here, differences from the class D amplifier circuit 101 according to the first embodiment of Fig. 1 will be mainly described.

[0098] As shown in FIG. 12, a class D amplifier circuit 901 according to this embodiment is similar to the class D amplifier circuit 101 according to the first embodiment of FIG. 1, except that it has a logic circuit configuration including a timer X901 and an OR gate X902. The logic circuit configuration including the timer X901 and the OR gate X902 is connected to the output terminal of the XOR gate X105. Specifically, one of the pair of input terminals of the OR gate X902 is connected to the output terminal of the XOR gate X105 via the timer X901. In other words, one of the pair of input terminals of the OR gate X902 is connected to the output terminal (N901) of the timer X901. The output terminal of the OR gate X902 is connected to the inverter X106 and OR gates X107 and X109, similar to the output terminal of the XOR gate X105 in the class D amplifier circuit 101 according to the first embodiment of FIG. 1.

[0099] In the class D amplifier circuit 901 according to this embodiment, the timer X901 is configured to output “H” or “L” depending on the time that has elapsed since the voltage VLOAD across the load at the output terminals OUTP and OUTN has become close to the zero level.

[0100] When handling an audio signal such as a burst signal while driving a capacitive load, the output voltage and output current are out of phase with each other by 90 degrees, as shown in Figure 13. This means that even when the voltage VLOAD across the load reaches zero, the load current ILOAD remains at its maximum value, resulting in resonance at the LC resonant frequency of inductor L101P and load capacitance CLOAD. Therefore, when the voltage VLOAD across the load approaches zero and low on-resistance driving occurs frequently, the power consumption in the current path is very small, preventing the LC resonant current from decreasing, resulting in the generation of unwanted signals. Here, when the voltage VLOAD across the load approaches zero, the input signal from input terminal IN approaches zero, resulting in the output signals PWMP and PWMN of the ternary PWM modulation circuit X102 being in a state where the logic levels are equal more often than not, resulting in low on-resistance driving occurring more frequently.

[0101] Therefore, in the class-D amplifier circuit 901 according to this embodiment, the timer X901 measures the elapsed time from when the XOR gate X105 outputs "L," outputs "L" until the elapsed time reaches a predetermined time, and outputs "H" when the predetermined time is reached. When the output (N901) of the timer X901 becomes "H," the PMOS transistors M103 and M107 and the NMOS transistors M104 and M108 are turned off. That is, in the class-D amplifier circuit 901 according to this embodiment, when the input signal is near zero level for a certain period set by the timer X901, depending on the elapsed time from when the voltage VLOAD across the load becomes near zero level, the circuit enters a high on-resistance drive state, and the resonant current decreases.

[0102] In this way, the class-D amplifier circuit 901 according to this embodiment is configured to increase the frequency of high on-resistance driving when the load voltage VLOAD approaches zero, which increases the power consumption of the current path, causing the resonant current to be consumed as heat and reducing the resonant current.

[0103] The technology according to the sixth embodiment can be combined with the technology according to each of the first to third and fifth embodiments as appropriate.

[0104] (Seventh embodiment) 14 is a diagram showing an example of the configuration of a class-D amplifier circuit 1101 according to the seventh embodiment. Here, differences from the class-D amplifier circuit 101 according to the first embodiment shown in FIG. 1 will be mainly described.

[0105] As shown in FIG. 14, the class D amplifier circuit 1101 according to this embodiment has a logic circuit configuration including a timer X1101 and an OR gate X1102, and is similar to the class D amplifier circuit 101 according to the first embodiment shown in FIG. 1 except that an LC filter is added to the load end.

[0106] The logic circuit configuration including the timer X1101 and OR gate X1102 is connected to the output terminal of the XOR gate X105. Specifically, one of the pair of input terminals of the OR gate X1102 is connected to the output terminal (N1101) of the timer X1101, and the other is connected to the output terminal of the XOR gate X105. The output terminal of the OR gate X1102 is connected to the inverter X106 and OR gates X107 and X109, similar to the output terminal of the XOR gate X105 in the class D amplifier circuit 101 according to the first embodiment of FIG.

[0107] In consideration of radiation noise, an LC filter is connected to the output terminals OUTP and OUTN. In the example shown in Fig. 14, an LC filter including an inductor L101P and a capacitor C1101 is connected between the positive output terminal OUTP and the capacitive load CLOAD. Similarly, an LC filter including an inductor L101N and a capacitor C1102 is connected between the capacitive load CLOAD and the negative output terminal OUTN.

[0108] As shown in Figure 14, when an LC filter is connected to the output terminals OUTP and OUTN in consideration of radiation noise, LC resonance occurs between inductors L101P and L101N and capacitors C1101 and C1102, generating unwanted signals, as in the case described in the sixth embodiment.

[0109] Therefore, in the class D amplifier circuit 1101 according to this embodiment, the timer X1101 is configured to output an output signal of "H" until a predetermined time has elapsed since the class D amplifier circuit 901 is activated and switching has begun, and to output an output signal of "L" after the predetermined time has elapsed. As a result, for a certain period from the start of switching, the output signal (N1101) of the timer X1101 becomes "H," and the PMOS transistors M103, M107 and the NMOS transistors M104, M108 are turned off.

[0110] As described above, in the class D amplifier circuit 1101 according to this embodiment, the high on-resistance state HS is maintained for a certain period from the start of the switching operation, so that LC filter resonance at startup can be suppressed.

[0111] The technology according to the seventh embodiment can be combined with the technologies according to the first to third and fifth to sixth embodiments as appropriate.

[0112] In the above-described embodiments, a ternary PWM modulation circuit X102 having a three-value output logic is used, but a multilevel PWM modulation circuit having five or more values ​​of output logic may also be used. For example, if the PWM modulation circuit has an N-value (N is an odd number greater than or equal to 3) output logic, the output voltage levels from the output terminals OUTP and OUTN will each have (N-1) / 2+1 output voltage levels.

[0113] In addition, in the above-described embodiments, the power transistors connected to the positive output terminal OUTP and the negative output terminal OUTN are configured by PMOS transistors and NMOS transistors, as shown in Fig. 1, for example, but this is not limiting. NMOS transistors may be used instead of PMOS transistors, and even in this case, similar to the above-described embodiments, an equivalent on-resistance can be achieved with a small chip area.

[0114] Furthermore, a power transistor such as a GaN FET may be externally connected to the class-D amplifier circuit according to each of the above-described embodiments. This configuration makes it possible to further reduce the on-resistance of the class-D amplifier circuit according to each of the above-described embodiments.

[0115] According to at least one of the embodiments described above, it is possible to reduce the mounting area and power consumption in capacitive load driving applications.

[0116] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are intended to be included within the scope and spirit of the invention, as well as within the scope of the inventions and their equivalents as set forth in the claims. [Explanation of symbols]

[0117] 101,301,501,601,801,901,1101 Class D amplifier circuit CLOAD Capacitive load I401,I402 Current source IN input terminal L101P, L101N inductors M101, M103, M105, M107, M601, M603 PMOS transistors M102, M104, M106, M108, M602, M604 NMOS transistors OUTP, OUTN output terminals V101 Input signal source X102 3-value PWM modulation circuit X103, X104, X106, X602, X603, X606 inverter X105, X601 XOR gate X107, X109, X604, X605, X802, X902, X1102 OR gate X108, X110, X502 AND gate X301, X303, X302, X304 Gate control circuit X501 Counter X801 Load current detection circuit X901,X1101 timer

Claims

1. A PWM modulation circuit having three-value output logic; a first output driver and a second output driver each having two output voltage levels according to the output logic of the PWM modulation circuit; Equipped with when the output voltage levels of the first output driver and the second output driver are equal, the output resistances of the first output driver and the second output driver are each a first output resistance; When the output voltage levels of the first output driver and the second output driver are different, an output resistance of at least one of the first output driver and the second output driver is a second output resistance greater than the first output resistance. Class D amplifier circuit.

2. 2. The class D amplifier circuit according to claim 1, further comprising an output resistance control circuit that controls the output resistance of at least one of the first output driver and the second output driver, the output driver being the second output resistance, in accordance with a change in junction temperature in the output driver so that the second output resistance is kept constant.

3. 3. The class D amplifier circuit according to claim 1, further comprising a logic circuit configuration that counts the number of pulses at which the first output driver and the second output driver have different output voltage levels, and sets the output resistances of the first output driver and the second output driver as first output resistances until the number of pulses reaches a predetermined count number, and sets the output resistances of the first output driver and the second output driver as second output resistances when the number of pulses reaches the predetermined count number.

4. a load current detection circuit for detecting an output current from the first output driver and the second output driver; when the output current is equal to or less than a predetermined threshold for a predetermined period, an output resistance of the first output driver and the second output driver is the second output resistance regardless of an output voltage level of the first output driver and the second output driver; 4. The class D amplifier circuit according to claim 1.

5. 5. The class D amplifier circuit according to claim 1, further comprising a logic circuit configuration that measures an elapsed time since the output voltage levels of the first output driver and the second output driver become equal, sets output resistances by the first output driver and the second output driver to first output resistances until the elapsed time reaches a predetermined time, and sets output resistances by the first output driver and the second output driver to the second output resistances when the elapsed time reaches the predetermined time.

6. 6. The class D amplifier circuit according to claim 1, further comprising a logic circuit configuration that sets output resistances by the first output driver and the second output driver to the second output resistance, regardless of output voltage levels of the first output driver and the second output driver, until a predetermined time has elapsed from the start of a switching operation.

7. 2. The class D amplifier circuit of claim 1, wherein when the output voltage levels of the first output driver and the second output driver are equal, the output voltage levels of the first output driver and the second output driver are each a minimum voltage level.

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