Method for manufacturing a line device

Abstract

A process and structure for fabricating a line device structure that allows for miniaturization of the spacing between stress relief and contact window structures is provided. [Solution] The device comprises a substrate, a first metal pillar (68), and a second metal pillar, wherein the first metal pillar (68) is located on the substrate, and the maximum lateral dimension (Hw) of the first metal pillar (68) divided by the height (Ht) of the first metal pillar (68) is less than 4, and the height of the first metal pillar (68) is between 20 μm and 300 μm, and the second metal pillar is located on the substrate, and the maximum lateral dimension (Hw) of the second metal pillar (68) divided by the height of the second metal pillar (68) is less than 4, and the distance (Hb) from the center point of the first metal pillar to the center point of the second metal pillar (68) is between 10 μm and 250 μm.

Description

[Technical Field]

[0001] The present invention relates to a method for manufacturing a line device, and more particularly to a method for manufacturing a line device that effectively improves the performance of an IC. [Background technology]

[0002] Semiconductor wafers are used to manufacture ICs, which are becoming increasingly dense and feature-reducing. They provide interconnections and isolation between semiconductor devices on different layers through a structure of multiple conductive and insulating layers. For example, in large ICs containing active and passive devices, thin-film transistors (TFTs), CMOS transistors, capacitors, chokes, and resistors, numerous electromagnetic connections are required between different layers and semiconductor devices. At the same time, assembled ICs require a large number of wires. These wires pass through the protective layer inside the IC chip, are exposed to the outside, and ultimately connect to the input and output pads. These wires are then used to connect to the external contact structures of the chip packaging.

[0003] Wafer-Level Chip Scale Packaging (WLCSP) is a wafer-level packaging technology for IC chips. It differs from traditional chip-cutting and single-unit packaging processes. Therefore, WLCSP integrates wafer fabrication, packaging, testing, and wafer-level burn-in (WLBI) before cutting the chips into single units and packaging them into final chip carriers, such as ball grid array (BGA) packages. Its advantages include reduced volume and thickness, resulting in smaller dimensions, lighter weight, a relatively simple assembly process, lower overall production costs, and better electromagnetic characteristics. WLCSP also simplifies the process of transporting a single device from silicon to the customer, increasing IC chip packaging production and reducing costs. However, it faces significant challenges in terms of manufacturing capacity and structural reliability.

[0004] WLCSP can essentially be extended to the bonded device fabrication process and device protection fabrication process during wafer fabrication. The first step of WLCSP is to form post-passivation and extend the standard pad spacing through reconfigurable semiconductor IC line technology. This allows for the formation of low-cost solder strips and the realization of sill or aligned solder. Regarding reconfigurable technology, the applicants of patents 1-3, for example, are the same as those of the present invention. As disclosed in this patent, a single line layout layer connects the output and input pads of a semiconductor structure. The RDL layer is formed on a post-passivation polymer layer or elastic material layer. Post-shaped contact windows are fabricated on the RDL layer using a mask fabrication process. The post-shaped contact windows formed after the reaction are laterally independent and completely unsupported. Using flip-chip assembly technology, the structure formed after the reaction is then further assembled into a chip carrier package. Although this post-passivation structure and the corresponding fabrication process can improve the spacing problem present in IC packages, the ever-increasing integration requirements of ICs will place stricter limitations on the design and potential risk of stress-induced damage.

[0005] Patent Document 4 (Patent Document 4) includes a WLCSP with a post-passivation structure using a separate RDL layer. This RDL layer is formed on a polymer layer on top of the post-passivation, and another polymer layer is then placed over the RDL layer. Microvias are formed in this polymer layer by etching or drilling, and metal is then filled into the microvia holes to form interconnects, known as conductive pillars. However, the upper and lower polymer layers are isolated from each other by a chromium-copper layer to prevent contact with the RDL layer, and the other is attached to electroless screen-printed or stenciled tin-lead on the protruding tails of the conductive pillars. Because the conductive pillars extend outside the polymer layer and the top surface of the structure is not smooth, high-resolution lithography is not possible, making it impossible to form microvias with the conductive pillars and electroplated tin-lead. Ultimately, the spacing of contact windows in the IC package is limited. Moreover, this limitation becomes more pronounced as the thickness of the polymer layer increases, but as the thickness of the polymer layer increases, it still provides satisfactory stress relief.

[0006] This point will be discussed below. Also, as mentioned above, because the lower polymer layer is isolated from the upper polymer layer, the lower polymer layer cannot provide better stress relief on its own, and the thickness of the current lower polymer layer is made thin to reduce lateral movement of the RDL layer, resulting in somewhat weaker stress relief, an issue that will be discussed below.

[0007] One challenge in structural reliability is providing sufficient stress relief to the multilayer structure formed by WLCSP, which includes the semiconductor IC chip and the oversized post-passivation structure. To illustrate, a thin film bonded to the passivation layer is subjected to bi-shear stress, and this stress is thermally induced. Equation (1) shows the mathematical theory of the bi-shear stress in the post-passivation structure, and provides the physical parameters of the silicon substrate structure in the IC chip.

number

[0008] σppt: twin shear stress in post-passivation thin films R: Radius of curvature of the silicon substrate due to heat Ys: Young's modulus of silicon substrate vsi: Poisson's ratio of silicon substrate xSi: silicon substrate thickness xppt: Post-passivation thin film thickness From the above equation, besides increasing the Poisson's ratio of the silicon substrate, there are two ways to reduce the twin shear stress. (a) Decrease xSi, which means making the silicon substrate thinner, or (b) increase xppt, which means increasing the thickness of the post-passivation structure.

[0009] FIG. 1 shows a known post-passivation structure 10, which includes a RDL layer 12 and a stress-relief polymer layer 14. This stress-relief polymer layer 14, also known as a stress buffer layer, is formed on a protective layer 16 on the surface of a semiconductor IC chip 18. The polymer layer 14 can be made of an elastic material, epoxy resin, low-dielectric-constant material, or other polymeric material. The elastic material is primarily used to provide sufficient mechanical elasticity for the bonding structure. The inference in Equation (1) above indicates that covering the IC chip 18 with the polymer layer 14 fully absorbs or buffers the stress generated in the structure above the IC chip 18, thereby reducing localized damage to the IC chip 18 and improving the reliability of the post-passivation structure 10, especially for the precise and complex IC chip 18 electrical circuits. Furthermore, according to the relationship in Equation (1), the buffering effect improves as the thickness of the polymer layer 14 increases.

[0010] However, a problem often arises when using thick polymer layer 14. The RDL layer 12 shown in FIG. 1 is typically composed of copper and connects the input and output pads 20 of an IC chip 18 to external circuitry. When a tin-lead protrusion or copper conductive pillar is formed at the top of pad 20, either simultaneously or separately, the RDL layer 12 is tightly connected to the underlying package structure, which may be a single chip carrier. Therefore, the RDL layer 12 is defined by the polymer layer 14 as a sloped surface 22 with a certain degree of inclination. This RDL layer 12 gradually rises from a lower IC plane forming the input and output pads 20 to a higher IC plane. For example, the sloped surface 22 at the top of the polymer layer 14 is determined by the metallization process covering the openings in the thick polymer layer 14. In practical applications, the slope of the sloped surface 22 varies for each opening in the polymer layer 14, and the size of each opening is determined by the actual manufacturing process conditions and the underlying physical properties and characteristics of the polymer body. For example, the wetting contact angle is related to the energy of a material surface. For example, in many situations, the slope of the slope 22 of the polymer layer 14 on the IC protective layer 16 is approximately 45 degrees, so that the RDL layer 12 extends from the pad 20 in the IC to the top of the polymer layer 14 with a certain amount of lateral movement. Therefore, this lateral movement requires a certain amount of tolerance when fabricating the RDL layer 12. Finally, this tolerance allows for the slope of each type of slope 22 formed by different openings in the polymer layer 14. Because the lateral movement of each RDL layer is different, the spacing between adjacent contact windows is limited. The contact windows are jointly or separately defined by the tin-lead protrusions or copper bodies. The distance between the contact window structures and the openings in the protective layer increases accordingly, preventing the post-passivation structure from maintaining a fine spacing between the underlying package structure. Conversely, if a thick polymer layer 14 is not used, the stress buffering will be insufficient, resulting in stress-induced damage to the electrical traces in the precision IC chip. Also, the lateral support for the large conductive pillars will be insufficient, limiting the spacing distance of the input / output structures.However, large conductive pillar structures are necessary because they can provide sufficient distance to lower the coupling capacitance that occurs between the output / input pads 20 and the electromagnetic characteristic paths within the IC chip 18.

[0011] The above-mentioned proposal can be realized by reducing the spacing between the contact window structure on the post-passivation structure, which is causing the problem of hindering the integration scale in the IC.

[0012] Taking this into consideration, WLCSP and the corresponding fabrication process are proposed to improve stress relief while simultaneously achieving a smaller spacing distance for the contact window structures. [Patent Document 1] U.S. Patent No. 6,645,136 [Patent Document 2] U.S. Patent No. 6,784,087 [Patent Document 3] U.S. Patent No. 6,818,545 [Patent Document 4] U.S. Patent No. 6,103,552 DISCLOSURE OF THE INVENTION [Problem to be solved by the invention]

[0013] The main objective of the present invention is to provide a method for manufacturing a line device that can provide stress relief and minimize the spacing between contact window structures, with the spacing being 250 μm or less and the number of pinholes being limited to the target of 400 or less.

[0014] Another object of the present invention is to provide a method for manufacturing a line device, which includes a post-passivation structure supported by one RDL, which includes forming a support layer on the passivation layer with a relatively thinner thickness, e.g., a polymer layer, to support gaps between the RDL structures, and forming a support layer with a relatively thicker thickness, e.g., a polymer layer, to support gaps between the RDL structures between adjacent layered packing structures. [Means for solving the problem]

[0015] To achieve the above object, the present invention provides a method for manufacturing a line device, which includes providing a semiconductor base, a metal layer overlying the semiconductor base, and a first polymer layer overlying the semiconductor base and the metal layer, polishing the first polymer layer, forming a second polymer layer over the first polymer layer, and exposing the metal layer through an opening in the second polymer layer.

[0016] To achieve the above objectives, the present invention provides a method for manufacturing a line device. The manufacturing process includes providing a semiconductor base and a metal pillar located on the semiconductor base, where the maximum width of the metal pillar divided by the heights of the first and second metal pillars is less than 4, and the height of the first metal pillar is 20 μm to 300 μm. A first insulating layer is formed on the semiconductor base and covers the metal pillar. A second insulating layer is formed on the first insulating layer, exposing the first metal pillar in an opening in the second insulating layer.

[0017] To achieve the above objectives, the present invention provides a process and structure for fabricating a line device structure, comprising: a semiconductor wafer, a first metal layer disposed on the semiconductor wafer, and a polymer layer disposed on the semiconductor wafer and the first metal layer, wherein the semiconductor wafer includes a plurality of transistors, and the plurality of transistors incorporate trivalent or pentavalent ions into the semiconductor wafer; polishing the polymer layer; forming a second metal layer on the polymer layer and the first metal layer; forming a design-defining layer on the second metal layer, exposing the second metal layer in an opening in the design-defining layer; forming a third metal layer on the second metal layer exposed in the opening; removing the design-defining layer; and removing the second metal layer except for the area below the third metal layer.

[0018] To achieve the above objectives, the present invention provides a process and structure for fabricating a line device structure, comprising: a semiconductor wafer and a metal pillar located on the semiconductor wafer, the maximum width of the metal pillar divided by the height of the metal pillar being less than 4, and the height of the metal pillar being 20 μm to 300 μm; the semiconductor wafer including a plurality of transistors, the plurality of transistors incorporating trivalent and pentavalent ions into the semiconductor wafer; an insulating layer formed on the semiconductor wafer and covering the metal pillar; a first metal layer formed on the insulating layer and the metal pillar; a design-defining layer formed on the first metal layer, exposing the first metal layer in an opening in the design-defining layer; a second metal layer formed on the first metal layer exposed in the opening; the design-defining layer removed; and the first metal layer removed except for the portion below the second metal layer.

[0019] To achieve the above objectives, the present invention provides a process for fabricating a line device structure and the structure thereof, in which a semiconductor base, a first metal layer located on the semiconductor base, and a polymeric layer on the semiconductor base and the first metal layer are provided; the polymeric layer is polished; a protruding mass is formed on the first metal layer, the protruding mass including a second metal layer on the polymeric layer and the first metal layer; a design-defining layer is formed on the second metal layer, and an opening in the design-defining layer exposes the second metal layer; a third metal layer is formed on the second metal layer exposed in the opening; the design-defining layer is removed; and the second metal layer except for that below the third metal layer is removed.

[0020] To achieve the above objectives, the present invention provides a line structure fabrication device process and structure, which includes a semiconductor base and a metal pillar located on the semiconductor base, where the maximum width of the metal pillar divided by the height of the metal pillar is less than 4 and the height of the metal pillar is 20 μm to 300 μm. An insulating layer is formed on the semiconductor base to cover the metal pillar. An opening is formed in the insulating layer to expose the metal pillar.

[0021] To achieve the above objectives, the present invention provides a process and structure for fabricating a line device structure, which comprises providing a semiconductor substrate, a metal layer disposed on the semiconductor substrate, and a polymer layer disposed on the semiconductor substrate and the metal layer, polishing the polymer layer, and forming an opening in the polymer layer to expose the metal layer.

[0022] To achieve the above objectives, the present invention provides a process and structure for fabricating a line device structure, which includes a semiconductor base and a metal pillar located on the semiconductor base, where the maximum width of the metal pillar divided by the height of the metal pillar is less than 4 and the height of the metal pillar is 20 μm to 300 μm. An insulating layer is formed on the semiconductor base and covers the metal pillar. The insulating layer is then etched.

[0023] To achieve the above objectives, the present invention provides a process and structure for fabricating a line device structure, which comprises a semiconductor base, a metal pillar located on the semiconductor base, and a polymer layer located on the semiconductor base and the metal pillar, and removing the polymer layer to expose a top surface of the metal pillar, with the height from the top surface to the polymer layer being 10 μm to 150 μm.

[0024] To achieve the above objectives, the present invention provides a process for fabricating a line device structure and the structure thereof, which includes providing a semiconductor base, a metal layer overlying the semiconductor base, and a polymer layer overlying the semiconductor base and the metal layer, polishing the polymer layer, and etching the polymer layer.

[0025] To achieve the above objectives, the present invention provides a process and structure for fabricating a line device structure, in which a semiconductor substrate is provided, a polymer layer is provided on the semiconductor substrate, an opening in the polymer layer has a depth of 10 μm to 300 μm, a metal layer is formed on the polymer layer and in the opening, and the metal layer outside the opening is removed.

[0026] To achieve the above objectives, the present invention provides a process and structure for fabricating a line device structure, which includes a semiconductor base and a metal pillar located on the semiconductor base, where the maximum width of the metal pillar divided by the height of the metal pillar is less than 4 and the height of the metal pillar is 20 μm to 300 μm. An insulating layer is formed on the semiconductor base and covers the metal pillar. A protruding mass is formed on the metal layer. The protruding mass is connected to an external circuit. A second insulating layer is formed between the semiconductor base and the external circuit.

[0027] To achieve the above objectives, the present invention provides a process and structure for fabricating a line device structure, which includes providing a semiconductor base, a metal layer disposed on the semiconductor base, and a first polymer layer disposed on the semiconductor base and the metal layer, polishing the first polymer layer, forming a protruding mass on the metal layer, and connecting the protruding mass to an external circuit, and forming a second polymer layer between the semiconductor base and the external circuit.

[0028] To achieve the above object, the present invention provides a process for fabricating a line device structure and the structure thereof, the process comprising providing a semiconductor base, a metal layer disposed on the semiconductor base, and a first polymer layer disposed on the semiconductor base and the metal layer, polishing the first polymer layer, and forming a protruding mass on the metal layer, which includes an electroplating process.

[0029] To achieve the above objectives, the present invention provides a process and structure for fabricating a line device structure, which includes a semiconductor base and a metal pillar located on the semiconductor base, where the maximum width of the metal pillar divided by the height of the metal pillar is less than 4 and the height of the metal pillar is 20 μm to 300 μm. An insulating layer is formed on the semiconductor base and covers the metal pillar. A protruding portion is formed on the metal pillar, which is fabricated by an electroplating process.

[0030] To achieve the above objectives, the present invention provides a process and structure for fabricating a line device structure, which includes providing a semiconductor substrate, a metal layer disposed on the semiconductor substrate, and a polymer layer disposed on the semiconductor substrate and the metal layer, polishing the polymer layer, and forming a wire on the metal layer in a wire fabrication process.

[0031] To achieve the above objectives, the present invention provides a process and structure for fabricating a line device structure, which comprises a semiconductor base and a metal pillar located on the semiconductor base, the maximum width of the metal pillar divided by the height of the metal pillar being less than 4, and the height of the metal pillar being 20 μm to 300 μm. An insulating layer is formed on the semiconductor base and covers the metal pillar. A wire is formed in a wire fabrication process and connected to the metal pillar.

[0032] To achieve the above objectives, the present invention provides a process and structure for fabricating a line device structure, and provides a substrate for the process. A first metal pillar is disposed on the substrate, and the maximum width of the first metal pillar divided by the height of the first metal pillar is less than 4, and the height of the first metal pillar is 20 μm to 300 μm. A second metal pillar is disposed on the substrate, and the maximum width of the second metal pillar divided by the height of the second metal pillar is less than 4, and the height of the second metal pillar is 20 μm to 300 μm. The distance from the center point of the first metal pillar to the center point of the second metal pillar is 10 μm to 250 μm.

[0033] To achieve the above objectives, the present invention provides a process and structure for fabricating a line device structure, comprising: a semiconductor base; a first metal pillar disposed on the semiconductor base; a maximum width of the first metal pillar divided by the height of the first metal pillar being less than 4, and a height of the first metal pillar being 20 μm to 300 μm; a second metal pillar disposed on the semiconductor base; a maximum width of the second metal pillar divided by the height of the second metal pillar being less than 4, and a height of the second metal pillar being 20 μm to 300 μm; a second metal pillar having a diameter of 20 μm to 300 μm; an insulating layer disposed on the semiconductor base and covering the first and second metal pillars; a first protruding indentation formed on the first metal pillar; and a second protruding indentation formed on the second metal pillar; the distance from the center of the first protruding indentation to the center of the second protruding indentation being 10 μm to 250 μm.

[0034] To achieve the above objectives, the present invention provides a process and structure for fabricating a line device structure, which includes a semiconductor base. A first metal pillar is disposed on the semiconductor base, and the maximum width of the first metal pillar divided by the height of the first metal pillar is less than 4, and the height of the first metal pillar is 20 μm to 300 μm. A second metal pillar is disposed on the semiconductor base, and the maximum width of the second metal pillar divided by the height of the second metal pillar is less than 4, and the height of the second metal pillar is 20 μm to 300 μm. A metal line connects the top surface of the first metal pillar to the top surface of the second metal pillar, and the material of the metal line includes gold.

[0035] To achieve the above objectives, the present invention provides a process and structure for fabricating a line device structure, which includes providing a semiconductor base. A first metal pillar is disposed on the semiconductor base, and the maximum width of the first metal pillar divided by the height of the first metal pillar is less than 4, and the height of the first metal pillar is 20 μm to 300 μm. A second metal pillar is disposed on the semiconductor base, and the maximum width of the second metal pillar divided by the height of the second metal pillar is less than 4, and the height of the second metal pillar is 20 μm to 300 μm. A metal trace connects the top surface of the first metal pillar to the top surface of the second metal pillar. A polymer layer is disposed on the metal trace.

[0036] To achieve the above objectives, the present invention provides a process and structure for fabricating a line device structure, in which a semiconductor substrate is provided, a metal pillar is placed on the semiconductor substrate, the maximum width of the metal pillar divided by the height of the metal pillar is less than 4, and the height of the metal pillar is 20 μm to 300 μm, and a wire is formed during a wire fabrication process to connect the metal pillar and the polymer layer.

[0037] To achieve the above objectives, the present invention provides a process and structure for fabricating a line device structure, which comprises providing a semiconductor substrate, placing a metal pillar on the semiconductor substrate, and having a maximum width divided by a height of the metal pillar that is less than 4, and a height of the metal pillar ranging from 20 μm to 300 μm, placing a polymer layer on the metal line and covering the metal pillar, and forming a protruding nodule on the metal pillar with a thickness of 10 μm to 150 μm.

[0038] To achieve the above objectives, the present invention provides a process and structure for fabricating a line device structure, which comprises providing a semiconductor base. A metal pillar is disposed on the semiconductor base, and the maximum width of the metal pillar divided by the height of the metal pillar is less than 4, and the height of the metal pillar is 20 μm to 300 μm. A polymer layer is disposed on the semiconductor base and covers the metal pillar. A metal coil is disposed on the semiconductor base, and the thickness of the metal coil is 1 μm to 15 μm.

[0039] To achieve the above objectives, the present invention provides a process and structure for fabricating a line device structure, comprising: a semiconductor base on which a metal pillar is disposed, the maximum width of the metal pillar divided by the height of the metal pillar being less than 4, and the height of the metal pillar being 20 μm to 300 μm; a protruding indentation formed on the metal pillar, the protruding indentation comprising a gold layer having a thickness of 10 μm to 30 μm;

[0040] To achieve the above objectives, the present invention provides a process and structure for fabricating a line device structure, comprising: a semiconductor base; a metal pillar disposed on the semiconductor base, the maximum width of the metal pillar divided by the height of the metal pillar being less than 4, and the height of the metal pillar being 20 μm to 300 μm; a protruding indentation formed on the metal pillar, the protruding indentation comprising a titanium-containing gold layer.

[0041] To achieve the above objectives, the present invention provides a process and structure for fabricating a line device structure, comprising a semiconductor base, a metal pillar disposed on the semiconductor base, the maximum width of the metal pillar divided by the height of the metal pillar being less than 4, and the height of the metal pillar being 20 μm to 300 μm, and a protruding indentation formed on the metal pillar, the protruding indentation comprising a chromium-containing gold layer.

[0042] To achieve the above objectives, the present invention provides a process and structure for fabricating a line device structure, comprising: a semiconductor base on which a metal pillar is disposed, the maximum width of the metal pillar divided by the height of the metal pillar being less than 4, and the height of the metal pillar being 20 μm to 300 μm; a protruding indentation formed on the metal pillar, the protruding indentation comprising a tantalum-containing gold layer.

[0043] To achieve the above objectives, the present invention provides a process and structure for fabricating a line device structure, comprising: a semiconductor base; a metal pillar disposed on the semiconductor base; a maximum width of the metal pillar divided by its height being less than 4, and the height of the metal pillar being 20 μm to 300 μm; a first polymer layer disposed on the semiconductor base and covering the metal pillar; a substrate disposed; a protruding mass disposed between the metal pillar and the substrate; and a second polymer layer disposed between the substrate and the semiconductor base and covering the protruding mass.

[0044] The following detailed description will be given with specific examples and accompanying diagrams to make it easier to understand the purpose, technical contents, features and achieved effects of the present invention. BEST MODE FOR CARRYING OUT THE INVENTION

[0045] The present invention is a process and structure for fabricating a line device structure, in which a number of metal post structures are formed on a semiconductor substrate, and the spacing between adjacent metal posts is reduced to 250 μm or less. Several different embodiments are described below.

[0046] (First Example) The manufacturing process of the line device structure of the first embodiment is shown in FIG. First, a semiconductor substrate 30 is provided. This semiconductor substrate 30 may be a silicon substrate, a gallium arsenide (GaAs) substrate, a silicon germanium substrate, or a silicon-on-insulator (SOI) substrate. In this embodiment, the semiconductor substrate 30 is a circular semiconductor wafer. The semiconductor wafer 30 has a primary surface. The primary surface of the semiconductor wafer 30 is doped with pentavalent or trivalent ions (e.g., boron ions, phosphorus ions, etc.) to form several electronic devices 32. The electronic devices 32 may be metal oxide semiconductors, MOS devices, p-channel MOS devices, n-channel MOS devices, BICMOS devices, bipolar junction transistors (BJTs), diffusion areas, resistors, capacitors, CMOS, etc.

[0047] Referring to FIG. 3, a thin interconnect structure 34 is formed on the active surface of a semiconductor wafer 30. The thin interconnect structure 34 is composed of a plurality of thin insulating layers 36 each having a thickness of 3 μm or less and a thin track layer 38 each having a thickness of 3 μm or less, with the thin track layer 38 being made of copper or aluminum metal. The thin insulating layer 36, also known as a dielectric barrier, is typically formed by chemical vapor deposition (CVD) and may be silicon dioxide, chemical vapor deposition tetraethoxysilane (TEOS) oxide, SiCxOyHz, silicon nitride, or silicon oxynitride, or spin-on glass (SOG), fluorinated glass (FSG), silicon carbide (SiLK), black diamond, polyarylene ether, polybenzoxazole (PBO), or porous silicon oxide. Alternatively, the thin insulating layer 36 may be made of a material with a dielectric constant (FPI) of 3 or less.

[0048] During the formation of the plurality of thin line layers 38 on the semiconductor wafer 30, the metal damascene process first sputters a diffusion barrier layer onto the bottom and sidewalls of the openings in one of the thin film insulating layers 36 and onto the top surface of the thin film insulating layer 36. A seed layer, for example, made of copper, is sputtered onto the diffusion barrier layer, and then a copper layer is electroplated onto the seed layer. Then, photochemical mechanical polishing (CMP) is used to remove the copper layer, seed layer, and diffusion barrier layer outside the openings in the thin film insulating layer 36 until the top surface of the thin film insulating layer 36 is exposed. Another method is to first sputter an aluminum layer or aluminum alloy layer onto the thin film insulating layer 36, and then use lithographic etching to pattern the aluminum layer or aluminum alloy layer. These thin line layers 38 pass through through holes 40 in the thin film insulating layer 36 to connect to each other or to the electronic devices 32. The thin line layers 38 generally have a thickness of 0.1 μm to 0.5 μm. During the lithography process, the thin line layers 38 are fabricated using 5X steppers or scanners or better machines.

[0049] Next, a protective layer 42 is deposited on the surface of the semiconductor substrate 30 using chemical vapor deposition (CVD). This protective layer 42 has multiple cracks that expose pads 44, protecting the electronic devices 32 within the semiconductor substrate 30 from moisture and foreign ion contamination. That is, the protective layer 42 prevents mobile ions (e.g., sodium ions), moisture, transition metals (e.g., gold, silver, copper), and other impurities from penetrating and damaging the electronic devices 32 and thin metal lines of the transistors, polysilicon resistors, or polysilicon capacitors underneath the protective layer 42. To achieve this protection, the protective layer 42 is typically made of silicon oxide, silicon oxide compounds, silicon phosphide glass, silicon nitride, and silicon oxynitride.

[0050] The first method for fabricating the protective layer 42 involves first forming a silicon monoxide layer having a thickness of 0.2 μm to 1.2 μm using a chemical vapor deposition method, and then forming a silicon monoxide layer having a thickness of 0.2 μm to 1.2 μm on the silicon monoxide layer using a chemical vapor deposition method.

[0051] The second method for fabricating the protective layer 42 involves first forming a silicon monoxide layer with a thickness of 0.2 μm to 1.2 μm using a chemical vapor deposition process, and then forming a silicon monoxide layer with a thickness of 0.05 μm to 0.15 μm on the silicon oxynitride layer using a plasma-enhanced chemical vapor deposition process.

[0052] The third method for fabricating the protective layer 42 involves first using a chemical vapor deposition process to form a silicon oxynitride layer having a thickness of 0.05 μm to 0.15 μm, then using a chemical vapor deposition process to form a silicon monoxide layer having a thickness of 0.2 μm to 1.2 μm on the silicon oxynitride layer, and then using a chemical vapor deposition process to form a silicon monoxide layer having a thickness of 0.2 μm to 1.2 μm on the silicon oxide layer.

[0053] The fourth method for fabricating the protective layer 42 involves first forming a silicon monoxide layer 0.2 μm to 0.5 μm thick by chemical vapor deposition, then forming a silicon dioxide layer 0.5 μm to 1 μm thick on the silicon monoxide layer by spin coating, and then forming a silicon trinitride layer 0.2 μm to 1.2 μm thick on the silicon dioxide layer by chemical vapor deposition.

[0054] The fifth method for fabricating the protective layer 42 involves first forming a silicon monoxide layer 0.5 μm to 2 μm thick using high-density plasma chemical vapor deposition (HDP-CVD), and then forming a silicon mononitride layer 0.2 μm to 1.2 μm thick on the silicon oxide layer using chemical vapor deposition.

[0055] The sixth method for fabricating the protective layer 42 involves first depositing a 0.2 μm to 3 μm thick layer of undoped silicate glass (USG), followed by depositing a 0.5 μm to 3 μm thick insulating layer of, for example, tetraethoxysilane (TEOS) oxide-borophosphosilicate glass (BPSG) or phosphosilicate glass (PSG) on the undoped silicon glass. A 0.2 μm to 1.2 μm thick silicon mononitride layer is then deposited on the insulating layer by chemical vapor deposition.

[0056] The seventh method for fabricating the protective layer 42 alternatively involves first using a chemical vapor deposition process to form a silicon oxynitride layer having a thickness of 0.05 μm to 0.15 μm, and then using a chemical vapor deposition process to form a silicon monoxide nitride layer having a thickness of 0.2 μm to 1.2 μm on the silicon oxynitride layer or silicon oxide layer, or alternatively using a chemical vapor deposition process to first form a silicon trinitride layer having a thickness of 0.05 μm to 0.15 μm on the silicon nitride layer, and then using a chemical vapor deposition process to form a silicon oxide layer having a thickness of 0.2 μm to 1.2 μm on the silicon trinitride layer or silicon nitride layer.

[0057] The eighth method for fabricating the protective layer 42 involves first forming a silicon monoxide layer 0.2 μm to 1.2 μm thick using chemical vapor deposition (PECVD), then spin-coating a silicon dioxide layer 0.5 μm to 1 μm thick on the silicon monoxide layer, then chemical vapor depositing a silicon trinitride layer 0.2 μm to 1.2 μm thick on the silicon dioxide layer, then chemical vapor depositing a silicon mononitride layer 0.2 μm to 1.2 μm thick on the silicon trioxide layer, and finally chemical vapor depositing a silicon tetroxide layer 0.2 μm to 1.2 μm thick on the silicon nitride layer.

[0058] The ninth method for fabricating the protective layer 42 involves first using high-density plasma chemical vapor deposition (HDP-CVD) to form a silicon monoxide layer having a thickness of 0.2 μm to 2 μm, then using chemical vapor deposition to form a silicon mononitride layer having a thickness of 0.2 μm to 1.2 μm on the silicon monoxide layer, and then using high-density plasma chemical vapor deposition (HDP-CVD) to form a silicon dioxide layer having a thickness of 0.5 μm to 2 μm on the silicon nitride layer.

[0059] The tenth method for fabricating the protective layer 42 involves first using chemical vapor deposition to form a silicon monoxide layer having a thickness of 0.2 μm to 1.2 μm, then using chemical vapor deposition to form a silicon monoxide layer having a thickness of 0.2 μm to 1.2 μm on the silicon monoxide layer, and then using chemical vapor deposition to form a silicon dinitride layer having a thickness of 0.2 μm to 1.2 μm on the silicon monoxide layer.

[0060] The thickness of the protective layer 42 is typically greater than 0.35 μm, and under favorable conditions the thickness of the silicon nitride layer is typically greater than 0.3 μm.

[0061] After the protective layer 42 is completed, a first polymer layer 46 having a thickness of 3 μm to 50 μm is then formed on the protective layer 42, as shown in FIG. 4a. This first polymer layer 46 has an insulating function and is made of a material selected from thermoplastic plastics, thermosetting plastics, polyimide (PI), benzocyclobutene (BCB), polyurethane, epoxy resin, poly-p-xylene polymers, welding mask materials, elastic materials, or porous dielectric materials. The first polymer layer 46 can be applied by hot lamination, dry film, screen printing, or spin coating. Then, as shown in FIG. 4b, the first polymer layer 46 is patterned using an etching process, exposing numerous openings 48 for the pads 44 on the semiconductor substrate 30. It should be noted that if the first polymer layer 46 is made of a photosensitive material, a photolithography process is used to pattern the first polymer layer 46. If the first polymer layer 46 is not made of a photosensitive material, a photolithography and etching process is used to pattern the first polymer layer 46.

[0062] After the first polymer layer 46 is patterned, it is heated to a temperature of 200°C to 320°C by baking, microwave heating, or infrared heating, or to a temperature of 320°C to 450°C, to cure the first polymer layer 46. After curing, the volume of the first polymer layer 46 shrinks, and the moisture content of the first polymer layer 46 is 1% or less, and the weight change rate of this moisture content when the first polymer layer 46 is heated to a temperature of 425°C to 450°C is 1% or less.

[0063] As shown in FIG. 5, a first adhesion / barrier / seed layer 50 having a thickness of 400 Å to 7000 Å is formed on the first polymer layer 46 and the pads by sputtering. The material of the first adhesion / barrier layer 50 is titanium metal, titanium nitride, titanium-tungsten alloy, tantalum metal, chromium, chromium-copper alloy, or tantalum nitride, or a combination thereof. The first adhesion / barrier layer 50 serves as a seed layer formed on the first adhesion / barrier layer 50. Because this seed layer serves to establish the subsequent metal lines, the material of the seed layer varies depending on the material of the subsequent metal lines. In subsequent embodiments, a seed layer is formed on all adhesion / barrier layers.

[0064] If the metal traces on the seed layer are electroplated with copper, the seed layer material should be copper. If the metal traces are electroplated with silver, the seed layer material should be silver. If the metal traces are electroplated with palladium, the seed layer material should be palladium. If the metal traces are electroplated with platinum, the seed layer material should be platinum. If the metal traces are electroplated with rhodium, the seed layer material should be rhodium. If the metal traces are electroplated with ruthenium, the seed layer material should be ruthenium. If the metal traces are electroplated with rhenium, the seed layer material should be rhenium. If the metal traces are electroplated with nickel, the seed layer material should be nickel.

[0065] Next, as shown in FIG. 6a, a first patterned hardened photoresist layer 54 is formed on the seed layer on the first adhesive / inhibitory layer 50, and the first patterned hardened photoresist layer 54 has several openings 56 that expose portions of the seed layer on the first adhesive / inhibitory layer 50. The openings 56 are formed using 1X steppers or scanners or better machines, and the first patterned hardened photoresist layer 54 is then removed. The seed layer on the first adhesion / inhibition layer 50 within the opening 36 is then exposed, and a first metal layer 58 is electroplated thereon to a thickness of 1 μm to 50 μm, preferably between 2 μm and 30 μm. This first metal layer 58 connects to the thin connecting structure 34, and the material of this first metal layer 58 is gold, copper, silver, palladium, platinum, rhodium, ruthenium, rhenium, or nickel, or at least one of these in combination. After the first patterned hardened photoresist layer 54 is removed, a first RDL line layer 60 is formed. Note that this first RDL line layer 60 is primarily formed over the opening 48 and also extends onto a portion of the first polymer layer 46. Rather than simply being formed over the opening 48, the extended first metal layer 58 serves for subsequent line placement.

[0066] Next, as shown in Figure 6b, a second patterned hardened photoresist layer 62 is formed on the seed layer on the first RDL line layer 60 and the first adhesion / inhibition layer 50, and the second patterned hardened photoresist layer 62 exposes the first metal layer 58 of the first RDL line layer 60 through several openings 64. Then, as shown in Figure 6c, a second metal layer 66 formed by electroplating is formed in the openings 64, with a thickness of 20 μm to 300 μm and a maximum width of 3 μm to 50 μm. The second metal layer 66 is made of one or at least one of gold, copper, silver, palladium, platinum, rhodium, ruthenium, rhenium, or nickel, and the thickness of the second metal layer 66 is preferably between 30 μm and 100 μm.

[0067] The second metal layer 66 is made of copper, and the first RDL line layer 60 is preferably copper; the second metal layer 66 is made of silver, and the first RDL line layer 60 is preferably silver; the second metal layer 66 is made of palladium, and the first RDL line layer 60 is preferably palladium; the second metal layer 66 is made of platinum, and the first RDL line layer 60 is preferably platinum; the second metal layer 66 is made of rhodium, and the first RDL line layer 60 is preferably rhodium; the second metal layer 66 is made of ruthenium, and the first RDL line layer 60 is preferably ruthenium; the second metal layer 66 is made of rhenium, and the first RDL line layer 60 is preferably rhenium; the second metal layer 66 is made of nickel, and the first RDL line layer 60 is preferably nickel.

[0068] As shown in Figure 6d, the second patterned hardened photoresist layer 62 is then removed, and the first adhesion / inhibition layer 50 beneath the first metal layer 58 is similarly etched away using hydrogen peroxide. Alternatively, an iodine-containing etchant such as potassium iodide may be used instead of hydrogen peroxide. As shown in Figure 6e, the step of removing the seed layer beneath the first metal layer 58 and the first adhesion / inhibition / seed layer 50 may be performed after removing the second patterned hardened photoresist layer 62 or the first patterned hardened photoresist layer 54.

[0069] As shown in Figures 7a and 7b, after removing the first adhesion / inhibition layer 50 under the first metal layer 58, the maximum width Hw of each second metal layer 66 (i.e., the metal pillars 68 defining the cost invention) divided by their height Ht is less than 4, and can even be less than 3 or 2. The maximum width of these metal pillars 68 is 3 μm to 50 μm. These metal pillars 68 are small pillars, unlike the metal layers or wiring layers described above, and the center-to-center spacing Hb between adjacent metal pillars 68 is between 10 μm and 250 μm, and can be reduced to even better spacings of 10 μm to 200 μm, 10 μm to 175 μm, or 10 μm to 150 μm. Figure 7b shows a top-down view of these metal pillars 68 installed on the second metal layer 66. As can be clearly seen from the figure, the metal pillar 68 is not formed on the RDL line layer 60 above the opening 48, but is formed on the area extending from the RDL line layer 60.

[0070] As shown in FIG. 8a, a second polymer layer 70 is formed on the semiconductor substrate 30, covering the metal pillars 68. The second polymer layer 70 may be made of a material selected from thermoplastic plastics, thermosetting plastics, polyimide (PI), benzocyclobutene (BCB), polyurethane, epoxy resin, poly-p-xylene polymers, welding mask materials, elastic materials, or porous dielectric materials. The second polymer layer 70 is deposited by screen printing or spin coating. Referring to FIG. 8b, when deposited by screen printing, multiple openings 72 are directly formed in the second polymer layer 70, and the top ends of the metal pillars 68 are exposed. When deposited by spin coating, multiple openings 72 are formed through a patterning step, and then exposed at the top ends of the metal pillars 68. When deposited by spin coating, the openings 72 are formed by lithographic etching. 8c, the metal pillars 68 can be exposed by polishing instead of opening 72. However, before the polishing step, the second polymer layer 70 is first cured, and then the second polymer layer 70 is polished by chemical-physical polishing (CMP) to expose the metal pillars 68. The curing step can be performed by baking, microwave heating, or infrared heating.

[0071] It should be noted here that many of the embodiments are extensions of the structure shown in FIGS. 8b and 8c. For the present invention, these two figures show the formation of a number of metal pillars 68 on the semiconductor substrate 30, with a fine pitch between adjacent metal pillars, where the pitch is between 10 μm and 250 μm, and the maximum width Hw of the metal pillars 68 divided by the height Ht is less than 4. Therefore, many of the following embodiments all make variations on the metal pillars 68, with the first embodiment being based on the structure shown in FIG. 8c.

[0072] 9, a third polymer layer 74 is formed on the second polymer layer 70 by coating, and a number of openings 72 are formed in the third polymer layer 74 through a patterning process. The patterning process for the third polymer layer 74 is performed using lithography or lithography etching. Alternatively, the third polymer layer 74 may be patterned using a dry film and hot-laminated onto the second polymer layer 70, or the third polymer layer 74 may be formed on the second polymer layer 70 using a screen printing process. The material for the third polymer layer 74 may be selected from thermoplastic plastics, thermosetting plastics, polyimide (PI), benzocyclobutene (BCB), polyurethane, epoxy resin, poly-p-xylene polymers, welding mask materials, elastic materials, porous dielectric materials, etc.

[0073] 10a, a second adhesion / inhibition layer 78 having a thickness of 400 Å to 7000 Å is formed by sputtering on the third polymer layer 74 and the top surface of the metal posts 68. The material of this second adhesion / inhibition layer 78 is titanium metal, titanium nitride, titanium-tungsten alloy, tantalum metal, chromium, chromium-copper alloy, or tantalum nitride, or a combination thereof, and a seed layer is formed on the second adhesion / inhibition layer 78. Next, as shown in FIG. 10b, a third patterned hardened photoresist layer 82 is formed on the seed layer of the second adhesion / inhibition layer 78. The third patterned hardened photoresist layer 82 is a positive photoresist type, and several openings 83 in the third patterned hardened photoresist layer 82 expose the seed layer of the second adhesion / inhibition layer 78 over and around the openings 76.

[0074] Next, as shown in FIG. 10c, a third metal layer 84 is formed by electroplating on the seed layer exposed in the opening 83 and on the second adhesion / inhibition layer 78. The material of this third metal layer 84 is gold, copper, silver, palladium, platinum, rhodium, ruthenium, rhenium, or nickel, or a combination of at least one of these. Next, as shown in FIG. 10d, the second adhesion / inhibition layer 78 beneath the third metal layer 84 is similarly etched away using hydrogen peroxide. Alternatively, an iodine-containing etchant, such as potassium iodide, may also be used. Note that the thickness of this third metal layer 84 varies depending on the material and thickness of the third metal layer 84. This results in different patterns and applications for connecting the semiconductor substrate 30 to an external circuit. That is, the thickness of the third patterned hardened photoresist layer 82, the width of the opening 83, and the position of the opening 82 may vary depending on the application, and the third metal layer 84 may have different thicknesses, positions, and materials after electroplating. The external circuit may be a flexible substrate, a semiconductor chip, a printed wiring board, a ceramic substrate, a glass substrate, etc.

[0075] In this embodiment, the third metal layer 84 is formed in the form of a bump, pad, RDL, or solder. As shown in FIG. 10d, the material of the third metal layer 84 is gold, copper, silver, palladium, platinum, rhodium, ruthenium, or rhenium. The thickness (Ha) of the formed third metal layer 84 is between 5 μm and 30 μm, with a preferred thickness being between 10 μm and 25 μm. Therefore, the third metal layer 84 is defined as a bump 86. The center-to-center spacing between adjacent bumps 86 is between 250 μm and 250 μm, and can be reduced to a preferred spacing of 200 μm to 150 μm. As shown in FIG. 11, the semiconductor base 30 is cut to form multiple semiconductor units 88, and the bumps 86 on each semiconductor unit 88 can be connected to an external circuit by forming an ACF.

[0076] 12a and 12b, the material of the third metal layer 84 is one of solder, tin-lead alloy, tin-silver-copper alloy, or lead-free solder, and the thickness (Ha) of the formed third metal layer 84 is between 20 μm and 150 μm, preferably between 30 μm and 105 μm. Next, as shown in FIG. 12c, the semiconductor substrate 30 is heated, and the third metal layer 84 melts into a spherical shape. These spherically molten third metal layer 84 are defined as tin balls 92, and the center-to-center spacing between adjacent tin balls 92 is between 250 μm and 150 μm, and can be reduced to a distance of 200 μm to 150 μm. A third method for the third metal layer 84 is to form a copper layer 1 μm to 100 μm thick by electroplating in the openings 83 of the third patterned hardened photoresist layer 82, followed by a nickel layer 1 μm to 10 μm thick by electroplating on top of the copper layer, and finally a tin layer, or a tin-silver layer, or a tin-silver-copper alloy layer 20 μm to 150 μm thick by electroplating on top of the nickel layer.

[0077] Then, the semiconductor substrate 30 is cut as shown in FIG. 12d to form a plurality of semiconductor units 88, and the tin balls 92 on each semiconductor unit 88 can be bonded to an external substrate 94, which can be a semiconductor chip, a printed wiring board, a ceramic substrate, or a glass substrate.

[0078] As shown in FIG. 12e, when the tin ball 92 on the semiconductor unit 88 is bonded to an external substrate 94, before bonding the semiconductor unit 88 to the external substrate 94, a fourth polymer layer 96 is first formed on the substrate 94, and the material of the fourth polymer layer 96 is selected from thermoplastic plastic, thermosetting plastic, polyimide (PI), benzocyclobutene (BCB), polyurethane, epoxy resin, poly-p-xylene polymer, welding mask material, elastic material, porous dielectric material, etc. The fourth polymer layer 96 is formed by hot laminating a patterned dry film onto the substrate 94, or by hot laminating a photosensitive dry film onto the substrate 94 and then lithographically patterning the photosensitive dry film, or by screen printing the fourth polymer layer 96 onto the substrate 94, or by forming a photosensitive thin film on the substrate 94 by spin coating, and then forming a photosensitive dry film by lithography or a non-photosensitive thin film on the substrate 94 by spin coating and then lithographically etching the non-photosensitive thin film. After the tin balls 92 on the semiconductor units 88 are bonded to the substrate 94, they are heated to harden the fourth polymer layer 96. This heating step can be performed by baking, microwave heating, infrared heating, or the like.

[0079] 13a and 13b, the material of the third metal layer 84 is gold, copper, silver, palladium, platinum, rhodium, ruthenium, or rhenium, and the thickness (Ha) of the formed third metal layer 84 is between 1 μm and 15 μm, preferably between 2 μm and 10 μm. This third metal layer 84 is defined as a pad 98, and the center-to-center spacing between adjacent pads 98 is between 250 μm and 300 μm, although it can be reduced to a better spacing of 200 μm to 150 μm. This pad 98 forms a wire during the wire manufacturing process and connects to an external circuit.

[0080] 14a and 14b, the third metal layer 84 is made of gold, copper, silver, palladium, platinum, rhodium, ruthenium, or rhenium. The thickness (Ha) of the formed third metal layer 84 is between 5 μm and 30 μm, preferably between 10 μm and 25 μm. The third metal layer 84 is formed not only on the opening 76 of the third polymer layer 74 but also on the second adhesion / inhibition layer 78 on the sides of the opening 76. This third metal layer 84 is defined as an RDL layer 100, which forms a wire during the wire fabrication process and connects to an external circuit. It should be emphasized that the third metal layer 84 on the sides of the opening 76 functions similarly to a pad 98. This eccentric design prevents the pad 98 from being too small, resulting in insufficient wire area during the wire fabrication process, which can be difficult.

[0081] In this embodiment, the applications of bumps, pads, RDLs, solder, etc. in FIGS. 9 to 14b are all extensions of the structure of FIG. 8c. However, these applications can also be directly extensions of the structure of FIG. 8c. This is because the structure of FIG. 9 is formed from the third polymer layer 74 of the structure of FIG. 8c, and this third polymer layer 74 is patterned with multiple openings. However, the structure of FIG. 8b does not expose the metal posts 68 by polishing, but rather exposes the metal posts 68 through multiple openings in a patterned manner, eliminating the need for a third polymer layer 74. In other words, the structure of FIG. 8b is like the structure of FIG. 8c with the third polymer layer 74 added. Therefore, the applications of bumps, pads, RDLs, solder, etc. in FIGS. 10a-d, 11, 12a-e, 13a-b, and 14a-b that are extensions of FIG. 9 will not be described here.

[0082] (Second Example) This embodiment is an extension of the first embodiment shown in FIG. 8c. Referring to FIG. 15a, in this embodiment, the top of the metal pillar 68 is a gold layer 102, which is 1 μm to 30 μm thick. A wire 104 is formed on the metal 102 of the metal pillar 68 during a wire fabrication process to connect to an external circuit. Note that the metal below the gold layer 102 is a copper layer 104 and a nickel layer 106 (copper-nickel-gold structure), with the copper layer 104 being 10 μm to 100 μm thick and the nickel layer 106 being 1 μm to 30 μm thick. Alternatively, as shown in FIG. 15b, the gold layer 102 is on top of the copper layer 104, with the gold layer 102 being 1 μm to 30 μm thick. Alternatively, as shown in FIG. 15c, the entire metal pillar 68 is made of gold, with the metal pillar 68 being 10 μm to 100 μm thick.

[0083] (Third Example) This embodiment is an extension of the first embodiment shown in Fig. 8c. Referring to Fig. 16a, a third adhesive / inhibitory layer 105 is formed on the second polymer layer 70, and a seed layer is formed on the third adhesive / inhibitory layer 105. As shown in Fig. 16b, a fourth patterned hardened photoresist layer 110 is formed on the third adhesive / inhibitory layer 105. The fourth patterned hardened photoresist layer 110 has a number of openings 112, at least one of which is located above the metal post 68. The opening 112 is electroplated in a coil shape to form a fourth metal layer 114 on the fourth patterned hardened photoresist layer 110, as shown in Fig. 16c. A fourth metal layer 114 is formed in the opening 112 of the don photoresist layer 110. The material of the fourth metal layer 114 is gold, copper, silver, palladium, platinum, rhodium, ruthenium, or rhenium. The fourth metal layer 114 has a thickness of 1 μm to 30 μm. The fourth metal layer 114 is a composite metal layer, which is formed by electroplating a copper layer having a thickness of 1 μm to 30 μm, followed by a nickel layer having a thickness of 1 μm to 10 μm on top of the copper layer, and finally a gold layer having a thickness of 1 μm to 10 μm on top of the nickel layer.

[0084] As shown in FIG. 16d, the fourth patterned hardened photoresist layer 110 is removed, and the third adhesion / inhibition layer 105 underneath the fourth patterned hardened photoresist layer 110 is similarly removed using an etching solution containing hydrogen peroxide or iodine. As shown in FIG. 16e, the fourth metal layer 114 has a coil shape, which is defined as a first coil metal layer 116, and the first coil metal layer 116 is connected to the semiconductor base 30 through the metal posts 68. As shown in FIG. 16f, in addition to connecting to the semiconductor base 30, it can also be connected to an external circuit through a wire fabrication process (not shown). A protective layer 117 can be formed on the first coil metal layer 116 to protect it from damage and moisture intrusion. The thickness of the protective layer 117 is 5 μm to 25 μm. The protective layer 117 may be made of organic or inorganic materials such as thermoplastic plastics, thermosetting plastics, polyimide (PI), benzocyclobutene (BCB), polyurethane, epoxy resin, poly-p-xylene polymers, welding mask materials, elastic materials, porous dielectric materials, silicon oxide, silicon oxide compounds, silicon-phosphorus glass, silicon nitride, and SiON (silicon oxynitride), etc. The first coil metal layer 116 is used in the area of ​​passive devices such as inductors, capacitors, and resistors.

[0085] 16g, the first coil metal layer 116 covers a fifth polymer layer 118, which has a thickness of 20 μm to 300 μm and is made of polyimide (PI). The second coil metal layer 120 can be connected to an external circuit. When a change occurs in the current in the external circuit, an induced electromotive force is generated through the second circular metal layer 120, which is sensed by the first coil metal layer 116 and transmitted to the semiconductor substrate 30. The fabrication of this passive device is now complete.

[0086] Using the above electroplating method, it is also possible to form a capacitor device 121 on the second polymer layer 70. As shown in FIG. 16h, a low dielectric layer 121a having a thickness of 500 Å to 5000 Å is formed on the second polymer layer 70, and the low dielectric layer 121a is made of titanium, titanium tungsten alloy, tantalum, tantalum nitride, etc., and the low dielectric layer 121a is connected to a metal pillar 68. Then, a high dielectric layer 121b is coated on the low dielectric layer 121a, and the high dielectric layer 121b is made of silicon oxynitride. The low-resistance metal layer 121c is formed on adjacent metal pillars 68 by electroplating, and the low-dielectric layer 121a is formed by two methods. One method involves forming an adhesion / inhibition layer 400 Å to 7500 Å thick on the second polymer layer 70 and the high-dielectric layer 121b, and the material of this adhesion / inhibition layer is titanium, titanium-tungsten alloy, tantalum, tantalum nitride, etc., and then forming a seed layer 500 Å to 5000 Å thick on the adhesion / inhibition layer. Then forming a copper layer 121a by electroplating and having a thickness of 1 μm to 30 μm on the seed layer, and then forming a nickel layer 121a by electroplating and having a thickness of 1 μm to 10 μm on the copper layer.

[0087] Alternatively, a 400-7500 Å thick adhesion / inhibition layer may be placed on top of the second polymer layer 70 and the high-dielectric layer 121b, followed by a 500-5000 Å thick seed layer on top of the adhesion / inhibition layer, and finally a 1-30 μm thick gold layer formed by electroplating may be placed on top of the gold seed layer. When a voltage is applied to adjacent metal pillars 68, a large voltage difference is formed between the top and bottom of the high-dielectric layer 121b, providing a capacitor function. Finally, a protective layer 121d may be applied over the low-resistance metal layer 121c and the second polymer layer 70 to protect the capacitor device 121 from damage.

[0088] (Fourth Example) This embodiment is an extension of the first embodiment shown in FIG. 8b. As shown in FIG. 17a, a fourth adhesive / inhibitory layer 122 is formed on the second polymer layer 70. The material of the fourth adhesive / inhibitory layer 122 is titanium, titanium tungsten alloy, tantalum, or tantalum nitride, etc. The material of the seed layer is gold, copper, silver, palladium, platinum, rhodium, ruthenium, or rhenium. As shown in FIG. 17b, a fifth patterned hardened photoresist layer 126 is formed on the fourth adhesive / inhibitory layer 122. 17c, a fifth metal layer 130 having a thickness of 100 μm to 30 μm is formed by electroplating on the fourth adhesion / blocking / seed layer 122 in the openings 128 of the fifth patterned hardened photoresist layer 126, and the fifth metal layer 130 has a low resistance, such as gold, silver, or copper. Next, as shown in FIG. 17d, the fifth patterned hardened photoresist layer 126 is removed, and the fourth adhesion / blocking layer 122 under the fifth patterned hardened photoresist layer 110 is similarly removed using an etching solution containing hydrogen peroxide or iodine. Then, the fifth metal layer 130 is connected to the two metal pillars 68. The fifth metal layer 130 is the current path of the two metal pillars 68, and a protective layer 132 is formed on the fifth metal layer 130 to protect it from damage and moisture intrusion. A fifth metal layer 130 can be formed on the double alloy layer 70 and the fifth metal layer 130, with a thickness of 1 μm to 30 μm. The fifth metal layer 130 is a composite metal layer, which includes a copper layer formed by electroplating with a thickness of 1 μm to 30 μm, followed by a nickel layer formed by electroplating with a thickness of 1 μm to 10 μm on top of the copper layer, and finally a gold layer formed by electroplating with a thickness of 1 μm to 10 μm on top of the nickel layer.

[0089] The fifth metal layer 130 can be used not only to connect metal lines but also to extend to a multi-layer line structure. As shown in Figure 17e, a sixth polymer layer 134 is formed on the second polymer layer 70 and the fifth metal layer 130. Then, as shown in Figure 17f, a plurality of openings in the sixth polymer layer 134 are patterned to expose the fifth metal layer 130. As shown in Figure 17g, a fifth adhesive / blocking layer 136 is formed by sputtering. The fifth adhesive / blocking layer 136 is made of titanium, titanium-tungsten alloy, tantalum, or tantalum nitride, and the seed layer is made of gold, copper, silver, palladium, platinum, rhodium, ruthenium, or rhenium. As shown in Figure 17h, a sixth patterned hardened photoresist layer 140 is formed thereon. The sixth patterned hardened photoresist layer 140 is then patterned. The multiple openings in the photoresist layer 140 are exposed to the openings in the sixth polymer layer 134, and a sixth metal layer 142 is formed on the sixth patterned hardened photoresist layer 140, as shown in Figure 17i. The sixth metal layer 142 is made of gold, copper, silver, palladium, platinum, rhodium, ruthenium, and rhenium, and has a thickness of 1 μm to 30 μm. The sixth metal layer 142 is a composite metal layer, and is formed by electroplating a copper layer of 1 μm to 30 μm in thickness, followed by electroplating a nickel layer of 1 μm to 10 μm in thickness on top of the copper layer, and finally electroplating a gold layer of 1 μm to 10 μm in thickness on top of the nickel layer.

[0090] As shown in Figure 17j, after removing the sixth patterned hardened photoresist layer 140 and the fifth adhesion / inhibition layer 136 and the seed layer except for the area under the sixth metal layer 142, as shown in Figure 17k, a seventh polymer layer 144 is formed on the sixth polymer layer 134 and the sixth metal layer 142, and the seventh polymer layer 144 is patterned to have a thickness of 10 μm to 25 μm, as shown in Figure 17l, to expose multiple openings in this seventh polymer layer 144 to the sixth metal layer 142, and as shown in Figure 17m, a wire is exposed to the sixth metal layer 142 during the wire manufacturing process to connect to an external circuit.

[0091] (Fifth Example) This embodiment is an extension of the first embodiment shown in FIG. 8b, and is similar to the fourth embodiment. As shown in FIG. 18, the manufacturing method of this embodiment is the same as that of the fourth embodiment, except that the fifth metal layer 130 in the fourth embodiment is made of a low-resistance material, allowing current to flow quickly through the fifth metal layer 130, while the seventh metal layer 146 in the fifth embodiment (see FIG. 18) is made of a high-resistance material, such as chromium / nickel alloy (Cr / Ni), titanium, tungsten, etc., and the thickness of the seventh metal layer 146 is 1 μm to 3 μm. Therefore, the seventh metal layer 146 is used as a resistive device in this embodiment.

[0092] (Sixth Example) While the first to fifth embodiments are extensions of the structures shown in Figures 8b and 8c, this embodiment is an extension of the structure shown in Figure 8a. As shown in Figures 19a and 19b, this embodiment uses an etching method to remove a portion of the second polymer layer 70 until metal pillars 68 with a height of 1 μm to 150 μm are exposed. This exposed height is the distance from the top surface of the metal pillars to the top surface of the second polymer layer 70. If the material of the metal pillars 68 is gold, copper, silver, palladium, platinum, rhodium, ruthenium, or rhenium, the preferred exposed height of the metal pillars 68 is between 15 μm and 30 μm. These metal pillars 68 are used as protruding blocks, and as shown in Figure 19c, the same cutting step is performed to cut the semiconductor substrate 30 into multiple semiconductor units 88. Similarly, the protruding blocks 86 on each semiconductor unit 88 can be connected to an external circuit by forming an ACF.

[0093] If the material of the metal posts 68 is solder, tin-lead alloy, tin-silver alloy, tin-silver-copper alloy, or lead-free solder, the preferred exposed height of the metal posts 68 is between 50 μm and 100 μm. As shown in Fig. 19d, the exposed metal posts 68 are melted into ball-shaped (solder tin balls) by the same heating step, and then, as shown in Fig. 19e, the same cutting step is performed to cut the semiconductor base 30 into multiple semiconductor units 88, and the protruding masses 86 on each semiconductor unit 88 are bonded to an external substrate, and an eighth polymer layer 148 is formed between the semiconductor units and the substrate to cover each ball-shaped protruding mass.

[0094] As shown in Figure 19f, if the material of the metal pillars 68 is gold, copper, silver, palladium, platinum, rhodium, ruthenium, or rhenium, the preferred exposed height of the metal pillars 68 is between 1 μm and 15 μm, and the exposed metal pillars 68 are used as pads to form a wire during the wire fabrication process, connecting the metal layer and the polymer layer.

[0095] As shown in Figure 19g, if the material of the exposed metal pillars 68 is gold, copper, silver, palladium, platinum, rhodium, ruthenium, or rhenium and the exposed height is between 5000 Å and 10 μm, a sixth adhesion / inhibition layer 150 is formed on the second polymer layer 70 and the exposed surface of the metal pillars 68, and the material of this sixth adhesion / inhibition layer 150 is titanium, titanium-tungsten alloy, tantalum, or tantalum nitride, etc., and this seed layer is on top of the sixth adhesion / inhibition layer 150, and the material of this seed layer is gold, copper, silver, palladium, platinum, rhodium, ruthenium, or rhenium, and the thickness of this sixth adhesion / inhibition layer 150 is one of 1000 Å to 7500 Å.

[0096] As shown in Figure 19h, a seventh patterned hardened photoresist layer 152 is formed on the sixth adhesion / inhibition layer 150, and the multiple openings in the seventh patterned hardened photoresist layer 152 expose the sixth adhesion / inhibition layer 150. As shown in Figure 19i, an eighth metal layer 154 is formed in the openings of the seventh patterned hardened photoresist layer 152. As shown in Figure 19j, the seventh patterned hardened photoresist layer 152 is removed, and the sixth adhesion / inhibition / seed layer 150 other than that under the eighth metal layer 154 is also removed. This eighth metal layer 154 connects the metal lines and connects between the two metal posts 68. The eighth metal layer 154 is made of gold, copper, silver, palladium, platinum, rhodium, ruthenium, or rhenium, and has a thickness of 1 μm to 30 μm. The eighth metal layer 154 is a composite metal layer, which is formed by electroplating a copper layer having a thickness of 1 μm to 30 μm, followed by a nickel layer having a thickness of 1 μm to 10 μm formed by electroplating on top of the copper layer, and finally a gold layer having a thickness of 1 μm to 10 μm formed by electroplating on top of the nickel layer.

[0097] 19k, finally, the eighth metal layer 154 and the second polymer layer 70 are coated with a protective layer 154 to protect them from damage. The material of the protective layer 154 is selected from thermoplastic plastics, thermosetting plastics, polyimide (PI), benzocyclobutene (BCB), polyurethane, epoxy resin, poly-p-xylene polymers, welding mask materials, elastic materials, porous dielectric materials, silicon oxide, silicon oxide compounds, silicon phosphide glass, silicon nitride, silicon oxynitride, etc.

[0098] This method of exposing the metal pillars 68 by etching is not only applicable to the above-mentioned protruding masses, pads, and metal line connections, but also to coil structures, capacitor structures, and resistor structures. The fabrication steps are similar to those of the above embodiment, so a repeated description will not be given.

[0099] (Seventh Example) The structure of this embodiment is similar to the structure of FIG. 8c, except for the manufacturing process of the metal posts 68 and the second polymer layer 70. As shown in FIG. 20a, after the first RDL layer 60 is formed on the semiconductor substrate 30, a ninth patterned hardened photoresist layer 158 is formed on the first RDL layer 60 and the first adhesion / blocking / seed layer 50, with multiple openings in the ninth patterned hardened photoresist layer 158 exposing the first RDL layer 60, and the opening depth of the ninth patterned hardened photoresist layer 158 is between 20 μm and 300 μm.

[0100] The material of this ninth patterned hardened photoresist layer 158 is selected from thermoplastic plastics, thermosetting plastics, polyimide (PI), benzocyclobutene (BCB), polyurethane, epoxy resin, poly-p-xylene polymer, welding mask material, elastic material, or porous dielectric material, etc. The ninth patterned hardened photoresist layer 158 may be formed by hot laminating a patterned dry film onto the semiconductor substrate 30, or by hot laminating a photosensitive dry film onto the semiconductor substrate 30 and then lithographically patterning the photosensitive dry film, or by hot laminating a non-photosensitive thin film onto the semiconductor substrate 30 and then lithographically patterning the non-photosensitive thin film, or by forming the ninth patterned polymer layer 158 on the semiconductor substrate 30 by screen printing, or by forming a photosensitive thin film on the semiconductor substrate 30 by spin coating, and then lithographically forming a photosensitive dry film or a non-photosensitive thin film on the semiconductor substrate 30 by spin coating, and then lithographically etching the non-photosensitive thin film.

[0101] As shown in Figure 20b, a seventh adhesive / inhibitory layer 160 having a thickness of 400 Å to 7000 Å is formed on the ninth patterned polymer layer 158 and the first RDL layer 60 in the opening of the ninth patterned polymer layer 158, and the material of this seventh adhesive / inhibitory layer 160 is titanium, titanium-tungsten alloy, tantalum, or tantalum nitride, etc., and this seed layer is on top of the seventh adhesive / inhibitory layer 160, and the material of this seed layer is gold, copper, silver, palladium, platinum, rhodium, ruthenium, or rhenium, and this sixth adhesive / inhibitory layer 150 has a thickness of 1000 Å to 7500 Å.

[0102] As shown in Figure 20c, a ninth metal layer 162 is formed on the seventh adhesion / blocking / seed layer 160 using a damascene method, and then the openings in the ninth patterned polymer layer 158 are filled. The material of this eighth metal layer 154 is gold, copper, silver, palladium, platinum, rhodium, ruthenium, or rhenium. The thickness of this ninth metal layer 162 is 1 μm to 30 μm. The ninth metal layer 162 is a composite metal layer, which is a copper layer formed by electroplating with a thickness of 1 μm to 30 μm, followed by a nickel layer formed by electroplating with a thickness of 1 μm to 10 μm on top of the copper layer, and finally a gold layer formed by electroplating with a thickness of 1 μm to 10 μm on top of the nickel layer.

[0103] 20d, a single polishing step is performed to remove the ninth metal layer 162 and the seventh adhesion / inhibition layer 160 except for the openings in the ninth patterned polymer layer 158, completing the installation of the metal pillars 68. The maximum width Hw of each metal pillar 68 divided by its height Ht is less than 4, and the maximum width of each metal pillar 68 is between 3 μm and 50 μm. The spacing Hb between adjacent metal pillars 68 is between 10 μm and 250 μm.

[0104] The structure of the metal pillars 68 formed using the Damascene method is very similar to the structure shown in Figure 8c above, so the subsequent ninth patterned polymer layer 158 and other device fabrication methods on the metal pillars 68 follow the same steps.

[0105] As shown in Figures 21a to 21d, these figures show the fabrication of the protruding masses, pads, tin balls and RDL layer on the ninth patterned polymer layer 158 and metal posts 68. Since the fabrication process has been described in the above examples, only the final completed structure is shown here, and the fabrication process is omitted.

[0106] As shown in Figures 22 to 25, these figures show metal interconnection, coils, capacitors, and resistors on the ninth patterned polymer layer 158 and metal posts 68. The manufacturing process has been described in the above embodiments, so only the final completed structure is shown here, and the manufacturing process is omitted.

[0107] The present invention provides a miniaturized spacing between stress relief and contact window structures, with spacings of 250 μm or less and pinhole counts of 400 or less being achieved, resulting in improved IC performance and significantly reduced resistance and load on IC metal interconnects for low-power IC elements.

[0108] The above-mentioned examples are intended to illustrate the features of the present invention, and are intended only to enable those skilled in the art to fully understand and practice the present invention, and are not intended to limit the scope of the present invention. Therefore, any modifications or alterations made without departing from the spirit of the present invention and having the same effect should be included in the scope of the following claims. [Brief explanation of the drawings]

[0109] [Figure 1] FIG. [Figure 2] FIG. 2 is a cross-sectional view illustrating a semiconductor base according to the first embodiment of the present invention. [Figure 3] 1 is a cross-sectional view illustrating a state where a thin connection structure and a protective layer are provided on a semiconductor base according to a first embodiment of the present invention; [Figure 4a] FIG. 3 is a cross-sectional view illustrating a first polymer layer formed in the first embodiment of the present invention. [Figure 4b]FIG. 3 is a cross-sectional view illustrating a first polymer layer formed in the first embodiment of the present invention. [Figure 5] 1 is a cross-sectional view illustrating a first adhesive / inhibitory layer formed in a first embodiment of the present invention. [Figure 6a] FIG. 2 is a cross-sectional view illustrating a first RDL layer and a metal pillar formed in the first embodiment of the present invention. [Figure 6b] FIG. 2 is a cross-sectional view illustrating a first RDL layer and a metal pillar formed in the first embodiment of the present invention. [Figure 6c] FIG. 2 is a cross-sectional view illustrating a first RDL layer and a metal pillar formed in the first embodiment of the present invention. [Figure 6d] FIG. 2 is a cross-sectional view illustrating a first RDL layer and a metal pillar formed in the first embodiment of the present invention. [Figure 6e] FIG. 2 is a cross-sectional view illustrating a first RDL layer and a metal pillar formed in the first embodiment of the present invention. [Figure 7a] FIG. 2 is an explanatory diagram of the physical properties of a metal pillar formed in the first embodiment of the present invention. [Figure 7b] FIG. 2 is a plan view of the physical properties of a metal pillar formed in the first embodiment of the present invention. [Figure 8a] FIG. 3 is a cross-sectional view illustrating a second polymer layer formed in the first embodiment of the present invention. [Figure 8b] FIG. 4 is a cross-sectional view illustrating an opening in the second polymer layer formed in the first embodiment of the present invention. [Figure 8c] FIG. 3 is a cross-sectional view of a second polymer layer polished in the first embodiment of the present invention. [Figure 9] FIG. 4 is a cross-sectional view illustrating a third polymer layer formed in the first embodiment of the present invention. [Figure 10a] FIG. 3 is a cross-sectional view illustrating a third metal layer formed in the first embodiment of the present invention. [Figure 10b] FIG. 3 is a cross-sectional view illustrating a third metal layer formed in the first embodiment of the present invention. [Figure 10c] FIG. 3 is a cross-sectional view illustrating a third metal layer formed in the first embodiment of the present invention. [Figure 10d] FIG. 3 is a cross-sectional view illustrating a third metal layer formed in the first embodiment of the present invention. [Figure 11] FIG. 2 is a cross-sectional view illustrating a semiconductor base cutting process according to the first embodiment of the present invention. [Figure 12a]FIG. 2 is a cross-sectional view of a tin ball formed in the first embodiment of the present invention. [Figure 12b] FIG. 2 is a cross-sectional view of a tin ball formed in the first embodiment of the present invention. [Figure 12c] FIG. 2 is a cross-sectional view of a tin ball formed in the first embodiment of the present invention. [Figure 12d] 3A to 3C are cross-sectional explanatory views showing the semiconductor base portion being cut and being bonded to a substrate according to the first embodiment of the present invention. [Figure 12e] 3A to 3C are cross-sectional explanatory views showing the semiconductor base portion being cut and being bonded to a substrate according to the first embodiment of the present invention. [Figure 13a] 1A to 1C are cross-sectional explanatory views illustrating a process for manufacturing a metal pillar wire according to a first embodiment of the present invention. [Figure 13b] 1A to 1C are cross-sectional explanatory views illustrating a process for manufacturing a metal pillar wire according to a first embodiment of the present invention. [Figure 14a] FIG. 2 is a cross-sectional view illustrating an RDL layer formed on a metal pillar in the first embodiment of the present invention. [Figure 14b] FIG. 2 is a cross-sectional view illustrating an RDL layer formed on a metal pillar in the first embodiment of the present invention. [Figure 15a] FIG. 2 is a cross-sectional view illustrating the manufacturing process of a copper / nickel / gold or copper / gold metal pillar wire according to a second embodiment of the present invention. [Figure 15b] FIG. 2 is a cross-sectional view illustrating the manufacturing process of a copper / nickel / gold or copper / gold metal pillar wire according to a second embodiment of the present invention. [Figure 15c] FIG. 2 is a cross-sectional view illustrating the manufacturing process of a copper / nickel / gold or copper / gold metal pillar wire according to a second embodiment of the present invention. [Figure 16a] FIG. 10 is a cross-sectional view of a first coil metal layer formed on a metal pillar in a third embodiment of the present invention. [Figure 16b] FIG. 10 is a cross-sectional view of a first coil metal layer formed on a metal pillar in a third embodiment of the present invention. [Figure 16c] FIG. 10 is a cross-sectional view of a first coil metal layer formed on a metal pillar in a third embodiment of the present invention. [Figure 16d] FIG. 10 is a cross-sectional view of a first coil metal layer formed on a metal pillar in a third embodiment of the present invention. [Figure 16e] FIG. 10 is a cross-sectional view of a first coil metal layer formed on a metal pillar in a third embodiment of the present invention. [Figure 16f] FIG. 10 is a cross-sectional view of a first coil metal layer formed on a metal pillar in a third embodiment of the present invention. [Figure 16g] FIG. 10 is a cross-sectional view illustrating a second coil metal layer formed in a third embodiment of the present invention. [Figure 16h] FIG. 10 is a cross-sectional view of a capacitor device formed on a metal pillar according to a third embodiment of the present invention. [Figure 17a] FIG. 10 is a cross-sectional view illustrating the connection between the metal layer and two metal pillars formed in the fourth embodiment of the present invention. [Figure 17b] FIG. 10 is a cross-sectional view illustrating the connection between the metal layer and two metal pillars formed in the fourth embodiment of the present invention. [Figure 17c] FIG. 10 is a cross-sectional view illustrating the connection between the metal layer and two metal pillars formed in the fourth embodiment of the present invention. [Figure 17d] FIG. 10 is a cross-sectional view illustrating the connection between the metal layer and two metal pillars formed in the fourth embodiment of the present invention. [Figure 17e] FIG. 10 is a cross-sectional view of a multilayer wiring layer formed on a metal pillar according to a fourth embodiment of the present invention. [Figure 17f] FIG. 10 is a cross-sectional view of a multilayer wiring layer formed on a metal pillar according to a fourth embodiment of the present invention. [Figure 17g] FIG. 10 is a cross-sectional view of a multilayer wiring layer formed on a metal pillar according to a fourth embodiment of the present invention. [Figure 17h] FIG. 10 is a cross-sectional view of a multilayer wiring layer formed on a metal pillar according to a fourth embodiment of the present invention. [Figure 17i] FIG. 10 is a cross-sectional view of a multilayer wiring layer formed on a metal pillar according to a fourth embodiment of the present invention. [Figure 17j] FIG. 10 is a cross-sectional view of a multilayer wiring layer formed on a metal pillar according to a fourth embodiment of the present invention. [Figure 17k] FIG. 10 is a cross-sectional view of a multilayer wiring layer formed on a metal pillar according to a fourth embodiment of the present invention. [Figure 17l] FIG. 10 is a cross-sectional view of a multilayer wiring layer formed on a metal pillar according to a fourth embodiment of the present invention. [Figure 17m] FIG. 10 is a cross-sectional view of a multilayer wiring layer formed on a metal pillar according to a fourth embodiment of the present invention. [Figure 18]FIG. 10 is a cross-sectional view of a resistive device formed on a metal pillar according to a fifth embodiment of the present invention. [Figure 19a] FIG. 10 is a cross-sectional view illustrating a portion of the second polymer layer removed by an etching method used in a sixth embodiment of the present invention. [Figure 19b] FIG. 10 is a cross-sectional view illustrating a portion of the second polymer layer removed by an etching method used in a sixth embodiment of the present invention. [Figure 19c] FIG. 13 is a cross-sectional view illustrating a semiconductor base cutting process according to a sixth embodiment of the present invention. [Figure 19d] FIG. 10 is a cross-sectional view illustrating a tin ball and a cut step formed in a sixth embodiment of the present invention. [Figure 19e] FIG. 10 is a cross-sectional view illustrating a tin ball and a cut step formed in a sixth embodiment of the present invention. [Figure 19f] FIG. 10 is a cross-sectional view of a pad formed in a sixth embodiment of the present invention. [Figure 19g] FIG. 13 is a cross-sectional view illustrating the connection between the metal layer and two metal pillars formed in the sixth embodiment of the present invention. [Figure 19h] FIG. 13 is a cross-sectional view illustrating the connection between the metal layer and two metal pillars formed in the sixth embodiment of the present invention. [Figure 19i] FIG. 13 is a cross-sectional view illustrating the connection between the metal layer and two metal pillars formed in the sixth embodiment of the present invention. [Figure 19j] FIG. 13 is a cross-sectional view illustrating the connection between the metal layer and two metal pillars formed in the sixth embodiment of the present invention. [Figure 19k] FIG. 13 is a cross-sectional view illustrating the connection between the metal layer and two metal pillars formed in the sixth embodiment of the present invention. [Figure 20a] 10 is a cross-sectional view of a ninth patterned polymer layer formed on a semiconductor substrate according to a seventh embodiment of the present invention. FIG. [Figure 20b] FIG. 13 is a cross-sectional view illustrating a metal pillar formed by a damascene method according to a seventh embodiment of the present invention. [Figure 20c] FIG. 13 is a cross-sectional view illustrating a metal pillar formed by a damascene method according to a seventh embodiment of the present invention. [Figure 20d] FIG. 13 is a cross-sectional view illustrating a metal pillar formed by a damascene method according to a seventh embodiment of the present invention. [Figure 21a]FIG. 10 is a cross-sectional view illustrating a protruding nodule, pad, tin ball, and RDL layer structure formed in another embodiment of the present invention. [Figure 21b] FIG. 10 is a cross-sectional view illustrating a protruding nodule, pad, tin ball, and RDL layer structure formed in another embodiment of the present invention. [Figure 21c] FIG. 10 is a cross-sectional view illustrating a protruding nodule, pad, tin ball, and RDL layer structure formed in another embodiment of the present invention. [Figure 21d] FIG. 10 is a cross-sectional view illustrating a protruding nodule, pad, tin ball, and RDL layer structure formed in another embodiment of the present invention. [Figure 22] 10 is a cross-sectional view of a freeway coil, capacitor device, and resistor device structure formed in another embodiment of the present invention; FIG. [Figure 23] 10 is a cross-sectional view of a freeway coil, capacitor device, and resistor device structure formed in another embodiment of the present invention; FIG. [Figure 24] 10 is a cross-sectional view of a freeway coil, capacitor device, and resistor device structure formed in another embodiment of the present invention; FIG. [Figure 25] 10 is a cross-sectional view of a freeway coil, capacitor device, and resistor device structure formed in another embodiment of the present invention; FIG. [Explanation of symbols]

[0110] 10: post-passivation structure, 12: RDL layer, 14: polymer layer, 16: protective layer, 18: semiconductor IC chip, 20: pad, 22: slope, 30: semiconductor base, 32: electronic element element, 34: thin connection structure, 36: thin insulating layer, 38: thin line layer, 40: through hole 42: protective layer; 44: pad; 46: first polymer layer; 48: opening; 50: first adhesive / Inhibition layer, 54: First patterned hardened photoresist layer, 56: Opening, 58: First metal layer ,60: First RDL layer, 62: Second patterned hardened photoresist layer, 64: Opening, 66: second metal layer, 68: metal column, 70: second polymer layer, 72: opening, 74: third polymer layer, 76: Opening, 78: Second adhesive / inhibitory layer, 82: Third patterned hardened photoresist layer, 8 3: opening, 84: third metal layer, 86: protruding mass, 88: semiconductor unit, 92: tin ball , 94: substrate, 96: fourth polymer layer, 98: pad, 100: RDL layer, 102: gold layer, 1 04: Copper layer, 105: Third adhesive / inhibitory layer, 106: Nickel layer, 110: Fourth patterned hard Photoresist layer 112, opening 114, fourth metal layer 116, first coil metal layer 117: protective layer, 118: fifth polymer layer, 120: second coil metal layer, 121: capacitor sensor device, 121a: low dielectric layer, 121b: insulating layer, 121c: low resistance metal layer, 1 21d: protective layer, 122: fourth adhesive / inhibitory layer, 126: fifth patterned hardened photoresist layer, 128: opening, 130: fifth metal layer, 132: protective layer, 134: sixth polymer layer, 1 36: fifth adhesive / inhibitory layer, 140: sixth patterned hardened photoresist layer, 142: sixth Metal layer, 144: Seventh polymer layer, 146: Seventh metal layer, 148: Eighth polymer layer, 150: Sixth adhesion / inhibition layer, 152: Seventh patterned hardened photoresist layer, 154: Eighth metal layer 156: protective layer, 158: ninth patterned polymer layer, 160: seventh adhesive / inhibitory layer, 162: Ninth metal layer The inventions described in the original claims of the present invention are as follows: [C1] A line device structure, a substrate, a first metal pillar, and a second metal pillar; The first metal pillar is located on the substrate, and the maximum width of the first metal pillar is equal to the height of the first metal pillar. The ratio is smaller than 4, and the height of the first metal pillar is between 20 μm and 300 μm, The second metal pillar is located on the substrate, and the maximum width of the second metal pillar is the height of the second metal pillar. The ratio is smaller than 4, and the height of the first metal pillar is between 20 μm and 300 μm, and the distance from the center point of the first metal pillar to the center point of the second metal pillar is 10 μm or more. 250 μm。 Line device structure characterized in that the thickness is between 250 μm. [C2] A first polymer layer having a thickness of 20 μm to 300 μm is formed on the substrate, and The line device according to C1, characterized in that the first metal pillar and the second metal pillar are covered. Chair structure. [C3] The first metal pillar is characterized by having a gold layer having a thickness of 30 μm to 100 μm. The line device structure according to C1. [C4] The first metal pillar is characterized by having a copper layer having a thickness of 30 μm to 100 μm. The line device structure according to C1. [C5] A method for connecting a first metal pillar and a second metal pillar with a metal connection line. 1. The line device structure according to claim 1. [C6] The substrate comprises a semiconductor substrate, a first metal structure located on the semiconductor substrate, a metal line a protective layer containing a silicon nitride compound located on the road; a second metal structure located on the protective layer; a first pad having an opening located in the protective layer exposing a first metal structure; The second metal structure has a second pad connected to the first pad and has an appearance of the first pad. The position seen from the top view is different from the position seen from the top view of the second pad. The line device structure according to C1, wherein one metal pillar is located on the second pad. [C7] A protruding mass is provided on the first metal pillar, and the protruding mass is a pre-formed outer C, which is connected to the internal circuit and characterized in that the protruding mass has a gold layer with a thickness of 10 μm to 30 μm. 1. The line device structure according to claim 1. [C8] A protruding mass is provided on the first metal pillar, and the protruding mass is a pre-formed outer The protruding mass is connected to the internal circuit and is characterized by having a tin solder layer with a thickness of 10 μm to 150 μm. The line device structure according to C1. [C9] A pad is provided on the first metal pillar, and the maximum width of the pad is The pad is larger than the maximum width of the metal pillar and is connected to the wire during the wire manufacturing process. The line device structure according to C1, characterized in that it is used for connection. [C10] The top surface of the first metal pillar is used for connection with the wire produced in the wire production process. The line device structure according to C1, characterized in that it is used. [C11] A metal coil is provided to connect the first metal column and the second metal column. The line device structure according to C1, characterized in that: [C12] A second metal structure and a protruding mass are provided, the second metal structure being connected to the first metal pillar. and a pad connected to the first metal pillar is provided, and the position of the pad as viewed from above is Unlike the position seen from the top view, the protruding mass is located on the pad and has a pre-formed outer surface. The protruding mass is connected to the external circuit, and the protruding mass has a gold layer having a thickness of 10 μm to 30 μm. The line device structure according to C1. [C13] A second metal structure and a protruding mass, the second metal structure being located on a substrate, The second metal structure has a pad connected to the first metal post, and a top-down view of the pad The position seen from above is different from the position seen from above of the first metal pillar, and the protruding mass Located on the pad and connected to a pre-formed external circuit, the protruding mass has a thickness of 10 μm to 3 The line device structure of C1, characterized in that it comprises a tin solder layer of 0 μm. [C14] A second metal structure is provided on the substrate, the second metal structure being in contact with the first metal pillar. The pad is connected to the body, and the position of the pad when viewed from above is Unlike the position seen from the top view of the column, the pad is located at the wire The line device structure according to C1, characterized in that it is used for connection with an ear. [C15] A line device structure, a semiconductor substrate, a first metal pillar, a second metal pillar, an insulating layer, a first protruding mass, and a first protruding a mass; A first metal pillar is located on the semiconductor substrate, and a maximum width of the first metal pillar is set to a first metal pillar width. When divided by the height of the body, it is less than 4, and the height of the first metal pillar is between 20 μm and 300 μm and The second metal pillar is located on the semiconductor substrate, and the maximum width of the second metal pillar is set to the second metal pillar width. When divided by the height of the body, it is less than 4, and the height of the first metal pillar is between 20 μm and 300 μm and an insulating layer located on the semiconductor substrate and covering the first metal pillars and the second metal pillars; The first protruding mass is located on the first metal pillar or the insulating layer and is connected to a pre-formed external circuit. Suitable for connection with The second protruding mass is located on the second metal pillar or the insulating layer and is connected to a pre-formed external circuit. and the distance from the center point of the first protruding mass to the center point of the second protruding mass is 10 μm. and 250 μm. [C16] The distance from the center point of the first protruding mass to the center point of the second protruding mass is 100 μ The line device structure according to C15, characterized in that the thickness is between 100 μm and 200 μm. [C17] The first metal pillar has a gold layer having a thickness of between 20 μm and 300 μm. 13. The line device structure according to claim 12, wherein: [C18] The first metal pillars have a copper layer having a thickness of between 20 μm and 300 μm. 13. The line device structure according to claim 12, wherein: [C19] The first metal pillar is characterized in that it has a gold layer having a thickness of 10 μm to 30 μm. The line device structure described in C15 is characterized. [C20] The first metal pillar has a tin solder layer having a thickness of between 10 μm and 150 μm. The line device structure according to C15, [C21] The line according to C15, wherein the material of the first insulating layer includes polyimide. Device structure. [C22] A first metal structure located on a conductor base, a nitride silicon layer located on the first metal structure, a protective layer containing a silicon compound; a second metal structure located on the protective layer; and a second metal structure located within the protective layer. The opening located therein comprises a first pad exposing a first metal structure, the second metal structure being in contact with the first pad. and a second pad connected to the first pad, and the position of the first pad as viewed from above is Unlike the position of the second pad when viewed from above, the first metal pillar is positioned on the second pad. The line device structure according to C15, characterized in that [C23] A first metal structure is provided on the first insulating layer and the first metal pillars, The metal structure has a pad connected to the first metal post, and the pad is The position is different from the position of the second pad when viewed from above, and the first protruding mass is located at the position of the second pad when viewed from above. The line device structure according to C15, characterized in that it is located on a pad.

Claims

1. A circuit component comprising: a semiconductor base having an active surface with a plurality of electronic elements; a connection structure on the active surface, the connection structure comprising a plurality of thin film insulating layers and a plurality of line layers each having a thickness of 3 μm or less; a protective layer on the semiconductor base configured to protect the electronic elements on the semiconductor base from ionic impurities, the protective layer being composed of silicon nitride or silicon oxynitride; a plurality of pads exposed by openings in the protective layer; a first polymeric layer on the protective layer, the first polymeric layer having a plurality of openings exposing the pads; a first adhesive / inhibitory layer on the first polymer layer, the protective layer, and the pad, the first adhesive / inhibitory layer having depressions corresponding to the surface shapes of the first polymer layer, the protective layer, and the pad; a first metal layer on the first adhesion / inhibition layer in contact with the pad through the opening in the protective layer and the first polymer layer, and the first metal layer and the first adhesion / inhibition layer constitute a RDL layer; wherein the RDL layer has a depression in the opening of the protective layer and the first polymer layer, the depression corresponding to the surface shapes of the protective layer and the first polymer layer; the first metal layer has a depression in the depression of the first adhesive / inhibition layer that corresponds to the surface shape of the first adhesive / inhibition layer; the first adhesive / inhibitory layer has recesses in the openings of the protective layer and the openings of the first polymer layer, the recesses corresponding to the surface shapes of the protective layer and the first polymer layer; the first metal layer is formed in the recess of the first adhesion / inhibition layer within the opening of the protective layer; a second metal layer having a thickness of 20 μm to 300 μm on the first metal layer, the second metal layer constituting first metal pillars; wherein the first metal pillars have a height of 20 μm to 300 μm, and the spacing between the first metal pillars is between 10 μm and 250 μm. a second polymer layer covering the recessed RDL layer, thereby exposing the top ends of the first metal posts; a third polymer layer on the second polymer layer; a plurality of openings on the top ends of the first metal posts in the third polymer layer; a second adhesion / inhibition layer on the third polymer layer and the top ends of the first metal posts; a third metal layer on the second adhesion / inhibition layer within the opening in the third polymeric layer; wherein the ratio of the maximum width Hw of the first metal pillar to the height Ht of the first metal pillar is less than 4; wherein the first metal posts are located within the openings of the protective layer and the first polymer layer, not on the RDL layer, but on the RDL layer above the first polymer layer. A circuit component comprising:

2. The circuit component of claim 1 , wherein the line layer is made of aluminum.

3. The circuit component of claim 1 , wherein the line layer is made of copper.

4. 10. The circuit component of claim 1, wherein the first adhesion / inhibition layer comprises a titanium metal layer.

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