Semiconductor device and manufacturing method thereof

Abstract

To provide a technique that can reduce the stress of the entire semiconductor device.SOLUTION: A semiconductor device further comprises: a plurality of sub-modules including a first sealing member; an insulating substrate provided with a first circuit pattern electrically connected to at least one of the conductor plates of the plurality of sub-modules; a connecting member electrically connected to at least one of conductor pieces of the plurality of sub-modules; and a second sealing member encapsulating the plurality of sub-modules, the insulating substrate and the connecting member and having a lower hardness than the first sealing member.SELECTED DRAWING: Figure 7

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device. [Background technology]

[0002] For example, Patent Document 1 proposes a semiconductor device that includes a plurality of submodules, each of which includes a plurality of semiconductor elements. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2018 / 047474 Summary of the Invention [Problem to be solved by the invention]

[0004] In the technology of Patent Document 1, as the number of submodules increases and the size of the semiconductor device increases, there is a problem in that stress such as thermal stress and the resulting warpage increase.

[0005] Therefore, the present disclosure has been made in consideration of the above-mentioned problems, and has an object to provide a technique capable of reducing stress in the entire semiconductor device. [Means for solving the problem]

[0006] A semiconductor device according to the present disclosure includes a plurality of submodules each having a first main surface, a second main surface opposite to the first main surface, and one or more side surfaces between the first main surface and the second main surface, and each of the plurality of submodules includes a plurality of semiconductor elements each having a drain electrode provided on the first main surface side and a source electrode and a control electrode provided on the second main surface side, a conductor plate provided on the first main surface side of the plurality of semiconductor elements and electrically connected to the drain electrodes of the plurality of semiconductor elements, a conductor piece provided on the second main surface side of the plurality of semiconductor elements and electrically connected to the source electrodes of the plurality of semiconductor elements, and a conductor piece provided on the second main surface side of the plurality of semiconductor elements and electrically connected to the control electrodes of the plurality of semiconductor elements. the plurality of sub-modules includes a first control terminal connected to the plurality of semiconductor elements, the conductor plate, the conductor piece, and the first control terminal, and a first sealing member that seals the plurality of semiconductor elements, the conductor plate, the conductor piece, and the first control terminal while leaving the portion of the conductor plate on the first main surface side, the portion of the conductor piece on the second main surface side, and the first control terminal exposed; and further includes an insulating substrate on which a first circuit pattern is provided that is electrically connected to at least one of the conductor plates of the plurality of sub-modules; a connecting member that is electrically connected to at least one of the conductor pieces of the plurality of sub-modules; and a second sealing member that seals the plurality of sub-modules, the insulating substrate, and the connecting member and has a hardness lower than that of the first sealing member. [Effects of the Invention]

[0007] According to the present disclosure, the hardness of the second sealing member is lower than that of the first sealing member, so that the stress in the entire semiconductor device can be reduced. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 2 is a perspective view schematically illustrating the configuration of a submodule according to the first embodiment. [Figure 2] FIG. 2 is a perspective view schematically illustrating the configuration of a submodule according to the first embodiment. [Figure 3] 1 is a cross-sectional view schematically showing the configuration of a submodule according to a first embodiment. [Figure 4]FIG. 2 is an enlarged perspective view schematically showing the configuration of a submodule according to the first embodiment. [Figure 5] 1 is a perspective view schematically illustrating a configuration of a semiconductor device according to a first embodiment. [Figure 6] 1 is a perspective view schematically illustrating a configuration of a semiconductor device according to a first embodiment. [Figure 7] 1 is a perspective view schematically illustrating a configuration of a semiconductor device according to a first embodiment. [Figure 8] 1 is a perspective view schematically illustrating a configuration of a semiconductor device according to a first embodiment. [Figure 9] 1 is a cross-sectional view schematically showing a configuration of a semiconductor device according to a first embodiment. [Figure 10] FIG. 10 is a cross-sectional view schematically showing the configuration of a semiconductor device according to a second embodiment. [Figure 11] FIG. 10 is a cross-sectional view schematically showing the configuration of a semiconductor device according to a third embodiment. [Figure 12] FIG. 10 is an enlarged perspective view schematically showing the configuration of a semiconductor device according to a fourth embodiment. [Figure 13] FIG. 11 is a perspective view schematically showing the configuration of a submodule according to a fifth embodiment. [Figure 14] FIG. 10 is a cross-sectional view schematically showing the configuration of a semiconductor device according to a fifth embodiment. [Figure 15] FIG. 13 is a plan view schematically showing the configuration of a submodule according to a sixth embodiment. [Figure 16] FIG. 13 is a cross-sectional view schematically showing the configuration of a submodule according to a sixth embodiment. [Figure 17] FIG. 13 is a plan view schematically showing the configuration of a submodule according to a sixth embodiment. [Figure 18] FIG. 13 is a plan view schematically showing the configuration of a submodule according to a sixth embodiment. [Figure 19] FIG. 13 is a plan view schematically showing the configuration of a submodule according to a sixth embodiment. [Figure 20] 13 is a plan view schematically showing a manufacturing process of a submodule according to a sixth embodiment. FIG. [Figure 21]13A to 13C are plan views schematically showing a manufacturing process for a submodule according to a first modification of the sixth embodiment. [Figure 22] 13A to 13C are plan views schematically showing a manufacturing process for a submodule according to a first modification of the sixth embodiment. [Figure 23] 13A and 13B are plan views schematically showing a manufacturing process of a submodule according to a second modification of the sixth embodiment. [Figure 24] FIG. 22 is a plan view schematically showing the configuration of a submodule according to a second modification of the sixth embodiment. [Figure 25] FIG. 22 is a plan view schematically showing the configuration of a submodule according to a second modification of the sixth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, embodiments will be described with reference to the accompanying drawings. Features described in each of the following embodiments are exemplary, and not all features are necessarily required. In addition, in the following description, similar components in multiple embodiments are denoted by the same or similar reference numerals, and different components will be mainly described. In addition, in the following description, specific positions and directions such as "upper," "lower," "left," "right," "front," or "back" may not necessarily correspond to positions and directions in actual implementation.

[0010] <First Embodiment> The semiconductor device according to the first embodiment includes a plurality of submodules. The configuration of each submodule will be described below.

[0011] <submodule> Fig. 1 is a perspective view schematically showing the configuration of a submodule 1 according to the first embodiment, and Fig. 2 is a perspective view showing the configuration of Fig. 1 excluding a first sealing member 31. Fig. 3 is a cross-sectional view of the configuration of the submodule 1 taken along line AA in Fig. 2.

[0012] 3, the submodule 1 according to the first embodiment has a bottom surface S1 which is a first main surface, a top surface S2 which is a second main surface opposite to the bottom surface S1, and a side surface S3 between the bottom surface S1 and the top surface S2. In the following description, the number of side surfaces S3 will be described as being plural, but the number of side surfaces S3 may be one.

[0013] As shown in FIGS. 1 to 3, the submodule 1 includes a plurality of semiconductor elements 11, conductive connection members 14, 17, a conductor plate 21, a conductor piece 22, a first control terminal 23, a wire 24, and a first sealing member 31.

[0014] 2 has a drain electrode (not shown) provided on the lower surface S1 side, and a source electrode 11a and a control electrode 11b provided on the upper surface S2 side. By controlling the voltage of the control electrode 11b, electricity can be conducted between the drain electrode on the lower surface S1 side and the source electrode 11a on the upper surface S2 side.

[0015] The semiconductor element 11 may be, for example, a semiconductor switching element, or a combination of a semiconductor switching element and a diode. The semiconductor switching element may be, for example, a metal oxide semiconductor field effect transistor (MOSFET), an insulated gate bipolar transistor (IGBT), or a reverse conducting IGBT (RC-IGBT). The diode may be, for example, a Schottky barrier diode (SBD), a PN junction diode (PND), or the like.

[0016] The material of the semiconductor element 11 may be ordinary silicon (Si), or may be a wide bandgap semiconductor such as silicon carbide (SiC), gallium nitride (GaN), or diamond. When the material of the semiconductor element 11 is a wide bandgap semiconductor, stable operation under high temperatures and high voltages and high switching speeds are possible. In the following description, the material of the semiconductor element 11 is assumed to be SiC.

[0017] 3, the conductor plate 21 has, for example, a flat plate shape, is provided on the lower surface S1 side of the plurality of semiconductor elements 11, and is electrically connected to the drain electrodes of the plurality of semiconductor elements 11. The conductive connection member 14 electrically connects the conductor plate 21 and the drain electrodes of the plurality of semiconductor elements 11.

[0018] The conductor piece 22 is provided on the upper surface S2 side of the plurality of semiconductor elements 11, and is electrically connected to the source electrodes 11a of the plurality of semiconductor elements 11. The conductive connection member 17 electrically connects the conductor piece 22 and the source electrodes 11a of the plurality of semiconductor elements 11.

[0019] 2, the first control terminal 23 is electrically connected to the control electrodes 11b of the plurality of semiconductor elements 11. In the first embodiment, the first control terminal 23 and the control electrodes 11b of the semiconductor elements 11 are connected by wires 24, but the present invention is not limited to this.

[0020] The first sealing member 31 seals the semiconductor elements 11, the conductor plate 21, the conductor piece 22, the first control terminal 23, and the wires 24, while leaving exposed the portion of the conductor plate 21 on the lower surface S1 side, the portion of the conductor piece 22 on the upper surface S2 side, and the portion of the first control terminal 23. The material of the first sealing member 31 includes, for example, a curable resin.

[0021] The bottom surface, top surface, and side surface of the first sealing member 31 correspond to the bottom surface S1, top surface S2, and side surface S3 of the submodule 1, respectively, and are substantially the same. In the first embodiment, the portion of the first control terminal 23 exposed from the first sealing member 31 is exposed from only one of the multiple side surfaces of the first sealing member 31 corresponding to each of the multiple side surfaces S3 of the submodule 1, but this is not limited to this. For example, the exposed portion of the first control terminal 23 may be exposed from multiple side surfaces of the first sealing member 31, or may be exposed from the top surface of the first sealing member 31 corresponding to the top surface S2 of the submodule 1, as in the fifth embodiment.

[0022] The material of the conductor plate 21 and the first control terminal 23 may include, for example, copper. Each of the conductor plate 21 and the first control terminal 23 may be, for example, a frame-like member integrated with external connecting parts and used for simultaneously manufacturing multiple sub-modules 1. The material of the conductor piece 22 may include, for example, copper or silver.

[0023] It is desirable that the melting point of at least one of the conductive connection members 14, 17 is higher than the process temperature when assembling a semiconductor device from multiple submodules 1. With this configuration, it is possible to prevent at least one of the conductive connection members 14, 17 inside the submodule 1 from melting and causing a connection failure when assembling a semiconductor device from multiple submodules 1. The material of the conductive connection members 14, 17 may include, for example, silver or copper, and the conductive connection members 14, 17 may be formed by, for example, a sintering process so that the relationship between the melting point and the process temperature is satisfied.

[0024] It is desirable to electrically connect the multiple semiconductor elements 11 and the conductor pieces 22 using a pressure-free connection process that does not involve the application of pressure. A pressure-free connection process can prevent damage to the multiple semiconductor elements 11 caused by pressing the conductor pieces 22 against the multiple semiconductor elements 11. In particular, a pressure-free connection process is effective in a configuration in which a termination structure for maintaining a withstand voltage is provided on the source electrode 11a side of the semiconductor element 11 and the portion of the semiconductor element 11 that connects to the conductor pieces 22 is smaller than the semiconductor element 11, as the semiconductor element 11 is prone to damage. Furthermore, pressure-free connection can prevent misalignment of the conductor pieces 22 due to pressure, thereby improving the yield of the submodule 1.

[0025] 2, in which the material of the wire 24 includes, for example, aluminum, the cost of the wire 24 can be reduced. In a configuration in which the material of the wire 24 includes, for example, at least one of silver and gold, the size of the control pad of the control electrode 11b can be reduced, which is expected to reduce the cost of the semiconductor element 11. Furthermore, in this configuration, the diameter of the wire 24 can be reduced, and the height of the loop of the wire 24 can be lowered. Therefore, even if the thickness of the submodule 1, and therefore the thickness of the first sealing member 31, is reduced, the exposure of the wire 24 from the first sealing member 31 can be suppressed. Reducing the thickness of the submodule 1 not only facilitates replacement of the semiconductor element 11, but also reduces the stress that the first sealing member 31 applies to the semiconductor element 11.

[0026] 2, the semiconductor elements 11 may be arranged in multiple rows (two rows in FIG. 2) along the extension direction of the conductor plate 21, and the first control terminal 23 may include a lead portion 23a provided between the semiconductor elements 11 in adjacent rows. The lead portion 23a may also be provided parallel to the conductor plate 21. With this configuration, it is possible to reduce the variation in the distance between the first control terminal 23 and the control electrode 11b for each of the semiconductor elements 11, and therefore, for example, it is possible to synchronize the operation timing of the semiconductor elements 11.

[0027] The control pads of the control electrode 11b may include not only a gate pad to which a gate drive voltage for controlling the on / off of the semiconductor element 11 is applied, but also, for example, a current sense pad, a Kelvin emitter pad, and a temperature sense diode pad. The current sense pad is a control pad for detecting the current flowing in the cell region of the semiconductor element 11 and for directing a current that is a fraction to several tens of thousands of the current flowing through the entire cell region to a portion of the cell region when a current flows through the cell region of the semiconductor element 11. The Kelvin emitter pad is a control pad to which a gate drive voltage for controlling the on / off of the semiconductor element 11 is applied. The temperature sense diode pad is a control pad electrically connected to the anode and cathode of a temperature sensor provided in the semiconductor element 11. The temperature of the semiconductor element 11 is measured based on the voltage between the anode and cathode of the temperature sense diode provided in the cell region.

[0028] As described above, in the submodule 1, the conductor plate 21 is exposed on the bottom surface S1 side, the conductor piece 22 is exposed on the top surface S2 side, and the first control terminal 23 is exposed on the side surface S3 side from the first sealing member 31. With this configuration, it is possible to increase the creepage distance between the exposed portion of the conductor piece 22 and the exposed portion of the conductor plate 21 and the exposed portion of the first control terminal 23, and therefore it is possible to perform a screening test at a high voltage and a high current.

[0029] 4 is an enlarged perspective view schematically showing a portion of side surface S3 of submodule 1. As shown in FIG. 4, the side surface of first sealing member 31 corresponding to side surface S3 of submodule 1 may include protrusion 31a that protrudes outward in a plan view of first sealing member 31 and partially covers first control terminal 23. With this configuration, it is possible to increase the creepage distance between first control terminal 23 and each of conductor plate 21, which is at the drain potential, and conductor piece 22, which is at the source potential, during screening testing and when mounted in a product.

[0030] 3, a step 31b may be provided in a portion of the protrusion 31a that is positioned in a direction different from the direction in which the protrusion 31a protrudes, i.e., in a side portion of the protrusion 31a. In FIG. 3, the side portion of the protrusion 31a is the portion on the lower surface S1 side of the protrusion 31a, but it may also be the portion on the upper surface S2 side of the protrusion 31a. With this configuration, the creepage distance can be further increased.

[0031] <Configuration of semiconductor device> Fig. 5 is a perspective view schematically showing the configuration of the semiconductor device according to the first embodiment, and Fig. 6 is a perspective view showing the configuration obtained by removing the second sealing member 41 from the configuration of Fig. 5. Fig. 7 is a perspective view showing the configuration obtained by removing the case 51 from the configuration of Fig. 6, and Fig. 8 is a view showing the configuration obtained by removing the connecting members 72a and 72b from the configuration of Fig. 7.

[0032] As shown in Figures 5 to 8, the semiconductor device according to the first embodiment includes a plurality of submodules 1 (submodules 1a, 1b), a second sealing member 41, an insulating substrate 42, a case 51, and connecting members 72a, 72b.

[0033] 8, first circuit patterns 42a, 42b, 42c, and 42d are provided on an insulating substrate 42. The first circuit patterns 42a to 42d are electrically connected to at least one of the conductor plates 21 of the plurality of submodules 1. In the first embodiment, the first circuit patterns 42b and 42c are electrically connected to the conductor plates 21 of the submodules 1a and 1b, respectively.

[0034] 7, connection members 72a and 72b are electrically connected to at least one of the conductor pieces 22 of the multiple submodules 1. In the first embodiment, connection member 72a electrically connects first circuit pattern 42a to conductor piece 22 of submodule 1a, and connection member 72a electrically connects first circuit patterns 42b and 42d to conductor piece 22 of submodule 1b. With this configuration, first circuit patterns 42a to 42d of insulating substrate 42 allow current to flow in the in-plane direction of the semiconductor device, and each submodule 1 allows current to flow in the out-of-plane direction of the semiconductor device.

[0035] 6, a case 51 surrounds the side surface S3 of the multiple submodules 1. Electrodes 51a, 51b, and 51c are provided on the case 51. One of the electrodes 51a and 51b is electrically connected to the first circuit pattern 42a, and the other of the electrodes 51a and 51b is electrically connected to the first circuit pattern 42c. The electrode 51c is electrically connected to the first circuit pattern 42d.

[0036] As shown in FIG. 5, the second sealing member 41 seals the multiple submodules 1, the insulating substrate 42, and the connecting members 72a and 72b. In the example shown in FIG. 5, the second sealing member 41 is provided within the opening of the case 51, and a portion of the first control terminal 23 is exposed through the second sealing member 41. The hardness of the second sealing member 41 is lower than that of the first sealing member 31, and the second sealing member 41 is more flexible than the first sealing member 31. The hardness can be measured using, for example, a push-in test method. The material of the second sealing member 41 may be, for example, a gel-like insulating sealing material. This configuration easily ensures insulation between an external housing, such as a cooling base plate (not shown), and the first circuit patterns 42a to 42d of the insulating substrate 42.

[0037] FIG. 9 is a cross-sectional view schematically showing the connection between the first control terminal 23 and the control board 61 of the submodule 1 according to the first embodiment.

[0038] The case 51 has a lid 52 that fits along the top surface S2 of the submodule 1, and the lid 52 is attached to the main body of the case 51 while covering the opening of the case 51. The control board 61 is provided on the opposite side of the lid 52 from the submodule 1. In other words, the control board 61 and the submodule 1 are provided so as to sandwich the lid 52 therebetween.

[0039] The first control terminal 23 of the submodule 1 is electrically connected to the control board 61. This allows the control board 61 to control the submodule 1 by inputting a signal to the first control terminal 23.

[0040] 9, the first control terminal 23 is electrically connected to the control board 61 via a through hole in the lid 52. With this configuration, the position of the first control terminal 23 is restricted by the through hole in the lid 52, thereby improving the positioning accuracy of the first control terminal 23. As a result, the first control terminal 23 and the control board 61 can be connected easily and reliably.

[0041] The lid 52 may include a guide portion 53 that guides the first control terminal 23 into the through-hole of the lid 52. This configuration facilitates the task of passing the first control terminal 23 through the through-hole of the lid 52. The case 51 may also include a mounting portion 54 on which the control board 61 is mounted. This configuration reduces the area where the control board 61 and the lid 52 come into contact, thereby reducing damage to the control board 61 and the lid 52.

[0042] <Manufacturing method> Next, a method for manufacturing the semiconductor device according to the first embodiment will be described.

[0043] First, a preparation step is performed to prepare the above-described plurality of submodules 1. In the preparation step, for example, a plurality of submodules 1 are formed. In the sealing step of forming the first sealing member 31 among the steps of forming the submodule 1, a film that deforms in response to stress may be sandwiched between the conductor piece 22 and a sealing mold (not shown) to bring the film into close contact with the conductor piece 22. With this configuration, it is possible to prevent the resin of the first sealing member 31 from flowing around onto the upper surface of the conductor piece 22.

[0044] After the preparation process for the plurality of submodules 1, an electrical characteristic test is performed for each of the plurality of submodules 1 by applying a voltage to the conductor plate 21, the conductor piece 22, and the first control terminal 23. As described above, the creepage distance between the exposed portion of the conductor piece 22 and the exposed portion of the conductor plate 21 and the exposed portion of the first control terminal 23 can be increased, so that a screening test can be performed at a high voltage and a high current. After the screening test process, the process of forming the semiconductor device is performed.

[0045] <Summary of the First Embodiment> In the semiconductor device according to the first embodiment, the conductor plate 21 electrically connected to the drain electrode is exposed from the lower surface S1 side of the first sealing member 31, and the conductor piece 22 electrically connected to the source electrode 11a is exposed from the upper surface S2 side of the first sealing member 31. With this configuration, electricity can be passed between the lower surface S1 and the upper surface S2 of the submodule 1, so that even the semiconductor element 11 made of SiC can be passed through in the same way as a semiconductor element made of Si. This makes it easy to replace a semiconductor element made of Si with a semiconductor element 11 made of SiC.

[0046] Furthermore, in the first embodiment, the hardness of the first sealing member 31 of the submodule 1 is relatively high, and therefore the submodule 1 can withstand screening tests at high temperatures, high voltages, and high currents better than a configuration that does not include the first sealing member 31. Furthermore, by performing a screening test under such appropriate conditions for each submodule 1, it is possible to increase the likelihood of removing unsuitable submodules 1 before assembling the semiconductor device, thereby improving the final yield of the semiconductor device.

[0047] Furthermore, in the first embodiment, the hardness of second sealing member 41 is lower than that of first sealing member 31, so that it is possible to reduce stress in the entire semiconductor device. As a result, it is possible to suppress stress such as thermal stress in the semiconductor device and the warpage that accompanies the stress, and to improve reliability and manufacturing yield.

[0048] In the first embodiment, the conductor plate 21 is exposed from the bottom surface S1, the conductor piece 22 is exposed from the top surface S2, and the first control terminal 23 is exposed from the side surface S3 of the first sealing member 31. This configuration increases the creepage distance between the exposed portion of the conductor piece 22 and the exposed portion of the conductor plate 21 and the exposed portion of the first control terminal 23, making it possible to perform screening tests at high voltages and currents. Furthermore, exposing the first control terminal 23 from the side surface S3 of the first sealing member 31 increases the number of connecting members 72a and 72b connected to the conductor piece 22 and the degree of freedom in design.

[0049] Furthermore, when the material of a semiconductor element contains SiC, the defect density of the wafer base material of the semiconductor element is generally higher than that of Si, making it difficult to increase the chip size of the semiconductor element, and the chip size constraints also limit the electrode area of ​​the semiconductor element. Therefore, each semiconductor element 11 made of SiC does not have a sufficient area for connecting connecting members such as wires and ribbons. However, by providing a conductor piece 22 that straddles the source electrodes 11a of multiple semiconductor elements 11, the connection area is not the source electrodes 11a of the semiconductor elements 11, but the wider conductor piece 22, so the connection area can be secured.

[0050] Furthermore, in the first embodiment, since the submodule 1 is provided with the first control terminal 23, it can be connected to the control board 61 without providing any other control terminal. As a result, the manufacturing cost of the semiconductor device can be reduced.

[0051] <Embodiment 2> FIG. 10 is a cross-sectional view schematically showing the connection between the first control terminal 23 and the control board 61 of the submodule 1 according to the second embodiment.

[0052] The semiconductor device according to the second embodiment includes a case 51, a control board 61, a wire 73, and a second control terminal 81. The case 51 and the control board 61 according to the second embodiment are generally similar to the case 51 and the control board 61 according to the first embodiment.

[0053] The exposed portion of the first control terminal 23 is exposed from the side surface of the first sealing member 31 corresponding to the side surface S3 of the submodule 1, and includes an end portion 23b that is mounted on the upper surface S2 of the submodule 1 by the bending process.

[0054] The second control terminal 81 has a first end 81a and a second end 81b, and is provided in the case 51. The control board 61 is electrically connected to the first end 81a of the second control terminal 81. The wire 73 electrically connects the end 23b of the first control terminal 23 and the second end 81b of the second control terminal 81.

[0055] According to the semiconductor device of the second embodiment as described above, the first control terminal 23 is electrically connected to the control board 61 via the second control terminal 81 provided on the case 51. With this configuration, the positioning accuracy of the second control terminal 81 can be improved compared to the positioning accuracy of the first control terminal 23 in FIG.

[0056] <Third Embodiment> FIG. 11 is a cross-sectional view schematically showing the connection between the first control terminal 23 and the control board 61 of the submodule 1 according to the third embodiment.

[0057] The semiconductor device according to the third embodiment includes a control board 61 and a third control terminal 82. The control board 61 according to the third embodiment is generally similar to the control board 61 according to the first embodiment.

[0058] In addition to the first circuit patterns 42b and 42c described in the first embodiment, a second circuit pattern 42e is provided on the insulating substrate 42. The exposed portion of the first control terminal 23 is exposed from the side surface of the first sealing member 31 corresponding to the side surface S3 of the submodule 1, and is electrically connected to the second circuit pattern 42e.

[0059] The third control terminal 82 has a first end 82a and a second end 82b, and the first end 82a is electrically connected to the second circuit pattern 42e. The control board 61 is electrically connected to the second end 82b of the third control terminal 82.

[0060] According to the semiconductor device of the third embodiment as described above, the first control terminal 23 is electrically connected to the control board 61 via the third control terminal 82 connected to the second circuit pattern 42e. With this configuration, the semiconductor device has a configuration similar to that of a general semiconductor device in which a control terminal is connected to a circuit pattern, and therefore the design of the semiconductor device of the third embodiment can be standardized with the design of a general semiconductor device. This standardization also allows peripheral components to be standardized, thereby reducing the cost of the semiconductor device and shortening the development period.

[0061] <Fourth Embodiment> FIG. 12 is an enlarged perspective view schematically showing the first control terminal 23 of the submodule 1 according to the fourth embodiment.

[0062] The semiconductor device according to the fourth embodiment includes a control board (not shown), a wire 74 that is a conductive member, and a fourth control terminal 83. The control board according to the fourth embodiment is generally similar to the control board 61 according to the first embodiment.

[0063] The exposed portion of the first control terminal 23 is exposed by a cutout in the boundary portion of the first sealing member 31 that corresponds to the boundary portion between the top surface S2 and the side surface S3 of the submodule 1. The surface of the exposed portion of the first control terminal 23 on the side of the bottom surface S1 is fixed to the first sealing member 31.

[0064] The fourth control terminal 83 has a first end and a second end 83b and is spaced apart from the submodule 1. The control board is electrically connected to the first end of the fourth control terminal 83. The wire 74 electrically connects the exposed portion of the first control terminal 23 to the second end 83b of the fourth control terminal 83.

[0065] According to the semiconductor device of the fourth embodiment as described above, as in the second embodiment, the portion of the first control terminal 23 exposed by the notch is electrically connected to the control board via the fourth control terminal 83. With this configuration, it is possible to achieve substantially the same configuration and effect as in the second embodiment without bending the first control terminal 23 as in the second embodiment. In addition, the wire 74 can be directly connected to the submodule 1.

[0066] <Fifth Embodiment> Fig. 13 is a perspective view schematically showing the configuration of a submodule 1 according to the present embodiment 5. Fig. 14 is a cross-sectional view schematically showing the connection between a first control terminal 23 of the submodule 1 according to the present embodiment 5 and a control board 61.

[0067] The semiconductor device according to the fifth embodiment includes a control board 61 and a fifth control terminal 84. The control board 61 according to the fifth embodiment is generally similar to the control board 61 according to the first embodiment.

[0068] 13 and 14, in the fifth embodiment, the metal tube portion 23c, which is the exposed portion of the first control terminal 23, is exposed from the upper surface of the first sealing member 31 corresponding to the upper surface S2 of the submodule 1. The material of the metal tube portion 23c may be any material as long as it is conductive, and includes, for example, copper.

[0069] 14, the fifth control terminal 84 is provided with an elastic portion 84a having a width greater than that of other portions, thereby enabling a press-fit connection between the elastic portion 84a and the metal tubular portion 23c. This configuration allows the first control terminal 23 and the fifth control terminal 84 to be easily connected, thereby improving the ease of assembly of the semiconductor device.

[0070] 14, the fifth control terminal 84 and the control board 61 may be press-fit connected in a similar manner. Although not shown, the conductor piece 22 in FIG. 8 may be provided with a metal tubular portion similar to the metal tubular portion 23c, and the connecting members 72a and 72b in FIG. 7 may be provided with an elastic portion similar to the elastic portion 84a, thereby press-fit connecting the conductor piece 22 and the connecting members 72a and 72b. Even in these cases, the ease of assembly of the semiconductor device can be improved.

[0071] <Sixth Embodiment> In the first embodiment, two conductor pieces 22 are provided for one submodule as shown in FIG. 1, and the two conductor pieces 22 are connected by a connecting member 72a as shown in FIG. 7. However, when a current flows in the configuration as shown in FIG. 7, a potential difference occurs between the two conductor pieces 22 due to the resistance of the connecting member 72a. As a result, a difference occurs between the gate-source voltage of the semiconductor element 11 connected to one conductor piece 22 and the corresponding voltage of the semiconductor element 11 connected to the other conductor piece 22, which may result in non-uniform operation. In contrast, the semiconductor device according to the sixth embodiment is capable of suppressing such non-uniform operation as will be described below.

[0072] Fig. 15 is a plan view schematically showing the configuration of submodule 1 according to the sixth embodiment, excluding first sealing member 31, and Fig. 16 is a cross-sectional view of the configuration of submodule 1 taken along line BB in Fig. 15. Fig. 17 is a plan view schematically showing the configuration of submodule 1 according to the sixth embodiment.

[0073] The dotted lines on the conductor pieces 22 in Fig. 15 indicate hidden lines of the semiconductor elements 11. As shown in Fig. 15, the multiple semiconductor elements 11 are arranged in a line in a plan view. Hereinafter, the direction in which the multiple semiconductor elements 11 are arranged (the left-right direction in Fig. 15) will be referred to as the arrangement direction. Note that the line arrangement means that the multiple semiconductor elements 11 are not connected in parallel with respect to the direction in which current flows.

[0074] The semiconductor elements 11 have a rectangular shape in plan view with the long sides extending in a direction different from the arrangement direction. In the example of FIG. 15, the semiconductor elements 11 extend in the vertical direction perpendicular to the arrangement direction, but this is not limited to this. Also, in the example of FIG. 15, each semiconductor element 11 has a rectangular shape in plan view, but this is not limited to this. Also, in the example of FIG. 15, the number of semiconductor elements 11 is six, but this is not limited to this, and for example, the number may be ten as in the first embodiment.

[0075] According to the configuration of the semiconductor device of the sixth embodiment, the semiconductor elements 11 are arranged in a row, and therefore can be connected by a single conductor piece 22. Furthermore, since no current flows in one conductor piece 22 in the arrangement direction, it is possible to prevent a potential difference from occurring in the arrangement direction within the conductor piece 22. This reduces the difference in applied voltage between the semiconductor elements 11 in one submodule 1, thereby reducing the possibility of non-uniform operation. Furthermore, since the semiconductor elements 11 have a rectangular shape with long sides in a direction different from the arrangement direction in a plan view, the shape of the submodule 1 in a plan view does not become too long in the left-right direction of FIG. 15, and therefore can maintain a general aspect ratio.

[0076] Furthermore, in the sixth embodiment, the crystal orientation of SiC in semiconductor element 11 is adjusted so that the defect expansion direction in semiconductor element 11 corresponds to the short-side direction of the shape of semiconductor element 11 in a plan view. The defect expansion direction here refers to a direction in which defects tend to expand due to bipolar current flow or the like in a semiconductor element containing SiC. With this configuration, defect expansion in semiconductor element 11 can be suppressed.

[0077] Furthermore, in the sixth embodiment, the semiconductor elements 11 are arranged in a zigzag pattern along the arrangement direction of the semiconductor elements 11. In the region 11c between two adjacent semiconductor elements 11, heat generated from each of the adjacent semiconductor elements 11 causes a temperature rise, resulting in thermal interference. By arranging the semiconductor elements 11 in a zigzag pattern along the arrangement direction, the region 11c between the two adjacent semiconductor elements 11 can be reduced, thereby reducing thermal interference. This effect is particularly effective in a configuration in which a conductor plate made of copper or the like that promotes heat diffusion is used as the conductor plate 21.

[0078] Furthermore, in the sixth embodiment, the conductor plate 21 has a recess 21a in plan view, and the first control terminal 23 has a protrusion 23d surrounded by the recess 21a in plan view. With this configuration, even if the plurality of semiconductor elements 11 are arranged in a zigzag pattern along the arrangement direction, the distance between each of the plurality of semiconductor elements 11 and the first control terminal 23 can be made as uniform as possible. This makes it possible to make the impedance of the wire 24 as uniform as possible, thereby suppressing differences in voltages applied to the gates of the plurality of semiconductor elements 11.

[0079] The semiconductor device according to the sixth embodiment further includes a drain sense terminal 25 connected to the conductor plate 21. In the example of Fig. 15, the portion where the conductor plate 21 and the drain sense terminal 25 are connected is hatched with diagonal lines. The drain sense terminal 25 is a terminal for detecting the current flowing through the drain of the semiconductor element 11, and can perform protection such as stopping the supply of current to the semiconductor element 11 if the current is not within a certain range, for example.

[0080] Furthermore, in the sixth embodiment, the drain sense terminal 25 is connected to a region 11d adjacent to two semiconductor elements 11, not a region 11c between two adjacent semiconductor elements 11, among the regions on the conductor plate 21. With this configuration, the drain sense terminal 25 and the conductor plate 21 can be connected at a position as far away as possible from the semiconductor elements 11. This makes it possible to effectively utilize the region created by providing the multiple semiconductor elements 11 in a zigzag pattern, and also makes it possible to increase the creepage distance between the drain sense terminal 25 and the conductor piece 22.

[0081] The semiconductor device according to the sixth embodiment also includes a gate resistor 26. The gate resistor 26 is provided in a portion of the first control terminal 23 that faces the semiconductor element 11 in a plan view and is connected between the first control terminal 23 and the semiconductor element 11. The gate resistor 26 is, for example, a laminate of a silicon film, a silicon oxide film, and a polysilicon film, and has a relatively large resistance. Although not shown, a wire bond electrode is provided on the upper surface of the gate resistor 26. In the example of FIG. 15 , the gate resistor 26 is provided on the protrusion 23d of the first control terminal 23, and the upper surface of the gate resistor 26 is connected to the semiconductor element 11 by the wire 24. With this configuration, the difference in threshold voltage Vth among the multiple semiconductor elements 11 can be ignored, thereby reducing the difference in operation timing caused by the difference in threshold voltage Vth.

[0082] If an element having the same function as the gate resistance element 26 were provided in a circuit external to the submodule 1, the distance between the gate resistance element 26 and the semiconductor element 11 would increase, and the element would be affected by the resistance of the first control terminal 23. In contrast, according to the sixth embodiment, the gate resistance element 26 is connected between the first control terminal 23 and the semiconductor element 11, and therefore the effect of the resistance of the first control terminal 23 can be suppressed. Furthermore, if an element having the same function as the gate resistance element 26 were provided inside the semiconductor element 11, the cost per area within the substrate of the semiconductor element 11 would be high, and therefore the cost of the semiconductor device would increase. In contrast, according to the sixth embodiment, the gate resistance element 26 is provided outside the semiconductor element 11, and therefore the cost can be suppressed.

[0083] In the sixth embodiment, as shown in FIG. 16 , the thickness of the first control terminal 23 is smaller than the thickness of the conductive plate 21. By making the thickness of the first control terminal 23 relatively small in this manner, even if the thickness of the first control terminal 23 or its position in the thickness direction is slightly misaligned, it is possible to prevent the first control terminal 23 from being exposed from the lower surface of the first sealing member 31 corresponding to the lower surface S1 of the submodule 1. Furthermore, it is possible to easily perform the bending process for providing the bent portion 23e in the first control terminal 23. On the other hand, by making the thickness of the conductive plate 21 relatively large, it is possible to easily expose the conductive plate 21 from the lower surface of the first sealing member 31 corresponding to the lower surface S1 of the submodule 1. Furthermore, it is possible to promote heat diffusion by the conductive plate 21.

[0084] Furthermore, in the sixth embodiment, similar to the bent portion 23e of the first control terminal 23, the drain sense terminal 25 also has a bent portion 25a. As a result, as shown in Fig. 17, the exposed portions of the conductor piece 22, the first control terminal 23, and the drain sense terminal 25 are exposed from the upper surface of the first sealing member 31 corresponding to the upper surface of the submodule 1. With this configuration, the electrical connection of the submodule 1 can be performed in the same way as the electrical connection of the semiconductor element 11.

[0085] 17 facilitates wire bonding, making it easy to form a configuration in which the exposed portion of the conductor piece 22, the exposed portion of the first control terminal 23, and the exposed portion of the drain sense terminal are each connected to wire 75, as shown in Fig. 18. Furthermore, since press-fit connection is facilitated, it is easy to form a configuration in which the exposed portion of the conductor piece 22, the exposed portion of the first control terminal 23, and the exposed portion of the drain sense terminal are each press-fit connected, as shown in Fig. 19. In Fig. 19, a metal tube portion 22a similar to the metal tube portion 23c in Fig. 14 for press-fit connection is provided on the exposed portion of the conductor piece 22.

[0086] Although not shown, the exposed portions of the conductor piece 22, the first control terminal 23, and the drain sense terminal may be bent so that they stand upright from the upper surface of the first sealing member 31. With a configuration using press-fit connection and a configuration in which the exposed portions are bent, it is not necessary to provide circuits or the like in the horizontal direction of the submodule 1, and therefore the size of the semiconductor device in plan view can be reduced.

[0087] In the sixth embodiment, as shown in Fig. 17, the exposed portion of the conductor piece 22 has a recess 22b in a plan view, and the exposed portion of the drain sense terminal 25 is provided opposite the recess 22b. With this configuration, the creepage distance between the drain sense terminal 25 and the conductor piece 22 can be increased, making it possible to perform a screening test at a high voltage and current. In the example of Fig. 17, the recess 22b is provided at a corner of the exposed portion of the conductor piece 22, but this is not limiting.

[0088] In addition, in the sixth embodiment, in plan view, the exposed portion of first control terminal 23 is provided from the left end to the right end of first sealing member 31. With this configuration, for example, in the configurations shown in Figures 18 and 19, a probe needle for performing a screening test can easily come into contact with the portion of first control terminal 23 where wire 75 and metal tube portion 22a are not provided.

[0089] FIG. 20 is a plan view schematically showing a manufacturing process of the submodule 1 according to the sixth embodiment. First, a metal pattern 2 is prepared, which includes a first control terminal 23, a drain sense terminal 25, and a frame 27. The first control terminal 23 and the drain sense terminal 25 are integrated with the frame 27, but the conductor piece 22 is not integrated with the frame 27. The conductor piece 22 has a source terminal 22c that protrudes from the side surface of the first sealing member 31, and the source terminal 22c is placed on a holding portion 27a that is part of the frame 27. The metal pattern 2 is formed by, for example, punching. The thickness of the metal pattern 2 is smaller than that of the conductor plate 21.

[0090] After preparing the metal pattern 2, the portion of the metal pattern 2 that will become the drain sense terminal 25 is connected to the conductor plate 21. In parallel with or before or after this, the multiple semiconductor elements 11 are connected to the conductor plate 21 and the conductor pieces 22. Then, after forming the first sealing member 31, the first control terminal 23 and the drain sense terminal 25 are separated from the frame 27.

[0091] According to this configuration, the position of the first control terminal 23 relative to the conductive plate 21 is fixed by the frame 27, and after the first sealing member 31 is formed, the first control terminal 23 is separated from the frame 27. This makes it possible to prevent the first control terminal 23 from being misaligned relative to the conductive plate 21. Furthermore, since the drain sense terminal 25 can be formed from the portion of the frame 27 that is connected to the conductive plate 21, the material of the frame 27 can be used effectively.

[0092] Furthermore, in the sixth embodiment, the process temperature when assembling a semiconductor device from a plurality of submodules 1 is lower than the melting point of the connection portion connecting the metal pattern 2 and the conductor plate 21. With this configuration, when assembling a semiconductor device from a plurality of submodules 1, it is possible to avoid the occurrence of poor connection between the drain sense terminal 25 and the conductor plate 21.

[0093] <Variation 1> 21 and 22 are plan views schematically showing the manufacturing process of the submodule 1 according to the present modified example 1 of the present embodiment 6. The submodule 1 according to the present modified example 1 of the present embodiment 6 differs from the submodule 1 according to the embodiment 6 in the positions where signals and power are taken out.

[0094] In the present modified example 1, the drain sense terminal 25 protrudes from the side surface of the first sealing member 31, and does not have a bent portion 25a. The first control terminal 23 protrudes from the side surface of the first sealing member 31, and does not have a bent portion 23e. The conductor piece 22 has a source terminal 22c protruding from the side surface of the first sealing member 31, and the source terminal 22c has a bent portion 22d. The positions of the drain sense terminal 25 and the first control terminal 23 in the thickness direction are generally the same. However, these positions are different from the position of the source terminal 22c in the thickness direction, and the source terminal 22c is spaced apart from the conductor plate 21. To ensure this difference in position, the frame 27 is provided with a holding portion 27a that holds the end of the source terminal 22c.

[0095] 21 is formed, a first sealing member 31 is formed as shown in FIG. 22, and the first control terminal 23 and the drain sense terminal 25 are separated from the frame 27. Thereafter, the portions exposed from the first sealing member 31, i.e., the exposed portion of the source terminal 22c, the exposed portion of the first control terminal 23, and the exposed portion of the drain sense terminal 25, are bent toward the front or back side of FIG. 22. With this configuration, it is not necessary to provide circuits or the like in the horizontal direction of the submodule 1, and therefore the size of the semiconductor device in plan view can be reduced.

[0096] <Variation 2> 23 is a plan view schematically showing the manufacturing process of the submodule 1 according to the present modified example 2 of the present embodiment 6, and Fig. 24 is a plan view schematically showing the configuration of the submodule 1 according to the present modified example 2. In the submodule 1 according to the modified example 2 of the present embodiment 6, the signal and power extraction positions are different from those of the submodule 1 according to the embodiment 6.

[0097] In this second modification, as shown in FIG. 24, the exposed portion of the conductor piece 22 in plan view has a protrusion 22e that protrudes in the direction in which current flows across multiple submodules 1 (see the arrow in FIG. 24). In this second modification, the direction in which current flows across multiple submodules 1 is the short direction of the submodule 1, as in FIG. 7. With this configuration, the creepage distance between the exposed portion of the conductor piece 22 and the exposed portion of the drain sense terminal 25 can be increased, making it possible to perform screening tests at high voltages and currents. Furthermore, circuit patterns are often generally provided in the direction in which current flows across multiple submodules 1. In such cases, the new circuit pattern can be placed next to the existing circuit pattern without having to separately secure space for it, thereby reducing the size of the semiconductor device in plan view.

[0098] 24, similar to the configuration in Fig. 17, the exposed portion of the conductor piece 22, the exposed portion of the first control terminal 23, and the exposed portion of the drain sense terminal 25 are exposed from the upper surface of the first sealing member 31 corresponding to the upper surface of the submodule 1. Therefore, it is possible to easily form a configuration in which the exposed portion of the conductor piece 22, the exposed portion of the first control terminal 23, and the exposed portion of the drain sense terminal are each connected to wire 75 as in Fig. 25, or a configuration in which they are press-fit connected (not shown).

[0099] It should be noted that the embodiments and modifications may be freely combined, and the embodiments and modifications may be modified or omitted as appropriate.

[0100] Various aspects of the present disclosure are summarized below as appendices.

[0101] (Appendix 1) a plurality of sub-modules each having a first main surface, a second main surface opposite to the first main surface, and one or more side surfaces between the first main surface and the second main surface; Each of the plurality of sub-modules comprises: a plurality of semiconductor elements each having a drain electrode provided on the first main surface side and a source electrode and a control electrode provided on the second main surface side; a conductor plate provided on the first main surface side of the plurality of semiconductor elements and electrically connected to the drain electrodes of the plurality of semiconductor elements; conductor pieces provided on the second main surface side of the plurality of semiconductor elements and electrically connected to the source electrodes of the plurality of semiconductor elements; a first control terminal electrically connected to the control electrodes of the plurality of semiconductor elements; a first sealing member that seals the semiconductor elements, the conductor plate, the conductor piece, and the first control terminal while exposing the first main surface side portion of the conductor plate, the second main surface side portion of the conductor piece, and the first control terminal portion; Including, an insulating substrate provided with a first circuit pattern electrically connected to at least one of the conductor plates of the plurality of sub-modules; a connection member electrically connected to at least one of the conductor pieces of the plurality of sub-modules; a second sealing member that seals the plurality of sub-modules, the insulating substrate, and the connection member and has a hardness lower than that of the first sealing member; The semiconductor device further comprises:

[0102] (Appendix 2) The semiconductor device described in Appendix 1, wherein the side surface of the first sealing member corresponding to the side surface of the submodule includes a protrusion that protrudes outward in a planar view of the first sealing member and partially covers the first control terminal.

[0103] (Appendix 3) 3. The semiconductor device according to claim 2, wherein a step portion is provided on a side of the protrusion.

[0104] (Appendix 4) a case having a lid along the second main surface of the submodule; a control board provided on the opposite side of the lid from the sub-module; Furthermore, 4. The semiconductor device according to claim 1, wherein the first control terminal of the submodule is electrically connected to the control board through a through hole in the lid.

[0105] (Appendix 5) the lid includes a guide portion that guides the first control terminal into the through hole, 5. The semiconductor device according to claim 4, wherein the case includes a mounting portion on which the control board is mounted.

[0106] (Appendix 6) 6. The semiconductor device according to any one of claims 1 to 5, wherein the material of the conductive connecting member electrically connecting the plurality of semiconductor elements to the conductive plate or the conductive piece includes silver or copper.

[0107] (Appendix 7) the exposed portion of the first control terminal is exposed from a side surface of the first sealing member corresponding to the side surface of the sub-module and includes an end portion that is mounted on the second main surface of the sub-module; a case surrounding the side surfaces of the plurality of sub-modules; a second control terminal having a first end and a second end and provided on the case; a control board electrically connected to the first end of the second control terminal; a wire electrically connecting the end of the first control terminal and the second end of the second control terminal; 2. The semiconductor device according to claim 1, further comprising:

[0108] (Appendix 8) The insulating substrate further includes a second circuit pattern; the exposed portion of the first control terminal is exposed from a side surface of the first sealing member corresponding to the side surface of the sub-module and is electrically connected to the second circuit pattern; a third control terminal having a first end and a second end, the first end being electrically connected to the second circuit pattern; a control board electrically connected to the second end of the third control terminal; 2. The semiconductor device according to claim 1, further comprising:

[0109] (Appendix 9) the exposed portion of the first control terminal is exposed by a cutout in a boundary portion of the first sealing member corresponding to a boundary portion between the second main surface and the side surface of the sub-module, a surface of the exposed portion of the first control terminal on the first main surface side is fixed to the first sealing member; a fourth control terminal having a first end and a second end and spaced apart from the sub-module; a control board electrically connected to the first end of the fourth control terminal; a conductive member electrically connecting the exposed portion of the first control terminal and the second end of the fourth control terminal; 2. The semiconductor device according to claim 1, further comprising:

[0110] (Appendix 10) 10. The semiconductor device according to claim 9, wherein the conductive member is a wire.

[0111] (Appendix 11) the one or more aspects is a plurality of aspects, The semiconductor device described in Appendix 1, wherein the exposed portion of the first control terminal is exposed from only one of the multiple side surfaces of the first sealing member that respectively corresponds to the multiple side surfaces of the submodule.

[0112] (Appendix 12) the plurality of semiconductor elements are arranged in a plurality of rows, each row extending along the direction in which the conductor plate extends; 12. The semiconductor device according to claim 1, wherein the first control terminal includes a lead portion provided between the semiconductor elements in the adjacent rows.

[0113] (Appendix 13) 13. The semiconductor device according to claim 12, wherein the lead portion is provided parallel to the conductive plate.

[0114] (Appendix 14) 12. The semiconductor device according to claim 1, wherein the plurality of semiconductor elements are arranged in a line in a plan view.

[0115] (Appendix 15) 15. The semiconductor device according to claim 14, wherein the semiconductor element has a rectangular shape in a plan view with long sides in a direction different from the arrangement direction of the plurality of semiconductor elements.

[0116] (Appendix 16) 16. The semiconductor device according to claim 15, wherein the defect extension direction of the semiconductor element corresponds to the short-side direction of the shape of the semiconductor element in a plan view.

[0117] (Appendix 17) 17. The semiconductor device according to claim 1, wherein the semiconductor elements are arranged in a zigzag pattern along an arrangement direction of the semiconductor elements.

[0118] (Appendix 18) the conductive plate has a recess in a plan view, 18. The semiconductor device according to claim 17, wherein the first control terminal has a protrusion surrounded by the recess in a plan view.

[0119] (Appendix 19) 19. The semiconductor device according to any one of Supplementary Note 1 to Supplementary Note 18, wherein a thickness of the first control terminal is smaller than a thickness of the conductive plate.

[0120] (Appendix 20) a drain sense terminal connected to the conductive plate; 19. The semiconductor device according to claim 1, wherein the portion of the conductor piece, the portion of the first control terminal, and the portion of the drain sense terminal are exposed from a surface of the first sealing member corresponding to the second main surface of the submodule.

[0121] (Appendix 21) 21. The semiconductor device according to claim 20, wherein the portion of the conductor piece, the portion of the first control terminal, and the portion of the drain sense terminal are each connected to a wire.

[0122] (Appendix 22) 21. The semiconductor device according to claim 20, wherein the portion of the conductor piece, the portion of the first control terminal, and the portion of the drain sense terminal are press-fit connected to each other.

[0123] (Appendix 23) a drain sense terminal connected to the conductive plate; the portion of the conductor piece and the portion of the drain sense terminal are exposed from a surface of the first sealing member corresponding to the second main surface of the submodule, the portion of the conductor piece has a recess in a plan view, 20. The semiconductor device according to claim 1, wherein the portion of the drain sense terminal is provided opposite the recess.

[0124] (Appendix 24) The semiconductor device described in Appendix 17, further comprising a drain sense terminal connected to a region on the conductor plate that is adjacent to the two semiconductor elements and is not a region between the two adjacent semiconductor elements.

[0125] (Appendix 25) the portion of the first control terminal is exposed from a surface of the first sealing member corresponding to the second main surface of the sub-module; 25. The semiconductor device according to claim 1, wherein, in a plan view, the portion of the first control terminal is provided from one end to the other end of the first sealing member.

[0126] (Appendix 26) a drain sense terminal connected to the conductive plate and protruding from a side surface of the first sealing member corresponding to the side surface of the submodule; the first control terminal protrudes from the side surface of the first sealing member; 20. The semiconductor device according to claim 1, wherein the conductor piece has a source terminal protruding from the side surface of the first sealing member.

[0127] (Appendix 27) 27. The semiconductor device according to claim 1, wherein the portion of the conductor piece in plan view has a convex portion that protrudes in a direction in which current flows across the plurality of submodules.

[0128] (Appendix 28) 28. The semiconductor device according to claim 1, further comprising a gate resistor provided in a portion of the first control terminal facing the semiconductor element in a plan view, the gate resistor being connected between the first control terminal and the semiconductor element.

[0129] (Appendix 29) a preparation step of preparing a plurality of sub-modules each having a first main surface, a second main surface opposite to the first main surface, and one or more side surfaces between the first main surface and the second main surface; Each of the plurality of sub-modules comprises: a plurality of semiconductor elements each having a drain electrode provided on the first main surface side and a source electrode and a control electrode provided on the second main surface side; a conductor plate provided on the first main surface side of the plurality of semiconductor elements and electrically connected to the drain electrodes of the plurality of semiconductor elements; conductor pieces provided on the second main surface side of the plurality of semiconductor elements and electrically connected to the source electrodes of the plurality of semiconductor elements; a first control terminal electrically connected to the control electrodes of the plurality of semiconductor elements; a first sealing member that seals the semiconductor elements, the conductor plate, the conductor piece, and the first control terminal while exposing the first main surface side portion of the conductor plate, the second main surface side portion of the conductor piece, and the first control terminal portion; Including, a screening test step of applying a voltage to the conductor plate, the conductor piece, and the first control terminal of each of the plurality of sub-modules after the preparation step to perform an electrical characteristic test; forming a semiconductor device after the screening test step; Furthermore, The semiconductor device includes: the plurality of sub-modules; an insulating substrate provided with a first circuit pattern electrically connected to at least one of the conductor plates of the plurality of sub-modules; a connection member electrically connected to at least one of the conductor pieces of the plurality of sub-modules; a second sealing member that seals the plurality of sub-modules, the insulating substrate, and the connection member and has a hardness lower than that of the first sealing member; A method for manufacturing a semiconductor device, comprising:

[0130] (Appendix 30) 30. The method for manufacturing a semiconductor device according to claim 29, wherein the plurality of semiconductor elements and the conductor pieces are electrically connected without applying pressure.

[0131] (Appendix 31) 31. The method for manufacturing a semiconductor device according to claim 29 or 30, wherein the melting point of a conductive connecting member electrically connecting the plurality of semiconductor elements to the conductor plate or the conductor piece is higher than a process temperature when assembling the semiconductor device from the plurality of sub-modules.

[0132] (Appendix 32) connecting a metal pattern including the first control terminal and a frame to the conductor plate; 32. The method for manufacturing a semiconductor device according to claim 29, wherein the first control terminal is separated from the frame after the first sealing member is formed.

[0133] (Appendix 33) the metal pattern further includes a drain sense terminal connected to the conductive plate; 33. The method for manufacturing a semiconductor device according to claim 32, wherein the drain sense terminal is separated from the frame after the first sealing member is formed.

[0134] (Appendix 34) 34. The method for manufacturing a semiconductor device according to claim 32, wherein a process temperature when assembling the semiconductor device from the plurality of sub-modules is lower than the melting point of the connection portion connecting the metal pattern and the conductive plate. [Explanation of symbols]

[0135] REFERENCE SIGNS LIST 1 submodule, 2 metal pattern, 11 semiconductor element, 11a source electrode, 11b control electrode, 11c, 11d region, 14, 17 conductive connection member, 21 conductor plate, 21a recess, 22 conductor piece, 22b recess, 22c source terminal, 23 first control terminal, 23a lead portion, 23b end portion, 23d protrusion, 25 drain sense terminal, 26 gate resistor element, 27 frame, 31 first sealing member, 31a protrusion, 31b step portion, 41 second sealing member, 42 insulating substrate, 42a, 42b, 42c, 42d first circuit pattern, 42e second circuit pattern, 51 case, 52 lid, 61 control board, 72 connection member, 73, 74 wire, 81 second control terminal, 82 third control terminal, 83 4th control terminal, 81a, 82a, 83a first end, 81b, 82b, 83b second end, S1 bottom surface, S2 top surface, S3 side surface.

Claims

1. a plurality of sub-modules each having a first main surface, a second main surface opposite to the first main surface, and one or more side surfaces between the first main surface and the second main surface; Each of the plurality of sub-modules comprises: a plurality of semiconductor elements each having a drain electrode provided on the first main surface side and a source electrode and a control electrode provided on the second main surface side; a conductor plate provided on the first main surface side of the plurality of semiconductor elements and electrically connected to the drain electrodes of the plurality of semiconductor elements; a conductor piece provided on the second main surface side of the plurality of semiconductor elements and electrically connected to the source electrodes of the plurality of semiconductor elements; a first control terminal electrically connected to the control electrodes of the plurality of semiconductor elements; a first sealing member that seals the semiconductor elements, the conductor plate, the conductor pieces, and the first control terminals while exposing the first main surface side portion of the conductor plate, the second main surface side portion of the conductor pieces, and the first control terminals; Including, an insulating substrate provided with a first circuit pattern electrically connected to at least one of the conductor plates of the plurality of sub-modules; a connection member electrically connected to at least one of the conductor pieces of the plurality of sub-modules; a second sealing member that seals the plurality of sub-modules, the insulating substrate, and the connection member and has a hardness lower than that of the first sealing member; The semiconductor device further comprises:

2. 2. The semiconductor device according to claim 1, a side surface of the first sealing member corresponding to the side surface of the submodule includes a protrusion that protrudes outward in a plan view of the first sealing member and partially covers the first control terminal.

3. 3. The semiconductor device according to claim 2, The semiconductor device further comprises a step portion provided on a side of the protrusion.

4. 4. The semiconductor device according to claim 1, a case having a lid along the second main surface of the submodule; a control board provided on the opposite side of the lid from the sub-module; Furthermore, The first control terminal of the sub-module is electrically connected to the control board through a through hole in the lid.

5. 5. The semiconductor device according to claim 4, the cover includes a guide portion that guides the first control terminal into the through hole, The case includes a mounting portion on which the control board is mounted.

6. 4. The semiconductor device according to claim 1, A semiconductor device, wherein the material of the conductive connecting member that electrically connects the plurality of semiconductor elements to the conductive plate or the conductive piece includes silver or copper.

7. 2. The semiconductor device according to claim 1, the exposed portion of the first control terminal is exposed from a side surface of the first sealing member corresponding to the side surface of the sub-module and includes an end portion that is mounted on the second main surface of the sub-module, a case surrounding the side surfaces of the plurality of sub-modules; a second control terminal having a first end and a second end and provided on the case; a control board electrically connected to the first end of the second control terminal; a wire electrically connecting the end of the first control terminal and the second end of the second control terminal; The semiconductor device further comprises:

8. 2. The semiconductor device according to claim 1, The insulating substrate further includes a second circuit pattern; the exposed portion of the first control terminal is exposed from a side surface of the first sealing member corresponding to the side surface of the sub-module and is electrically connected to the second circuit pattern; a third control terminal having a first end and a second end, the first end being electrically connected to the second circuit pattern; a control board electrically connected to the second end of the third control terminal; The semiconductor device further comprises:

9. 2. The semiconductor device according to claim 1, the exposed portion of the first control terminal is exposed by a cutout in a boundary portion of the first sealing member corresponding to a boundary portion between the second main surface and the side surface of the sub-module, a surface of the exposed portion of the first control terminal on the first main surface side is fixed to the first sealing member; a fourth control terminal having a first end and a second end, the fourth control terminal being spaced apart from the sub-module; a control board electrically connected to the first end of the fourth control terminal; a conductive member electrically connecting the exposed portion of the first control terminal and the second end of the fourth control terminal; The semiconductor device further comprises:

10. 10. The semiconductor device according to claim 9, The semiconductor device, wherein the conductive member is a wire.

11. 2. The semiconductor device according to claim 1, the one or more aspects is a plurality of aspects, the exposed portion of the first control terminal is exposed from only one of a plurality of side surfaces of the first sealing member corresponding to the plurality of side surfaces of the sub-module, respectively.

12. 4. The semiconductor device according to claim 1, the plurality of semiconductor elements are arranged in a plurality of rows, each row extending along the direction in which the conductor plate extends; The semiconductor device, wherein the first control terminal includes a lead portion provided between the semiconductor elements in the adjacent rows.

13. 13. The semiconductor device according to claim 12, The lead portion is provided parallel to the conductive plate.

14. 2. The semiconductor device according to claim 1, The semiconductor device, wherein the plurality of semiconductor elements are arranged in a line in a plan view.

15. 15. The semiconductor device according to claim 14, The semiconductor device, wherein the semiconductor element has a rectangular shape in a plan view with a long side in a direction different from the arrangement direction of the plurality of semiconductor elements.

16. 16. The semiconductor device according to claim 15, A semiconductor device, wherein the defect extension direction of the semiconductor element corresponds to the short-side direction of the shape of the semiconductor element in a plan view.

17. 2. The semiconductor device according to claim 1, The semiconductor device, wherein the plurality of semiconductor elements are provided in a zigzag pattern along an arrangement direction of the plurality of semiconductor elements.

18. 18. The semiconductor device according to claim 17, the conductive plate has a recess in a plan view, The first control terminal has a protrusion surrounded by the recess in a plan view.

19. 2. The semiconductor device according to claim 1, The semiconductor device, wherein the thickness of the first control terminal is smaller than the thickness of the conductive plate.

20. 2. The semiconductor device according to claim 1, a drain sense terminal connected to the conductive plate; the portion of the conductor piece, the portion of the first control terminal, and the portion of the drain sense terminal are exposed from a surface of the first sealing member corresponding to the second main surface of the submodule.

21. 21. The semiconductor device according to claim 20, The semiconductor device, wherein the portion of the conductor piece, the portion of the first control terminal, and the portion of the drain sense terminal are each connected to a wire.

22. 21. The semiconductor device according to claim 20, The semiconductor device, wherein the portion of the conductor piece, the portion of the first control terminal, and the portion of the drain sense terminal are press-fit connected to each other.

23. 2. The semiconductor device according to claim 1, a drain sense terminal connected to the conductive plate; the portion of the conductor piece and the portion of the drain sense terminal are exposed from a surface of the first sealing member corresponding to the second main surface of the submodule, the portion of the conductor piece has a recess in a plan view, The portion of the drain sense terminal is provided facing the recess.

24. 18. The semiconductor device according to claim 17, The semiconductor device further comprises a drain sense terminal connected to a region on the conductor plate that is not a region between the two adjacent semiconductor elements but is adjacent to the two semiconductor elements.

25. 2. The semiconductor device according to claim 1, the portion of the first control terminal is exposed from a surface of the first sealing member corresponding to the second main surface of the sub-module; In a plan view, the portion of the first control terminal is provided from one end to the other end of the first sealing member.

26. 2. The semiconductor device according to claim 1, a drain sense terminal connected to the conductive plate and protruding from a side surface of the first sealing member corresponding to the side surface of the submodule; the first control terminal protrudes from the side surface of the first sealing member; The semiconductor device, wherein the conductor piece has a source terminal that protrudes from the side surface of the first sealing member.

27. 2. The semiconductor device according to claim 1, The semiconductor device, wherein the portion of the conductor piece in plan view has a convex portion that protrudes in a direction in which a current flows across the plurality of submodules.

28. 2. The semiconductor device according to claim 1, a gate resistor provided in a portion of the first control terminal facing the semiconductor element in a plan view, the gate resistor being connected between the first control terminal and the semiconductor element;

29. a preparation step of preparing a plurality of sub-modules each having a first main surface, a second main surface opposite to the first main surface, and one or more side surfaces between the first main surface and the second main surface; Each of the plurality of sub-modules comprises: a plurality of semiconductor elements each having a drain electrode provided on the first main surface side and a source electrode and a control electrode provided on the second main surface side; a conductor plate provided on the first main surface side of the plurality of semiconductor elements and electrically connected to the drain electrodes of the plurality of semiconductor elements; a conductor piece provided on the second main surface side of the plurality of semiconductor elements and electrically connected to the source electrodes of the plurality of semiconductor elements; a first control terminal electrically connected to the control electrodes of the plurality of semiconductor elements; a first sealing member that seals the semiconductor elements, the conductor plate, the conductor pieces, and the first control terminals while exposing the first main surface side portion of the conductor plate, the second main surface side portion of the conductor pieces, and the first control terminals; Including, a screening test step of applying a voltage to the conductor plate, the conductor piece, and the first control terminal to test electrical characteristics of each of the plurality of sub-modules after the preparation step; forming a semiconductor device after the screening test step; Furthermore, The semiconductor device includes: the plurality of sub-modules; an insulating substrate provided with a first circuit pattern electrically connected to at least one of the conductor plates of the plurality of sub-modules; a connection member electrically connected to at least one of the conductor pieces of the plurality of sub-modules; a second sealing member that seals the plurality of sub-modules, the insulating substrate, and the connection member and has a hardness lower than that of the first sealing member; A method for manufacturing a semiconductor device, comprising:

30. 30. The method of manufacturing a semiconductor device according to claim 29, The method for manufacturing a semiconductor device, wherein the plurality of semiconductor elements and the conductor pieces are electrically connected without applying pressure.

31. 31. The method for manufacturing a semiconductor device according to claim 29 or 30, A method for manufacturing a semiconductor device, wherein the melting point of the conductive connecting member that electrically connects the plurality of semiconductor elements to the conductive plate or the conductive piece is higher than the process temperature when assembling the semiconductor device from the plurality of sub-modules.

32. 31. The method for manufacturing a semiconductor device according to claim 29 or 30, connecting a metal pattern including the first control terminal and a frame to the conductor plate; the first control terminal is separated from the frame after the first sealing member is formed.

33. 33. The method of manufacturing a semiconductor device according to claim 32, the metal pattern further includes a drain sense terminal connected to the conductive plate; the drain sense terminal is separated from the frame after the first sealing member is formed.

34. 33. The method of manufacturing a semiconductor device according to claim 32, A method for manufacturing a semiconductor device, wherein a process temperature when assembling the semiconductor device from the plurality of sub-modules is lower than a melting point of a connection portion connecting the metal pattern and the conductive plate.

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