Reinforcement learning of tactile grasping policies

Abstract

Apparatus, systems, and techniques for grasping objects using an articulated robotic hand equipped with one or more tactile sensors. In at least one embodiment, a machine-learned model trained in simulation to grasp a rectangular prism using signals received from the tactile sensors is applied to grasp objects of various shapes in a real-world environment.

Description

[Technical Field]

[0001] This application claims priority to U.S. Patent Application No. 16 / 663,222, filed October 24, 2019, entitled "REINFORCEMENT LEARNING OF TACTILE GRASP POLICIES," the entire contents of which are incorporated herein by reference and for all purposes.

[0002] At least one embodiment relates to processing resources used to perform and facilitate a robotic control system, for example, at least one embodiment relates to a processor or computing system used to train a neural network that enables controlling a haptic robotic grasp. [Background technology]

[0003] Robotic automation is a developing field of technology with great potential. A key problem within the field of automation is robotic manipulation of physical objects. Generally, to manipulate a physical object, a robotic control system determines the position and orientation of the robot relative to the position and orientation of the object, and then positions the robot so that the object can be grasped by a mechanical hand or gripper. Based on the characteristics of the object, grasping from a particular direction or on a particular portion of the object may lead to a more or less secure grip. Establishing a secure grip can be extremely difficult given the wide variety of objects and potential orientations. Therefore, improving robotic control systems to be able to perform grasping on a wide variety of objects is a key problem. [Brief explanation of the drawings]

[0004] [Figure 1] FIG. 10 illustrates a visualization of context variable key points for two-object inference and / or training logic, according to at least one embodiment. [Figure 2]FIG. 10 illustrates the effectiveness of the techniques described herein compared to other baselines for a rectangular parallelepiped object, according to at least one embodiment. [Figure 3] FIG. 10 illustrates success rates of different methods for non-cuboid shapes, according to at least one embodiment. [Figure 4] FIG. 10 illustrates the average reward achieved during training for different methods averaged over four initial seeds, according to at least one embodiment. [Figure 5] FIG. 10 illustrates a representative grasp generated by a policy trained on a cuboid object but tested on a rectangular object, according to at least one embodiment. [Figure 6] FIG. 10 illustrates a representative grasp generated by a policy trained on a cuboid object but tested on a cylindrical object, according to at least one embodiment. [Figure 7] FIG. 10 illustrates a representative grasp generated by a policy trained on a cuboid object but tested on an ellipsoid object, according to at least one embodiment. [Figure 8] FIG. 10 illustrates a representative grasp generated by a policy trained on a cuboid object but tested on a spherical object, according to at least one embodiment. [Figure 9] FIG. 10 illustrates the benefits of performing parameter adaptation on key points to improve policy performance, according to at least one embodiment. [Figure 10] FIG. 10 illustrates how a loss curve changes during an exemplary run of a CMA-ES optimization process covering after 13 iterations, according to at least one embodiment. [Figure 11] FIG. 10 illustrates a chart showing the grasp success rate for each of the different formats, according to at least one embodiment. [Figure 12] FIG. 10 illustrates training a policy for grasping using a grasp form illustrating a two-finger grasp, according to at least one embodiment. [Figure 13] FIG. 10 illustrates training a policy for grasping using a grasp form illustrating a two-finger grasp, according to at least one embodiment. [Figure 14] FIG. 10 illustrates training a policy for grasping using a grasp form illustrating a two-finger grasp, according to at least one embodiment. [Figure 15] FIG. 10 illustrates training a policy for grasping using a grasp form illustrating a three-finger grasp, according to at least one embodiment. [Figure 16] FIG. 10 illustrates training a policy for grasping using a grasp form illustrating a three-finger grasp, according to at least one embodiment. [Figure 17] FIG. 10 illustrates training a policy for grasping using a grasp form illustrating a four-finger grasp, according to at least one embodiment. [Figure 18] FIG. 1 illustrates a representative grasp of a soup can generated by a policy executed on a physical robot, according to at least one embodiment. [Figure 19] FIG. 1 illustrates a representative grasp of a soft bottle-can generated by a policy executed on a physical robot, according to at least one embodiment. [Figure 20] FIG. 1 illustrates an exemplary grasp of a rectangular box generated by a policy executed on a physical robot, according to at least one embodiment. [Figure 21] FIG. 1 illustrates a representative grasp of a rolled rectangular can generated by a policy executed on a physical robot, according to at least one embodiment. [Figure 22] FIG. 1 illustrates a representative grasp of a box generated by a policy executed on a physical robot, according to at least one embodiment. [Figure 23A] FIG. 1 illustrates inference and / or training logic, according to at least one embodiment. [Figure 23B] FIG. 1 illustrates inference and / or training logic, according to at least one embodiment. [Figure 24] 1 illustrates training and deployment of a neural network, according to at least one embodiment. [Figure 25]FIG. 1 illustrates an exemplary data center system, according to at least one embodiment. [Figure 26A] FIG. 1 illustrates an example of an autonomous vehicle, according to at least one embodiment. [Figure 26B] FIG. 26B illustrates example camera locations and fields of view for the autonomous vehicle of FIG. 26A, according to at least one embodiment. [Figure 26C] FIG. 26B is a block diagram illustrating an example system architecture of the autonomous vehicle of FIG. 26A, according to at least one embodiment. [Figure 26D] FIG. 26B illustrates a system for communicating between a cloud-based server and the autonomous vehicle of FIG. 26A, according to at least one embodiment. [Figure 27] FIG. 1 is a block diagram illustrating a computer system according to at least one embodiment. [Figure 28] FIG. 1 is a block diagram illustrating a computer system according to at least one embodiment. [Figure 29] FIG. 1 illustrates a computer system according to at least one embodiment. [Figure 30] FIG. 1 illustrates a computer system according to at least one embodiment. [Figure 31A] FIG. 1 illustrates a computer system according to at least one embodiment. [Figure 31B] FIG. 1 illustrates a computer system according to at least one embodiment. [Figure 31C] FIG. 1 illustrates a computer system according to at least one embodiment. [Figure 31D] FIG. 1 illustrates a computer system according to at least one embodiment. [Figure 31E] FIG. 1 illustrates a shared programming model, according to at least one embodiment. [Figure 31F] FIG. 1 illustrates a shared programming model, according to at least one embodiment. [Figure 32] FIG. 1 illustrates an exemplary integrated circuit and associated graphics processor, according to at least one embodiment. [Figure 33A] FIG. 1 illustrates an exemplary integrated circuit and associated graphics processor, according to at least one embodiment. [Figure 33B] FIG. 1 illustrates an exemplary integrated circuit and associated graphics processor, according to at least one embodiment. [Figure 34A] FIG. 10 illustrates additional exemplary graphics processor logic, according to at least one embodiment. [Figure 34B] FIG. 10 illustrates additional exemplary graphics processor logic, according to at least one embodiment. [Figure 35] FIG. 1 illustrates a computer system according to at least one embodiment. [Figure 36A] FIG. 1 illustrates a parallel processor, according to at least one embodiment. [Figure 36B] FIG. 1 illustrates a partition unit, according to at least one embodiment. [Figure 36C] FIG. 1 illustrates a processing cluster, according to at least one embodiment. [Figure 36D] FIG. 1 illustrates a graphics multiprocessor according to at least one embodiment. [Figure 37] FIG. 1 illustrates a multi-graphics processing unit (GPU) system, according to at least one embodiment. [Figure 38] FIG. 1 illustrates a graphics processor according to at least one embodiment. [Figure 39] FIG. 1 is a block diagram illustrating a micro-architecture for a processor, according to at least one embodiment. [Figure 40] FIG. 1 illustrates a deep learning application processor according to at least one embodiment. [Figure 41] FIG. 1 is a block diagram illustrating an exemplary neuromorphic processor, according to at least one embodiment. [Figure 42] FIG. 1 illustrates at least a portion of a graphics processor according to one or more embodiments. [Figure 43] FIG. 1 illustrates at least a portion of a graphics processor according to one or more embodiments. [Figure 44] FIG. 1 illustrates at least a portion of a graphics processor according to one or more embodiments. [Figure 45] FIG. 4 is a block diagram of a graphics processing engine 4510 of a graphics processor, according to at least one embodiment. [Figure 46] FIG. 1 is a block diagram of at least a portion of a graphics processor core, according to at least one embodiment. [Figure 47A] FIG. 47 illustrates thread execution logic 4700 including an array of processing elements of a graphics processor core, according to at least one embodiment. [Figure 47B] FIG. 47 illustrates thread execution logic 4700 including an array of processing elements of a graphics processor core, according to at least one embodiment. [Figure 48] FIG. 1 illustrates a parallel processing unit (“PPU”), according to at least one embodiment. [Figure 49] FIG. 1 illustrates a general purpose processing cluster (“GPC”), according to at least one embodiment. [Figure 50] FIG. 1 illustrates a memory partition unit of a parallel processing unit (“PPU”), according to at least one embodiment. [Figure 51] FIG. 1 illustrates a streaming multiprocessor, according to at least one embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0005] Guiding a robot to autonomously grasp objects of various shapes and sizes with a multi-fingered, articulated robotic hand is an important part of performing manipulation skills such as pick-and-place tasks, human handoffs, and dexterous tool use. In at least one embodiment, a solution to this problem takes a model-based planning and control approach. In at least one embodiment, a pipeline estimates the object pose given either a 3D point cloud or mesh of the object, then plans a set of contact locations and hand configurations to define the grasp, and finally generates a motion plan to reach and grasp the object. In at least one embodiment, such systems are sensitive to perception and calibration errors and often require significant computational time to plan and execute, which can cause such systems to misbehave and be unable to grasp the object.

[0006] In at least one embodiment, improved grasping is produced by using deep reinforcement learning (“RL”) to learn a policy for grasping objects of various geometries and scales with a multi-finger gripper. In at least one embodiment, fewer significant challenges arise in formulating the multi-finger grasping problem as an RL problem. In at least one embodiment, the system accommodates the relatively high dimensions of the configuration space of a multi-finger hand to effectively explore the space of possible grasping policies. In at least one embodiment, the system represents the object to be grasped in a way that is clear enough to train efficiently, yet generalizes effectively across objects of various shapes. In at least one embodiment, the system determines how the policy can be simply learned in a simulation without the need to fine-tune the policy for use in the physical world.

[0007] In at least one embodiment, recent developments in camera-based human hand pose estimation and imitation learning are applied to capture human grasp demonstrations from an RGB camera to efficiently explore a high-dimensional space of grasp policies. In at least one embodiment, the system uses the grasp demonstrations as a component in a reward function to provide the learner with a prior for preferred grasp trajectories during simulation.

[0008] In at least one embodiment, these key points are explicitly used as context variables and trained on a variable set of object shapes, allowing the policy to adapt to different block-shaped objects at deployment time without requiring further training.

[0009] However, in at least one embodiment, this does not allow the robot to robustly compensate for object geometries, such as cylinders or cones, that are not tightly captured by the bounding box. In at least one embodiment, tactile sensing is used to provide contact information as part of the robot's state. In at least one embodiment, this allows the policy to learn that making and maintaining contact is necessary for grasping. In at least one embodiment, this has the further advantage of helping to bridge the gap between simulation and reality, where tactile sensors on the physical robot compensate for object shape mismatches as well as localization and calibration from visual sensing. In at least one embodiment, the final learned policy is deployed on a real-world system, where visual input to the policy comes from an RGB pose estimator and contact information is retrieved from a BioTac tactile sensor.

[0010] In at least one embodiment, the system seeks to learn a separate grasping policy for each grasp type from a single human hand demonstration, without relying on any planning algorithm for grasp execution.

[0011] In at least one embodiment, grasping is a fundamental problem in robotics, and applying a method to learn grasping policies using physically based simulators and demonstrations opens up possibilities for learning more complex behaviors in the future.

[0012] In at least one embodiment, using simulation to learn robot manipulation policies provides a large amount of safe, securely generated training data. One challenge of using simulation is bridging the reality gap so that policies trained in the simulation can be deployed in real-world situations. In at least one embodiment, a reality gap learning context policy for multi-finger robot grasping is provided. In at least one embodiment, a learning object grasping approach ("GOAT") for tactile robotic hands is presented to overcome the reality gap problem. In at least one embodiment, the system uses motion demonstrations of human hands to initialize and reduce the search space for learning. In at least one embodiment, the policy comprises combining the cubic dimensions of the object of interest, allowing the policy to consider a more flexible representation than directly using images or point clouds. In at least one embodiment, leveraging fingertip contact sensors on the hand overcomes the reduction in geometric information guided by coarse bounding boxes and enables the policy to make inferences uncertainly. In at least one embodiment, the learned policy performs well on a real-world robot without fine-tuning, thus bridging the reality gap.

[0013] In at least one embodiment, the autonomous grasping of objects of various shapes and sizes by a robot with multi-fingered hands provides more general manipulation skills such as pick-and-place tasks, human handoffs, and dexterous tool use. In at least one embodiment, the techniques described herein overcome these limitations by using deep reinforcement learning (“RL”) to learn policies for grasping objects of various geometries and scales with a multi-fingered gripper. In at least one embodiment, challenges arise in formulating the multi-fingered grasping problem as an RL problem. In at least one embodiment, various advantages are provided, including the ability to address the relatively high dimensions of the multi-fingered hand configuration space to effectively explore the space of possible grasping policies; representations of objects that can be grasped in a way that generalizes effectively across objects of various shapes while still being concise enough to train efficiently; and the ability to simply learn the policy during simulation without having to fine-tune the policy for use in the physical world.

[0014] In at least one embodiment, to efficiently explore the high-dimensional space for grasping policies, the system provides human grasp demonstrations from an RGB camera. In at least one embodiment, these grasp demonstrations are used as components in a reward function to provide the learner with a prior for preferred grasp trajectories during simulation.

[0015] In at least one embodiment, the problem of object representation and simulation-to-real transfer is addressed by proposing a bounding box-based object representation. In at least one embodiment, the positions of the eight vertices of a cube enclosing the object are extracted to provide the object's pose, overall shape, and size as variable context for the policy.

[0016] In at least one embodiment, these key points are explicitly used as context variables and trained on a variable set of object shapes, allowing the policy to adapt to different block-shaped objects at deployment time without requiring further training.

[0017] In at least one embodiment, the system utilizes tactile sensing to provide contact information as part of the robot's state, allowing the robot to roughly compensate for object geometries, such as cylinders or cones, that are not tightly captured by a bounding box. In at least one embodiment, this allows the policy to learn that making and maintaining contact is necessary for grasping. In at least one embodiment, this has the further advantage of helping bridge the gap between simulation and reality, where tactile sensors on the physical robot compensate for object shape mismatches as well as localization and calibration from visual sensing. In at least one embodiment, the final learned policy is deployed on a real-world system, where visual input to the policy comes from an RGB pose estimator and contact information is retrieved from a BioTac tactile sensor.

[0018] In at least one embodiment, the system reduces uncertain object appearance and geometry to a concise set of geometric properties. In at least one embodiment, to construct a coarse approximation that these properties guide, the system utilizes tactile sensors in the robot's fingertips to explicitly observe contact as part of the state. In at least one embodiment, this also differs from standard approaches to grasping learning, in that richer visual properties are utilized to understand object geometry at a relatively high resolution, and these properties are learned or handcrafted.

[0019] In at least one example, the system utilizes human demonstrations of grasping, reinforcement learning, and sim-2-real to accomplish multi-finger grasping tasks on a real-world system. In at least one example, the system generalizes to shapes never seen in the real world without fine-tuning.

[0020] In at least one embodiment, the system fuses visual and tactile information in a learned grasping policy using 3D key points for context variables that encode object shape and binary contact signals within the object state. In at least one embodiment, the robotic manipulator is equipped with a force sensor that measures force information at the tip of the manipulator. In at least one embodiment, the force information may be digital, binary, or analog information. In at least one embodiment, this allows the policy to implicitly infer object dimensions and orientation, creating versatile policies that can be locally adapted by utilizing sensed contact information.

[0021] In at least one embodiment, empirical results demonstrating the benefits of various embodiments are provided herein. In at least one embodiment, key point representations coupled with haptic feedback can successfully grasp objects of various shapes not seen during training. In at least one embodiment, the benefits of using human hand grasp demonstration motions in learning a multi-finger grasp policy are quantified. In at least one embodiment, the learned policy achieves results comparable to hand-engineered policies on real-world physical robots without any fine-tuning. In at least one embodiment, the ability to grasp with various grasp styles is demonstrated by simply modifying the human demonstrations provided during training. In at least one embodiment, a dataset of captured human hand motions is provided that can be used to teach a robot to grasp with the published styles.

[0022] In at least one embodiment, robotic grasping is approached using either analytical model-based or data-driven methods, using either supervised or reinforcement learning. In at least one embodiment, analytical methods focus on constructing a grasp that satisfies specific criteria, such as gripper configuration, object contact points, force occlusion, and task completion. In at least one embodiment, learning-based methods learn from annotated datasets or from the robot interacting with its environment. In at least one embodiment, learned grasping behavior tends to generalize better to unseen objects and situations. In at least one embodiment, the techniques described herein utilize simulation to train policies that are deployed in the real world.

[0023] In at least one embodiment, the system learns grasping policies for different grasp types using reinforcement learning initialized by human demonstrations. In at least one embodiment, the grasp type is a function of surface mesh similarity to that seen during training, and therefore, it is not possible to reinforce specific types a priori. In at least one embodiment, the system seeks to learn a separate grasping policy for each grasp type from a single human hand demonstration, without relying on any planning algorithm for grasp execution.

[0024] In at least one embodiment, representations play an important role for learning in robotic manipulation. In at least one embodiment, selecting the correct representation enables the completion of learning downstream tasks. In at least one embodiment, the state representation also includes finger contact information to overcome shape and pose uncertainty. In at least one embodiment, the system explores using visual key points coupled with haptic feedback to learn grasping behaviors in RL.

[0025] In at least one embodiment, an approach is provided for learning a grasping policy for a multi-fingered hand. In at least one embodiment, a grasping problem is encoded into a context-policy exploration framework. In at least one embodiment, a policy is learned using RL, as reported by demonstration. In at least one embodiment, the policy is deployed on a physical robot.

[0026] In at least one embodiment, the task of multi-finger grasping is formulated as a context-policy exploration problem. In at least one embodiment, this means that the agent (robot) must determine the reward function

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[0027] In at least one embodiment, a context variable κ is defined for a multi-finger grasping problem as key points of a bounding box that encloses the object of interest in its pose at the beginning of the episode (see Figure 1). In at least one embodiment, this defines a low-dimensional feature representation for encoding object geometry. In at least one embodiment, there are several ways to infer these features at runtime, such as using a known object pose estimate. In at least one embodiment, providing this method of object pose at the beginning of a trial eliminates the need to explicitly track the object during execution. This is advantageous because, in at least one embodiment, stably tracking an object is a challenge, even when a known model exists, due to possible (partial) occlusion of the object caused by an interacting hand. In at least one embodiment, because initial estimates are inaccurate and objects are likely to move during execution, binary contact information for each robot fingertip is provided as part of the robot's state space.

[0028] FIG. 1 illustrates a visualization of context variable key points for two-object reasoning and / or training logic, according to at least one embodiment. In at least one embodiment, a robotic hand 102 is used to grasp one or more objects. In at least one embodiment, the robotic hand 102 is an articulated hand having multiple fingers. In at least one embodiment, the robotic hand 102 includes a first finger 104, a second finger 106, a third finger 108, and a fourth finger 110. In at least one embodiment, each finger includes a tactile sensor that indicates contact between the tip of the finger and the object. In at least one embodiment, each finger can be articulated under the control of electronic logic including a neural network.

[0029] In at least one embodiment, the robotic hand 102 is capable of grasping an object under the control of electronic control logic. In at least one embodiment, the electronic control logic comprises a processor and memory storing executable instructions that, when executed by the processor, cause the robotic hand to grasp an object. In at least one embodiment, the object is located using a cubic bounding box. In at least one embodiment, the cubic bounding box is established by estimating the 6D pose (orientation and position) of the object. In at least one embodiment, a first cubic bounding box 112 identifies the location of the box. In at least one embodiment, a second cubic bounding box 114 identifies the location of the cylinder.

[0030] In at least one embodiment, a neural network is trained to guide the robotic hand 102 to grasp an object by relying primarily on tactile information. In at least one embodiment, the approximate location and dimensions of the object are determined by a bounding box provided to an electronic control system. In at least one embodiment, the exact location and shape of the object is unknown, so the neural network learns to rely primarily on tactile feedback rather than the absolute positions of individual fingers.

[0031] In at least one embodiment, in simulation, contact can be observed directly using models of the robot and the object. In at least one embodiment, on the physical system, contact is estimated using pressure sensors from BioTac sensors embedded in each fingertip. In at least one embodiment, in addition to object localization, contact information provides extremely useful signals in learning a stable grasp that can generalize across different object geometries. In at least one embodiment, the state space is

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[0032] In at least one embodiment, the task of reaching and grasping a wide range of objects with a multi-fingered hand is non-trivial, and therefore reward terms are introduced to overcome several different challenges. In at least one embodiment, each reward term is then presented below. In at least one embodiment, the final reward is defined as the sum of these terms, with weights chosen so that each component has a relatively equal scale.

[0033] Hand position relative to object: In at least one embodiment, a first reward component encourages moving the palm close enough to the object to allow contact. In at least one embodiment, assuming a valid object pose estimate, keypoint locations for object k are calculated in the robot base frame. In at least one embodiment, the average of four keypoint locations on the top surface of the object is used to calculate the reward: κ offset is shown as: R pos =exp{-w1||P xyz -κ offset ||} (1)

[0034] Hand Motion: In at least one embodiment, the second reward component serves to focus the policy search on motions that are likely to work in order to overcome the relatively high-dimensional configuration space of a multi-fingered hand (16 DOF for the Allegro hand). To address this issue, in at least one embodiment, human demonstrations are used, captured from a hand pose estimator, as useful prior information for policy learning. In at least one embodiment, this introduces another problem, however, since the kinematic structure of a human hand is different from that of a robot. In at least one embodiment, to solve this problem, the robot's fingertip positions q e Human hand posture estimator

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[0035] Task success: In at least one embodiment, once the robot grasps the object, it returns the object to its starting position.

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[0036] Contact: In at least one embodiment, the reward function encourages the robot to make fingertip contact with the object. In at least one embodiment, the contact information improves the ability to learn a stable grasping policy across objects of various sizes and geometries. In at least one embodiment, when fingertip contact is present, the reward function i are defined to have the value 1, others 0.

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[0037] In at least one embodiment, a proximal policy optimization (PPO) algorithm is used to learn the policy. In at least one embodiment, the policy is depicted as a simple multilayer perceptron (MLP) with two hidden layers containing 128 neurons each. In at least one embodiment, during training, at the beginning of each rollout, a new cubic object is generated with dimensions uniformly sampled from a pre-specified range, the object's keypoints are estimated, noise is sampled, added to the keypoint locations to simulate sensor noise present in the physical system, and passed as context to the policy. In at least one embodiment, the keypoint values ​​then remain the same throughout the rollout. In at least one embodiment, to deploy the learned policy in simulation on a real robot, domain randomization is added to the object to account for differences between the simulator and the physical world. In at least one embodiment, in addition to the keypoint position noise, uniform noise is added to the object mass, the friction coefficient between the finger and object, the robot's PD gain, and the robot joint damping coefficients. In at least one embodiment, the range of uniform distribution is manually identified based on initial results on the robot.

[0038] In at least one embodiment, the goal is to learn a policy that generalizes to non-cubic shaped objects not seen during training. In at least one embodiment, new objects imply new contexts for the policy. In at least one embodiment, the bounding box of the new object can be used to extract key points that define the context variables, but this may not work for objects with shapes that differ significantly from the bounding box. In at least one embodiment, the techniques described herein optimize over the context variables to find values ​​that enable the pre-trained policy to succeed. In at least one embodiment, the constraint that the key points define a rectilinear box is removed, thereby allowing any point in 3D to be taken.

[0039] In at least one embodiment, given a policy trained in simulation on a uniform distribution of context, when presented with a new object, the policy network is fixed and explored on the context variables using CMA-ES. In at least one embodiment, key points are initialized using the object bounding box. In at least one embodiment, the objective function is evaluated by performing a rollout in simulation, providing the height reached by the object when lifted as a continuous reward for the planner to maximize.

[0040] In at least one embodiment, the techniques described herein are evaluated both in simulation and on a real robot. In at least one embodiment, the experience answers the following overarching questions: how important is hand demonstration data for learning an effective policy; how does including contact information change the effectiveness of the grasp; how sensitive is policy learning to object property representations; and can the policy be successfully transferred to a real robot without adaptation.

[0041] In at least one embodiment, parameterization studies on keypoint representations improve the performance of the learned policy. In at least one embodiment, experience shows that using the techniques described herein, objects can be grasped in six different formats and the effectiveness of different grasp formats can be evaluated.

[0042] In at least one embodiment, to fully evaluate the proposed method, three baselines are identified and compared against:

[0043] Baseline 1 In at least one embodiment, the baseline does not use contact information in the policy and settings of Equation 4 to 0; local contact information is important when conforming to non-cubic shapes and for identifying stable grasps once the robot's hand makes contact with an object.

[0044] Baseline 2: In at least one embodiment, contact information is included, but the policy does not reward human hand demonstration pairings, i.e., the weights are set to 0 in Equation 2. In at least one embodiment, the importance of demonstration data when learning in this high-dimensional action space is tested, which, combined with the coarse nature of the rewards, makes this a challenging reinforcement learning problem.

[0045] Baseline 3: In at least one embodiment, the context variable k is changed to a single 6-DoF pose vector of the object's center. In at least one embodiment, using keypoint information as a context variable provides a coarse representation of the object geometry that allows the policy to adapt to objects of various shapes.

[0046] In at least one embodiment, two different tests are conducted to compare the effectiveness of the method to that of a policy trained using a baseline method. In at least one embodiment, 100 random objects not seen by the policy during training are generated, and test grasps are made for each object from five random poses on a table. In at least one embodiment, the number of successful grasps out of these 500 resulting trials is measured.

[0047] In at least one embodiment, FIG. 2 shows the number of successful grasps achieved by each method. In at least one embodiment, the techniques described herein achieve an 88% grasp success rate, surpassing the three baseline approaches. In at least one embodiment, baseline 1204, which has no access to contact information, performs the worst. In at least one embodiment, baseline 2206, which does not have demonstration data but does include contact information, performs slightly better, indicating that contact information provides a stronger learning signal for this task than demonstration. In at least one embodiment, baseline 3208 performs the best.

[0048] 2 illustrates the effectiveness of GOAT 202 compared to other baselines for cuboid objects, according to at least one embodiment. In at least one embodiment, FIG. 2 illustrates the grasp success rate of a policy trained in a simulation. In at least one embodiment, FIG. 2 illustrates the effectiveness of GOAT compared to other baselines for cuboid objects.

[0049] 3 illustrates the success rates of different methods for non-cuboid shapes, according to at least one embodiment. In at least one embodiment, FIG. 3 illustrates the success rates of different methods for non-cuboid shapes, which are more challenging for the policy because these objects are not seen during training. In at least one embodiment, FIG. 3 illustrates that GOAT 302, which relies at least in part on tactile sensing, outperforms either baseline 1304, baseline 2306, or baseline 3308.

[0050] 4 is a diagram illustrating the average reward achieved during training for different methods averaged over four initial seeds, according to at least one embodiment. In at least one embodiment, FIG. 4 is a diagram illustrating the average reward achieved during training for different methods averaged over four initial seeds.

[0051] In at least one embodiment, Baseline 3 performs considerably better, achieving a 70% success rate. In at least one embodiment, this success is due to access to both contact information and hand demonstration data during training, but it lacks the same level of geometric information as the full approach, using only object pose as a context variable. However, in at least one embodiment, the shortcomings of this method are more pronounced when testing objects with non-cubic shapes, where geometry plays a more important role.

[0052] In at least one embodiment, the second test demonstrates the effectiveness of the policy for grasping previously unseen objects. In at least one embodiment, this experiment selects 20 objects with five different non-cubic shapes. In at least one embodiment, each of these objects is initialized with five random poses and subjected to similar grasping tests. Figure 3 shows the number of successful grasps achieved by each method, broken down by object type, such as cones, spheres, cylinders, and objects from the grasp database. In at least one embodiment, GOAT achieves the best performance, demonstrating robustness for grasping novel shapes. In at least one embodiment, representative grasps generated by the methods are shown in Figures 5 through 8.

[0053] 5 illustrates a representative grasp generated by a policy trained on a cuboid object but tested on a rectangular object, according to at least one embodiment. In at least one embodiment, a robotic hand 502 attempts to grasp a cuboid object 504.

[0054] 6 illustrates a representative grasp generated by a policy trained on a cuboid object but tested on a cylindrical object, according to at least one embodiment. In at least one embodiment, a robotic hand 602 attempts to grasp a cylindrical object 604.

[0055] 7 illustrates a representative grasp generated by a policy trained on a rectangular object but tested on an oval object, according to at least one embodiment. In at least one embodiment, a robotic hand 702 attempts to grasp an oval object 704.

[0056] 8 illustrates a representative grasp generated by a policy trained on a rectangular object but tested on a spherical object, according to at least one embodiment. In at least one embodiment, a robotic hand 802 attempts to grasp a cylindrical object 804.

[0057] In at least one embodiment, the learning curves for the average reward achieved by each method during training are shown in Figure 4. In at least one embodiment, the learning curves show the mean and variance over four different seeds.

[0058] In at least one embodiment, prior experience with unseen objects allows the trained policy to be tested with context parameters selected from object bounding boxes provided by the simulator, in order to investigate the effectiveness of keypoint matching approaches.

[0059] FIG. 9 illustrates the benefits of performing parameter adaptation on key points to improve policy performance, according to at least one embodiment. In at least one embodiment, FIG. 9 shows the improvement in grasp success rate after parameter adaptation for both rectangular and non-rectangular objects. In at least one embodiment, FIG. 10 illustrates how the optimization loss decreases during the parameter adaptation process. In at least one embodiment, it takes an average of approximately 10 iterations of CMA-ES to identify key point inputs that allow the policy to pick up novel objects. FIG. 10 illustrates how the loss curve changes during an exemplary run of the CMA-ES optimization process, covering 13 iterations, according to at least one embodiment.

[0060] In at least one embodiment, different grasp styles are learned to utilize the hand posture data made available by the hand posture estimator. In at least one embodiment, six different styles can be trained to grasp an object, as seen in Figures 12 through 17.

[0061] 11 illustrates the grasp success rate for each of the different styles, according to at least one embodiment. In at least one embodiment, two-finger grasps are not as successful as three- or four-finger grasps. In at least one embodiment, the objects used for this test are a mix of 50% cuboid and 50% non-cuboid shapes. In at least one embodiment, a policy is trained to grasp using grasp styles that represent different finger combinations.

[0062] 12 is a diagram illustrating training a policy for grasping using a grasp form illustrating a two-finger grasp, according to at least one embodiment. In at least one embodiment, a human hand 1202 provides a demonstrated grasp that is provided as an example of a reward function for a neural network training system. In at least one embodiment, a robotic hand 1204 mimics the demonstrated grasp 1202 under the control of the trained neural network.

[0063] 13 is a diagram illustrating training a policy for grasping using a grasp form illustrating a two-finger grasp, according to at least one embodiment. In at least one embodiment, a human hand 1302 provides a demonstrated grasp that is provided as an example of a reward function for a neural network training system. In at least one embodiment, a robotic hand 1304 mimics the demonstrated grasp 1302 under the control of the trained neural network.

[0064] 14 is a diagram illustrating training a policy for grasping using a grasp form illustrating a two-finger grasp, according to at least one embodiment. In at least one embodiment, a human hand 1402 provides a demonstrated grasp that is provided as an example of a reward function for a neural network training system. In at least one embodiment, a robotic hand 1404 mimics the demonstrated grasp 1402 under the control of the trained neural network.

[0065] 15 is a diagram illustrating training a policy for grasping using a grasp format illustrating a three-finger grasp, according to at least one embodiment. In at least one embodiment, a human hand 1502 provides the demonstrated grasp provided as an example of a reward function for a neural network training system. In at least one embodiment, a robotic hand 1504 mimics the demonstrated grasp 1502 under the control of the trained neural network.

[0066] 16 is a diagram illustrating training a policy for grasping using a grasp format illustrating a three-finger grasp, according to at least one embodiment. In at least one embodiment, a human hand 1602 provides the demonstrated grasp provided as an example of a reward function for a neural network training system. In at least one embodiment, a robotic hand 1604 mimics the demonstrated grasp 1602 under the control of the trained neural network.

[0067] 17 is a diagram illustrating training a policy for grasping using a grasp format illustrating a four-finger grasp, according to at least one embodiment. In at least one embodiment, a human hand 1702 provides the demonstrated grasp provided as an example of a reward function for a neural network training system. In at least one embodiment, a robotic hand 1704 mimics the demonstrated grasp 1702 under the control of the trained neural network.

[0068] In at least one embodiment, one test for GOAT is whether the learned policy can be deployed on a real-world robot. In at least one embodiment, an Allegro robot hand equipped with four BioTac sensors mounted on a 7DOF LBR iiwa Kuka arm is used. In at least one embodiment, DOPE is used to localize objects and generate their bounding box keypoint locations. In at least one embodiment, five objects DOPE can detect from the YCB dataset: cracker box, meat, mustard, soup, and sugar box. In at least one embodiment, three different noise levels are modeled: no noise, 1 mm, and 10 mm. No noise refers to the natural noise introduced by DOPE, and the latter two refer to the variance used when adding noise to the transformation values. In at least one embodiment, for each noise value and object, the object is randomly placed within the robot's workspace five times at a planar orientation between -30° and 30°, with 0° meaning the object's axes are aligned with the robot base.

[0069] In at least one embodiment, the method compares against a handwritten grasp policy that depicts a baseline. In at least one embodiment, the baseline is simply moved to a position 6 cm above the estimated center of the object. In at least one embodiment, once this position is reached, the hand begins to close its fingers toward the object. In at least one embodiment, each finger stops moving when it detects contact with the object. In at least one embodiment, when all fingers have contacted the object, the hand applies more force to the object before lifting it 7 cm up.

[0070] Table 1: Experiments showing real-world GOAT performance against hand-tuned baselines. [Table 1]

[0071] In at least one embodiment, Figure 1 shows results indicating that GOAT performs similarly to the baseline at different noise levels. In at least one embodiment, soup is a challenging object to grasp, but GOAT, while not trained on such a physical object, explores the object and moves its fingers to achieve a stable grasp on the cylinder. In at least one embodiment, representative grasps generated by the policy are shown for each object in Figures 18 through 22.

[0072] 18 illustrates an exemplary grasp of a soup can generated by a policy executed on a physical robot, according to at least one embodiment. In at least one embodiment, a robotic hand 1802 grasps a can 1804. In at least one embodiment, the can 1804 is positioned by providing a control system with a bounding box (or cuboid) that approximately covers the object. In at least one embodiment, the robotic hand 1802 grasps the can 1804 under the control of a neural network, which comprises a cuboid that approximately covers the can 1804. In at least one embodiment, the neural network is not explicitly trained using an object shaped like the can 1804.

[0073] FIG. 19 illustrates an exemplary grasp of a soft bottle-can generated by a policy executed on a physical robot, according to at least one embodiment. In at least one embodiment, a robotic hand 1902 grasps a plastic bottle 1904. In at least one embodiment, the plastic bottle 1904 is positioned by providing a control system with a bounding box (or cuboid) that approximately covers the object. In at least one embodiment, the robotic hand 1902 grasps the plastic bottle 1904 under the control of a neural network, which comprises a cuboid that approximately covers the plastic bottle 1904. In at least one embodiment, the neural network is not explicitly trained using objects shaped like the plastic bottle 1904.

[0074] 20 illustrates an exemplary grasp of a rectangular box generated by a policy executed on a physical robot, according to at least one embodiment. In at least one embodiment, a robotic hand 2002 grasps a box 2004. In at least one embodiment, the box 2004 is positioned by providing a control system with a bounding box (or cuboid) that approximately covers the object. In at least one embodiment, the robotic hand 2002 grasps the box 2004 under the control of a neural network, which comprises a cuboid that approximately covers the box 2004. In at least one embodiment, the neural network is not explicitly trained using an object shaped like the box 2004.

[0075] 21 illustrates an exemplary grasp of a rounded rectangular can generated by a policy executed on a physical robot, according to at least one embodiment. In at least one embodiment, a robotic hand 2102 grasps a square can 2104. In at least one embodiment, the square can 2104 is positioned by providing a control system with a bounding box (or cuboid) that approximately covers the object. In at least one embodiment, the robotic hand 2102 grasps the square can 2104 under the control of a neural network, and the neural network comprises a cuboid that approximately covers the square can 2104. In at least one embodiment, the neural network is not explicitly trained using objects shaped like the square can 2104.

[0076] 22 illustrates an exemplary grasp of a box generated by a policy executed on a physical robot, according to at least one embodiment. In at least one embodiment, a robotic hand 2202 grasps a tall box 2204. In at least one embodiment, the tall box 2204 is positioned by providing a control system with a bounding box (or cuboid) that approximately covers the object. In at least one embodiment, the robotic hand 2202 grasps the tall box 2204 under the control of a neural network, which comprises a cuboid that approximately covers the tall box 2204. In at least one embodiment, the neural network is not explicitly trained using an object shaped like the tall box 2204.

[0077] In at least one embodiment, a context-policy exploration approach to learning policies for grasping unknown objects with a multi-fingered hand is provided. In at least one embodiment, the approach is shown to be capable of being trained solely in simulation and successfully deployed in the real world on a physical robot. In at least one embodiment, the use of bounding box keypoints is introduced as a context representation for the reward and subsequently the policy. In at least one embodiment, coupling this keypoint representation with contact sensing in the policy allows the robot to adapt to previously unseen shapes and overcome uncertainty in object pose estimation that arises from noisy visual sensing. In at least one embodiment, for objects with shapes that deviate significantly from the shape of the bounding box (e.g., a cone), the techniques described herein optimize over context variables to enable greater grasping performance without the need to maintain the learned policy.

[0078] In at least one embodiment, a system includes: a processor having one or more processing circuits for performing a grasp of an object using a robotic gripper having one or more tactile sensors using a neural network, the neural network being trained at least in part by performing multiple simulated grasps on objects having different shapes; one or more processors for guiding a robotic hand having one or more tactile sensors to grasp a first object using one or more neural networks that have been trained at least in part by simulating grasps of a second object having a different shape than the first object; and one or more memories for storing the one or more neural networks.

[0079] In at least one embodiment, a method for grasping an object includes using a neural network that is trained at least in part by simulating a robotic hand with one or more tactile sensors using the neural network, wherein the neural network is trained at least in part by evaluating in the simulation a plurality of grasps on objects having different shapes.

[0080] In at least one embodiment, the techniques described herein are used to implement a robotic pick and / or place system. In at least one embodiment, a robotic hand is guided to grasp an object from a bin or container containing objects of various shapes and sizes. In at least one embodiment, the robotic hand places the picked object in a box or container. In at least one embodiment, a warehouse automation system utilizes the above-described pick and place system for automated inventory management.

[0081] Logic of inference and training Figure 23A illustrates inference and / or training logic 2315 used to perform inference and / or training operations for one or more embodiments. More details regarding inference and / or training logic 2315 are provided below in conjunction with Figures 23A and / or 23B.

[0082] In at least one embodiment, the inference and / or training logic 2315 may include, without limitation, code and / or data storage 2301 for storing forward and / or output weights, and / or input / output data, and / or other parameters for configuring neurons or layers of a neural network that is trained and / or used to infer in one or more embodiments. In at least one embodiment, the training logic 2315 may include or be coupled to code and / or data storage 2301 for storing graph code or other software for controlling the timing and / or sequence of logic loaded with weights and / or other parameter information, including integer and / or floating-point units (collectively, arithmetic logic units (ALUs)). In at least one embodiment, code, such as graph code, loads weights or other parameter information into a processor ALU based on the architecture of the neural network to which the code corresponds. In at least one embodiment, code and / or data storage 2301 stores weight parameters and / or input / output data for each layer of a neural network trained or used in conjunction with one or more embodiments during forward propagation of the input / output data and / or weight parameters during training and / or inference using aspects of one or more embodiments. In at least one embodiment, any portion of code and / or data storage 2301 may be included with other on-chip or off-chip data storage, including a processor's L1, L2, or L3 cache, or system memory.

[0083] In at least one embodiment, any portion of code and / or data storage 2301 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, code and / or data storage 2301 may be cache memory, dynamic randomly addressable memory (“DRAM”), static randomly addressable memory (“SRAM”), non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, the choice of whether code and / or data storage 2301 is internal or external to a processor, or comprised of DRAM, SRAM, flash, or some other storage type, may depend on the available storage on-chip versus off-chip, the latency requirements of the training and / or inference functions being performed, the batch size of data used in neural network inference and / or training, or some combination of these factors.

[0084] In at least one embodiment, the inference and / or training logic 2315 may include, without limitation, code and / or data storage 2305 for storing back and / or output weights and / or input / output data corresponding to neurons or layers of a neural network trained and / or used to infer in accordance with one or more aspects of the embodiment. In at least one embodiment, the code and / or data storage 2305 stores weight parameters and / or input / output data for each layer of a neural network trained or used in conjunction with one or more embodiments while backpropagating input / output data and / or weight parameters during training and / or inference using one or more aspects of the embodiment. In at least one embodiment, training logic 2315 may include or be coupled to code and / or data storage 2305 for storing graph code or other software for timing and / or sequencing control, and code and / or data storage 2305 may be loaded with weights and / or other parameter information to configure logic including integer and / or floating-point units (collectively, arithmetic logic units (ALUs)). In at least one embodiment, code, such as graph code, loads weights or other parameter information into processor ALUs based on the architecture of the neural network to which the code corresponds. In at least one embodiment, any portion of code and / or data storage 2305 may be included with other on-chip or off-chip data storage, including processor L1, L2, or L3 cache, or system memory. In at least one embodiment, any portion of code and / or data storage 2305 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, code and / or data storage 2305 may be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage.In at least one embodiment, the choice of whether code and / or data storage 2305 is internal or external to the processor, for example, or whether it is comprised of DRAM, SRAM, flash, or some other storage type, may depend on the storage available on-chip versus off-chip, the latency requirements of the training and / or inference functions being performed, the batch size of data used in neural network inference and / or training, or some combination of these factors.

[0085] In at least one embodiment, code and / or data storage 2301 and code and / or data storage 2305 may be separate storage structures. In at least one embodiment, code and / or data storage 2301 and code and / or data storage 2305 may be the same storage structure. In at least one embodiment, code and / or data storage 2301 and code and / or data storage 2305 may be partially the same storage structure and partially separate storage structures. In at least one embodiment, any portion of code and / or data storage 2301 and code and / or data storage 2305 may be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory.

[0086] In at least one embodiment, inference and / or training logic 2315 may include one or more arithmetic logic units (“ALUs”) 2310, including, without limitation, integer and / or floating point units, for performing logical and / or arithmetic operations based at least in part on or indicated by training and / or inference code (e.g., graph code), the results of which may generate activations (e.g., output values ​​from layers or neurons in a neural network) stored in activation storage 2320, which are functions of input / output and / or weight parameter data stored in code and / or data storage 2301 and / or code and / or data storage 2305. In at least one embodiment, the activations stored in activation storage 1320 are generated according to linear algebra and / or matrix-based calculations performed by ALU 2310 in response to executing instructions or other code, where weight values ​​stored in code and / or data storage 2305 and / or data 2301 are used as operands along with other values ​​such as bias values, gradient information, momentum values, or other parameters or hyperparameters, any or all of which may be stored in code and / or data storage 2305, or code and / or data storage 2301, or in separate storage on-chip or off-chip.

[0087] In at least one embodiment, ALU 2310 is included within one or more processors or other hardware logic devices or circuits, while in other embodiments, ALU 2310 may be external to the processors or other hardware logic devices or circuits that use them (e.g., a coprocessor). In at least one embodiment, ALU 2310 may be included within an execution unit of a processor or may otherwise be included within an ALU bank accessible by execution units of a processor, either within the same processor or distributed among different processors of different types (e.g., central processing unit, graphics processing unit, fixed function unit, etc.). In at least one embodiment, data storage 2301, code and / or data storage 2305, and activation storage 2320 may be in the same processor or other hardware logic devices or circuits, while in other embodiments, they may be in different processors or other hardware logic devices or circuits, or some combination of the same processor or other hardware logic devices or circuits and different processors or other hardware logic devices or circuits. In at least one embodiment, any portion of activation storage 2320 may be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory. Additionally, inference and / or training code may be stored with other code accessible to the processor or other hardware logic or circuitry, and may be fetched and / or processed using the processor's fetch, decode, schedule, execute, retire, and / or other logic.

[0088] In at least one embodiment, active storage 2320 may be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, active storage 2320 may be completely or partially internal to or external to one or more processors or other logic circuits. In at least one embodiment, the choice of whether active storage 2320 is internal or external to a processor, or whether it is comprised of DRAM, SRAM, flash, or some other storage type, for example, may depend on available on-chip versus off-chip storage, latency requirements of the training and / or inference functions being performed, batch sizes of data used in inference and / or training of a neural network, or some combination of these factors. In at least one embodiment, the inference and / or training logic 2315 shown in Figure 23A may be used in conjunction with an application-specific integrated circuit ("ASIC"), such as a Tensorflow® processing unit from Google, an inference processing unit (IPU) from Graphcore™, or a Nervana® (e.g., "Lake Crest") processor from Intel Corporation. In at least one embodiment, the inference and / or training logic 2315 shown in Figure 23A may be used in conjunction with other hardware, such as central processing unit ("CPU") hardware, graphics processing unit ("GPU") hardware, or a field programmable gate array ("FPGA").

[0089] FIG. 23B illustrates inference and / or training logic 2315 according to at least one various embodiment. In at least one embodiment, the inference and / or training logic 2315 may include, without limitation, hardware logic in which computational resources are dedicated to, or otherwise used only in conjunction with, weight values ​​or other information corresponding to one or more layers of neurons in a neural network. In at least one embodiment, the inference and / or training logic 2315 illustrated in FIG. 23B may be used in conjunction with an application-specific integrated circuit (ASIC), such as a Tensorflow® processing unit from Google, an inference processing unit (IPU) from Graphcore™, or a Nervana® (e.g., “Lake Crest”) processor from Intel Corporation. In at least one embodiment, inference and / or training logic 2315 shown in FIG. 23B may be used in conjunction with other hardware, such as central processing unit ("CPU") hardware, graphics processing unit ("GPU") hardware, or field programmable gate array ("FPGA"). In at least one embodiment, inference and / or training logic 2315 includes, without limitation, code and / or data storage 2301 and code and / or data storage 2305, which may be used to store code (e.g., graph code), weight and / or bias values, gradient information, momentum values, and / or other parameter or hyperparameter information. In at least one embodiment shown in FIG. 23B, each of code and / or data storage 2301 and code and / or data storage 2305 is associated with dedicated computational resources, such as compute hardware 2302 and compute hardware 2306, respectively.In at least one embodiment, computation hardware 2302 and computation hardware 2306 each include one or more ALUs that perform mathematical functions, such as linear algebraic functions, only on information stored in code and / or data storage 2301 and code and / or data storage 2305, respectively, with the results stored in activation storage 2320.

[0090] In at least one embodiment, each of code and / or data storage 2301 and 2305 and corresponding computational hardware 2302 and 2306 corresponds to a different layer of a neural network, whereby activations resulting from one "storage / computation pair 2301 / 2302" of code and / or data storage 2301 and computational hardware 2302 are provided as input to a "storage / computation pair 2305 / 2306" of the next code and / or data storage 2305 and computational hardware 2306 to reflect the conceptual organization of the neural network. In at least one embodiment, storage / computation pairs 2301 / 2302 and 2305 / 2306 may correspond to two or more layers of the neural network. In at least one embodiment, additional storage / computation pairs (not shown) may be included in inference and / or training logic 2315 after or in parallel with storage / computation pairs 2301 / 2302 and 2305 / 2306.

[0091] Neural network training and deployment FIG. 24 illustrates training and deployment of a deep neural network, according to at least one embodiment. In at least one embodiment, an untrained neural network 92406 is trained using a training dataset 2402. In at least one embodiment, the training framework 2404 is the PyTorch framework, while in other embodiments, the training framework 2404 is Tensorflow, Boost, Caffe, Microsoft Cognitive Toolkit / CNTK, MXNet, Chainer, Keras, Deeplearning4j, or other training framework. In at least one embodiment, the training framework 2404 trains the untrained neural network 2406 and enables it to be trained using processing resources described herein to generate a trained neural network 2408. In at least one embodiment, the weights may be selected randomly or by pre-training using a deep belief network. In at least one embodiment, the training may be performed in a supervised, semi-supervised, or unsupervised manner.

[0092] In at least one embodiment, the untrained neural network 2406 is trained using supervised learning, where the training data set 2402 includes inputs paired with desired outputs for the inputs, or the training data set 2402 includes inputs with known outputs, and the outputs of the neural network 2406 are manually scored. In at least one embodiment, the untrained neural network 2406 is trained in a supervised manner, processing inputs from the training data set 2402 and comparing the resulting outputs to a set of expected or desired outputs. In at least one embodiment, errors are then back-propagated through the untrained neural network 2406. In at least one embodiment, the training framework 2404 adjusts the weights that control the untrained neural network 2406. In at least one embodiment, the training framework 2404 includes tools to monitor how well the untrained neural network 2406 is converging toward a model, such as the trained neural network 2408, that is suitable for generating correct answers, such as in the results 2414, based on known input data, such as new data 2412. In at least one embodiment, the training framework 2404 iteratively trains the untrained neural network 2406 while adjusting weights to refine the output of the untrained neural network 2406 using a loss function and a tuning algorithm, such as stochastic gradient descent. In at least one embodiment, the training framework 2404 trains the untrained neural network 2406 until the untrained neural network 2406 reaches a desired accuracy. In at least one embodiment, the trained neural network 2408 can then be deployed to implement any number of machine learning operations.

[0093] In at least one embodiment, the untrained neural network 2406 is trained using unsupervised learning, where the untrained neural network 2406 attempts to train itself using unlabeled data. In at least one embodiment, the training dataset 2402 for unsupervised learning includes input data without any associated output data or “ground truth” data. In at least one embodiment, the untrained neural network 2406 can learn groupings within the training dataset 2402 and determine how individual inputs relate to the untrained dataset 2402. In at least one embodiment, unsupervised training can be used to generate self-organizing maps, which are a type of trained neural network 2408 that can perform operations useful for reducing the dimensionality of the new dataset 2412. In at least one embodiment, unsupervised training can also be used to perform anomaly detection, which allows for the identification of data points in the new dataset 2412 that deviate from the normal patterns of the new dataset 2412.

[0094] In at least one embodiment, semi-supervised learning may be used, which is a technique in which labeled and unlabeled data are mixed in the training data set 2402. In at least one embodiment, the training framework 2404 may be used to perform incremental learning, such as by transfer learning techniques. In at least one embodiment, incremental learning allows the trained neural network 2408 to adapt to a new data set 2412 without forgetting the knowledge instilled in the network during initial training.

[0095] Data Center 25 illustrates an exemplary data center 2500 in which at least one embodiment may be used. In at least one embodiment, the data center 2500 includes a data center infrastructure layer 2510, a framework layer 2520, a software layer 2530, and an application layer 2540.

[0096] 25, data center infrastructure layer 2510 may include a resource orchestrator 2512, grouped computing resources 2514, and node computing resources (“node CRs”) 2516(1) through 2516(N), where “N” represents any positive integer. In at least one embodiment, node CRs 2516(1) through 2516(N) may include, but are not limited to, any number of central processing units (“CPUs”) or other processors (including accelerators, field programmable gate arrays (FPGAs), graphics processors, etc.), memory devices (e.g., dynamic read-only memory), storage devices (e.g., solid-state drives or disk drives), network input / output (“NW I / O”) devices, network switches, virtual machines (“VMs”), power supply modules, and cooling modules. In at least one embodiment, one or more of the nodes CR 2516(1)-2516(N) may be a server having one or more of the computing resources described above.

[0097] In at least one embodiment, grouped computing resources 2514 may include separate groups of node CRs housed within one or more racks (not shown), or multiple racks housed in a data center at various graphical locations (also not shown). Separate groups of node CRs within grouped computing resources 2514 may include grouped compute resources, network resources, memory resources, or storage resources that may be configured or allocated to support one or more workloads. In at least one embodiment, several node CRs, including CPUs or processors, may be grouped within one or more racks to provide compute resources to support one or more workloads. In at least one embodiment, one or more racks may also include any number of power supply modules, cooling modules, and network switches in any combination.

[0098] In at least one embodiment, resource orchestrator 2512 may configure or otherwise control one or more nodes CR 2516(1)-2516(N) and / or grouped computing resources 2514. In at least one embodiment, resource orchestrator 2512 may include a software design infrastructure (“SDI”) management entity for data center 2500. In at least one embodiment, resource orchestrator may include hardware, software, or some combination thereof.

[0099] In at least one embodiment shown in FIG. 25 , framework layer 2520 includes job scheduler 2532, configuration manager 2534, resource manager 2536, and distributed file system 2538. In at least one embodiment, framework layer 2520 may include frameworks to support software 2531 in software layer 2530 and / or one or more applications 2542 in application layer 2540. In at least one embodiment, software 2532 or applications 2542 may each include web-based service software or applications, such as those offered by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, framework layer 2520 may be a type of free and open-source software web application framework, such as, but not limited to, Apache Spark™ (hereinafter “Spark”), which can use distributed file system 2538 for large-scale data processing (e.g., “big data”). In at least one embodiment, job scheduler 2532 may include a Spark driver to facilitate scheduling of workloads supported by various tiers of data center 2500. In at least one embodiment, configuration manager 2534 may be capable of configuring different tiers, such as software tier 2530 and framework tier 2520, which includes Spark and distributed file system 2538 to support large-scale data processing. In at least one embodiment, resource manager 2536 may be capable of managing clustered or grouped computing resources that are mapped or allocated to support distributed file system 2538 and job scheduler 2532. In at least one embodiment, the clustered or grouped computing resources may include grouped computing resources 2514 in data center infrastructure tier 2510.In at least one embodiment, resource manager 2536 may manage these mappings or allocated computing resources in conjunction with resource orchestrator 2512.

[0100] In at least one embodiment, software 2532 included in software layer 2530 may include software used by nodes CR 2516(1)-2516(N), grouped computing resources 2514, and / or at least a portion of distributed file system 2538 of framework layer 2520. The one or more types of software may include, but are not limited to, internet web page searching software, email virus scanning software, database software, and streaming video content software.

[0101] In at least one embodiment, applications 2542 included in application layer 2540 may include one or more types of applications used by at least a portion of nodes CR 2516(1)-2516(N), grouped computing resources 2514, and / or distributed file system 2538 of framework layer 2520. The one or more types of applications may include, but are not limited to, any number of genomics applications, cognitive compute, and machine learning applications including training or inference software, machine learning framework software (e.g., PyTorch, Tensorflow, Caffe, etc.), or other machine learning applications used in conjunction with one or more embodiments.

[0102] In at least one embodiment, any of configuration manager 2534, resource manager 2536, and resource orchestrator 2512 may implement any number and types of self-correcting actions based on any amount and type of data obtained in any technically feasible manner. In at least one embodiment, the self-correcting actions may enable data center operators of data center 2500 to avoid determining potentially faulty configurations and eliminate underutilized and / or underperforming portions of the data center.

[0103] In at least one embodiment, data center 2500 may include tools, services, software, or other resources for training one or more machine learning models or for predicting or inferring information using one or more machine learning models according to one or more embodiments described herein. For example, in at least one embodiment, machine learning models may be trained by calculating weight parameters according to a neural network architecture using the software and computing resources described above with respect to data center 2500. In at least one embodiment, trained machine learning models corresponding to one or more neural networks may be used to infer or predict information using the resources described above with respect to data center 2500 by using weight parameters calculated by one or more training techniques described herein.

[0104] In at least one embodiment, the data center may use a CPU, application specific integrated circuit (ASIC), GPU, FPGA, or other hardware to perform training and / or inference using the resources described above. Additionally, one or more of the software and / or hardware resources described above may be configured as a service to enable a user to train or perform inference on information, such as image recognition, speech recognition, or other artificial intelligence services.

[0105] Inference and / or training logic 2315 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 2315 are provided herein in conjunction with FIG. 23A and / or FIG. 23B . In at least one embodiment, inference and / or training logic 2315 may be used in the system of FIG. 25 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein. In at least one embodiment, a robotic grasping system may use the training and inference hardware described above to control a haptic hand.

[0106] Autonomous Vehicles 26A illustrates an example of an autonomous vehicle 2600 according to at least one embodiment. In at least one embodiment, the autonomous vehicle 2600 (alternatively referred to herein as "vehicle 2600") may be a passenger vehicle, such as, without limitation, a car, truck, bus, and / or another type of vehicle that accommodates one or more occupants. In at least one embodiment, the vehicle 2600 may be a semi-tractor trailer truck for hauling cargo. In at least one embodiment, the vehicle 2600 may be an aircraft, a robotic vehicle, or other type of vehicle.

[0107] Autonomous vehicles may be described in terms of levels of automation as defined by the National Highway Traffic Safety Administration (“NHTSA”), a division of the U.S. Department of Transportation, and the Society of Automotive Engineers (“SAE”) “Taxonomy and Definitions for Terms Related to Driving Automation Systems for On-Road Motor Vehicles” (e.g., Standard No. J3016-201806, issued June 15, 2018, Standard No. J3016-201609, issued September 30, 2016, and previous and new versions of this standard). In one or more embodiments, vehicle 2600 may be capable of functionality according to one or more of Levels 1 through 5 of autonomous driving. For example, in at least one embodiment, vehicle 2600 may be capable of conditional automation (Level 3), high automation (Level 4), and / or full automation (Level 5), depending on the embodiment.

[0108] In at least one embodiment, vehicle 2600 may include components such as, without limitation, a chassis, a vehicle body, wheels (e.g., 2, 4, 6, 8, 18, etc.), tires, axles, and other vehicle components. In at least one embodiment, vehicle 2600 may include a propulsion system 2650 such as, without limitation, an internal combustion engine, a hybrid power plant, a fully electric engine, and / or another propulsion system type. In at least one embodiment, propulsion system 2650 may be coupled to a drive train of vehicle 2600, which may include, without limitation, a transmission to enable propulsion of vehicle 2600. In at least one embodiment, propulsion system 2650 may be controlled in response to receiving a signal from throttle / accelerator 2652.

[0109] In at least one embodiment, a steering system 2654, which may include without limitation a steering wheel, is used to steer the vehicle 2600 (e.g., along a desired path or route) when the propulsion system 2650 is operating (e.g., when the vehicle is moving). In at least one embodiment, the steering system 2654 may receive signals from a steering actuator 2656. The steering wheel may be optional for fully automated (Level 5) functionality. In at least one embodiment, a brake sensor system 2646 may be used to operate the vehicle brakes in response to receiving signals from a brake actuator 2648 and / or brake sensor.

[0110] In at least one embodiment, controller 2636, which may include, without limitation, one or more systems on a chip (“SoC”) (not shown in FIG. 26A ) and / or graphics processing units (“GPUs”), provides signals (e.g., representing commands) to one or more components and / or systems of vehicle 2600. For example, in at least one embodiment, controller 2636 may send signals to operate vehicle brakes via brake actuator 2648, steering system 2654 via steering actuator 2656, and propulsion system 2650 via throttle / accelerator 2652. Controller 2636 may include one or more on-board (e.g., integrated) computing devices (e.g., supercomputers) that process sensor signals and output operational commands (e.g., signals representing commands) to enable autonomous driving and / or assist a human driver in driving vehicle 2600. In at least one embodiment, the controllers 2636 may include a first controller 2636 for autonomous driving functions, a second controller 2636 for functional safety functions, a third controller 2636 for artificial intelligence functions (e.g., computer vision), a fourth controller 2636 for infotainment functions, a fifth controller 2636 for redundancy in emergency situations, and / or other controllers. In at least one embodiment, a single controller 2636 may handle two or more of the above functionalities, two or more controllers 2636 may handle a single functionality, and / or some combination thereof.

[0111] In at least one embodiment, controller 2636 provides signals to control one or more components and / or systems of vehicle 2600 in response to sensor data (e.g., sensor inputs) received from one or more sensors. In at least one embodiment, sensor data may be received from, for example, without limitation, global navigation satellite system ("GNSS") sensors 2658 (e.g., global positioning system sensors), RADAR sensors 2660, ultrasonic sensors 2662, LIDAR sensors 2664, inertial measurement units ("IMUs"). 26A ), a long-range camera (not shown in FIG. 26A ), a mid-range camera (not shown in FIG. 26A ), a speed sensor 2644 (e.g., for measuring the speed of the vehicle 2600), a vibration sensor 2642, a steering sensor 2640, a brake sensor (e.g., as part of a brake sensor system 2646), and / or other sensor types.

[0112] In at least one embodiment, one or more of the controllers 2636 may receive input (e.g., represented by input data) from the instrument cluster 2632 of the vehicle 2600 and provide output (e.g., represented by output data, display data, etc.) via a human-machine interface (“HMI”) display 2634, an audible annunciator, a loudspeaker, and / or via other components of the vehicle 2600. In at least one embodiment, the output may include information such as vehicle speed, speeding, time, map data (e.g., a high definition map (not shown in FIG. 26A )), location data (e.g., the location of the vehicle 2600 on a map, etc.), direction, the location of other vehicles (e.g., an occupancy grid), information about objects and object conditions sensed by the controller 2636, etc. For example, in at least one embodiment, the HMI display 2634 may display information about the presence of one or more objects (e.g., road signs, warning signs, traffic light changes, etc.) and / or information about a driving maneuver that the vehicle has made, is making, or will make (e.g., currently changing lanes, taking exit 34B in 2 miles, etc.).

[0113] In at least one embodiment, vehicle 2600 further includes network interface 2624, which may use a wireless antenna 2626 and / or a modem for communicating over one or more networks. For example, in at least one embodiment, network interface 2624 may be capable of communicating over Long-Term Evolution ("LTE"), Wideband Code Division Multiple Access ("WCDMA"), Universal Mobile Telecommunications System ("UMTS"), Global System for Mobile communications ("GSM"), IMT-CDMA Multi-Carrier ("CDMA2000"), etc. Additionally, in at least one embodiment, wireless antenna 2626 may enable communication between objects in the environment (e.g., vehicles, mobile devices, etc.) using local area networks such as Bluetooth, Bluetooth Low Energy ("LE"), Z-Wave, ZigBee, etc., and / or low power wide-area networks ("LPWAN") such as LoRaWAN, SigFox, etc.

[0114] Inference and / or training logic 2315 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 2315 are provided herein in conjunction with FIG. 23A and / or FIG. 23B . In at least one embodiment, inference and / or training logic 2315 may be used in the system of FIG. 26A for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein. In at least one embodiment, the robotic grasping system described above may be used to assemble an autonomous vehicle.

[0115] 26B is a diagram illustrating example camera locations and fields of view for autonomous vehicle 2600 of FIG. 26A, according to at least one embodiment. In at least one embodiment, the cameras and their respective fields of view are an example example and are not limiting. For example, in at least one embodiment, additional and / or alternative cameras may be included and / or cameras may be positioned at different locations on vehicle 2600.

[0116] In at least one embodiment, the camera type may include, but is not limited to, a digital camera that may be adapted for use with components and / or systems of vehicle 2600. The camera may operate at Automotive Safety Integrity Level ("ASIL") B and / or another ASIL. In at least one embodiment, the camera type may be capable of any image capture rate, such as 60 frames per second (fps), 1220 fps, 240 fps, etc., depending on the embodiment. In at least one embodiment, the camera may be capable of using a rolling shutter, a global shutter, another type of shutter, or a combination thereof. In at least one embodiment, the color filter array may include a red, clear, clear, clear ("RCCC") color filter array, a red, clear, clear, blue ("RCCB") color filter array, a red, blue, green, clear ("RBGC") color filter array, a Foveon X3 color filter array, a Bayer sensor ("RGGB") color filter array, a monochrome sensor color filter array, and / or another type of color filter array. In at least one embodiment, a clear pixel camera may be used, such as a camera with RCCC, RCCB, and / or RBGC color filter arrays, to increase light sensitivity.

[0117] In at least one embodiment, one or more of the cameras may be used to perform advanced driver assistance systems ("ADAS") functions (e.g., as part of a redundant or fail-safe design). For example, in at least one embodiment, a multi-function mono camera may be installed to provide functions including lane departure warning, traffic sign assist, and intelligent headlight control. In at least one embodiment, one or more of the cameras (e.g., all of the cameras) may simultaneously record and provide image data (e.g., video).

[0118] In at least one embodiment, one or more of the cameras may be mounted on a mounting assembly, such as a custom-designed (e.g., three-dimensionally (“3D”) printed) assembly, to eliminate stray light and reflections from the interior of the vehicle (e.g., reflections reflected from the dashboard onto the windshield) that may interfere with the camera's image data capture capabilities. With reference to door mirror mounting assemblies, in at least one embodiment, the door mirror assembly may be custom 3D printed so that the camera mounting plate conforms to the shape of the door mirror. In at least one embodiment, the camera may be integral with the door mirror. For side view cameras, in at least one embodiment, the cameras may again be integrated into the four pillars at each corner of the cabin.

[0119] In at least one embodiment, a camera (e.g., a front-facing camera) having a field of view that includes a portion of the environment ahead of vehicle 2600 may be used for a surroundings view to facilitate identification of the path and obstacles ahead and, in conjunction with controller 2636 and / or one or more of the control SoCs, may assist in providing information essential for generating an occupancy grid and / or determining a preferred vehicle path. In at least one embodiment, the front-facing camera may be used to perform many of the same ADAS functions as LIDAR, including, without limitation, emergency braking, pedestrian detection, and collision avoidance. In at least one embodiment, the front-facing camera may also be used for ADAS features and systems, including, without limitation, other features such as lane departure warnings ("LDW"), autonomous cruise control ("ACC"), and / or traffic sign recognition.

[0120] In at least one embodiment, various cameras may be used in a front-facing configuration, including, for example, a monocular camera platform including a CMOS (complementary metal oxide semiconductor) color imager. In at least one embodiment, a wide-angle camera 2670 may be used to sense objects (e.g., pedestrians, cross traffic, or bicyclists) coming into view from the periphery. While FIG. 26B shows only one wide-angle camera 2670, in other embodiments, there may be any number (including zero) of wide-angle cameras 2670 on the vehicle 2600. In at least one embodiment, any number of long-range cameras 2698 (e.g., a pair of long-view stereo cameras) may be used for depth-based object detection, particularly for objects for which a neural network has not yet been trained. In at least one embodiment, the long-range cameras 2698 may also be used for object detection and classification, as well as basic object tracking.

[0121] In at least one embodiment, any number of stereo cameras 2668 may also be included in a front-facing configuration. In at least one embodiment, one or more stereo cameras 2668 may include an integrated control unit with a scalable processing unit, which may provide a programmable logic gate array ("FPGA") and a multi-core microprocessor with an integrated controller area network ("CAN") or Ethernet interface on a single chip. In at least one embodiment, such a unit may be used to generate a 3D map of the vehicle's 2600 environment, including distance estimates for all points in the image. In at least one embodiment, one or more of the stereo cameras 2668 may include, without limitation, a compact stereo vision sensor, which may include, without limitation, two camera lenses (one on each side) and an image processing chip that can measure the distance from the vehicle 2600 to target objects and use the generated information (e.g., metadata) to activate autonomous emergency braking and lane departure warning features. In at least one embodiment, other types of stereo cameras 2668 may be used in addition to or instead of those described herein.

[0122] In at least one embodiment, a camera having a field of view that includes a portion of the environment to the side of the vehicle 2600 (e.g., a side view camera) may be used for the surrounding view to provide information used to create and update the occupancy grid and generate side collision warnings. For example, in at least one embodiment, surrounding cameras 2674 (e.g., four surrounding cameras 2674 as shown in FIG. 26B ) may be disposed on the vehicle 2600. The surrounding cameras 2674 may include, without limitation, any number and combination of wide-angle cameras 2670, fisheye cameras, and / or 360-degree cameras. For example, in at least one embodiment, four fisheye cameras may be disposed in front, behind, and on the sides of the vehicle 2600. In at least one embodiment, the vehicle 2600 may use three surrounding cameras 2674 (e.g., left, right, and rear) and may utilize one or more other cameras (e.g., a front camera) as a fourth surrounding camera.

[0123] In at least one embodiment, a camera having a field of view that includes a portion of the environment behind vehicle 2600 (e.g., a rear view camera) may be used for parking assistance, surrounding view, rear collision warning, and to create and update the occupancy grid. In at least one embodiment, a variety of cameras may be used, including, but not limited to, cameras also suitable as front cameras described herein (e.g., long-range camera 2698, and / or mid-range camera 2676, stereo camera 2668, infrared camera 2672, etc.).

[0124] Inference and / or training logic 2315 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 2315 are provided herein in conjunction with FIG. 23A and / or FIG. 23B . In at least one embodiment, inference and / or training logic 2315 may be used in the system of FIG. 26B for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein. In at least one embodiment, a robotic grasping system may use the training and inference hardware described above to control a haptic hand.

[0125] FIG. 26C is a block diagram illustrating an example system architecture for the autonomous vehicle 2600 of FIG. 26A according to at least one embodiment. In at least one embodiment, each of the components, features, and systems of the vehicle 2600 of FIG. 26C is shown as connected via a bus 2602. In at least one embodiment, the bus 2602 may include, without limitation, a CAN data interface (alternatively referred to herein as a (CAN bus)). In at least one embodiment, the CAN may be a network internal to the vehicle 2600 used to assist in controlling various features and functions of the vehicle 2600, such as brake application, acceleration, brake control, steering, windshield wipers, etc. In at least one embodiment, the bus 2602 may be configured with tens or even hundreds of nodes, each with its own unique identifier (e.g., a CAN ID). In at least one embodiment, the bus 2602 may be read to determine steering angle, ground speed, engine revolutions per minute ("RPM"), button position, and / or other vehicle status indicators. In at least one embodiment, bus 2602 may be an ASIL B compliant CAN bus.

[0126] In at least one embodiment, FlexRay and / or Ethernet may be used in addition to or instead of CAN. In at least one embodiment, any number of buses 2602 may be present, including, without limitation, zero or more CAN buses, zero or more FlexRay buses, zero or more Ethernet buses, and / or zero or more other types of buses using different protocols. In at least one embodiment, two or more buses 2602 may be used to perform different functions and / or to provide redundancy. For example, a first bus 2602 may be used for collision avoidance functions and a second bus 2602 may be used for actuation control. In at least one embodiment, each bus 2602 may communicate with any of the components of the vehicle 2600, or two or more buses 2602 may communicate with the same component. In at least one embodiment, each of any number of systems on a chip (“SoC”) 2604, each of the controllers 2636, and / or each computer in the vehicle may have access to the same input data (e.g., input from sensors in the vehicle 2600) and may be connected to a common bus, such as a CAN bus.

[0127] In at least one embodiment, vehicle 2600 may include one or more controllers 2636, such as those described herein with respect to FIG. 26A. Controller 2636 may be used for a variety of functions. In at least one embodiment, controller 2636 may be coupled to any of a variety of other components and systems of vehicle 2600 and may be used to control vehicle 2600, artificial intelligence of vehicle 2600, and / or infotainment of vehicle 2600, etc.

[0128] In at least one embodiment, vehicle 2600 may include any number of SoCs 2604. Each of the SoCs 2604 may include, without limitation, a central processing unit ("CPU") 2606, a graphics processing unit ("GPU") 2608, a processor 2610, a cache 2612, an accelerator 2614, a data store 2616, and / or other components and features not shown. In at least one embodiment, SoC 2604 may be used to control vehicle 2600 in a variety of platforms and systems. For example, in at least one embodiment, SoC 2604 may be incorporated into a system (e.g., that of vehicle 2600) having a high definition ("HD") map 2622 that can obtain map refreshes and / or updates via a network interface 2624 from one or more servers (not shown in FIG. 26C ).

[0129] In at least one embodiment, CPU 2606 may include a CPU cluster, or CPU complex (also referred to herein as a "CCPLEX"). In at least one embodiment, CPU 2606 may include multiple cores and / or level 2 ("L2") caches. For example, in at least one embodiment, CPU 2606 may include eight cores in a coherent multiprocessor configuration. In at least one embodiment, CPU 2606 may include four dual-core clusters, where each cluster has a dedicated L2 cache (e.g., 2 MB of L2 cache). In at least one embodiment, CPU 2606 (e.g., a CCPLEX) may be configured to support simultaneous cluster operation, allowing any combination of clusters of CPUs 2606 to be active at any given time.

[0130] In at least one embodiment, one or more of the CPUs 2606 may implement power management functionality, including, without limitation, one or more of the following features: individual hardware blocks may be automatically clock gated when idle to save dynamic power; each core clock may be gated when the core is not actively executing instructions due to execution of a Wait for Interrupt ("WFI") / Wait for Event ("WFE") instruction; each core may be independently power gated; when all cores are clock gated or power gated, each core cluster may be independently clock gated; and / or when all cores are power gated, each core cluster may be independently power gated. In at least one embodiment, the CPUs 2606 may further implement an advanced algorithm for managing power states, where, given allowed power states and expected wake-up times, the hardware / microcode determines the best power state for cores, clusters, and CCPLEXes to enter. In at least one embodiment, a processing core may support in software a simple sequence of entering power states, with work offloaded to microcode.

[0131] In at least one embodiment, GPU2608 may include an integrated GPU (alternatively referred to herein as an “iGPU”). In at least one embodiment, GPU2608 may be programmable and efficient for parallel workloads. In at least one embodiment, GPU2608 may use an extended tensor instruction set. In one embodiment, GPU2608 may include one or more streaming microprocessors, where each streaming microprocessor may include a level 1 (“L1”) cache (e.g., an L1 cache having at least 96 KB of storage capacity) and two or more of the streaming microprocessors may share an L2 cache (e.g., an L2 cache having 512 KB of storage capacity). In at least one embodiment, GPU2608 may include at least eight streaming microprocessors. In at least one embodiment, GPU2608 may use a compute application programming interface (API). In at least one embodiment, GPU 2608 may use one or more parallel computing platforms and / or programming modules (e.g., NVIDIA's CUDA).

[0132] In at least one embodiment, one or more of the GPUs 2608 may be power-optimized for best performance in automotive and embedded use cases. For example, in one embodiment, the GPUs 2608 may be fabricated on fin field-effect transistors ("FinFETs"). In at least one embodiment, each streaming microprocessor may incorporate a number of mixed-precision processing cores partitioned into multiple blocks. For example, without limitation, 64 PF32 cores and 32 PF64 cores may be partitioned into four processing blocks. In at least one embodiment, each processing block may be allocated 16 FP32 cores, 8 FP64 cores, 16 INT32 cores, two mixed-precision NVIDIA TENSOR cores for deep learning matrix operations, a level-zero ("L0") instruction cache, a warp scheduler, a dispatch unit, and / or a 64KB register file. In at least one embodiment, the streaming microprocessor includes independent parallel integer and floating-point data paths to achieve efficient execution of workloads by mixing computational and addressing calculations. In at least one embodiment, the streaming microprocessor may include independent thread scheduling to enable finer-grained synchronization and coordination between parallel threads. In at least one embodiment, the streaming microprocessor may include a combination of an L1 data cache and a shared memory unit to improve performance while simplifying programming.

[0133] In at least one embodiment, one or more of GPUs 2608 may include high bandwidth memory ("HBM") and / or a 16 GB HBM2 memory subsystem, providing, in some instances, approximately 900 GB / s of peak memory bandwidth. In at least one embodiment, synchronous graphics random-access memory ("SGRAM"), such as graphics double data rate type five ("GDDR5"), may be used in addition to or in place of the HBM memory.

[0134] In at least one embodiment, the GPU 2608 may include unified memory technology. In at least one embodiment, address translation services ("ATS") support may be used to allow the GPU 2608 to directly access the CPU 2606's page tables. In at least one embodiment, when the GPU 2608 memory management unit ("MMU") encounters a miss, an address translation request may be sent to the CPU 2606. In at least one embodiment, in response, the CPU 2606 may look up the virtual-to-physical address mapping in its page table and send the translation back to the GPU 2608. In at least one embodiment, the unified memory technology allows for a single, unified virtual address space for both the CPU 2606 and the GPU 2608's memory, thereby simplifying programming the GPU 2608 and porting applications to the GPU 2608.

[0135] In at least one embodiment, GPU 2608 may include any number of access counters that can record the frequency of GPU 2608's accesses to the memory of other processors. In at least one embodiment, the access counters may help ensure that memory pages are moved to the physical memory of the processor that is accessing the pages most frequently, thereby improving the efficiency of memory ranges shared between processors.

[0136] In at least one embodiment, one or more of the SoCs 2604 may include any number of caches 2612, including those described herein. For example, in at least one embodiment, the caches 2612 may include a level 3 (“L3”) cache available to both the CPU 2606 and the GPU 2608 (e.g., connected to both the CPU 2606 and the GPU 2608). In at least one embodiment, the caches 2612 may include a write-back cache that can record line state through the use of a cache coherence protocol or the like (e.g., MEI, MESI, MSI, etc.). In at least one embodiment, the L3 cache may include 4 MB or more, depending on the embodiment, although smaller cache sizes may also be used.

[0137] In at least one embodiment, one or more of the SoCs 2604 may include one or more accelerators 2614 (e.g., hardware accelerators, software accelerators, or a combination thereof). In at least one embodiment, the SoCs 2604 may include a hardware acceleration cluster, which may include optimized hardware accelerators and / or large on-chip memory. In at least one embodiment, the large on-chip memory (e.g., 4 MB of SRAM) may enable the hardware acceleration cluster to accelerate neural networks and other calculations. In at least one embodiment, the hardware acceleration cluster may be used to complement the GPU 2608 and offload some of the GPU 2608's tasks (e.g., freeing up more cycles for the GPU 2608 to perform other tasks). In at least one embodiment, accelerator 2614 may be used for targeted workloads that are stable enough to accommodate acceleration (e.g., perception, convolutional neural networks (“CNNs”), recurrent neural networks (“RNNs”), etc.). In at least one embodiment, CNNs may include region-based, i.e., regional convolutional neural networks (“RCNNs”), and Fast RCNNs (e.g., used for object detection), or other types of CNNs.

[0138] In at least one embodiment, the accelerator 2614 (e.g., a hardware-accelerated cluster) may include a deep learning accelerator (“DLA”). The DLA may include, without limitation, one or more tensor processing units (“TPU”), which may be further configured to provide tens of trillions of operations per second for deep learning applications and inference. In at least one embodiment, the TPU may be an accelerator configured and optimized to perform image processing functions (e.g., CNN, RCNN, etc.). The DLA may further be optimized for a specific set of neural network types and floating-point operations, as well as for inference. In at least one embodiment, the DLA's design allows for improved performance per millimeter over typical general-purpose GPUs, typically significantly exceeding the performance of a CPU. In at least one embodiment, the TPU may perform several functions, including, for example, single-instance convolution functions supporting INT8, INT16, and FP16 data types for both features and weights, as well as post-processing functions. In at least one embodiment, the DLA may quickly and efficiently run neural networks, particularly CNNs, on processed or unprocessed data for any of a variety of functions, including, for example, without limitation, a CNN for object identification and detection using data from a camera sensor, a CNN for distance estimation using data from a camera sensor, a CNN for emergency vehicle detection and identification using data from microphone 2696, a CNN for face recognition and vehicle owner identification using data from a camera sensor, and / or a CNN for security and / or safety events.

[0139] In at least one embodiment, the DLA may perform any function of the GPU 2608, and a designer may target either the DLA or the GPU 2608 for any function, for example, by using an inference accelerator. For example, in at least one embodiment, a designer may centralize CNN and floating-point processing in the DLA and offload other functions to the GPU 2608 and / or other accelerators 2614.

[0140] In at least one embodiment, the accelerator 2614 (e.g., a hardware acceleration cluster) may include a programmable vision accelerator (“PVA”), which may alternatively be referred to herein as a computer vision accelerator. In at least one embodiment, the PVA may be designed and configured to accelerate computer vision algorithms for advanced driver assistance systems (“ADAS”) 2638, autonomous driving, augmented reality (“AR”) applications, and / or virtual reality (“VR”) applications. The PVA may balance performance and versatility. For example, in at least one embodiment, each PVA may include, by way of example and without limitation, any number of reduced instruction set computer (“RISC”) cores, direct memory access (“DMA”) processors, and / or any number of vector processors.

[0141] In at least one embodiment, the RISC core may interact with an image sensor (e.g., an image sensor of any of the cameras described herein), an image signal processor, and / or the like. In at least one embodiment, each of the RISC cores may include any amount of memory. In at least one embodiment, the RISC core may use any of a number of protocols, depending on the embodiment. In at least one embodiment, the RISC core may execute a real-time operating system ("RTOS"). In at least one embodiment, the RISC core may be implemented using one or more integrated circuit devices, application specific integrated circuits ("ASICs"), and / or memory devices. For example, in at least one embodiment, the RISC core may include an instruction cache and / or tightly coupled RAM.

[0142] In at least one embodiment, the DMA may allow components of the PVA to access system memory independently of the CPU 2606. In at least one embodiment, the DMA may support any number of features used to provide optimizations to the PVA, including, but not limited to, multi-dimensional addressing and / or circular addressing. In at least one embodiment, the DMA may support up to six or more addressing dimensions, which may include, without limitation, block width, block height, block depth, horizontal block stepping, vertical block stepping, and / or depth stepping.

[0143] In at least one embodiment, the vector processor may be a programmable processor that may be designed to efficiently and flexibly execute programming for computer vision algorithms and provide signal processing functions. In at least one embodiment, the PVA may include a PVA core and two vector processing subsystem partitions. In at least one embodiment, the PVA core may include a processor subsystem, a DMA engine (e.g., two DMA engines), and / or other peripheral devices. In at least one embodiment, the vector processing subsystem may operate as the primary processing engine of the PVA and may include a vector processing unit ("VPU"), an instruction cache, and / or a vector memory (e.g., "VMEM"). In at least one embodiment, the VPU may include a digital signal processor, such as a single instruction, multiple data ("SIMD"), very long instruction word ("VLIW") digital signal processor. In at least one embodiment, the combination of SIMD and VLIW may improve throughput and speed.

[0144] In at least one embodiment, each of the vector processors may include an instruction cache and may be coupled to dedicated memory. As a result, in at least one embodiment, each of the vector processors may be configured to execute independently of other vector processors. In at least one embodiment, the vector processors included in a particular PVA may be configured to employ data parallelism. For example, in at least one embodiment, multiple vector processors included in a single PVA may execute the same computer vision algorithm on different regions of an image. In at least one embodiment, the vector processors included in a particular PVA may execute different computer vision algorithms simultaneously on the same image, or even execute different algorithms on consecutive images or portions of an image. In at least one embodiment, among other things, any number of PVAs may be included in a hardware-accelerated cluster, and any number of vector processors may be included in each PVA. In at least one embodiment, the PVA may include additional error correction code ("ECC") memory to enhance the overall security of the system.

[0145] In at least one embodiment, the accelerator 2614 (e.g., a hardware acceleration cluster) may include an on-chip computer vision network and static random access memory (“SRAM”) to provide high-bandwidth, low-latency SRAM for the accelerator 2614. In at least one embodiment, the on-chip memory may include, for example, without limitation, at least 4 MB of SRAM consisting of eight field-configurable memory blocks, which may be accessible from both the PVA and the DLA. In at least one embodiment, each pair of memory blocks may include an advanced peripheral bus (“APB”) interface, configuration circuitry, a controller, and a multiplexer. In at least one embodiment, any type of memory may be used. In at least one embodiment, the PVA and DLA may access the memory through a backbone that provides the PVA and DLA with high-speed access to the memory. In at least one embodiment, the backbone may include an on-chip computer vision network that interconnects the PVA and DLA to the memory (e.g., using the APB).

[0146] In at least one embodiment, the on-chip computer vision network may include an interface that determines whether both the PVA and DLA provide ready and enable signals before transmitting any control signals / addresses / data. In at least one embodiment, the interface may provide separate phases and separate channels for transmitting control signals / addresses / data, as well as burst-based communication for continuous data transfer. In at least one embodiment, the interface may conform to International Organization for Standardization (“ISO”) 26262 or International Electrotechnical Commission (“IEC”) 61508 standards, although other standards and protocols may be used.

[0147] In at least one embodiment, one or more of the SoCs 2604 may include a real-time ray tracing hardware accelerator, which may be used to quickly and efficiently determine the location and range of objects (e.g., within a world model) to generate real-time visualization simulations for RADAR signal interpretation, sound propagation synthesis and / or analysis, SONAR system simulation, general waveform propagation simulation, comparison with LIDAR data for localization and / or other functions, and / or other uses.

[0148] In at least one embodiment, accelerator 2614 (e.g., a hardware accelerator cluster) has diverse uses for autonomous driving. In at least one embodiment, the PVA may be a programmable vision accelerator that can be used for key processing stages in ADAS and autonomous vehicles. In at least one embodiment, the performance of the PVA is well suited to algorithm domains that require low-power, low-latency, and predictable processing. In other words, the PVA works well for semi-dense or dense regular computations that require low-latency, low-power, and predictable run-times, even with small data sets. In at least one embodiment, in an autonomous vehicle such as vehicle 2600, the PVA is designed to run traditional computer vision algorithms because they are effective for object detection and integer arithmetic.

[0149] For example, according to at least one embodiment of the technology, computer stereo vision may be performed using the PVA. In at least one embodiment, algorithms based on semi-global matching may be used in some instances, but this is not intended to be limiting. In at least one embodiment, applications for Level 3-5 autonomous driving use motion estimation / stereo matching (e.g., structure from motion, pedestrian recognition, lane detection, etc.) on the fly. In at least one embodiment, the PVA may perform computer stereo vision functions on input from two monocular cameras.

[0150] In at least one embodiment, the PVA may be used to perform dense optical flow. For example, in at least one embodiment, the PVA may process raw RADAR data (e.g., using a 4D Fast Fourier Transform) to provide processed RADAR data. In at least one embodiment, the PVA may be used for time-of-flight depth processing, e.g., by processing raw time-of-flight data to provide processed time-of-flight data.

[0151] In at least one embodiment, the DLA may be used to implement any type of network for enhancing control and driving safety, including, for example, without limitation, a neural network that outputs a confidence measure for each object detection. In at least one embodiment, the confidence may be expressed or interpreted as the probability of each detection compared to other detections or as providing its relative “weight.” In at least one embodiment, the confidence may further enable the system to make decisions regarding which detections should be considered true positive detections rather than false positive detections. For example, in at least one embodiment, the system may set a threshold for confidence and consider only detections above the threshold to be true positive detections. In embodiments where automatic emergency braking (“AEB”) is used, a false positive detection may cause the vehicle to automatically apply the emergency brakes, which is clearly undesirable. In at least one embodiment, a highly confident detection may be considered to trigger AEB. In at least one embodiment, the DLA may implement a neural network to regress the confidence value. In at least one embodiment, the neural network may take as its input at least some subset of parameters, such as bounding box dimensions, a ground surface estimate obtained (e.g., from another subsystem), an output from an IMU sensor 2666 that correlates with the orientation of the vehicle 2600, distance, and a 3D location estimate of the object obtained from the neural network and / or other sensors (e.g., a LIDAR sensor 2664 or a RADAR sensor 2660), among others.

[0152] In at least one embodiment, one or more of the SoCs 2604 may include a data store 2616 (e.g., memory). In at least one embodiment, the data store 2616 may be on-chip memory of the SoC 2604, which may store neural networks running on the GPU 2608 and / or DLA. In at least one embodiment, the capacity of the data store 2616 may be large enough to store multiple instances of the neural network for redundancy and safety. In at least one embodiment, the data store 2616 may comprise an L2 or L3 cache.

[0153] In at least one embodiment, one or more of the SoCs 2604 may include any number of processors 2610 (e.g., embedded processors). The processors 2610 may include a boot and power management processor, which may be a dedicated processor and subsystem for handling boot power and management functions and related security enforcement. In at least one embodiment, the boot and power management processor may be part of the boot sequence of the SoC 2604 and may provide runtime power management services. In at least one embodiment, the boot power and management processor may provide clock and voltage programming, assist in transitioning the system to a low power state, manage the thermal and temperature sensors of the SoC 2604, and / or manage the power state of the SoC 2604. In at least one embodiment, each temperature sensor may be implemented as a ring oscillator whose output frequency is proportional to temperature, and the SoC 2604 may use the ring oscillator to detect the temperature of the CPU 2606, GPU 2608, and / or accelerator 2614. In at least one embodiment, if the temperature is determined to exceed a threshold, the boot and power management processor may enter a temperature fault routine, place the SoC 2604 in a low power state, and / or place the vehicle 2600 in a driver-safety shutdown mode (e.g., bring the vehicle 2600 to a safety shutdown).

[0154] In at least one embodiment, processor 2610 may further include a set of embedded processors that can act as an audio processing engine. In at least one embodiment, the audio processing engine may be an audio subsystem that enables full hardware support for multi-channel audio over multiple interfaces and a wide variety of flexible audio I / O interfaces. In at least one embodiment, the audio processing engine is a dedicated processor core that includes a digital signal processor with dedicated RAM.

[0155] In at least one embodiment, processor 2610 may further include an always-on processor engine capable of providing the hardware features necessary to support low-power sensor management and bring-up use cases. In at least one embodiment, the always-on processor engine may include, without limitation, a processor core, tightly coupled RAM, supporting peripherals (e.g., timers and interrupt controllers), various I / O controller peripherals, and routing logic.

[0156] In at least one embodiment, the processor 2610 may further include a safety cluster engine, which may include, without limitation, a processor subsystem dedicated to handling safety management for automotive applications. In at least one embodiment, the safety cluster engine may include, without limitation, two or more processor cores, tightly coupled RAM, supporting peripherals (e.g., timers, interrupt controllers, etc.), and / or routing logic. In safety mode, in at least one embodiment, two or more cores may operate in lockstep mode and function as a single core with comparison logic to detect any differences between their operations. In at least one embodiment, the processor 2610 may further include a real-time camera engine, which may include, without limitation, a processor subsystem dedicated to handling real-time camera management. In at least one embodiment, the processor 2610 may further include a high dynamic range signal processor, which may include, without limitation, an image signal processor, which is a hardware engine that is part of a camera processing pipeline.

[0157] In at least one embodiment, processor 2610 may include a video image composer, which may be a processing block (e.g., implemented in a microprocessor) that implements video post-processing functions required by a video playback application to generate a final image in a playback device window. In at least one embodiment, the video image composer may perform lens distortion correction for wide-angle camera 2670, surrounding camera 2674, and / or in-cabin surveillance camera sensors. In at least one embodiment, the in-cabin surveillance camera sensors are preferably monitored by a neural network running on a separate instance of SoC 2604 that is configured to identify in-cabin events and respond accordingly. In at least one embodiment, the in-cabin system may perform lip reading, without limitation, to activate cellular service, make phone calls, write emails, change the vehicle's destination, activate or change the vehicle's infotainment system and settings, and provide voice-activated web surfing. In at least one embodiment, certain functions are available to the driver when the vehicle is operating in autonomous mode and are unavailable at other times.

[0158] In at least one embodiment, the video image combiner may include enhanced temporal noise reduction for both spatial and temporal noise reduction. For example, in at least one embodiment, when motion occurs in the video, the noise reduction appropriately weights spatial information and downweights information provided by adjacent frames. In at least one embodiment, when an image or portion of an image does not contain motion, the temporal noise reduction performed by the video image combiner may use information from previous images to reduce noise in the current image.

[0159] In at least one embodiment, the video image composer may also be configured to perform stereo correction on the input stereo lens frames. In at least one embodiment, the video image composer may also be used to composite a user interface when the operating system desktop is in use, eliminating the need for the GPU 2608 to continually render new surfaces. In at least one embodiment, the video image composer may be used to offload the GPU 2608 when it is powered on and actively performing 3D rendering, improving performance and responsiveness.

[0160] In at least one embodiment, one or more of the SoCs 2604 may further include a mobile industry processor interface ("MIPI") camera serial interface for receiving input from video and cameras, a high-speed interface, and / or a video input block that may be used for camera and associated pixel input functions. In at least one embodiment, one or more of the SoCs 2604 may further include an input / output controller, which may be controlled by software and may be used to receive I / O signals that are not tied to a specific role.

[0161] In at least one embodiment, one or more of the SoCs 2604 may further include peripherals, audio encoders / decoders ("codecs"), power management, and / or a wide range of peripheral interfaces to enable communication with other devices. The SoCs 2604 may be used to process data from cameras (e.g., connected via a gigabit multimedia serial link and Ethernet), data from sensors (e.g., LIDAR sensor 2664, RADAR sensor 2660, etc., which may be connected via Ethernet), data from bus 2602 (e.g., vehicle 2600 speed, steering wheel position, etc.), data from GNSS sensor 2658 (e.g., connected via Ethernet or CAN bus), etc. In at least one embodiment, one or more of the SoCs 2604 may further include a dedicated high-performance mass storage controller, which may include its own DMA engine and may be used to offload routine data management tasks from the CPU 2606.

[0162] In at least one embodiment, the SoC2604 may be an end-to-end platform with a flexible architecture spanning levels 3-5 of automation, providing a comprehensive functional safety architecture that leverages and efficiently utilizes computer vision and ADAS techniques for diversity and redundancy, and a flexible, reliable driving software stack, along with deep learning tools. In at least one embodiment, the SoC2604 is faster, more reliable, and more energy- and space-efficient than conventional systems. For example, in at least one embodiment, the accelerator 2614, when combined with the CPU 2606, GPU 2608, and data store 2616, can provide a fast and efficient platform for levels 3-5 of autonomous vehicles.

[0163] In at least one embodiment, computer vision algorithms may run on a CPU, which may be configured using a high-level programming language, such as the C programming language, to perform various processing algorithms across various visual data. However, in at least one embodiment, CPUs often cannot meet the performance, execution time, and power consumption requirements of many computer vision applications. In at least one embodiment, many CPUs are unable to run complex object detection algorithms used in in-vehicle ADAS applications and realistic Level 3-5 autonomous vehicles in real time.

[0164] Embodiments described herein enable multiple neural networks to run simultaneously and / or sequentially, and the results can be combined to enable Level 3-5 autonomous driving capabilities. For example, in at least one embodiment, the CNN running on the DLA or a separate GPU (e.g., GPU2620) may include text and word recognition, enabling the supercomputer to read and understand traffic signs, including signs for which the neural network was not specifically trained. In at least one embodiment, the DLA may further include a neural network that can identify and interpret signs and provide a semantic understanding of the signs, which can then be passed to a route planning module running on the CPU complex.

[0165] In at least one embodiment, for Level 3, 4, or 5 driving, multiple neural networks may be running simultaneously. For example, in at least one embodiment, a warning sign displaying "Caution: Flashing Icy Conditions" in conjunction with an electric light may be interpreted separately or collectively by several neural networks. In at least one embodiment, the sign itself may be identified as a traffic sign by a first deployed neural network (e.g., a neural network that has been trained), and the words "Flashing Icy Conditions" may be interpreted by a second deployed neural network, which, if the flashing light is detected, notifies the vehicle's route planning software (preferably running on the CPU complex) that an icy condition exists. In at least one embodiment, the flashing light may be identified by running a third deployed neural network over multiple frames, and the presence (or absence) of the flashing light is notified to the vehicle's route planning software. In at least one embodiment, all three neural networks may be running simultaneously, such as within the DLA and / or on the GPU 2608.

[0166] In at least one embodiment, a CNN for facial recognition and vehicle owner identification may use data from the camera sensor to identify the presence of an authorized driver and / or owner of the vehicle 2600. In at least one embodiment, an always-on sensor processing engine may be used to unlock the vehicle and turn on the lights when the owner approaches the driver's door, and to disable the vehicle in security mode when the owner leaves the vehicle. In this way, the SoC2604 provides security against theft and / or carjacking.

[0167] In at least one embodiment, a CNN for emergency vehicle detection and identification may use data from microphone 2696 to detect and identify emergency vehicle sirens. In at least one embodiment, SoC 2604 uses a CNN to classify environmental and urban sounds as well as visual data. In at least one embodiment, the CNN running on the DLA is trained to identify the relative speed at which an emergency vehicle is approaching (e.g., by using the Doppler effect). In at least one embodiment, the CNN may also be trained to identify emergency vehicles specific to the region in which the vehicle is operating, as identified by GNSS sensor 2658. In at least one embodiment, when operating in Europe, the CNN attempts to detect European sirens, and when in the United States, it attempts to identify only North American sirens. In at least one embodiment, when an emergency vehicle is detected, a control program to execute an emergency vehicle safety routine may be used to slow the vehicle, pull over, stop the vehicle, and / or idle the vehicle in conjunction with ultrasonic sensor 2662 until the emergency vehicle has passed.

[0168] In at least one embodiment, vehicle 2600 may include a CPU 2618 (e.g., a discrete CPU or dCPU), which may be coupled to SoC 2604 via a high-speed interconnect (e.g., PCIe). In at least one embodiment, CPU 2618 may include, for example, an X86 processor. CPU 2618 may be used to perform any of a variety of functions, including, for example, reconciling potentially inconsistent results between ADAS sensors and SoC 2604 and / or monitoring the status and health of controller 2636 and / or infotainment system on a chip (“infotainment SoC”) 2630.

[0169] In at least one embodiment, vehicle 2600 may include a GPU 2620 (e.g., a discrete GPU or dGPU), which may be coupled to SoC 2604 via a high-speed interconnect (e.g., NVIDIA's NVLINK). In at least one embodiment, GPU 2620 may provide additional artificial intelligence functionality, such as by running redundant and / or different neural networks, and may be used to train and / or update neural networks based at least in part on input (e.g., sensor data) from sensors in vehicle 2600.

[0170] In at least one embodiment, vehicle 2600 may further include a network interface 2624, which may include, without limitation, a wireless antenna 2626 (e.g., one or more wireless antennas 2626 for different communication protocols, such as a cellular antenna, a Bluetooth antenna, etc.). In at least one embodiment, network interface 2624 may be used to enable wireless connectivity over the Internet with the cloud (e.g., servers and / or other network devices), other vehicles, and / or computing devices (e.g., passenger client devices). In at least one embodiment, to communicate with other vehicles, a direct link may be established between vehicle 2600 and the other vehicles, and / or an indirect link (e.g., across a network and via the Internet) may be established. In at least one embodiment, the direct link may be provided using a vehicle-to-vehicle communication link. The vehicle-to-vehicle communication link may provide vehicle 2600 with information about vehicles in its vicinity (e.g., vehicles in front of, to the sides of, and / or behind vehicle 2600). In at least one embodiment, the above-described functionality may be part of a cooperative adaptive cruise control function of the vehicle 2600.

[0171] In at least one embodiment, network interface 2624 may include an SoC that provides modulation and demodulation functionality and enables controller 2636 to communicate over a wireless network. In at least one embodiment, network interface 2624 may include a radio frequency front end for up-conversion from baseband to radio frequency and down-conversion from radio frequency to baseband. In at least one embodiment, frequency conversion may be performed in any technically feasible manner. For example, frequency conversion may be performed by well-known processes and / or using a super-heterodyne process. In at least one embodiment, radio frequency front-end functionality may be provided by a separate chip. In at least one embodiment, network interface may include wireless functionality for communicating via LTE, WCDMA, UMTS, GSM, CDMA2000, Bluetooth, Bluetooth LE, Wi-Fi, Z-Wave, ZigBee, LoRaWAN, and / or other wireless protocols.

[0172] In at least one embodiment, vehicle 2600 may further include a data store 2628, which may include, without limitation, off-chip (e.g., not on SoC 2604) storage. In at least one embodiment, data store 2628 may include one or more storage elements, including, without limitation, RAM, SRAM, dynamic random access memory (“DRAM”), video random-access memory (“VRAM”), flash, a hard disk, and / or other components and / or devices capable of storing at least one bit of data.

[0173] In at least one embodiment, vehicle 2600 may further include GNSS sensors 2658 (e.g., GPS and / or assisted GPS sensors) to assist in mapping, perception, occupancy grid generation, and / or route planning functions. In at least one embodiment, any number of GNSS sensors 2658 may be used, including, for example, without limitation, a GPS using a USB connector with an Ethernet to serial (e.g., RS-232) bridge.

[0174] In at least one embodiment, vehicle 2600 may further include RADAR sensor 2660. RADAR sensor 2660 may be used by vehicle 2600 for long-range vehicle detection, even in low light and / or severe weather conditions. In at least one embodiment, the RADAR functional safety level may be ASIL B. RADAR sensor 2660 may use CAN and / or bus 2602 for control (e.g., to transmit data generated by RADAR sensor 2660) and to access object tracking data, and in some instances may have Ethernet access to access raw data. In at least one embodiment, various types of RADAR sensors may be used. For example, without limitation, RADAR sensor 2660 may be suitable for forward, rearward, and side RADAR use. In at least one embodiment, one or more of RADAR sensors 2660 are pulse-Doppler RADAR sensors.

[0175] In at least one embodiment, the RADAR sensor 2660 may include different configurations, such as long-range with a narrow field of view, short-range with a wide field of view, and short-range with side coverage. In at least one embodiment, the long-range RADAR may be used for adaptive cruise control functions. In at least one embodiment, the long-range RADAR system may provide a wide field of view, such as within a 250 meter range, achieved by two or more independent scans. In at least one embodiment, the RADAR sensor 2660 may help distinguish between static and moving objects and may be used by the ADAS system 2638 to provide emergency braking assistance and forward collision warning. The sensors 2660 included in a long-range RADAR system may include, without limitation, multiple (e.g., six or more) fixed RADAR antennas, as well as monostatic multi-mode RADAR with high-speed CAN and FlexRay interfaces. In at least one embodiment, where there are six antennas, the center four antennas may generate a focused beam pattern designed to record the surroundings of vehicle 2600 at higher speeds with minimal interference from adjacent lanes. In at least one embodiment, the other two antennas may extend the field of view, allowing for quick detection of vehicles entering or exiting vehicle 2600's lane.

[0176] In at least one embodiment, the medium-range RADAR system may include, by way of example, a range of up to 160 meters (forward) or 80 meters (rearward) and a field of view of up to 42 degrees (forward) or 150 degrees (rearward). In at least one embodiment, the short-range RADAR system may include, without limitation, any number of RADAR sensors 2660 designed to be mounted on either end of the rear bumper. When mounted on either end of the rear bumper, in at least one embodiment, the RADAR sensor system may generate two beams that constantly monitor blind spots behind and adjacent to the vehicle. In at least one embodiment, the short-range RADAR system may be used in an ADAS system 2638 to provide blind spot detection and / or lane change assistance.

[0177] In at least one embodiment, vehicle 2600 may further include ultrasonic sensors 2662. Ultrasonic sensors 2662 may be located at the front, rear, and / or sides of vehicle 2600 and may be used for parking assistance and / or to generate and update an occupancy grid. In at least one embodiment, multiple ultrasonic sensors 2662 may be used, and different ultrasonic sensors 2662 may be used for different detection ranges (e.g., 2.5 m, 4 m). In at least one embodiment, ultrasonic sensors 2662 may operate at functional safety level ASIL B.

[0178] In at least one embodiment, vehicle 2600 may include a LIDAR sensor 2664. The LIDAR sensor 2664 may be used for object and pedestrian detection, emergency braking, collision avoidance, and / or other functions. In at least one embodiment, the LIDAR sensor 2664 may be functional safety level ASIL B. In at least one embodiment, vehicle 2600 may include multiple LIDAR sensors 2664 (e.g., two, four, six, etc.), which may use Ethernet (e.g., to provide data to a Gigabit Ethernet switch).

[0179] In at least one embodiment, the LIDAR sensor 2664 may be capable of providing a list of objects and their distances for a 360-degree field of view. In at least one embodiment, a commercially available LIDAR sensor 2664 may, for example, have an advertised range of approximately 100 m, an accuracy of 2 cm to 3 cm, and support a 100 Mbps Ethernet connection. In at least one embodiment, one or more non-protruding LIDAR sensors 2664 may be used. In such an embodiment, the LIDAR sensor 2664 may be implemented as a small device that can be integrated into the front, rear, sides, and / or corners of the vehicle 2600. In at least one embodiment, the LIDAR sensor 2664 of such an embodiment may provide a horizontal field of view of up to 120 degrees and a vertical field of view of 35 degrees, with a range of 200 m, even for low-reflectivity objects. In at least one embodiment, a front-mounted LIDAR sensor 2664 may be configured to provide a horizontal field of view of 45 degrees to 135 degrees.

[0180] In at least one embodiment, LIDAR technology such as 3D flash LIDAR may also be used. 3D flash LIDAR uses a laser flash as a transmission source to illuminate the surroundings of the vehicle 2600 up to approximately 200 meters. In at least one embodiment, the flash LIDAR unit includes, without limitation, a receptor that records the transit time of the laser pulse and the reflected light at each pixel, which corresponds to the range from the vehicle 2600 to the object. In at least one embodiment, flash LIDAR may enable a highly accurate, distortion-free image of the surroundings to be generated with each laser flash. In at least one embodiment, four flash LIDARs may be deployed, one on each side of the vehicle 2600. In at least one embodiment, the 3D flash LIDAR system includes, without limitation, a solid-state 3D staring array LIDAR camera (e.g., a non-scanning LIDAR device) with no moving parts other than a fan. In at least one embodiment, the flash LIDAR device may use 5 nanosecond Class I (eye-safe) laser pulses per frame and may capture reflected laser light in the form of a 3D range point cloud and co-registered intensity data.

[0181] In at least one embodiment, the vehicle may further include an IMU sensor 2666. In at least one embodiment, the IMU sensor 2666 may be positioned at the center of the rear axle of the vehicle 2600. In at least one embodiment, the IMU sensor 2666 may include, for example, without limitation, an accelerometer, a magnetometer, a gyroscope, a magnetic compass, and / or other sensor types. In at least one embodiment, such as in a 6-axis application, the IMU sensor 2666 may include, without limitation, an accelerometer and a gyroscope. In at least one embodiment, such as in a 9-axis application, the IMU sensor 2666 may include, without limitation, an accelerometer, a gyroscope, and a magnetometer.

[0182] In at least one embodiment, IMU sensor 2666 may be implemented as a compact, high-performance GPS-Aided Inertial Navigation System ("GPS / INS") that combines micro-electro-mechanical systems ("MEMS") inertial sensors, a highly sensitive GPS receiver, and advanced Kalman filtering algorithms to provide estimates of position, velocity, and attitude. In at least one embodiment, IMU sensor 2666 enables vehicle 2600 to estimate heading by directly observing velocity changes and correlating them from GPS to IMU sensor 2666 without requiring input from a magnetic sensor. In at least one embodiment, IMU sensor 2666 and GNSS sensor 2658 may be combined into a single integrated unit.

[0183] In at least one embodiment, vehicle 2600 may include microphones 2696 located in and / or around vehicle 2600. In at least one embodiment, microphones 2696 may be used for, among other things, detection and identification of emergency vehicles.

[0184] In at least one embodiment, vehicle 2600 may further include any number of camera types, including stereo camera 2668, wide-angle camera 2670, infrared camera 2672, perimeter camera 2674, long-range camera 2698, mid-range camera 2676, and / or other camera types. In at least one embodiment, cameras may be used to capture image data around the entire perimeter of vehicle 2600. In at least one embodiment, the types of cameras used vary depending on vehicle 2600. In at least one embodiment, any combination of camera types may be used to provide the required coverage around vehicle 2600. In at least one embodiment, the number of cameras may vary depending on the embodiment. For example, in at least one embodiment, vehicle 2600 may include six cameras, seven cameras, ten cameras, twelve cameras, or another number of cameras. The cameras may support, by way of example and without limitation, Gigabit Multimedia Serial Link (“GMSL”) and / or Gigabit Ethernet. In at least one embodiment, each camera is described in further detail herein above with respect to Figures 26A and 26B.

[0185] In at least one embodiment, vehicle 2600 may further include a vibration sensor 2642. Vibration sensor 2642 may measure vibrations of components of vehicle 2600, such as an axle. For example, in at least one embodiment, a change in vibration may indicate a change in the road surface. In at least one embodiment, if two or more vibration sensors 2642 are used, the difference between the vibrations may be used to determine the amount of friction or slippage of the road surface (e.g., if there is a vibration difference between a powered axle and a free-spinning axle).

[0186] In at least one embodiment, vehicle 2600 may include an ADAS system 2638. ADAS system 2638 may include, without limitation, an SoC in some instances. In at least one embodiment, the ADAS systems 2638 may include, without limitation, any number and combination of autonomous / adaptive / automatic cruise control ("ACC") systems, cooperative adaptive cruise control ("CACC") systems, forward crash warning ("FCW") systems, automatic emergency braking ("AEB") systems, lane departure warning ("LDW") systems, lane keep assist ("LKA") systems, blind spot warning ("BSW") systems, rear cross-traffic warning ("RCTW") systems, collision warning ("CW") systems, lane centering ("LC") systems, and / or other systems, features, and / or functions.

[0187] In at least one embodiment, the ACC system may use a RADAR sensor 2660, a LIDAR sensor 2664, and / or any number of cameras. In at least one embodiment, the ACC system may include a longitudinal ACC system and / or a lateral ACC system. In at least one embodiment, the longitudinal ACC system monitors and controls the distance to the vehicle immediately preceding the vehicle 2600 and automatically adjusts the speed of the vehicle 2600 to maintain a safe distance from the vehicle ahead. In at least one embodiment, the lateral ACC system enforces distance maintenance and notifies the vehicle 2600 to change lanes when necessary. In at least one embodiment, the lateral ACC is related to other ADAS applications, such as LC and CW.

[0188] In at least one embodiment, the CACC system uses information from other vehicles, which may be received by network interface 2624 and / or wireless antenna 2626 from other vehicles via a wireless link or indirectly via a network connection (e.g., via the Internet). In at least one embodiment, a vehicle-to-vehicle ("V2V") communication link may provide a direct link, while an infrastructure-to-vehicle ("I2V") communication link may provide an indirect link. Generally, the V2V communication concept provides information about the immediate preceding vehicle (e.g., a vehicle immediately in front of vehicle 2600 and in the same lane), while the I2V communication concept provides information about traffic ahead of that. In at least one embodiment, the CACC system may include either or both I2V and V2V information sources. In at least one embodiment, information about vehicles in front of vehicle 2600 may make the CACC system more reliable, potentially allowing for smoother traffic flow and reducing congestion on the roads.

[0189] In at least one embodiment, the FCW system is designed to alert the driver to hazards so that the driver can take corrective action. In at least one embodiment, the FCW system uses a front-facing camera and / or RADAR sensor 2660 coupled to a dedicated processor, DSP, FPGA, and / or ASIC that is electrically coupled to feedback to the driver, such as a display, speaker, and / or vibration component. In at least one embodiment, the FCW system may provide warnings in the form of an audible, visual warning, vibration, and / or a quick brake pulse.

[0190] In at least one embodiment, the AEB system may detect an imminent frontal collision with another vehicle or other object and automatically apply the brakes if the driver does not take corrective action within specified time or distance parameters. In at least one embodiment, the AEB system may use a front-facing camera and / or RADAR sensor 2660 coupled to a dedicated processor, DSP, FPGA, and / or ASIC. In at least one embodiment, when the AEB system detects a hazard, the AEB system typically first advises the driver to take corrective action to avoid the collision, and if the driver does not take corrective action, the AEB system may automatically apply the brakes to prevent or at least mitigate the severity of the predicted collision. In at least one embodiment, the AEB system may include techniques such as dynamic brake support and / or pre-collision braking.

[0191] In at least one embodiment, the LDW system provides visual, audible, and / or tactile warnings, such as vibration of the steering wheel or seat, to advise the driver when the vehicle 2600 crosses a lane marker. In at least one embodiment, the LDW system does not engage if the driver indicates an intentional lane departure by activating a turn signal. In at least one embodiment, the LDW system may use a front-facing camera coupled to a dedicated processor, DSP, FPGA, and / or ASIC that can be electrically coupled to feedback to the driver, such as a display, speaker, and / or vibration components. In at least one embodiment, the LKA system is a variation of the LDW system. The LKA system provides steering input or braking control to correct the vehicle 2600 if the vehicle 2600 begins to drift out of its lane.

[0192] In at least one embodiment, the BSW system detects vehicles in the vehicle's blind spot and warns the driver. In at least one embodiment, the BSW system may provide visual, audible, and / or haptic alerts to indicate that merging or changing lanes is unsafe. In at least one embodiment, the BSW system may provide an additional warning when the driver uses a turn signal. In at least one embodiment, the BSW system may use a rearview camera and / or RADAR sensor 2660 coupled to dedicated processors, DSPs, FPGAs, and / or ASICs, which are electrically coupled to feedback to the driver, such as a display, speaker, and / or vibration components.

[0193] In at least one embodiment, the RCTW system may provide visual, audible, and / or tactile notifications when an object is detected outside the range of the rear camera when reversing the vehicle 2600. In at least one embodiment, the RCTW system includes an AEB system to ensure vehicle braking is applied to avoid a collision. In at least one embodiment, the RCTW system may use one or more rear RADAR sensors 2660 coupled to a dedicated processor, DSP, FPGA, and / or ASIC electrically coupled to feedback to the driver, such as a display, speaker, and / or vibration components.

[0194] In at least one embodiment, conventional ADAS systems may be prone to false positive results, which can be annoying and distracting to the driver, but are typically not a major concern because conventional ADAS systems advise the driver and allow the driver to determine whether a safety condition truly exists and respond accordingly. In at least one embodiment, in the event of conflicting results, the vehicle 2600 itself determines whether to follow the results from the primary computer (e.g., first controller 2636) or the secondary computer (e.g., second controller 2636). For example, in at least one embodiment, the ADAS system 2638 may be a backup and / or secondary computer to provide perception information to a backup computer rationality module. In at least one embodiment, the backup computer rationality monitor may run redundant software on various hardware components to detect perception errors and dynamic driving tasks. In at least one embodiment, output from the ADAS system 2638 may be provided to a supervisory MCU. In at least one embodiment, if the output from the primary computer and the output from the secondary computer conflict, the supervisory MCU determines how to reconcile the conflict to ensure safe operation.

[0195] In at least one embodiment, the primary computer may be configured to provide the monitor MCU with a reliability score indicating the reliability of the primary computer's selected result. In at least one embodiment, if the reliability score exceeds a threshold, the monitor MCU may follow the primary computer's instructions regardless of whether the secondary computers are providing conflicting or inconsistent results. In at least one embodiment, if the reliability score does not meet the threshold and the primary and secondary computers provide different (e.g., conflicting) results, the monitor MCU may arbitrate between the computers to determine the appropriate result.

[0196] In at least one embodiment, the monitoring MCU may be configured to execute a neural network trained and configured to determine conditions under which the secondary computer will provide a false alarm based at least in part on outputs from the primary and secondary computers. In at least one embodiment, the monitoring MCU's neural network may learn when the secondary computer's output may be trusted and when it may not be trusted. For example, in at least one embodiment, if the secondary computer is a RADAR-based FCW system, the monitoring MCU's neural network may learn when the FCW system identifies a metal object that is not actually a hazard, such as a drain grate or manhole cover, which triggers an alarm. In at least one embodiment, if the secondary computer is a camera-based LDW system, the monitoring MCU's neural network may learn to disable LDW when a bicyclist or pedestrian is present and lane departure is actually the safest maneuver. In at least one embodiment, the monitoring MCU may include at least one of a DLA or a GPU suitable for executing the neural network along with associated memory. In at least one embodiment, the supervisory MCU may comprise and / or be included as a component of the SoC2604.

[0197] In at least one embodiment, the ADAS system 2638 may include a secondary computer that performs ADAS functions using traditional rules of computer vision. In at least one embodiment, the secondary computer may use traditional computer vision rules (if-then rules), and neural networks may reside in the supervisory MCU, improving reliability, safety, and performance. For example, in at least one embodiment, diverse implementations and intentional non-identity may increase the overall system's error tolerance, particularly against errors caused by software (or software-hardware interface) functionality. For example, in at least one embodiment, if there is a bug or error in the software running on the primary computer and non-identical software code running on the secondary computer provides the same overall result, the supervisory MCU may have greater confidence that the overall result is correct and that a software or hardware bug on the primary computer did not cause a critical error.

[0198] In at least one embodiment, the output of the ADAS system 2638 may be provided to a perception block of the primary computer and / or a dynamic driving task block of the primary computer. For example, in at least one embodiment, if the ADAS system 2638 indicates a frontal collision warning due to an immediately preceding object, the perception block may use this information when identifying the object. In at least one embodiment, the secondary computer may have its own neural network pre-trained, as described herein, thus reducing the risk of false positives.

[0199] In at least one embodiment, vehicle 2600 may further include an infotainment SoC 2630 (e.g., an in-vehicle infotainment system (IVI)). While infotainment system 2630 is shown and described as an SoC, in at least one embodiment, it may not be an SoC and may include, without limitation, two or more separate components. In at least one embodiment, infotainment SoC 2630 may include, without limitation, a combination of hardware and software that may be used to provide audio (e.g., music, personal digital assistant, navigation instructions, news, radio, etc.), video (e.g., TV, movies, streaming, etc.), telephony (e.g., hands-free calling), network connectivity (e.g., LTE, Wi-Fi, etc.), and / or information services (e.g., navigation system, rear park assist, wireless data system, vehicle-related information such as fuel level, total mileage, brake fuel level, oil level, door opening / closing, air filter information, etc.) to vehicle 2600. For example, infotainment SoC2630 may include a radio, a disc player, a navigation system, a video player, USB and Bluetooth® connectivity, a car computer, in-car entertainment, Wi-Fi, steering wheel audio controls, hands-free voice control, a heads-up display (“HUD”), an HMI display 2634, telematics devices, a control panel (e.g., for controlling and / or interacting with various components, features, and / or systems), and / or other components. In at least one embodiment, infotainment SoC2630 may also be used to provide information (e.g., visual and / or auditory) to a user of the vehicle, such as information from an ADAS system 2638, autonomous driving information such as a vehicle maneuver plan, a trajectory, surrounding environment information (e.g., intersection information, vehicle information, road information, etc.), and / or other information.

[0200] In at least one embodiment, infotainment SoC 2630 may include any amount and type of GPU functionality. In at least one embodiment, infotainment SoC 2630 may communicate with other devices, systems, and / or components of vehicle 2600 via bus 2602 (e.g., CAN bus, Ethernet, etc.). In at least one embodiment, infotainment SoC 2630 may be coupled to a supervisory MCU such that the infotainment system's GPU may perform some self-driving functions when primary controller 2636 (e.g., vehicle's 2600 primary and / or backup computer) fails. In at least one embodiment, infotainment SoC 2630 may place vehicle 2600 in a driver-safety shutdown mode, as described herein.

[0201] In at least one embodiment, the vehicle 2600 may further include an instrument cluster 2632 (e.g., a digital dashboard, an electronic instrument cluster, a digital instrument panel, etc.). The instrument cluster 2632 may include, without limitation, a controller and / or a supercomputer (e.g., a separate controller or supercomputer). In at least one embodiment, the instrument cluster 2632 may include any number and combination of instrument sets, such as, without limitation, a speedometer, fuel level, oil pressure, a tachometer, an odometer, turn signals, a shift lever position indicator, a seat belt warning light, a parking brake warning light, an engine malfunction light, supplemental restraint system (e.g., airbag) information, light control, safety system control, navigation information, etc. In some instances, information may be displayed and / or shared between the infotainment SoC 2630 and the instrument cluster 2632. In at least one embodiment, the instrument cluster 2632 may be included as part of the infotainment SoC 2630, or vice versa.

[0202] Inference and / or training logic 2315 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 2315 are provided herein in conjunction with FIG. 23A and / or FIG. 23B . In at least one embodiment, inference and / or training logic 2315 may be used in the system of FIG. 26C for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein. In at least one embodiment, a robotic grasping system may use the training and inference hardware described above to control a haptic hand.

[0203] 26D is a diagram of a system 2676 for communicating between a cloud-based server and the autonomous vehicle 2600 of FIG. 26A , according to at least one embodiment. In at least one embodiment, the system 2676 may include any number and type of vehicles, including, without limitation, a server 2678, a network 2690, and a vehicle 2600. The server 2678 may include, without limitation, multiple GPUs 2684(A)-2684(H) (collectively referred to herein as GPUs 2684), PCIe switches 2682(A)-2682(H) (collectively referred to herein as PCIe switches 2682), and / or CPUs 2680(A)-2680(B) (collectively referred to herein as CPUs 2680). The GPUs 2684, CPUs 2680, and PCIe switches 2682 may be interconnected by a high-speed interconnect, such as, for example, without limitation, an NVLink interface 2688 developed by NVIDIA, and / or a PCIe connection 2686. In at least one embodiment, the GPUs 2684 are connected to each other via an NVLink and / or an NVSwitch SoC, and the GPUs 2684 and PCIe switches 2682 are connected via a PCIe interconnect. In at least one embodiment, eight GPUs 2684, two CPUs 2680, and four PCIe switches 2682 are illustrated, but this is not intended to be limiting. In at least one embodiment, each of the servers 2678 may include any number of GPUs 2684, CPUs 2680, and / or PCIe switches 2682 in any combination, without limitation. For example, in at least one embodiment, the servers 2678 may each include 8, 16, 32, and / or more GPUs 2684.

[0204] In at least one embodiment, server 2678 may receive image data from the vehicle over network 2690 representing images showing unexpected or changed road conditions, such as recently begun road construction. In at least one embodiment, server 2678 may transmit neural network 2692, updated neural network 2692, and / or map information 2694, including, without limitation, information regarding traffic and road conditions, to the vehicle over network 2690. In at least one embodiment, updates to map information 2694 may include, without limitation, updates to HD map 2622, such as information regarding construction sites, potholes, detours, flooding, and / or other obstacles. In at least one embodiment, neural network 2692, updated neural network 2692, and / or map information 2694 may be derived from new training and / or experience represented in data received from any number of vehicles in the environment and / or may be derived based at least in part on training performed at a data center (e.g., using server 2678 and / or other servers).

[0205] In at least one embodiment, server 2678 may be used to train a machine learning model (e.g., a neural network) based at least in part on the training data. The training data may be generated by the vehicle and / or generated in a simulation (e.g., using a game engine). In at least one embodiment, any amount of the training data may be tagged and / or otherwise preprocessed (e.g., if the associated neural network benefits from supervised learning). In at least one embodiment, any amount of the training data may not be tagged and / or preprocessed (e.g., if the associated neural network does not require supervised learning). In at least one embodiment, once the machine learning model is trained, it may be used by the vehicle (e.g., transmitted to the vehicle via network 2690 and / or used by server 2678 to remotely monitor the vehicle).

[0206] In at least one embodiment, server 2678 may receive data from vehicles and apply the data to state-of-the-art, real-time neural networks to enable real-time intelligent inference. In at least one embodiment, server 2678 may include a deep learning supercomputer and / or special-purpose AI computer powered by a GPU 2684, such as the DGX and DGX Station machines developed by NVIDIA. However, in at least one embodiment, server 2678 may also include a deep learning infrastructure using a CPU-powered data center.

[0207] In at least one embodiment, the deep learning infrastructure of server 2678 may be capable of rapid real-time inference and may use that capability to assess and verify the health of the processor, software, and / or associated hardware of vehicle 2600. For example, in at least one embodiment, the deep learning infrastructure may receive periodic updates from vehicle 2600, such as a series of images and / or objects that vehicle 2600 has located in the series of images (e.g., via computer vision and / or other machine learning object classification techniques). In at least one embodiment, the deep learning infrastructure may run its own neural network to identify objects and compare them to those identified by vehicle 2600; if the results do not match and the deep learning infrastructure concludes that the AI ​​of vehicle 2600 has failed, server 2678 may send a signal to vehicle 2600 instructing the fail-safe computer of vehicle 2600 to take control, notify the occupants, and complete a safe stopping maneuver.

[0208] In at least one embodiment, server 2678 may include a GPU 2684 and one or more programmable inference accelerators (e.g., NVIDIA's TensorRT3). In at least one embodiment, the combination of a GPU-powered server and inference acceleration can enable real-time response. In at least one embodiment, CPU, FPGA, and other processor-powered servers may be used for inference, such as when performance is less critical. In at least one embodiment, a hardware structure 2315 is used to execute one or more embodiments. Details regarding hardware structure 2315 are provided herein in conjunction with FIG. 23A and / or FIG. 23B.

[0209] Computer Systems FIG. 27 is a block diagram illustrating an exemplary computer system, which may be a system having interconnected devices and components formed with a processor that may include an execution unit for executing instructions, a system-on-a-chip ("SoC"), or some combination thereof 2700, according to at least one embodiment. In at least one embodiment, computer system 2700 may include components such as, without limitation, a processor 2702 for using an execution unit that includes logic for executing algorithms for processing data in accordance with the present disclosure, such as in the embodiments described herein. In at least one embodiment, computer system 2700 may include a processor such as the PENTIUM® processor family, Xeon™, Itanium®, XScale™ and / or StrongARM™, Intel® Core™, or Intel® Nervana™ microprocessors available from Intel Corporation of Santa Clara, California, although other systems may be used (including PCs with other microprocessors, engineering workstations, set-top boxes, etc.). In at least one embodiment, computer system 2700 may run a version of the WINDOWS® operating system available from Microsoft Corporation of Redmond, Washington, although other operating systems (e.g., UNIX® and Linux®), embedded software, and / or graphical user interfaces may also be used.

[0210] Embodiments may be used in other devices, such as portable devices and embedded applications. Some examples of portable devices include cellular phones, Internet Protocol devices, digital cameras, personal digital assistants ("PDAs"), and portable PCs. In at least one embodiment, embedded applications may include microcontrollers, digital signal processors ("DSPs"), systems-on-chips, network computers ("NetPCs"), set-top boxes, network hubs, wide area network ("WAN") switches, or any other system capable of executing one or more instructions according to at least one embodiment.

[0211] In at least one embodiment, computer system 2700 may include, without limitation, a processor 2702, which may include one or more execution units 2708 for performing machine learning model training and / or inference according to the techniques described herein. In at least one embodiment, system 2700 is a single-processor desktop or server system, while in other embodiments, system 2700 may be a multiprocessor system. In at least one embodiment, processor 2702 may include, without limitation, a complex instruction set computer ("CISC") microprocessor, a reduced instruction set computing ("RISC") microprocessor, a very long instruction word ("VLIW") microprocessor, a processor implementing a combination of instruction sets, or any other processor device, such as a digital signal processor. In at least one embodiment, processor 2702 may be coupled to a processor bus 2710, which may transmit digital signals between processor 2702 and other components within computer system 2700.

[0212] In at least one embodiment, processor 2702 may include, without limitation, level 1 ("L1") internal cache memory ("cache") 2704. In at least one embodiment, processor 2702 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, cache memory may be external to processor 2702. Other embodiments may include a combination of both internal and external cache, depending on the particular implementation and needs. In at least one embodiment, register file 2706 may store different types of data in various registers, including, without limitation, integer registers, floating-point registers, status registers, and an instruction pointer register.

[0213] In at least one embodiment, processor 2702 also includes an execution unit 2708, including, without limitation, logic for performing integer and floating-point operations. Processor 2702 may also include microcode (“u-code”) read-only memory (“ROM”) that stores microcode for certain macroinstructions. In at least one embodiment, execution unit 2708 may include logic for a packed instruction set 2709. In at least one embodiment, including the packed instruction set 2709, along with associated circuitry for executing the instructions, in the instruction set of general-purpose processor 2702 allows operations used by many multimedia applications to be performed using packed data in general-purpose processor 2702. In one or more embodiments, many multimedia applications can be accelerated and run more efficiently by performing operations on packed data using the full width of the processor's data bus, thereby eliminating the need to transfer smaller units of data between the processor's data bus to perform one or more operations on one data element at a time.

[0214] In at least one embodiment, execution unit 2708 may also be used in microcontrollers, embedded processors, graphics devices, DSPs, and other types of logic circuits. In at least one embodiment, computer system 2700 may include, without limitation, memory 2720. In at least one embodiment, memory 2720 may be implemented as a dynamic random access memory ("DRAM") device, a static random access memory ("SRAM") device, a flash memory device, or other memory device. Memory 2720 may store instructions 2719 and / or data 2721 represented by data signals that may be executed by processor 2702.

[0215] In at least one embodiment, a system logic chip may be coupled to the processor bus 2710 and the memory 2720. In at least one embodiment, the system logic chip may include, without limitation, a memory controller hub (“MCH”) 2716, and the processor 2702 may communicate with the MCH 2716 via the processor bus 2710. In at least one embodiment, the MCH 2716 may provide a high-bandwidth memory path 2718 to the memory 2720 for storing instructions and data, and for storing graphics commands, data, and textures. In at least one embodiment, the MCH 2716 may route data signals between the processor 2702, the memory 2720, and other components of the computer system 2700, and may bridge data signals between the processor bus 2710, the memory 2720, and the system I / O 2722. In at least one embodiment, the system logic chip may provide a graphics port for coupling to a graphics controller. In at least one embodiment, MCH 2716 may be coupled to memory 2720 via a high-bandwidth memory path 2718, and graphics / video card 2712 may be coupled to MCH 2716 via an Accelerated Graphics Port (“AGP”) interconnect 2714.

[0216] In at least one embodiment, computer system 2700 may use system I / O 2722, a proprietary hub interface bus, to couple MCH 2716 to I / O controller hub (“ICH”) 2730. In at least one embodiment, ICH 2730 may provide direct connectivity to several I / O devices via a local I / O bus. In at least one embodiment, the local I / O bus may include, without limitation, a high-speed I / O bus for connecting peripherals to memory 2720, a chipset, and processor 2702. Examples may include, without limitation, an audio controller 2729, a firmware hub ("flash BIOS") 2728, a wireless transceiver 2726, data storage 2724, a legacy I / O controller 2723 including user input and keyboard interfaces, a serial expansion port 2727 such as a Universal Serial Bus ("USB"), and a network controller 2734. Data storage 2724 may comprise a hard disk drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device.

[0217] In at least one embodiment, Figure 27 illustrates a system including interconnected hardware devices or "chips," while in other embodiments, Figure 27 may illustrate an exemplary system-on-a-chip ("SoC"). In at least one embodiment, the devices illustrated in Figure 27 may be interconnected using a proprietary interconnect, a standard interconnect (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of system 2700 may be interconnected using a compute express link (CXL) interconnect.

[0218] Inference and / or training logic 2315 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 2315 are provided herein in conjunction with FIG. 23A and / or FIG. 23B . In at least one embodiment, inference and / or training logic 2315 may be used in the system of FIG. 27 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein. In at least one embodiment, a robotic grasping system may use computer system components such as those described above to control a tactile hand.

[0219] 28 is a block diagram illustrating an electronic device 2800 for utilizing a processor 2810, according to at least one embodiment. In at least one embodiment, electronic device 2800 may be, for example, without limitation, a notebook, a tower server, a rack server, a blade server, a laptop, a desktop, a tablet, a mobile device, a phone, an embedded computer, or any other suitable electronic device.

[0220] In at least one embodiment, system 2800 may include a processor 2810 communicatively coupled to any suitable number or type of components, peripherals, modules, or devices, including, without limitation, processor 2810 coupled using a bus or interface, such as a 1°C bus, a System Management Bus (“SMBus”), a Low Pin Count (“LPC”) bus, a Serial Peripheral Interface (“SPI”), a High Definition Audio (“HDA”) bus, a Serial Advance Technology Attachment (“SATA”) bus, a Universal Serial Bus (“USB”) (versions 1, 2, and 3), or a Universal Asynchronous Receiver / Transmitter (“UART”) bus. In at least one embodiment, FIG. 28 illustrates a system including interconnected hardware devices or "chips," while in other embodiments, FIG. 28 may illustrate an exemplary system-on-a-chip ("SoC"). In at least one embodiment, the devices illustrated in FIG. 28 may be interconnected using a proprietary interconnect, a standard interconnect (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of FIG. 28 may be interconnected using a compute express link (CXL) interconnect.

[0221] In at least one embodiment, FIG. 28 illustrates a display 2824, a touch screen 2825, a touch pad 2830, a Near Field Communications unit ("NFC") 2845, a sensor hub 2840, a thermal sensor 2846, an Express Chipset ("EC") 2835, a Trusted Platform Module ("TPM") 2838, a BIOS / firmware / flash memory ("BIOS,FW flash") 2822, a DSP 2860, a drive ("SSD or HDD") 2820, such as a solid state disk ("SSD") or hard disk drive ("HDD"), a wireless local area network unit ("WLAN"), and a wireless local area network ("WLAN") 2840. The memory may include a wireless LAN unit ("LAN unit") 2850, a Bluetooth® unit 2852, a Wireless Wide Area Network unit ("WWAN") 2856, a Global Positioning System (GPS) 2855, a camera such as a USB 3.0 camera ("USB 3.0 camera") 2854, or a Low Power Double Data Rate ("LPDDR") memory unit ("LPDDR3") 2815, implemented, for example, to the LPDDR3 standard. Each of these components may be implemented in any suitable manner.

[0222] In at least one embodiment, other components may be communicatively coupled to processor 2810 via the components described above. In at least one embodiment, accelerometer 2841, ambient light sensor (“ALS”) 2842, compass 2843, and gyroscope 2844 may be communicatively coupled to sensor hub 2840. In at least one embodiment, thermal sensor 2839, fan 2837, keyboard 2846, and touchpad 2830 may be communicatively coupled to EC 2835. In at least one embodiment, speaker 2863, headphones 2864, and microphone (“mic”) 2865 may be communicatively coupled to audio unit (audio codec and class D amplifier) ​​2864, which may be communicatively coupled to DSP 2860. In at least one embodiment, audio unit 2864 may include, for example, without limitation, an audio coder / decoder (“codec”) and a class D amplifier. In at least one embodiment, a SIM card (“SIM”) 2857 may be communicatively coupled to the WWAN unit 2856. In at least one embodiment, components such as the WLAN unit 2850 and Bluetooth® unit 2852, and the WWAN unit 2856 may be implemented in a Next Generation Form Factor (“NGFF”).

[0223] Inference and / or training logic 2315 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 2315 are provided herein in conjunction with FIG. 23A and / or FIG. 23B . In at least one embodiment, inference and / or training logic 2315 may be used in the system of FIG. 28 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein. In at least one embodiment, a robotic grasping system may use computer system components such as those described above to control a tactile hand.

[0224] 29 illustrates a computer system 2900 according to at least one embodiment. In at least one embodiment, the computer system 2900 is configured to implement the various processes and methods described throughout this disclosure.

[0225] In at least one embodiment, computer system 2900 includes at least one central processing unit ("CPU") 2902 connected to a communication bus 2910 implemented using any suitable protocol, such as, without limitation, PCI (Peripheral Component Interconnect), Peripheral Component Interconnect Express ("PCI-Express"), AGP (Accelerated Graphics Port), HyperTransport, or any other bus or point-to-point communication protocol. In at least one embodiment, computer system 2900 includes main memory 2904 and control logic (e.g., implemented as hardware, software, or a combination thereof), and data is stored in main memory 2904, which may be in the form of random access memory ("RAM"). In at least one embodiment, network interface subsystem (“network interface”) 2922 provides an interface with other computing devices and networks to receive data from other systems and transmit data from computer system 2900 to other systems.

[0226] In at least one embodiment, computer system 2900 includes, without limitation, input device(s) 2908, a parallel processing system 2912, and a display device 2906, which may be implemented using a conventional cathode ray tube ("CRT"), liquid crystal display ("LCD"), light emitting diode ("LED"), plasma display, or other suitable display technology. In at least one embodiment, user input is received from input device(s) 2908, such as a keyboard, mouse, touch pad, microphone, or the like. In at least one embodiment, each of the above modules may be located on a single semiconductor platform to form a processing system.

[0227] Inference and / or training logic 2315 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 2315 are provided herein in conjunction with FIG. 23A and / or FIG. 23B . In at least one embodiment, inference and / or training logic 2315 may be used in the system of FIG. 29 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein. In at least one embodiment, a robotic grasping system may use a computer system such as described above to control a haptic hand.

[0228] 30 illustrates a computer system 3000 according to at least one embodiment. In at least one embodiment, computer system 3000 may include, without limitation, a computer 3010 and a USB stick 3020. In at least one embodiment, computer 3010 may include, without limitation, any number and type of processor (not shown) and memory (not shown). In at least one embodiment, computer 3010 includes, without limitation, a server, a cloud instance, a laptop, and a desktop computer.

[0229] In at least one embodiment, the USB stick 3020 includes, without limitation, a processing unit 3030, a USB interface 3040, and USB interface logic 3050. In at least one embodiment, the processing unit 3030 may be any instruction execution system, apparatus, or device capable of executing instructions. In at least one embodiment, the processing unit 3030 may include, without limitation, any number and types of processing cores (not shown). In at least one embodiment, the processing cores 3030 comprise application specific integrated circuits ("ASICs") optimized to perform any quantity and type of operations related to machine learning. For example, in at least one embodiment, the processing cores 3030 are tensor processing units ("TPCs") optimized to perform machine learning inference operations. In at least one embodiment, the processing cores 3030 are vision processing units ("VPUs") optimized to perform machine vision and machine learning inference operations.

[0230] In at least one embodiment, USB interface 3040 may be any type of USB connector or socket. For example, in at least one embodiment, USB interface 3040 is a USB 3.0 Type-C socket for data and power. In at least one embodiment, USB interface 3040 is a USB 3.0 Type-A connector. In at least one embodiment, USB interface logic 3050 may include any amount and type of logic that enables processing unit 3030 to interface with a device (e.g., computer 3010) via USB connector 3040.

[0231] Inference and / or training logic 2315 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 2315 are provided herein in conjunction with FIG. 23A and / or FIG. 23B. In at least one embodiment, inference and / or training logic 2315 may be used in the system of FIG. 30 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein. In at least one embodiment, the robotic grasping system may use a multi-core processor, such as described above, to control a haptic hand.

[0232] 31A illustrates an exemplary architecture in which multiple GPUs 3110-3113 are communicatively coupled to multiple multi-core processors 3105-3106 via high-speed links 3140-3143 (e.g., buses, point-to-point interconnects, etc.). In one embodiment, the high-speed links 3140-3143 support communication throughput of 4 GB / s, 30 GB / s, 80 GB / s, or more. Various interconnect protocols may be used, including, but not limited to, PCIe 4.0 or 5.0 and NVLink 2.0.

[0233] Additionally, in one embodiment, two or more of GPUs 3110-3113 may be interconnected via high-speed links 3129-3130, which may be implemented using the same or different protocol / links as used for high-speed links 3140-3143. Similarly, two or more of multi-core processors 3105-3106 may be connected via high-speed link 3128, which may be a symmetric multi-processor (SMP) bus operating at 20 GB / s, 30 GB / s, 120 GB / s, or more. Alternatively, all communications between the various system components shown in FIG. 31A may be achieved using the same protocol / links (e.g., via a common interconnect fabric).

[0234] In one embodiment, each multi-core processor 3105-3106 is communicatively coupled to processor memory 3101-3102 via memory interconnects 3126-3127, respectively, and each GPU 3110-3113 is communicatively coupled to GPU memory 3120-3123 via GPU memory interconnects 3150-3153, respectively. Memory interconnects 3126-3127 and 3150-3153 may utilize the same or different memory access technologies. By way of example, and not limitation, processor memory 3101-3102 and GPU memory 3120-3123 may be volatile memory such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high-bandwidth memory (HBM), and / or may be non-volatile memory such as 3D XPoint or Nano-RAM. In one embodiment, some portions of processor memory 3101-3102 may be volatile memory and other portions may be non-volatile memory (e.g., using a two-level memory (2LM) hierarchy).

[0235] As described herein, the various processors 3105-3106 and GPUs 3110-3113 may each be physically coupled to a particular memory 3101-3102, 3120-3123, but a unified memory architecture may be implemented in which the same virtual system address space (also referred to as the "effective address" space) is distributed among the various physical memories. For example, the processor memories 3101-3102 may each have 64 GB of system memory address space, and the GPU memories 3120-3123 may each have 32 GB of system memory address space (resulting in a total of 256 GB of addressable memory in this example).

[0236] 31B shows further details of the interconnection between multi-core processor 3107 and graphics acceleration module 3146 according to one example embodiment. Graphics acceleration module 3146 may include one or more GPU chips integrated on a line card that is coupled to processor 3107 via high-speed link 3140. Alternatively, graphics acceleration module 3146 may be integrated in the same package or chip as processor 3107.

[0237] In at least one embodiment, the illustrated processor 3107 includes multiple cores 3160A-3160D, each having a translation lookaside buffer 3161A-3161D and one or more caches 3162A-3162D. In at least one embodiment, the cores 3160A-3160D may include various other components, not shown, for executing instructions and processing data. The caches 3162A-3162D may comprise level 1 (L1) and level 2 (L2) caches. Additionally, one or more shared caches 3156 may be included in the caches 3162A-3162D and shared by the set of cores 3160A-3160D. For example, one embodiment of the processor 3107 includes 24 cores, each with its own L1 cache, 12 shared L2 caches, and 12 shared L3 caches. In this embodiment, one or more L2 and L3 caches are shared by two adjacent cores. The processor 3107 and graphics acceleration module 3146 are connected to system memory 3114, which may include processor memories 3101-3102 of FIG. 31A.

[0238] Coherence is maintained for data and instructions stored in the various caches 3162A-3162D, 3156, and system memory 3114 through inter-core communication via coherence bus 3164. For example, each cache may have associated cache coherence logic / circuitry for communicating via coherence bus 3164 in response to detecting a read or write to a particular cache line. In one implementation, a cache snooping protocol is implemented via coherence bus 3164 to monitor cache accesses.

[0239] In one embodiment, proxy circuit 3125 communicatively couples graphics acceleration module 3146 to coherence bus 3164 to enable graphics acceleration module 3146 to participate in cache coherence protocols as a peer of cores 3160A-3160D. In particular, interface 3135 provides a connection to proxy circuit 3125 over high-speed link 3140 (e.g., PCIe bus, NVLink, etc.), and interface 3137 connects graphics acceleration module 3146 to link 3140.

[0240] In one implementation, the accelerator integrated circuit 3136 provides cache management, memory access, content management, and interrupt management services on behalf of the multiple graphics processing engines 3131, 3132, N of the graphics acceleration module 3146. The graphics processing engines 3131, 3132, N may each comprise a separate graphics processing unit (GPU). Alternatively, the graphics processing engines 3131, 3132, N may comprise different types of graphics processing engines within a GPU, such as a graphics execution unit, a media processing engine (e.g., a video encoder / decoder), a sampler, and a blit engine. In at least one embodiment, the graphics acceleration module 3146 may be a GPU having multiple graphics processing engines 3131-3132, N, or the graphics processing engines 3131-3132, N may be individual GPUs integrated into a common package, line card, or chip.

[0241] In one embodiment, the accelerator integrated circuitry 3136 includes a memory management unit (MMU) 3139 for performing various memory management functions, such as virtual-to-physical memory translation (also referred to as effective-to-real memory translation), and a memory access protocol for accessing the system memory 3114. The MMU 3139 may also include a translation lookaside buffer (TLB) (not shown) for caching virtual / effective to physical / real address translations. In one implementation, the cache 3138 stores commands and data for efficient access by the graphics processing engines 3131-3132, N. In one embodiment, data stored in the cache 3138 and the graphics memory 3133-3134, M is kept coherent with the core caches 3162A-3162D, 3156, and the system memory 3114. As noted above, this may be achieved via proxy circuit 3125 on behalf of cache 3138 and memory 3133-3134, M (e.g., sending updates regarding modifications / accesses of cache lines in processor caches 3162A-3162D, 3156 to cache 3138 and receiving updates from cache 3138).

[0242] A set of registers 3145 stores context data for threads executed by the graphics processing engines 3131-3132, N, and a context management circuit 3148 manages thread contexts. For example, the context management circuit 3148 may perform save and restore operations to save and restore the context of various threads during a context switch (e.g., where a first thread is saved and a second thread is saved so that the second thread can be executed by the graphics processing engine). For example, during a context switch, the context management circuit 3148 may store current register values ​​in a designated area of ​​memory (e.g., identified by a context pointer). Then, when returning to the context, the context management circuit 3148 may restore the register values. In one embodiment, the interrupt management circuit 3147 receives and processes interrupts received from system devices.

[0243] In one implementation, virtual / effective addresses from the graphics processing engine 3131 are translated to real / physical addresses in the system memory 3114 by the MMU 3139. One embodiment of the accelerator integration circuit 3136 supports multiple (e.g., four, eight, or sixteen) graphics accelerator modules 3146 and / or other accelerator devices. The graphics accelerator modules 3146 may be dedicated to a single application running on the processor 3107 or may be shared among multiple applications. In one embodiment, a virtualized graphics execution environment exists in which the resources of the graphics processing engines 3131-3132, N, are shared with multiple applications or virtual machines (VMs). In at least one embodiment, resources may be subdivided into "slices," which are allocated to different VMs and / or applications based on processing requirements and priorities associated with the VMs and / or applications.

[0244] In at least one embodiment, the accelerator integration circuitry 3136 acts as a bridge to the system for the graphics acceleration module 3146, providing address translation and system memory caching services. Additionally, the accelerator integration circuitry 3136 may provide virtualization facilities for the host processor to manage virtualization, interrupts, and memory management for the graphics processing engines 3131-3132.

[0245] The hardware resources of the graphics processing engines 3131-3132, N are explicitly mapped into the real address space seen by the host processor 3107, so that any host processor can directly address these resources using effective address values. In one embodiment, one function of the accelerator integrated circuit 3136 is to physically separate the graphics processing engines 3131-3132, N so that they appear as independent units to the system.

[0246] In at least one embodiment, one or more graphics memories 3133-3134, M are respectively coupled to each of the graphics processing engines 3131-3132, N. The graphics memories 3133-3134, M store instructions and data that are processed by the respective graphics processing engines 3131-3132, N. The graphics memories 3133-3134, M may be volatile memory such as DRAM (including stacked DRAM), GDDR memory (e.g., GDDR5, GDDR6), or HBM, and / or may be non-volatile memory such as 3D XPoint or Nano-Ram.

[0247] In one embodiment, to reduce data traffic over link 3140, biasing techniques are used to ensure that the data stored in graphics memory 3133-3134, M is data that will be most frequently used by graphics processing engines 3131-3132, N, and preferably is data that is not used (or at least not frequently used) by cores 3160A-3160D. Similarly, the biasing mechanism attempts to keep data needed by the cores (and therefore preferably not needed by graphics processing engines 3131-3132, N) in the cores' caches 3162A-3162D, 3156, and system memory 3114.

[0248] FIG. 31C shows another exemplary embodiment in which the accelerator integration circuitry 3136 is integrated within the processor 3107. In at least this embodiment, the graphics processing engines 3131-3132, N communicate directly with the accelerator integration circuitry 3136 via high-speed link 3140 via interface 3137 and interface 3135 (again, any form of bus or interface protocol can be utilized). The accelerator integration circuitry 3136 may perform the same operations as described with respect to FIG. 31B, but may potentially operate at a higher throughput given its proximity to the coherence bus 3164 and caches 3162A-3162D, 3156. One embodiment supports different programming models, including a dedicated process programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization), which may include a programming model controlled by the accelerator integration circuitry 3136 and a programming model controlled by the graphics acceleration module 3146.

[0249] In at least one embodiment, graphics processing engines 3131-3132, N are dedicated to a single application or process under a single operating system. In at least one embodiment, a single application can funnel other application requests to graphics processing engines 3131-3132, N, achieving virtualization within a VM / partition.

[0250] In at least one embodiment, graphics processing engines 3131-3132, N may be shared by multiple VM / application partitions. In at least one embodiment, the sharing model may use a system hypervisor to virtualize graphics processing engines 3131-3132, N and allow access by each operating system. In a single-partition system without a hypervisor, graphics processing engines 3131-3132, N are owned by the operating system. In at least one embodiment, the operating system may virtualize graphics processing engines 3131-3132, N and provide access to each process or application.

[0251] In at least one embodiment, the graphics acceleration module 3146 or the individual graphics processing engines 3131-3132,N selects a process element using a process handle. In at least one embodiment, the process element is stored in system memory 3114 and is addressable using the effective address to real address translation techniques described herein. In at least one embodiment, the process handle may be an implementation-specific value provided to a host process when registering the host process's context with the graphics processing engines 3131-3132,N (i.e., calling system software to add the process element to the process element linked list). In at least one embodiment, the low-order 16 bits of the process handle may be the offset of the process element within the process element linked list.

[0252] FIG. 31D illustrates an exemplary accelerator integration slice 3190. As used herein, a "slice" comprises a designated portion of the processing resources of the accelerator integration circuitry 3136. An application effective address space 3182 in system memory 3114 stores a process element 3183. In one embodiment, the process element 3183 is stored in response to a GPU call 3181 from an application 3180 running on the processor 3107. The process element 3183 contains the process state of the corresponding application 3180. A work descriptor (WD) 3184 contained in the process element 3183 can be a single job requested by the application or may contain a pointer to a queue of jobs. In at least one embodiment, the WD 3184 is a pointer to a job request queue in the application's address space 3182.

[0253] The graphics acceleration module 3146 and / or the individual graphics processing engines 3131-3132, N may be shared by all or a subset of the processes in the system. In at least one embodiment, infrastructure may be included for setting process state and sending WD 3184 to the graphics acceleration module 3146 to start a job in a virtualized environment.

[0254] In at least one embodiment, the dedicated process programming model is implementation specific, in which a single process owns the graphics acceleration module 3146 or an individual graphics processing engine 3131. Because the graphics acceleration module 3146 is owned by a single process, when the graphics acceleration module 3146 is allocated, the hypervisor initializes the accelerator integration circuitry 3136 for the owning partition, and the operating system initializes the accelerator integration circuitry 3136 for the owning process.

[0255] In operation, WD fetch unit 3191 in accelerator integrated slice 3190 fetches the next WD 3184, which contains an indication of work to be performed by one or more graphics processing engines of graphics acceleration module 3146. As shown, data from WD 3184 is stored in register 3145 and may be used by MMU 3139, interrupt management circuit 3147, and / or context management circuit 3148. For example, one embodiment of MMU 3139 includes segment / page walk circuitry for accessing segment / page table 3186 within OS virtual address space 3185. Interrupt management circuit 3147 may process interrupt events 3192 received from graphics acceleration module 3146. When performing graphics operations, effective addresses 3193 generated by graphics processing engines 3131-3132, N are translated to real addresses by MMU 3139.

[0256] In one embodiment, the same set of registers 3145 may be replicated for each graphics processing engine 3131-3132, N, and / or graphics acceleration module 3146 and initialized by the hypervisor or operating system. Each of these replicated registers may be included in the accelerator integration slice 3190. Exemplary registers that may be initialized by the hypervisor are shown in Table 1. [Table 2]

[0257] Exemplary registers that may be initialized by the operating system are shown in Table 2. [Table 3]

[0258] In one embodiment, each WD 3184 is specific to a particular graphics acceleration module 3146 and / or graphics processing engine 3131-3132, N. The WD 3184 contains all the information the graphics processing engine 3131-3132, N needs to do its work, or it can be a pointer to a memory location where the application has set up a command queue for work to be completed.

[0259] 31E shows further details of an exemplary embodiment of the sharing model. This embodiment includes a hypervisor real address space 3198 in which a process element list 3199 is stored. The hypervisor real address space 3198 is accessible through a hypervisor 3196 that virtualizes the graphics acceleration module engine of the operating system 3195.

[0260] In at least one embodiment, a shared programming model allows all or a subset of processes from all or a subset of partitions in a system to use the graphics acceleration module 3146. There are two programming models in which the graphics acceleration module 3146 is shared by multiple processes and partitions: timeslice shared and graphics-directed shared.

[0261] In this model, the system hypervisor 3196 owns the graphics acceleration module 3146 and makes its functions available to all operating systems 3195. In order for the graphics acceleration module 3146 to support virtualization by the system hypervisor 3196, the graphics acceleration module 3146 may comply with the following: 1) an application's job request must be autonomous (i.e., no state needs to be maintained between jobs) or the graphics acceleration module 3146 must provide a mechanism for saving and restoring context. 2) the application's job request must be guaranteed by the graphics acceleration module 3146 to complete in a specified amount of time, including any translation errors, or the graphics acceleration module 3146 must provide the ability to preempt job processing. 3) the graphics acceleration module 3146 must ensure fairness between processes when operating in a specified shared programming model.

[0262] In at least one embodiment, the application 3180 must make a system call to the operating system 3195 with a graphics acceleration module 3146 type, a work descriptor (WD), an authority mask register (AMR) value, and a context save / restore area pointer (CSRP). In at least one embodiment, the graphics acceleration module 3146 type describes the acceleration function targeted by the system call. In at least one embodiment, the graphics acceleration module 3146 type may be a system-specific value. In at least one embodiment, the WD is formatted specifically for the graphics acceleration module 3146 and may be in the form of a graphics acceleration module 3146 command, an effective address pointer to a user-defined structure, an effective address pointer to a queue of commands, or any other data structure for describing the work to be performed by the graphics acceleration module 3146. In one embodiment, the AMR value is the AMR state to use for the current process. In at least one embodiment, the value passed to the operating system is the same as the application setting the AMR. If the implementation of the accelerator integrated circuit 3136 and the graphics acceleration module 3146 does not support a User Permission Mask Override Register (UAMOR), the operating system may apply the current UAMOR value to the AMR value before passing the AMR to the hypervisor call. The hypervisor 3196 may optionally apply the current Permission Mask Override Register (AMOR) value before placing the AMR in the process element 3183. In at least one embodiment, the CSRP is one of the registers 3145 that contains the effective address of an area in the application's address space 3182 for the graphics acceleration module 3146 to save and restore context state. This pointer is optional if no state needs to be saved between jobs or when a job is preempted. In at least one embodiment, the context save / restore area may be pinned system memory.

[0263] Upon receiving the system call, the operating system 3195 may verify that the application 3180 is registered and authorized to use the graphics acceleration module 3146. The operating system 3195 then calls the hypervisor 3196 with the information shown in Table 3. [Table 4]

[0264] Upon receiving the hypervisor call, the hypervisor 3196 verifies that the operating system 3195 is registered and authorized to use the graphics acceleration module 3146. The hypervisor 3196 then places the process element 3183 into the process element linked list of the corresponding graphics acceleration module 3146 type. The process element may include the information shown in Table 4. [Table 5]

[0265] In at least one embodiment, the hypervisor initializes registers 3145 of multiple accelerator integrated slices 3190.

[0266] As shown in Figure 31F, at least one embodiment uses unified memory that is addressable via a common virtual memory address space used to access physical processor memories 3101-3102 and GPU memories 3120-3123. In this implementation, operations performed on GPUs 3110-3113 utilize the same virtual / effective memory address space as those used to access processor memories 3101-3102, and vice versa, thereby simplifying programmability. In one embodiment, a first portion of the virtual / effective address space is allocated to processor memory 3101, a second portion is allocated to second processor memory 3102, a third portion is allocated to GPU memory 3120, and so on. In at least one embodiment, the entire virtual / effective memory space (sometimes referred to as the effective address space) is thereby distributed across each of the processor memories 3101-3102 and GPU memories 3120-3123, allowing either processor or GPU to access either physical memory, with virtual addresses mapped to physical memory.

[0267] In one embodiment, bias / coherence management circuits 3194A-3194E in one or more of MMUs 3139A-3139E ensure cache coherence between the caches of one or more host processors (e.g., 3105) and the caches of GPUs 3110-3113 and implement biasing techniques to indicate the physical memory in which certain types of data should be stored. While multiple instances of bias / coherence management circuits 3194A-3194E are shown in FIG. 31F, the bias / coherence circuits may also be implemented within the MMUs of one or more host processors 3105 and / or within the accelerator integration circuit 3136.

[0268] One embodiment allows the GPU-associated memory 3120-3123 to be mapped as part of system memory and accessible using shared virtual memory (SVM) techniques, but without the performance penalty associated with full system cache coherence. In at least one embodiment, the GPU-associated memory 3120-3123 can be accessed as system memory without cumbersome cache coherence overhead, providing a beneficial operating environment for GPU offload. This configuration allows host processor 3105 software to set up operands and access computation results without the overhead of traditional I / O DMA data copies. These traditional copies require driver calls, interrupts, and memory-mapped I / O (MMIO) accesses, all of which are less efficient than simple memory accesses. In at least one embodiment, being able to access the GPU-associated memory 3120-3123 without cache coherence overhead can be crucial to the execution time of the offloaded computation. For example, in the presence of significant streaming write memory traffic, cache coherence overhead can significantly reduce the effective write bandwidth seen by the GPUs 3110-3113. In at least one embodiment, the efficiency of operand setup, the efficiency of result access, and the efficiency of GPU computation can be useful in determining the effectiveness of GPU offloading.

[0269] In at least one embodiment, the selection of the GPU bias and the host processor bias is determined by a bias tracker data structure. For example, a bias table may be used, which may be a page-granular structure containing one or two bits per GPU-attached memory page (i.e., controlled at memory page granularity). In at least one embodiment, the bias table may be implemented in a stolen memory range of one or more GPU-attached memories 3120-3123, with or without a bias cache in the GPUs 3110-3113 (e.g., for caching frequently / recently used entries of the bias table). Alternatively, the bias table may be maintained entirely within the GPU.

[0270] In at least one embodiment, the bias table entry associated with each access to GPU-biased memory 3120-3123 is accessed prior to the actual access to the GPU memory, resulting in the following actions: First, a local request from a GPU 3110-3113 that finds its page in the GPU bias is forwarded directly to the corresponding GPU memory 3120-3123. A local request from a GPU that finds its page in the host bias is forwarded to the processor 3105 (e.g., via the high-speed link described above). In one embodiment, a request from the processor 3105 that finds the requested page in the host processor bias completes the request similar to a normal memory read. Alternatively, a request directed to a GPU-biased page may be forwarded to the GPU 3110-3113. In at least one embodiment, the GPU may then migrate the page to the host processor bias if it is not currently using the page. In at least one embodiment, the bias state of a page can be changed by either a software-based mechanism, a hardware-assisted software-based mechanism, or for a limited set of cases, solely by a hardware-based mechanism.

[0271] One mechanism for changing the bias state utilizes an API call (e.g., OpenCL) that calls the GPU's device driver, which sends a message (or queues a command descriptor) to the GPU to change the bias state and, for some transitions, directs the GPU to perform a cache flushing operation in the host. In at least one embodiment, a cache flushing operation is used for transitions from host processor 3105 bias to GPU bias, but not for transitions in the opposite direction.

[0272] In one embodiment, cache coherence is maintained by temporarily rendering GPU-biased pages non-cacheable by the host processor 3105. To access these pages, the processor 3105 may request access from the GPU 3110, which may or may not immediately grant the access. Therefore, to reduce communication between the processor 3105 and the GPU 3110, it is beneficial for GPU-biased pages to be requested by the GPU but not by the host processor 3105, or vice versa.

[0273] To implement one or more embodiments, a hardware structure 2315 is used, details regarding the hardware structure 2315 are provided herein in conjunction with Figures 23A and / or 23B.

[0274] 32 illustrates an exemplary integrated circuit and associated graphics processor that can be fabricated using one or more IP cores according to various embodiments described herein. In addition to what is shown, in at least one embodiment, other logic and circuitry may be included, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0275] 32 is a block diagram illustrating an exemplary system-on-chip integrated circuit 3200 that can be fabricated using one or more IP cores according to at least one embodiment. In at least one embodiment, integrated circuit 3200 includes one or more application processors 3205 (e.g., CPUs), at least one graphics processor 3210, and may further include an image processor 3215 and / or a video processor 3220, any of which may be modular IP cores. In at least one embodiment, integrated circuit 3200 includes peripheral or bus logic including a USB controller 3225, a UART controller 3230, an SPI / SDIO controller 3235, and an I.sup.2S / I.sup.2C controller 3240. In at least one embodiment, integrated circuit 3200 may include a display device 3245 coupled to one or more of a high-definition multimedia interface (HDMI®) controller 3250 and a mobile industry processor interface (MIPI) display interface 3255. In at least one embodiment, storage may be provided by a flash memory subsystem 3260 including a flash memory and a flash memory controller. In at least one embodiment, a memory interface may be provided via memory controller 3265 to access an SDRAM or SRAM memory device. In at least one embodiment, some integrated circuits further include an embedded security engine 3270.

[0276] Inference and / or training logic 2315 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 2315 are provided herein in conjunction with FIG. 23A and / or FIG. 23B . In at least one embodiment, inference and / or training logic 2315 may be used in integrated circuit 3200 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein. In at least one embodiment, a robotic grasping system may use a graphics processor, such as described above, to control a haptic hand.

[0277] 33A-33B illustrate an exemplary integrated circuit and associated graphics processor that can be fabricated using one or more IP cores according to various embodiments described herein. In addition to what is shown, in at least one embodiment, other logic and circuitry may be included, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0278] 33A-33B are block diagrams illustrating exemplary graphics processors for use within an SoC according to embodiments described herein. FIG. 33A illustrates an exemplary graphics processor 3310 of a system-on-chip integrated circuit that can be fabricated using one or more IP cores according to at least one embodiment. FIG. 33B illustrates a further exemplary graphics processor 3340 of a system-on-chip integrated circuit that can be fabricated using one or more IP cores according to at least one embodiment. In at least one embodiment, graphics processor 3310 of FIG. 33A is a low-power graphics processor core. In at least one embodiment, graphics processor 3340 of FIG. 33B is a high-performance graphics processor core. In at least one embodiment, each of graphics processors 3310, 3340 can be a variation of graphics processor 3210 of FIG. 32.

[0279] In at least one embodiment, graphics processor 3310 includes a vertex processor 3305 and one or more fragment processors 3315A-3315N (e.g., 3315A, 3315B, 3315C, 3315D-3315N-1, and 3315N). In at least one embodiment, graphics processor 3310 can execute different shader programs through separate logic, such that vertex processor 3305 is optimized to perform operations for vertex shader programs, while one or more fragment processors 3315A-3315N perform fragment (e.g., pixel) shading operations for fragment or pixel shader programs. In at least one embodiment, vertex processor 3305 executes the vertex processing stage of the 3D graphics pipeline, generating primitive and vertex data. In at least one embodiment, fragment processors 3315A-3315N generate a frame buffer that is displayed on a display device using the primitive and vertex data generated by vertex processor 3305. In at least one embodiment, fragment processors 3315A-3315N are optimized to execute fragment shader programs provided in the OpenGL API, which may be used to perform operations similar to pixel shader programs provided in the Direct 3D API.

[0280] In at least one embodiment, graphics processor 3310 further includes one or more memory management units (MMUs) 3320A-3320B, caches 3325A-3325B, and circuit interconnects 3330A-3330B. In at least one embodiment, one or more MMUs 3320A-3320B provide virtual-to-physical address mapping for graphics processor 3310, including vertex processor 3305 and / or fragment processors 3315A-3315N, which may reference vertex or image / texture data stored in memory in addition to vertex or image / texture data stored in one or more caches 3325A-3325B. In at least one embodiment, one or more MMUs 3320A-3320B may be synchronized with other MMUs in the system, including one or more MMUs associated with one or more application processors 3205, image processor 3215, and / or video processor 3220 of Figure 32, allowing each processor 3205-3220 to participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 3330A-3330B enable graphics processor 3310 to interface with other IP cores in the SoC via the SoC's internal bus or via a direct connection.

[0281] In at least one embodiment, graphics processor 3340 includes one or more MMUs 3320A-3320B, caches 3325A-3325B, and circuit interconnects 3330A-3330B of graphics processor 3310 of FIG. 33A. In at least one embodiment, graphics processor 3340 includes one or more shader cores 3355A-3355N (e.g., 3355A, 3355B, 3355C, 3355D, 3355E, 3355F-3355N-1, and 3355N), which provide a unified shader core architecture in which a single core or type of core can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, the number of shader cores can vary. In at least one embodiment, graphics processor 3340 includes an inter-core task manager 3345 that acts as a thread dispatcher for dispatching execution threads to one or more shader cores 3355A-3355N, and a tiling unit 3358 for accelerating tiling operations for tile-based rendering, where scene rendering operations are subdivided in image space, e.g., to exploit local spatial coherence within a scene or to optimize internal cache usage.

[0282] Inference and / or training logic 2315 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 2315 are provided herein in conjunction with FIG. 23A and / or FIG. 23B. In at least one embodiment, inference and / or training logic 2315 may be used in integrated circuits 33A and / or 33B for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein. In at least one embodiment, a robotic grasping system may use a multi-core processor, such as those described above, to control a haptic hand.

[0283] Figures 34A-34B illustrate further exemplary graphics processor logic according to embodiments described herein. Figure 34A illustrates a graphics core 3400, which, in at least one embodiment, may be included in graphics processor 3210 of Figure 32, or, in at least one embodiment, may be integrated shader cores 3355A-3355N, as in Figure 33B. Figure 34B illustrates a highly parallel, general-purpose graphics processing unit 3430 suitable for incorporation into a multi-chip module in at least one embodiment.

[0284] In at least one embodiment, graphics core 3400 includes a shared instruction cache 3402, a texture unit 3418, and a cache / shared memory 3420, which are common to execution resources within graphics core 3400. In at least one embodiment, graphics core 3400 may include multiple slices 3401A-3401N, or partitions per core, and a graphics processor may include multiple instances of graphics core 3400. Slices 3401A-3401N may include supporting logic, including local instruction caches 3404A-3404N, thread schedulers 3406A-3406N, thread dispatchers 3408A-3408N, and sets of registers 3410A-3410N. In at least one embodiment, slices 3401A-3401N may include a set of additional functional units (AFUs 3412A-3412N), floating point units (FPUs 3414A-3414N), integer arithmetic logic units (ALUs 3416-3416N), address calculation units (ACUs 3413A-3413N), double precision floating point units (DPFPUs 3415A-3415N), and matrix processing units (MPUs 3417A-3417N).

[0285] In at least one embodiment, the FPUs 3414A-3414N can perform single-precision (32-bit) and half-precision (16-bit) floating-point operations, and the DPFPUs 3415A-3415N can perform double-precision (64-bit) floating-point operations. In at least one embodiment, the ALUs 3416A-3416N can perform variable-precision integer operations with 8-bit, 16-bit, and 32-bit precision and can be configured for mixed-precision operations. In at least one embodiment, the MPUs 3417A-3417N can also be configured for mixed-precision matrix operations, including half-precision floating-point and 8-bit integer operations. In at least one embodiment, the MPUs 3417A-3417N can perform various matrix operations to accelerate machine learning application frameworks, including being able to support general matrix-matrix multiplication ("GEMM") acceleration. In at least one embodiment, the AFUs 3412A-3412N can perform additional logical operations not supported by the floating-point unit or integer unit, including trigonometric operations (e.g., sine, cosine, etc.).

[0286] Inference and / or training logic 2315 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 2315 are provided herein in conjunction with FIG. 23A and / or FIG. 23B . In at least one embodiment, inference and / or training logic 2315 may be used in graphics core 3400 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network usage described herein. In at least one embodiment, a robotic grasping system may use a graphics processor such as described above to control a haptic hand.

[0287] FIG. 34B illustrates a general-purpose processing unit (GPGPU) 3430, which, in at least one embodiment, can be configured to enable highly parallel computational operations by an array of graphics processing units. In at least one embodiment, the GPGPU 3430 can be directly linked to other instances of the GPGPU 3430 to create multiple GPU clusters to improve the training speed of deep neural networks. In at least one embodiment, the GPGPU 3430 includes a host interface 3432 for enabling connection to a host processor. In at least one embodiment, the host interface 3432 is a PCI Express interface. In at least one embodiment, the host interface 3432 can be a vendor-specific communications interface or fabric. In at least one embodiment, the GPGPU 3430 receives commands from the host processor and, using a global scheduler 3434, distributes execution threads associated with those commands to a set of compute clusters 3436A-3436H. In at least one embodiment, compute clusters 3436A-3436H share cache memory 3438. In at least one embodiment, cache memory 3438 can act as a higher level cache for cache memories within compute clusters 3436A-3436H.

[0288] In at least one embodiment, GPGPU 3430 includes memory 3444A-3444B coupled to compute clusters 3436A-3436H via a set of memory controllers 3442A-3442B. In at least one embodiment, memory 3444A-3444B can include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory.

[0289] In at least one embodiment, compute clusters 3436A-3436H each include a set of graphics cores, such as graphics core 3400 of FIG. 34A, which may include multiple types of integer and floating-point logic units capable of performing computational operations with various precisions, including those suitable for machine learning computations. For example, in at least one embodiment, at least a subset of the floating-point units in each of compute clusters 3436A-3436H may be configured to perform 16-bit or 32-bit floating-point operations, while another subset of the floating-point units may be configured to perform 64-bit floating-point operations.

[0290] In at least one embodiment, multiple instances of GPGPU 3430 can be configured to operate as a compute cluster. In at least one embodiment, the communications used by compute clusters 3436A-3436H for synchronization and data exchange vary across embodiments. In at least one embodiment, multiple instances of GPGPU 3430 communicate through host interface 3432. In at least one embodiment, GPGPU 3430 includes I / O hub 3439, which couples GPGPU 3430 to GPU link 3440, which enables direct connection to other instances of GPGPU 3430. In at least one embodiment, GPU link 3440 is coupled to a dedicated GPU-to-GPU bridge, which enables communication and synchronization between multiple instances of GPGPU 3430. In at least one embodiment, GPU link 3440 is coupled to a high-speed interconnect for sending and receiving data to other GPGPUs or parallel processors. In at least one embodiment, multiple instances of GPGPU 3430 are located in separate data processing systems and communicate via a network device accessible via host interface 3432. In at least one embodiment, GPU link 3440 can be configured to allow connection to a host processor in addition to, or instead of, host interface 3432.

[0291] In at least one embodiment, the GPGPU 3430 can be configured to train a neural network. In at least one embodiment, the GPGPU 3430 can be used within an inference platform. In at least one embodiment, when the GPGPU 3430 is used for inference, the GPGPU may include fewer compute clusters 3436A-3436H than when the GPGPU is used to train a neural network. In at least one embodiment, the memory technology associated with memories 3444A-3444B may be different for the inference configuration and the training configuration, with higher bandwidth memory technology being devoted to the training configuration. In at least one embodiment, the inference configuration of the GPGPU 3430 can support inference-specific instructions. For example, in at least one embodiment, the inference configuration can support one or more 8-bit integer dot product instructions, which may be used during inference operations of a deployed neural network.

[0292] Inference and / or training logic 2315 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding the inference and / or training logic 2315 are provided herein in conjunction with FIG. 23A and / or FIG. 23B . In at least one embodiment, the inference and / or training logic 2315 may be used in the GPGPU 3430 for inference or prediction operations based at least in part on weight parameters calculated using the neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein. In at least one embodiment, a robotic grasping system may use a graphics processor, such as described above, to control a haptic hand.

[0293] 35 is a block diagram illustrating a computing system 3500 according to at least one embodiment. In at least one embodiment, computing system 3500 includes a processing subsystem 3501 having one or more processors 3502 and system memory 3504 that communicate via an interconnect path that may include a memory hub 3505. In at least one embodiment, memory hub 3505 may be a separate component within a chipset component or may be integrated within one or more processors 3502. In at least one embodiment, memory hub 3505 is coupled to an I / O subsystem 3511 via communication link 3506. In at least one embodiment, I / O subsystem 3511 includes an I / O hub 3507 that can enable computing system 3500 to receive input from one or more input devices 3508. In at least one embodiment, I / O hub 3507 can enable a display controller, which may be included in one or more processors 3502 and provide output to one or more display devices 3510A. In at least one embodiment, the one or more display devices 3510A coupled to I / O hub 3507 can include local, internal, or embedded display devices.

[0294] In at least one embodiment, processing subsystem 3501 includes one or more parallel processors 3512 coupled to memory hub 3505 via a bus or other communication link 3513. In at least one embodiment, communication link 3513 may be one of any number of standard-based communication link technologies or protocols, such as, but not limited to, PCI Express, or may be a vendor-specific communication interface or fabric. In at least one embodiment, one or more parallel processors 3512 form a computationally intensive parallel or vector processing system that may include multiple processing cores and / or processing clusters, such as a many integrated core (MIC) processor. In at least one embodiment, one or more parallel processors 3512 form a graphics processing subsystem that can output pixels to one of one or more display devices 3510A coupled via I / O hub 3507. In at least one embodiment, the one or more parallel processors 3512 may also include a display controller and display interface (not shown) that allows for direct connection to one or more display devices 3510B.

[0295] In at least one embodiment, system storage unit 3514 may be connected to I / O hub 3507 to provide a storage mechanism for computing system 3500. In at least one embodiment, I / O switch 3516 may be used to provide an interface mechanism to enable communication between I / O hub 3507 and other components, such as network adapter 3518 and / or wireless network adapter 3519, which may be integrated into the platform, as well as various other devices that may be added via one or more add-in devices 3520. In at least one embodiment, network adapter 3518 may be an Ethernet adapter or another wired network adapter. In at least one embodiment, wireless network adapter 3519 may include one or more of Wi-Fi, Bluetooth, near field communication (NFC), or other network devices including one or more wireless radios.

[0296] In at least one embodiment, computing system 3500 may include other components not shown, including USB or other port connections, optical storage drives, video capture devices, etc., which may also be connected to I / O hub 3507. In at least one embodiment, the communication paths interconnecting the various components of FIG. 35 may be implemented using any suitable protocol, such as a Peripheral Component Interconnect (PCI)-based protocol (e.g., PCI-Express), or other bus or point-to-point communication interface or interconnection protocol, such as the NV-Link high-speed interconnect.

[0297] In at least one embodiment, one or more parallel processors 3512 incorporate circuitry optimized for graphics and video processing, including, for example, video output circuitry, forming a graphics processing unit (GPU). In at least one embodiment, one or more parallel processors 3512 incorporate circuitry optimized for general-purpose processing. In at least one embodiment, components of computing system 3500 may be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, one or more parallel processors 3512, memory hub 3505, processor 3502, and I / O hub 3507 may be integrated into a system-on-chip (SoC) integrated circuit. In at least one embodiment, components of computing system 3500 may be integrated into a single package to form a system-in-package (SIP) configuration. In at least one embodiment, at least a portion of the components of computing system 3500 may be integrated into a multi-chip module (MCM), which may be interconnected with other multi-chip modules to form a modular computing system.

[0298] Inference and / or training logic 2315 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding the inference and / or training logic 2315 are provided herein in conjunction with FIG. 23A and / or FIG. 23B . In at least one embodiment, the inference and / or training logic 2315 may be used in system 3500 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein. In at least one embodiment, a processor such as described herein may be used to control a robotic hand equipped with tactile sensors, as described above.

[0299] Processor 36A illustrates a parallel processor 3600 according to at least one embodiment. In at least one embodiment, various components of parallel processor 3600 may be implemented using one or more integrated circuit devices, such as a programmable processor, an application specific integrated circuit (ASIC), or a field programmable gate array (FPGA). In at least one embodiment, the illustrated parallel processor 3600 is a variation of one or more parallel processors 3512 shown in FIG. 35 according to an example embodiment.

[0300] In at least one embodiment, parallel processor 3600 includes parallel processing unit 3602. In at least one embodiment, parallel processing unit 3602 includes I / O unit 3604 that enables communication with other devices, including other instances of parallel processing unit 3602. In at least one embodiment, I / O unit 3604 may be directly connected to other devices. In at least one embodiment, I / O unit 3604 is connected to other devices through the use of a hub or switch interface, such as memory hub 3605. In at least one embodiment, the connection between memory hub 3605 and I / O unit 3604 forms communication link 3513. In at least one embodiment, I / O unit 3604 is connected to host interface 3606 and memory crossbar 3616, where host interface 3606 receives commands directed to the execution of processing operations and memory crossbar 3616 receives commands directed to the execution of memory operations.

[0301] In at least one embodiment, when host interface 3606 receives command buffers via I / O unit 3604, host interface 3606 can direct work operations to execute these commands to front end 3608. In at least one embodiment, front end 3608 is coupled to scheduler 3610, which is configured to distribute commands or other work items to processing cluster array 3612. In at least one embodiment, scheduler 3610 ensures that processing cluster array 3612 is properly configured and in a valid state before tasks are distributed to processing cluster array 3612 of processing cluster array 3612. In at least one embodiment, scheduler 3610 is implemented via firmware logic running on a microcontroller. In at least one embodiment, the microcontroller-implemented scheduler 3610 is configurable to perform complex scheduling and work distribution operations at both coarse and fine granularities, allowing rapid preemption and context switching of threads executing in the processing array 3612. In at least one embodiment, host software can signal scheduling workloads in the processing array 3612 via one of multiple graphics processing doorbells. In at least one embodiment, the workload can then be automatically distributed across the processing array 3612 by scheduler 3610 logic in the microcontroller that includes the scheduler 3610.

[0302] In at least one embodiment, processing cluster array 3612 can include up to “N” processing clusters (e.g., cluster 3614A, cluster 3614B through cluster 3614N). In at least one embodiment, each cluster 3614A through 3614N of processing cluster array 3612 can execute a large number of simultaneous threads. In at least one embodiment, scheduler 3610 can allocate work to clusters 3614A through 3614N of processing cluster array 3612 using various scheduling and / or work distribution algorithms, which may vary depending on the workload generated by each program or type of computation. In at least one embodiment, scheduling may be handled dynamically by scheduler 3610 or may be partially assisted by compiler logic during compilation of program logic configured to be executed by processing cluster array 3612. In at least one embodiment, different clusters 3614A through 3614N of processing cluster array 3612 can be allocated to process different types of programs or perform different types of computations.

[0303] In at least one embodiment, processing cluster array 3612 may be configured to perform various types of parallel processing operations. In at least one embodiment, processing cluster array 3612 may be configured to perform general-purpose parallel compute operations. For example, in at least one embodiment, processing cluster array 3612 may include logic for performing processing tasks including filtering video and / or audio data, performing modeling operations including physics operations, and performing data transformations.

[0304] In at least one embodiment, processing cluster array 3612 is configured to perform parallel graphics processing operations. In at least one embodiment, processing cluster array 3612 may include additional logic to support the execution of such graphics processing operations, including, but not limited to, texture sampling logic for performing texture operations, as well as mosaic logic and other vertex processing logic. In at least one embodiment, processing cluster array 3612 may be configured to execute graphics processing related shader programs, such as, but not limited to, vertex shaders, mosaic shaders, geometry shaders, and pixel shaders. In at least one embodiment, parallel processing unit 3602 may transfer data from system memory via I / O unit 3604 for processing. In at least one embodiment, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 3622) during processing and then written back to system memory.

[0305] In at least one embodiment, when graphics processing is performed using parallel processing unit 3602, scheduler 3610 may be configured to divide the processing workload into roughly equal-sized tasks to better distribute graphics processing operations among multiple clusters 3614A-3614N of processing cluster array 3612. In at least one embodiment, portions of processing cluster array 3612 may be configured to perform different types of processing. For example, in at least one embodiment, to generate and display a rendered image, a first portion may be configured to perform vertex shading and topology generation, a second portion may be configured to perform mosaic and geometry shading, and a third portion may be configured to perform pixel shading or other screen space operations. In at least one embodiment, intermediate data generated by one or more of clusters 3614A-3614N may be stored in a buffer so that the intermediate data can be transmitted between clusters 3614A-3614N for further processing.

[0306] In at least one embodiment, processing cluster array 3612 can receive processing tasks to be performed via scheduler 3610, which receives commands defining the processing tasks from front end 3608. In at least one embodiment, a processing task can include an index of the data to be processed, e.g., surface (patch) data, primitive data, vertex data, and / or pixel data, as well as state parameters and commands defining how the data should be processed (e.g., which program to execute). In at least one embodiment, scheduler 3610 can be configured to fetch the index corresponding to the task or can receive the index from front end 3608. In at least one embodiment, front end 3608 can be configured to ensure that processing cluster array 3612 is configured to a valid state before a workload specified by an incoming command buffer (e.g., batch buffer, push buffer, etc.) is initiated.

[0307] In at least one embodiment, each of one or more instances of parallel processing unit 3602 can be coupled to parallel processor memory 3622. In at least one embodiment, parallel processor memory 3622 can be accessed via memory crossbar 3616, which can receive memory requests from processing cluster array 3612 as well as I / O unit 3604. In at least one embodiment, memory crossbar 3616 can access parallel processor memory 3622 via memory interface 3618. In at least one embodiment, memory interface 3618 can include multiple partition units (e.g., partition unit 3620A, partition unit 3620B through partition unit 3620N), each of which can be coupled to a portion (e.g., a memory unit) of parallel processor memory 3622. In at least one embodiment, the number of partition units 3620A-3620N is configured to be equal to the number of memory units, such that a first partition unit 3620A has a corresponding first memory unit 3624A, a second partition unit 3620B has a corresponding memory unit 3624B, and an Nth partition unit 3620N has a corresponding Nth memory unit 3624N. In at least one embodiment, the number of partition units 3620A-3620N does not have to be equal to the number of memory devices.

[0308] In at least one embodiment, the memory units 3624A-3624N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In at least one embodiment, the memory units 3624A-3624N may also include 3D stacked memory, including, but not limited to, high-bandwidth memory (HBM). In at least one embodiment, to efficiently use the available bandwidth of the parallel processor memory 3622, render targets, such as frame buffers or texture maps, may be stored across the memory units 3624A-3624N, allowing the partition units 3620A-3620N to write portions of each render target in parallel. In at least one embodiment, local instances of the parallel processor memory 3622 may be omitted in favor of a unified memory design that uses a combination of system memory and local cache memory.

[0309] In at least one embodiment, any one of the clusters 3614A-3614N in the processing cluster array 3612 can process data that is to be written to any one of the memory units 3624A-3624N in the parallel processor memory 3622. In at least one embodiment, the memory crossbar 3616 can be configured to forward the output of each cluster 3614A-3614N to any partition unit 3620A-3620N or to another cluster 3614A-3614N that can perform further processing operations on the output. In at least one embodiment, each cluster 3614A-3614N can communicate with a memory interface 3618 through the memory crossbar 3616 to read from or write to various external memory devices. In at least one embodiment, memory crossbar 3616 has connections to memory interface 3618 for communicating with I / O unit 3604, as well as connections to local instances of parallel processor memory 3622, allowing processing units in different processing clusters 3614A-3614N to communicate with system memory or other memory not local to parallel processing unit 3602. In at least one embodiment, memory crossbar 3616 can use virtual channels to separate traffic streams between clusters 3614A-3614N and partition units 3620A-3620N.

[0310] In at least one embodiment, multiple instances of parallel processing unit 3602 may be provided on a single add-in card, or multiple add-in cards may be interconnected. In at least one embodiment, different instances of parallel processing unit 3602 may be configured to interoperate even if the different instances have different numbers of processing cores, different amounts of local parallel processor memory, and / or other different configurations. For example, in at least one embodiment, some instances of parallel processing unit 3602 may include higher precision floating-point units than other instances. In at least one embodiment, systems incorporating one or more instances of parallel processing unit 3602 or parallel processor 3600 may be implemented in a variety of configurations and form factors, including, but not limited to, desktop, laptop, or portable personal computers, servers, workstations, game consoles, and / or embedded systems.

[0311] FIG. 36B is a block diagram of partition unit 3620 according to at least one embodiment. In at least one embodiment, partition unit 3620 is an instance of one of partition units 3620A-3620N of FIG. 36A. In at least one embodiment, partition unit 3620 includes L2 cache 3621, frame buffer interface 3625, and ROP (raster operations unit) 3626. L2 cache 3621 is a read / write cache configured to execute load and store operations received from memory crossbar 3616 and ROP 3626. In at least one embodiment, read misses and urgent writeback requests are output by L2 cache 3621 to frame buffer interface 3625 for processing. In at least one embodiment, updates are also sent to the frame buffer via frame buffer interface 3625 for processing. In at least one embodiment, frame buffer interface 3625 interfaces with one of the memory units of a parallel processor memory, such as memory units 3624A-3624N (eg, in parallel processor memory 3622) of FIG.

[0312] In at least one embodiment, the ROP 3626 is a processing unit that performs raster operations such as stencil, z-test, and blending. In at least one embodiment, the ROP 3626 then outputs the processed graphics data stored in graphics memory. In at least one embodiment, the ROP 3626 includes compression logic for compressing depth or color data being written to memory and decompressing depth or color data being read from memory. In at least one embodiment, the compression logic can be lossless compression logic that utilizes one or more of a number of compression algorithms. The type of compression performed by the ROP 3626 can be varied based on statistical characteristics of the data being compressed. For example, in at least one embodiment, delta color compression is performed on the depth and color data on a tile-by-tile basis.

[0313] In at least one embodiment, ROP 3626 is included within each processing cluster (e.g., clusters 3614A-3614N of FIG. 36 ) rather than within partition unit 3620. In at least one embodiment, read and write requests for pixel data, rather than pixel fragment data, are transmitted through memory crossbar 3616. In at least one embodiment, processed graphics data may be displayed on a display device, such as one of one or more display devices 3510 of FIG. 35 , may be routed for further processing by processor 3502, or may be routed for further processing by one of the processing entities in parallel processor 3600 of FIG. 36A.

[0314] FIG. 36C is a block diagram of a processing cluster 3614 within a parallel processing unit according to at least one embodiment. In at least one embodiment, the processing cluster is an instance of one of processing clusters 3614A-3614N of FIG. 36. In at least one embodiment, processing cluster 3614 may be configured to execute multiple threads in parallel, where the term "thread" refers to an instance of a particular program executing on a particular set of input data. In at least one embodiment, single-instruction, multiple-data (SIMD) instruction issue techniques are used to support parallel execution of multiple threads without providing multiple independent instruction units. In at least one embodiment, single-instruction, multiple-thread (SIMT) techniques are used to support parallel execution of multiple, generally synchronized threads using a common instruction unit configured to issue instructions to a set of processing engines within each processing cluster.

[0315] In at least one embodiment, operation of processing cluster 3614 may be controlled via a pipeline manager 3632, which distributes processing tasks to the SIMT parallel processors. In at least one embodiment, pipeline manager 3632 receives instructions from scheduler 3610 of FIG. 36 and manages the execution of those instructions via graphics multiprocessor 3634 and / or texture unit 3636. In at least one embodiment, graphics multiprocessor 3634 is an exemplary instance of a SIMT parallel processor. However, in at least one embodiment, various types of SIMT parallel processors with different architectures may be included within processing cluster 3614. In at least one embodiment, one or more instances of graphics multiprocessor 3634 may be included within processing cluster 3614. In at least one embodiment, graphics multiprocessor 3634 may process data, and data crossbar 3640 may be used to distribute the processed data to one of several possible destinations, including other shader units. In at least one embodiment, pipeline manager 3632 can facilitate distribution of the processed data by specifying destinations for the processed data to be distributed through data crossbar 3640.

[0316] In at least one embodiment, each graphics multiprocessor 3634 in a processing cluster 3614 may include an identical set of function execution logic (e.g., arithmetic logic units, load-store units, etc.). In at least one embodiment, the function execution logic may be configured in a pipelined manner, allowing new instructions to be issued before previous instructions complete. In at least one embodiment, the function execution logic supports a variety of operations, including integer and floating-point arithmetic, comparison operations, Boolean operations, bit shifts, and calculation of various algebraic functions. In at least one embodiment, the same functional unit hardware may be utilized to perform different operations, and any combination of functional units may be present.

[0317] In at least one embodiment, instructions sent to processing cluster 3614 constitute threads. In at least one embodiment, a set of threads executing across a set of parallel processing engines is a thread group. In at least one embodiment, a thread group executes a program on different input data. In at least one embodiment, each thread in a thread group can be assigned to a different processing engine in graphics multiprocessor 3634. In at least one embodiment, a thread group may include fewer threads than the number of processing engines in graphics multiprocessor 3634. In at least one embodiment, if a thread group includes fewer threads than the number of processing engines, one or more of the processing engines may be idle during the cycle in which the thread group is processed. In at least one embodiment, a thread group may also include more threads than the number of processing engines in graphics multiprocessor 3634. In at least one embodiment, if a thread group includes more threads than the number of processing engines in graphics multiprocessor 3634, processing may be performed over consecutive clock cycles. In at least one embodiment, multiple thread groups may execute simultaneously on graphics multiprocessor 3634.

[0318] In at least one embodiment, the graphics multiprocessor 3634 includes internal cache memory for performing load and store operations. In at least one embodiment, the graphics multiprocessor 3634 can forgo the internal cache and use cache memory (e.g., L1 cache 3648) within the processing cluster 3614. In at least one embodiment, each graphics multiprocessor 3634 can also access an L2 cache within a partition unit (e.g., partition units 3620A-3620N in FIG. 36 ), which may be shared among all processing clusters 3614 and used to transfer data between threads. In at least one embodiment, the graphics multiprocessor 3634 can also access off-chip global memory, which may include one or more of the local parallel processor memories and / or system memories. In at least one embodiment, any memory external to the parallel processing units 3602 may be used as global memory. In at least one embodiment, processing cluster 3614 includes multiple instances of graphics multiprocessor 3634 that can share common instructions and data, which may be stored in L1 cache 3648.

[0319] In at least one embodiment, each processing cluster 3614 may include an MMU 3645 (memory management unit) configured to map virtual addresses to physical addresses. In at least one embodiment, one or more instances of MMU 3645 may reside within memory interface 3618 of FIG. 36. In at least one embodiment, MMU 3645 includes a set of page table entries (PTEs) used to map virtual addresses to physical addresses for tiles (tiling is described in more detail below) and optionally cache line indices. In at least one embodiment, MMU 3645 may include an address translation lookaside buffer (TLB) or cache, which may reside within graphics multiprocessor 3634 or an L1 cache, or processing cluster 3614. In at least one embodiment, physical addresses are processed to locally distribute surface data accesses, allowing efficient interleaving of requests across partition units. In at least one embodiment, the cache line index may be used to determine whether a request for a cache line is a hit or a miss.

[0320] In at least one embodiment, processing cluster 3614 may be configured such that each graphics multiprocessor 3634 is coupled to a texture unit 3636 to perform texture mapping operations, such as determining texture sample locations, reading texture data, and filtering the texture data. In at least one embodiment, texture data is read from an internal texture L1 cache (not shown) or from an L1 cache within graphics multiprocessor 3634 and fetched as needed from an L2 cache, local parallel processor memory, or system memory. In at least one embodiment, each graphics multiprocessor 3634 outputs processed tasks to data crossbar 3640 to provide the processed tasks to another processing cluster 3614 for further processing, or stores the processed tasks in an L2 cache, local parallel processor memory, or system memory via memory crossbar 3616. In at least one embodiment, a pre-ROP 3642 (pre-raster operation unit) is configured to receive data from the graphics multiprocessor 3634 and direct the data to the ROP units, which may be located within partition units (e.g., partition units 3620A-3620N of FIG. 36) as described herein. In at least one embodiment, the pre-ROP 3642 unit can perform color blending optimizations, organize pixel color data, and perform address translation.

[0321] Inference and / or training logic 2315 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding the inference and / or training logic 2315 are provided herein in conjunction with FIG. 23A and / or FIG. 23B . In at least one embodiment, the inference and / or training logic 2315 may be used in graphics processing cluster 3614 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein. In at least one embodiment, a processor such as described herein may be used to control a robotic hand equipped with tactile sensors, as described above.

[0322] Figure 36D illustrates a graphics multiprocessor 3634 according to at least one embodiment. In at least one embodiment, graphics multiprocessor 3634 couples with pipeline manager 3632 of processing cluster 3614. In at least one embodiment, graphics multiprocessor 3634 has an execution pipeline including, but not limited to, instruction cache 3652, instruction unit 3654, address mapping unit 3656, register file 3658, one or more general-purpose graphics processing unit (GPGPU) cores 3662, and one or more load / store units 3666. GPGPU cores 3662 and load / store units 3666 are coupled to cache memory 3672 and shared memory 3670 via memory and cache interconnect 3668.

[0323] In at least one embodiment, instruction cache 3652 receives a stream of instructions to execute from pipeline manager 3632. In at least one embodiment, instructions are cached in instruction cache 3652 and dispatched for execution by instruction unit 3654. In at least one embodiment, instruction unit 3654 can dispatch instructions as thread groups (e.g., warps), with each thread of a thread group assigned to a different execution unit within GPGPU core 3662. In at least one embodiment, instructions can access either local, shared, or global address spaces by specifying addresses in the unified address space. In at least one embodiment, address mapping unit 3656 can be used to translate addresses in the unified address space into individual memory addresses accessible by load / store unit 3666.

[0324] In at least one embodiment, register file 3658 provides a set of registers to the functional units of graphics multiprocessor 3634. In at least one embodiment, register file 3658 provides temporary storage for operands connected to the data paths of the functional units (e.g., GPGPU cores 3662, load / store unit 3666) of graphics multiprocessor 3634. In at least one embodiment, register file 3658 is partitioned among the respective functional units, such that each functional unit is allocated a dedicated portion of register file 3658. In one embodiment, register file 3658 is partitioned among the different warps being executed by graphics multiprocessor 3634.

[0325] In at least one embodiment, the GPGPU cores 3662 may each include a floating-point unit (FPU) and / or an integer arithmetic logic unit (ALU) used to execute instructions for the graphics multiprocessor 3634. The GPGPU cores 3662 may have similar or different architectures. In at least one embodiment, a first portion of the GPGPU core 3662 includes a single-precision FPU and an integer ALU, and a second portion of the GPGPU core includes a double-precision FPU. In at least one embodiment, the FPU may implement the IEEE 754-2008 standard for floating-point operations or may enable variable-precision floating-point operations. In at least one embodiment, the graphics multiprocessor 3634 may further include one or more fixed-function or special-function units for performing specific functions, such as rectangle copy or pixel blending operations. In at least one embodiment, one or more of the GPGPU cores may also include fixed or special-function logic.

[0326] In at least one embodiment, GPGPU core 3662 includes SIMD logic capable of executing a single instruction on multiple data sets. In at least one embodiment, GPGPU core 3662 can physically execute SIMD4, SIMD8, and SIMD16 instructions and logically execute SIMD1, SIMD2, and SIMD32 instructions. In at least one embodiment, SIMD instructions for the GPGPU core may be generated at compile time by a shader compiler or may be generated automatically when executing a program written and compiled for a single program multiple data (SPMD) or SIMT architecture. In at least one embodiment, multiple threads of a program configured for the SIMT execution model may execute via a single SIMD instruction. For example, in at least one embodiment, eight SIMT threads performing the same or similar operations may execute in parallel via a single SIMD8 logical unit.

[0327] In at least one embodiment, memory and cache interconnect 3668 is an interconnect network connecting each functional unit of graphics multiprocessor 3634 to register file 3658 and shared memory 3670. In at least one embodiment, memory and cache interconnect 3668 is a crossbar interconnect that allows load / store unit 3666 to implement load and store operations between shared memory 3670 and register file 3658. In at least one embodiment, register file 3658 can operate at the same frequency as GPGPU cores 3662, and therefore data transfers between GPGPU cores 3662 and register file 3658 have very low latency. In at least one embodiment, shared memory 3670 can be used to enable communication between threads executing in functional units within graphics multiprocessor 3634. In at least one embodiment, cache memory 3672 can be used, for example, as a data cache to cache texture data communicated between the functional units and texture unit 3636. In at least one embodiment, shared memory 3670 can also be used as a program-managed cache. In at least one embodiment, threads running on GPGPU cores 3662 can programmatically store data in the shared memory in addition to automatically caching data stored in cache memory 3672.

[0328] In at least one embodiment, a parallel processor or GPGPU described herein is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. In at least one embodiment, the GPU may be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In at least one embodiment, the GPU may be integrated into the same package or chip as the core or may be communicatively coupled to the core via an internal (i.e., internal to the package or chip) processor bus / interconnect. In at least one embodiment, regardless of how the GPU is connected, the processor core may allocate work to the GPU in the form of a sequence of commands / instructions contained in a work descriptor. In at least one embodiment, the GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0329] Inference and / or training logic 2315 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 2315 are provided herein in conjunction with FIG. 23A and / or FIG. 23B . In at least one embodiment, inference and / or training logic 2315 may be used in graphics multiprocessor 3634 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein. In at least one embodiment, a multi-GPE computing system such as described herein may be used to control a robotic hand equipped with tactile sensors, as described above.

[0330] FIG. 37 illustrates a multi-GPU computing system 3700, according to at least one embodiment. In at least one embodiment, the multi-GPU computing system 3700 may include a processor 3702 coupled to multiple general-purpose graphics processing units (GPGPUs) 3706A-D via a host interface switch 3704. In at least one embodiment, the host interface switch 3704 is a PCI Express switch device that couples the processor 3702 to a PCI Express bus, via which the processor 3702 can communicate with the GPGPUs 3706A-D. The GPGPUs 3706A-D may be interconnected via a set of high-speed point-to-point GPU-to-GPU links 3716. In at least one embodiment, the GPU-to-GPU links 3716 are connected to each of the GPGPUs 3706A-D via dedicated GPU links. In at least one embodiment, P2P GPU link 3716 allows direct communication between each of GPGPUs 3706A-D without requiring communication via host interface bus 3704 to which processor 3702 is connected. In at least one embodiment, when there is GPU-to-GPU traffic directed to P2P GPU link 3716, host interface bus 3704 remains available to allow access to system memory or to communicate with other instances of multi-GPU computing system 3700, for example, via one or more network devices. In at least one embodiment, GPGPUs 3706A-D are connected to processor 3702 via host interface switch 3704, and in at least one embodiment, processor 3702 includes direct support for P2P GPU link 3716 and can be directly connected to GPGPUs 3706A-D.

[0331] Inference and / or training logic 2315 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding the inference and / or training logic 2315 are provided herein in conjunction with FIG. 23A and / or FIG. 23B . In at least one embodiment, the inference and / or training logic 2315 may be used in the multi-GPU computing system 3700 for inference or prediction operations based at least in part on weight parameters calculated using the neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein. In at least one embodiment, a graphics processor such as described herein may be used to control a robotic hand equipped with tactile sensors, as described above.

[0332] 38 is a block diagram of a graphics processor 3800 according to at least one embodiment. In at least one embodiment, graphics processor 3800 includes a ring interconnect 3802, a pipeline front end 3804, a media engine 3837, and graphics cores 3880A-3880N. In at least one embodiment, ring interconnect 3802 couples graphics processor 3800 to other processing units, including other graphics processors or one or more general-purpose processor cores. In at least one embodiment, graphics processor 3800 is one of multiple processors integrated within a multi-core processing system.

[0333] In at least one embodiment, graphics processor 3800 receives batches of commands via ring interconnect 3802. In at least one embodiment, the incoming commands are interpreted by command streamer 3803 of pipeline front end 3804. In at least one embodiment, graphics processor 3800 includes scalable execution logic for performing 3D geometry processing and media processing via graphics cores 3880A-3880N. In at least one embodiment, for 3D geometry processing commands, command streamer 3803 supplies the commands to geometry pipeline 3836. In at least one embodiment, for at least some media processing commands, command streamer 3803 supplies the commands to video front end 3834, which is coupled to media engine 3837. In at least one embodiment, the media engine 3837 includes a Video Quality Engine (VQE) 3830 for video and image post-processing and a Multi-Format Encode / Decode (MFX) 3833 engine that provides hardware-accelerated encoding and decoding of media data. In at least one embodiment, the geometry pipeline 3836 and the media engine 3837 each spawn execution threads for thread execution resources provided by at least one graphics core 3880A.

[0334] In at least one embodiment, graphics processor 3800 includes scalable thread execution resources characterized by modular cores 3880A-3880N (sometimes referred to as core slices), each having multiple sub-cores 3850A-3850N, 3860A-3860N (sometimes referred to as core sub-slices). In at least one embodiment, graphics processor 3800 can have any number of graphics cores 3880A-3880N. In at least one embodiment, graphics processor 3800 includes a graphics core 3880A having at least a first sub-core 3850A and a second sub-core 3860A. In at least one embodiment, graphics processor 3800 is a low-power processor having a single sub-core (e.g., 3850A). In at least one embodiment, graphics processor 3800 includes multiple graphics cores 3880A-3880N, each including a set of first sub-cores 3850A-3850N and a set of second sub-cores 3860A-3860N. In at least one embodiment, each of first sub-cores 3850A-3850N includes at least a first set of execution units 3852A-3852N and media / texture samplers 3854A-3854N. In at least one embodiment, each of second sub-cores 3860A-3860N includes at least a second set of execution units 3862A-3862N and samplers 3864A-3864N. In at least one embodiment, each sub-core 3850A-3850N, 3860A-3860N shares a set of shared resources 3870A-3870N. In at least one embodiment, the shared resources include shared cache memory and pixel operating logic.

[0335] Inference and / or training logic 2315 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding the inference and / or training logic 2315 are provided herein in conjunction with FIG. 23A and / or FIG. 23B . In at least one embodiment, the inference and / or training logic 2315 may be used in graphics processor 3800 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein. In at least one embodiment, a microarchitecture processor such as described herein may be used to control a robotic hand equipped with tactile sensors, as described above.

[0336] FIG. 39 is a block diagram illustrating the micro-architecture of a processor 3900 that may include logic circuits for executing instructions, according to at least one embodiment. In at least one embodiment, the processor 3900 may execute instructions, including x86 instructions, AMR instructions, special instructions for application-specific integrated circuits (ASICs), etc. In at least one embodiment, the processor 3910 may include registers for storing packed data, such as 64-bit wide MMX™ registers in microprocessors enabled with MMX technology by Intel Corporation of Santa Clara, California. In at least one embodiment, MMX registers, available in both integer and floating-point formats, may operate on packed data elements with Single Instruction Multiple Data (“SIMD”) and Streaming SIMD Extensions (“SSE”) instructions. In at least one embodiment, 128-bit wide XMM registers associated with SSE2, SSE3, SSE4, AVX, or higher (collectively referred to as “SSEx”) technology may hold such packed data operands. In at least one embodiment, the processor 3910 may execute instructions to accelerate machine learning or deep learning algorithms, training, or inference.

[0337] In at least one embodiment, processor 3900 includes an in-order front end ("front end") 3901 that fetches instructions to be executed and prepares the instructions for later use in the processor pipeline. In at least one embodiment, front end 3901 may include several units. In at least one embodiment, an instruction prefetcher 3926 fetches instructions from memory and provides the instructions to an instruction decoder 3928, which decodes or interprets the instructions. For example, in at least one embodiment, instruction decoder 3928 decodes received instructions into one or more operations, called "microinstructions" or "micro-operations" (also called "micro-ops" or "uops"), that the machine can execute. In at least one embodiment, instruction decoder 3928 parses instructions into opcodes and corresponding data and control fields that may be used by the micro-architecture to perform operations in accordance with at least one embodiment. In at least one embodiment, trace cache 3930 may assemble the decoded uops into program-order sequences, or traces, in uop queue 3934 for execution. In at least one embodiment, when trace cache 3930 encounters a complex instruction, microcode ROM 3932 provides the uops necessary to complete the operation.

[0338] In at least one embodiment, some instructions can be converted into a single micro-op, while other instructions require several micro-ops to complete the entire operation. In at least one embodiment, if an instruction requires more than four micro-ops to complete, the instruction decoder 3928 may access the microcode ROM 3932 to execute the instruction. In at least one embodiment, the instruction may be decoded into a smaller number of micro-ops for processing in the instruction decoder 3928. In at least one embodiment, if an operation requires a large number of micro-ops to complete, the instruction may be stored in the microcode ROM 3932. In at least one embodiment, the trace cache 3930 references an entry point programmable logic array (“PLA”) to determine the correct microinstruction pointer to read the microcode sequence from to complete one or more instructions from the microcode ROM 3932, in accordance with at least one embodiment. In at least one embodiment, after the microcode ROM 3932 has finished sequencing micro-ops for an instruction, the machine front end 3901 may resume fetching micro-ops from the trace cache 3930.

[0339] In at least one embodiment, out-of-order execution engine ("out-of-order engine") 3903 may prepare instructions for execution. In at least one embodiment, the out-of-order execution logic has multiple buffers to smooth and reorder the flow of instructions to optimize performance as instructions are scheduled for execution down the pipeline. Out-of-order execution engine 3903 includes, without limitation, allocator / register renamer 3940, memory uop queue 3942, integer / floating point uop queue 3944, memory scheduler 3946, fast scheduler 3902, slow / general purpose floating point scheduler ("slow / general purpose FP scheduler") 3904, and simple floating point scheduler ("simple FP scheduler") 3906. In at least one embodiment, fast scheduler 3902, slow / general purpose floating point scheduler 3904, and simple floating point scheduler 3906 are also collectively referred to herein as "uop schedulers 3902, 3904, 3906." Allocator / register renamer 3940 allocates the machine buffers and resources each uop needs to execute. In at least one embodiment, allocator / register renamer 3940 renames logical registers upon entry into the register file. In at least one embodiment, allocator / register renamer 3940 also distributes each uop's entry to one of two uop queues: memory uop queue 3942 for memory operations and integer / floating point uop queue 3944 for non-memory operations, before memory scheduler 3946 and uop schedulers 3902, 3904, 3906. In at least one embodiment, uop schedulers 3902, 3904, 3906 determine when uops are ready to execute based on the readiness of their dependent input register operand sources and the availability of the execution resources required by the uops to complete their operations.In at least one embodiment, the fast scheduler 3902 may schedule every half of the main clock cycle, and the slow / general purpose floating point scheduler 3904 and simple floating point scheduler 3906 may schedule once per main processor clock cycle. In at least one embodiment, the uop schedulers 3902, 3904, 3906 arbitrate for dispatch ports to schedule uops for execution.

[0340] In at least one embodiment, execution block b11 includes, without limitation, integer register file / bypass network 3908, floating point register file / bypass network (“FP register file / bypass network”) 3910, address generation units (“AGUs”) 3912 and 3914, fast arithmetic logic units (ALUs) (“fast ALUs”) 3916 and 3918, slower arithmetic logic unit (“slower ALU”) 3920, floating point ALU (“FP”) 3922, and floating point move unit (“FP move”) 3924. In at least one embodiment, integer register file / bypass network 3908 and floating point register file / bypass network 3910 are also referred to herein as “register files 3908, 3910.” In at least one embodiment, AGUs 3912 and 3914, fast ALUs 3916 and 3918, slow ALU 3920, floating-point ALU 3922, and floating-point move unit 3924 are also referred to herein as "execution units 3912, 3914, 3916, 3918, 3920, 3922, and 3924." In at least one embodiment, execution block b11 may include any number and type of register files (including zero), bypass networks, address generation units, and execution units, in any combination, without limitation.

[0341] In at least one embodiment, register files 3908, 3910 may be located between uop schedulers 3902, 3904, 3906 and execution units 3912, 3914, 3916, 3918, 3920, 3922, and 3924. In at least one embodiment, integer register file / bypass network 3908 performs integer operations. In at least one embodiment, floating point register file / bypass network 3910 performs floating point operations. In at least one embodiment, each of register files 3908, 3910 may include, without limitation, a bypass network that may bypass or forward recently completed results that have not yet been written to the register file to new dependent uops. In at least one embodiment, register files 3908, 3910 may communicate data with each other. In at least one embodiment, integer register file / bypass network 3908 may include, without limitation, two separate register files: one register file for the lower 32-bit data and a second register file for the higher 32-bit data. In at least one embodiment, floating-point instructions typically have operands that are 64-128 bits wide, and therefore floating-point register file / bypass network 3910 may include, without limitation, 128-bit wide entries.

[0342] In at least one embodiment, execution units 3912, 3914, 3916, 3918, 3920, 3922, and 3924 may execute instructions. In at least one embodiment, register files 3908 and 3910 store integer and floating-point data operand values ​​required by microinstructions to execute. In at least one embodiment, processor 3900 may include any number and combination of execution units 3912, 3914, 3916, 3918, 3920, 3922, and 3924, without limitation. In at least one embodiment, floating-point ALU 3922 and floating-point move unit 3924 may execute floating-point, MMX, SIMD, AVX, and SEE, or other operations, including special machine learning instructions. In at least one embodiment, the floating-point ALU 3922 may include, without limitation, a 64-bit floating-point divider to perform division, square root, and remaining micro-ops. In at least one embodiment, instructions involving floating-point values ​​may be handled by floating-point hardware. In at least one embodiment, ALU operations may be passed to the high-speed ALUs 3916, 3918. In at least one embodiment, the high-speed ALUs 3916, 3918 may perform high-speed operations with an effective latency of half a clock cycle. In at least one embodiment, the low-speed ALU 3920 may include, without limitation, integer execution hardware for long-latency type operations such as multipliers, shifts, flag logic, and branching, with most complex integer operations proceeding to the low-speed ALU 3920. In at least one embodiment, memory load / store operations may be performed by the ALUs 3912, 3914. In at least one embodiment, fast ALU 3916, fast ALU 3918, and slow ALU 3920 may perform integer operations on 64-bit data operands. In at least one embodiment, fast ALU 3916, fast ALU 3918, and slow ALU 3920 may be implemented to support various data bit sizes, including 16, 32, 128, 256, etc. In at least one embodiment, floating-point ALU 3922 and floating-point move unit 3924 may be implemented to support wide operands having various bit widths.In at least one embodiment, floating-point ALU 3922 and floating-point move unit 3924 may operate on 128-bit wide packed data operands in conjunction with SIMD and multimedia instructions.

[0343] In at least one embodiment, the uop schedulers 3902, 3904, 3906 dispatch dependent operations before the parent load finishes execution. In at least one embodiment, because uops may be speculatively scheduled and executed in the processor 3900, the processor 3900 may also include logic to handle memory misses. In at least one embodiment, if a data load misses in the data cache, there may be dependent operations in progress in the pipeline past the scheduler that have temporarily incorrect data. In at least one embodiment, a replay mechanism tracks and re-executes instructions that use the incorrect data. In at least one embodiment, the dependent operations may need to be replayed, and the independent operations may be allowed to complete. In at least one embodiment, the scheduler and replay mechanism of at least one embodiment of a processor may also be designed to capture instruction sequences for text string comparison operations.

[0344] In at least one embodiment, the term "register" may refer to an on-board processor storage location that can be used as part of an instruction to identify an operand. In at least one embodiment, a register may be available externally to the processor (from a programmer's perspective). In at least one embodiment, a register may not be limited to a particular type of circuit. Rather, in at least one embodiment, a register may store data, provide data, and perform the functions described herein. In at least one embodiment, the registers described herein may be implemented by circuitry within the processor using any number of different techniques, such as dedicated physical registers, dynamically allocated physical registers using register renaming, or a combination of dedicated and dynamically allocated physical registers. In at least one embodiment, integer registers store 32-bit integer data. The register file of at least one embodiment also includes eight multimedia SIMD registers for packed data.

[0345] Inference and / or training logic 2315 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding the inference and / or training logic 2315 are provided herein in conjunction with FIG. 23A and / or FIG. 23B . In at least one embodiment, some or all of the inference and / or training logic 2315 may be incorporated into the EXE block 3911 and other memory or registers, shown or not shown. For example, in at least one embodiment, the training and / or inference techniques described herein may use one or more of the ALUs shown in the EXE block 3911. Furthermore, weight parameters may be stored in on-chip or off-chip memory and / or registers (shown or not shown) that configure the ALUs of the EXE block 3911 to execute one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0346] 40 illustrates a deep learning application processor 4000 according to at least one embodiment. In at least one embodiment, the deep learning application processor 4000 uses instructions that, when executed by the deep learning application processor 4000, cause the deep learning application processor 4000 to perform some or all of the processes and techniques described throughout this disclosure. In at least one embodiment, the deep learning application processor 4000 is an application specific integrated circuit (ASIC). In at least one embodiment, the application processor 4000 performs a matrix multiplication operation, both "hard-wired" in hardware, as a result of executing one or more instructions or both. In at least one embodiment, the deep learning application processor 4000 includes, without limitation, processing clusters 4010(1)-4010(12), inter-chip links ("ICLs") 4020(1)-4020(12), inter-chip controllers ("ICCs") 4030(1)-4030(2), high-bandwidth memory second generation ("HBM2") 4040(1)-4040(4), memory controllers ("Mem Ctrlrs") 4042(1)-4042(4), high-bandwidth memory physical layers ("HBM PHY) 4044(1)-4044(4), Management-Controller Central Processing Unit ("Management-Controller CPU") 4050, Serial Peripheral Interface, Inter-Integrated Circuit, and General-Purpose Input / Output Block ("SPI, I2C, GPIO") 4060, Peripheral Component Interconnect Express Controller and Direct Memory Access Block ("PCIe Controller and DMA") 4070, and 16-lane Peripheral Component Interconnect Express Port ("PCI Express x16") 4080.

[0347] In at least one embodiment, the processing clusters 4010 may perform deep learning operations, including inference or prediction operations, based on weight parameters calculated using one or more training techniques, including the techniques described herein. In at least one embodiment, each processing cluster 4010 may include any number and types of processors, without limitation. In at least one embodiment, the deep learning application processor 4000 may include any number and types of processing clusters 4000. In at least one embodiment, the inter-chip link 4020 is bidirectional. In at least one embodiment, the inter-chip link 4020 and the inter-chip controller 4030 enable multiple deep learning application processors 4000 to exchange information, including activation information resulting from running one or more machine learning algorithms embodied in one or more neural networks. In at least one embodiment, the deep learning application processor 4000 may include any number and types (including zero) of ICLs 4020 and ICCs 4030.

[0348] In at least one embodiment, the HBM2 4040 provides a total of 32 Gigabytes (GB) of memory. Each HBM2 4040(i) is associated with both a memory controller 4042(i) and an HBM PHY 4044(i). In at least one embodiment, any number of HBM2 4040s may provide any type and total amount of high-bandwidth memory and may be associated with any number and types of memory controllers 4042 and HBM PHYs 4044 (including zero). In at least one embodiment, the SPI, I2C, GPIO 4060, PCIe controller and DMA 4070, and / or PCIe 4080 may be replaced with any number and types of blocks enabling any number and types of communication standards in any technically feasible manner.

[0349] Inference and / or training logic 2315 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding the inference and / or training logic 2315 are provided herein in conjunction with FIG. 23A and / or FIG. 23B. In at least one embodiment, the deep learning application processor 4000 is used to train a machine learning model, such as a neural network, to predict or infer information provided to the deep learning application processor 4000. In at least one embodiment, the deep learning application processor 4000 is used to infer or predict information based on a trained machine learning model (e.g., a neural network) that has been trained by another processor or system or by the deep learning application processor 4000. In at least one embodiment, the processor 4000 may be used to perform one or more neural network use cases described herein.

[0350] FIG. 41 is a block diagram of a neuromorphic processor 4100, according to at least one embodiment. In at least one embodiment, the neuromorphic processor 4100 can receive one or more inputs from sources external to the neuromorphic processor 4100. In at least one embodiment, these inputs may be sent to one or more neurons 4102 within the neuromorphic processor 4100. In at least one embodiment, the neurons 4102 and their components may be implemented using circuitry or logic including one or more arithmetic logic units (ALUs). In at least one embodiment, the neuromorphic processor 4100 may include, without limitation, thousands or millions of instances of neurons 4102, although any suitable number of neurons 4102 may be used. In at least one embodiment, each instance of a neuron 4102 may include a neuron input 4104 and a neuron output 4106. In at least one embodiment, neuron 4102 may generate an output, which may be sent to an input of another instance of neuron 4102. For example, in at least one embodiment, neuron input 4104 and neuron output 4106 may be interconnected via synapse 4108.

[0351] In at least one embodiment, neurons 4102 and synapses 4108 may be interconnected such that neuromorphic processor 4100 operates to process or analyze information received by neuromorphic processor 4100. In at least one embodiment, neuron 4102 may send an output pulse (or "fire" or "spike") when input received via neuron input 4104 exceeds a threshold. In at least one embodiment, neuron 4102 may sum or integrate signals received at neuron input 4104. For example, in at least one embodiment, neuron 4102 may be implemented as a leaky integrate-and-fire neuron, where if the sum (referred to as the "membrane potential") exceeds a threshold, neuron 4102 may generate an output (or "fire") using a transfer function such as a sigmoid function or a threshold function. In at least one embodiment, a leaky integrate-and-fire neuron may sum signals received at neuron input 4104 into a membrane potential and may apply a decay factor (or leakage) to reduce the membrane potential. In at least one embodiment, a leaky integrate-and-fire neuron may fire if multiple input signals are received at neuron input 4104 quickly enough to exceed a threshold (i.e., before the membrane potential decays too little to cause firing). In at least one embodiment, neuron 4102 may be implemented using circuitry or logic that receives inputs, integrates the inputs into a membrane potential, and decays the membrane potential. In at least one embodiment, the inputs may be averaged, or any other suitable transfer function may be used. Further, in at least one embodiment, neuron 4102 may include, without limitation, comparator circuitry or logic that generates an output spike at neuron output 4106 when the result of applying the transfer function to neuron input 4104 exceeds a threshold. In at least one embodiment, neuron 4102 may ignore previously received input information when firing, for example, by resetting the membrane potential to 0 or another suitable default value.In at least one embodiment, once the membrane potential is reset to zero, neuron 4102 may resume normal operation after a suitable period (or refractory period).

[0352] In at least one embodiment, neurons 4102 may be interconnected through synapses 4108. In at least one embodiment, synapses 4108 may operate to transmit a signal from an output of a first neuron 4102 to an input of a second neuron 4102. In at least one embodiment, neurons 4102 may transmit information through two or more instances of synapses 4108. In at least one embodiment, one or more instances of neuron outputs 4106 may be connected to instances of neuron inputs 4104 of the same neuron 4102 through instances of synapses 4108. In at least one embodiment, an instance of neuron 4102 that generates an output to be transmitted through an instance of synapse 4108 may be referred to as a "pre-synaptic neuron" with respect to that instance of synapse 4108. In at least one embodiment, an instance of neuron 4102 that receives an input to be transmitted through an instance of synapse 4108 may be referred to as a "post-synaptic neuron" with respect to that instance of synapse 4108. In at least one embodiment, an instance of neuron 4102 may receive input from one or more instances of synapse 4108 and may send output through one or more instances of synapse 4108, so that a single instance of neuron 4102 may therefore be both a "pre-synaptic neuron" and a "post-synaptic neuron" with respect to various instances of synapse 4108.

[0353] In at least one embodiment, neurons 4102 may be organized into one or more layers. Each instance of a neuron 4102 may have one neuron output 4106 that can fan out to one or more neuron inputs 4104 through one or more synapses 4108. In at least one embodiment, a neuron output 4106 of a neuron 4102 in a first layer 4110 may be connected to a neuron input 4104 of a neuron 4102 in a second layer 4112. In at least one embodiment, a layer 4110 may be referred to as a "feed-forward layer." In at least one embodiment, each instance of a neuron 4102 in an instance of a first layer 4110 may fan out to each instance of a neuron 4102 in a second layer 4112. In at least one embodiment, the first layer 4110 may be referred to as a "fully connected feed-forward layer." In at least one embodiment, each instance of a neuron 4102 in the second layer 4112 may fan out to fewer than all instances of a neuron 4102 in the third layer 4114. In at least one embodiment, the second layer 4112 may be referred to as a "sparsely connected feed-forward layer." In at least one embodiment, the neurons 4102 in the second layer 4112 may fan out to neurons 4102 in multiple other layers, including neurons 4102 in the same second layer 4112. In at least one embodiment, the second layer 4112 may be referred to as a "recurrent layer." The neuromorphic processor 4100 may include, without limitation, any suitable combination of recurrent and feed-forward layers, including, without limitation, both sparsely connected feed-forward layers and fully connected feed-forward layers.

[0354] In at least one embodiment, the neuromorphic processor 4100 may include, without limitation, a reconfigurable interconnect architecture or dedicated hardwired interconnects for connecting the synapses 4108 to the neurons 4102. In at least one embodiment, the neuromorphic processor 4100 may include, without limitation, circuitry or logic that allows synapses to be allocated to different neurons 4102 as needed based on the neural network topology and the fan-in / fan-out of the neurons. For example, in at least one embodiment, the synapses 4108 may be connected to the neurons 4102 using an interconnect fabric, such as a network-on-chip, or using dedicated connections. In at least one embodiment, the synaptic interconnects and their components may be implemented using circuitry or logic.

[0355] 42 is a block diagram of a processing system according to at least one embodiment. In at least one embodiment, system 4200 includes one or more processors 4202 and one or more graphics processors 4208 and may be a single-processor desktop system, a multi-processor workstation system, or a server system having multiple processors 4202 or processor cores 4207. In at least one embodiment, system 4200 is a processing platform integrated into a system-on-chip (SoC) integrated circuit for use in a mobile, handheld, or embedded device.

[0356] In at least one embodiment, system 4200 may include or be incorporated into a server-based gaming platform, a game console including a game and media console, a mobile gaming console, a handheld game console, or an online game console. In at least one embodiment, system 4200 is a mobile phone, a smart phone, a tablet computing device, or a mobile internet device. In at least one embodiment, processing system 4200 may also include, be coupled to, or be integrated into a wearable device, such as a smart watch wearable device, a smart eyewear device, an augmented reality device, or a virtual reality device. In at least one embodiment, processing system 4200 is a television or set-top box device having one or more processors 4202 and a graphical interface generated by one or more graphics processors 4208.

[0357] In at least one embodiment, the one or more processors 4202 each include one or more processor cores 4207 for processing instructions that, when executed, perform operations for system and user software. In at least one embodiment, each of the one or more processor cores 4207 is configured to process a particular instruction set 4209. In at least one embodiment, the instruction set 4209 may facilitate computing via complex instruction set computing (CISC), reduced instruction set computing (RISC), or very long instruction word (VLIW). In at least one embodiment, each processor core 4207 may process a different instruction set 4209, which may include instructions that facilitate emulation of other instruction sets. In at least one embodiment, the processor cores 4207 may also include other processing devices, such as a digital signal processor (DSP).

[0358] In at least one embodiment, processor 4202 includes cache memory 4204. In at least one embodiment, processor 4202 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, cache memory is shared among various components of processor 4202. In at least one embodiment, processor 4202 also uses an external cache (e.g., a level 3 (L3) cache or last level cache (LLC)) (not shown), which may be shared among processor cores 4207 using known cache coherence techniques. In at least one embodiment, processor 4202 further includes a register file 4206, which may include different types of registers (e.g., integer registers, floating-point registers, status registers, and instruction pointer registers) for storing different types of data. In at least one embodiment, register file 4206 may include general-purpose registers or other registers.

[0359] In at least one embodiment, the one or more processors 4202 are coupled to one or more interface buses 4210 to transmit communication signals, such as address, data, or control signals, between the processor 4202 and other components in the system 4200. In at least one embodiment, the interface bus 4210 may be a processor bus, such as, in one embodiment, a version of a Direct Media Interface (DMI) bus. In at least one embodiment, the interface 4210 is not limited to a DMI bus, but may include one or more Peripheral Component Interconnect buses (e.g., PCI, PCI Express), a memory bus, or other types of interface buses. In at least one embodiment, the processor 4202 includes an integrated memory controller 4216 and a platform controller hub 4230. In at least one embodiment, the memory controller 4216 facilitates communication between memory devices and other components of the system 4200, while the platform controller hub (PCH) 4230 provides connectivity to I / O devices via a local I / O bus.

[0360] In at least one embodiment, memory device 4220 may be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase change memory device, or any other memory device with performance suitable for serving as process memory. In at least one embodiment, memory device 4220 may operate as system memory for system 4200, storing data 4222 and instructions 4221 for use by one or more processors 4202 when executing applications or processes. In at least one embodiment, memory controller 4216 also couples to an optional external graphics processor 4212, which may communicate with one or more graphics processors 4208 within processor 4202 to perform graphics and media operations. In at least one embodiment, a display device 4211 may be connected to processor 4202. In at least one embodiment, display device 4211 may include one or more of an internal display device, such as a mobile electronic device or laptop device, or an external display device attached via a display interface (e.g., a display port, etc.). In at least one embodiment, display device 4211 may include a head-mounted display (HMD), such as a stereoscopic display device for use in virtual reality (VR) or augmented reality (AR) applications.

[0361] In at least one embodiment, the platform controller hub 4230 allows peripheral devices to connect to the memory device 4220 and the processor 4202 via a high-speed I / O bus. In at least one embodiment, the I / O peripherals include, but are not limited to, an audio controller 4246, a network controller 4234, a firmware interface 4228, a wireless transceiver 4226, a touch sensor 4225, and a data storage device 4224 (e.g., hard disk drive, flash memory, etc.). In at least one embodiment, the data storage device 4224 can be connected via a storage interface (e.g., SATA) or via a peripheral bus such as a peripheral component interconnect bus (e.g., PCI, PCI Express). In at least one embodiment, the touch sensor 4225 can include a touch screen sensor, a pressure sensor, or a fingerprint sensor. In at least one embodiment, wireless transceiver 4226 may be a WiFi transceiver, a Bluetooth transceiver, or a mobile network transceiver such as a 3G, 4G, or Long Term Evolution (LTE) transceiver. In at least one embodiment, firmware interface 4228 enables communication with system firmware and may be, for example, a Unified Extensible Firmware Interface (UEFI). In at least one embodiment, network controller 4234 may enable network connectivity to a wired network. In at least one embodiment, a high-performance network controller (not shown) couples to interface bus 4210. In at least one embodiment, audio controller 4246 is a multi-channel high-definition audio controller. In at least one embodiment, system 4200 includes an optional legacy I / O controller 4240 for coupling legacy (e.g., Personal System 2 (PS / 2)) devices to the system.In at least one embodiment, platform controller hub 4230 can also connect to one or more universal serial bus (USB) controller 4242 connected input devices, such as a keyboard and mouse 4243 combination, a camera 4244, or other USB input devices.

[0362] In at least one embodiment, instances of memory controller 4216 and platform controller hub 4230 may be integrated into a separate external graphics processor, such as external graphics processor 4212. In at least one embodiment, platform controller hub 4230 and / or memory controller 4216 may be external to one or more processors 4202. For example, in at least one embodiment, system 4200 may include an external memory controller 4216 and platform controller hub 4230, which may be configured as a memory controller hub and a peripheral controller hub within a system chipset...

Claims

1. one or more circuits that use one or more neural networks to cause the one or more robotic gripping mechanisms to grasp one or more objects based at least in part on tactile sensor data of the one or more robotic gripping mechanisms; training the neural network is based at least in part on one or more images of a human hand performing a grasp; the image of the human hand performing the grasp is a component of a reward function; The components of the reward function are calculated by using an average of four key-point locations on the top surface of the object.

2. 10. The processor of claim 1, wherein the one or more circuits use the one or more neural networks to determine a pose of the one or more robotic gripping mechanisms based at least in part on one or more tactile sensors.

3. the one or more objects comprise a virtual bounding box; the one or more neural networks are trained based at least in part on tactile sensor data from one or more sensors of the robotic gripping mechanism; The processor of claim 1 .

4. 10. The processor of claim 1, wherein an object grasped by the robotic grasping mechanism has a different shape than the one or more objects used to train the one or more neural networks.

5. the robotic gripping mechanism is a robotic hand having multiple fingers; Each of the plurality of fingers is provided with one or more tactile sensors. The processor of claim 1 .

6. The camera captures an image of the object being grasped, the images are used to estimate a 6D pose of the object; the virtual bounding box is generated based at least in part on the 6D pose of the object. The processor of claim 3 .

7. The processor of claim 3 , wherein the virtual bounding box is generated based at least in part on a point cloud of the object.

8. one or more circuits that use one or more neural networks to cause the one or more robotic gripping mechanisms to grasp one or more objects based at least in part on tactile sensor data of the one or more robotic gripping mechanisms; one or more memories for storing said one or more neural networks; the one or more neural networks are trained using a reward function; the reward function is based at least in part on a position of the robotic gripping mechanism relative to the object; The components of the reward function are calculated by using an average of four key-point locations on the top surface of the object.

9. 10. The system of claim 8, wherein the one or more circuits use the one or more neural networks to determine a pose of the one or more robotic gripping mechanisms based at least in part on one or more tactile sensors.

10. the one or more objects comprise a virtual bounding box; the one or more neural networks are trained based at least in part on tactile sensor data from one or more sensors of the robotic gripping mechanism; The system of claim 8.

11. 10. The system of claim 8, wherein training the one or more neural networks is accomplished based at least in part on human demonstrations of grasps provided to the system.

12. The system of claim 8 , wherein one or more tactile sensors provide force-sensing information indicative of contact with the object.

13. the robotic gripping mechanism having a plurality of fingers with a plurality of articulated joints; an action space for the system is defined as the position of each of the plurality of articulated joints; The system of claim 8.

14. the reward function is based at least in part on a demonstration of human hand motion; the reward function is based at least in part on a difference between the positions of the fingertips of the human hand and the fingertips of the robotic gripping mechanism. The system of claim 8.

15. The system of claim 8 , wherein the reward function is based at least in part on the ability of the robotic grasping mechanism to lift the object.

16. The processor: capturing an image of the object with a camera; Estimating a bounding box surrounding the object; The processor of claim 1 , wherein the processor is part of a computer system that positions the robotic gripping mechanism based at least in part on the bounding cuboid.

17. the neural network is based at least in part on rewards; the reward is based at least in part on the ability to successfully lift the grasped object; The processor of claim 1 .

18. 20. The processor of claim 17, wherein the reward is based at least in part on a comparison between a grasp style of a human hand and a grasp style of a robotic hand.

19. The processor of claim 1 , wherein the arbitrarily shaped objects are arranged in rectangular bounding boxes.

20. The processor of claim 1 , wherein training the neural network is formulated as a context policy research problem.

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