Controllable electromagnetic array elements and intelligence surfaces

Abstract

An embodiment of the present application provides a controllable electromagnetic array element and an intelligence surface, the controllable electromagnetic array element includes a reflecting unit and a parasitic unit, the reflecting unit includes at least one reflecting metal piece and at least one controllable element electrically connected to the reflecting metal piece and configured to control an electromagnetic parameter of the electromagnetic array element in response to a control signal, and the parasitic unit is disposed around the reflecting metal piece and is coupled to the reflecting metal piece.

Description

[Technical Field]

[0001] This application is filed based on and claims priority from a Chinese patent application bearing application number 202111331397.9 and filing date November 11, 2021, the entire contents of which are hereby incorporated by reference into this application.

[0002] FIELD Embodiments of the present application relate to the technical field of wireless communications, and more particularly to controllable electromagnetic array elements and intelligent surfaces. [Background technology]

[0003] Reconfigurable intelligent surfaces (RIS) are a key technology in wireless communications and are gaining industry recognition. RIS can create specific beam directionality by controlling the electrical parameters of the electromagnetic array elements, thereby filling or enhancing blind signals in desired areas. Reflective RIS can cover signals beyond the line of sight of the base station, making it a promising candidate for future applications. Reflective RIS can be divided into single-bit and multi-bit types based on the number of phase states of the reflected electromagnetic wave, single-polarized and multi-polarized types based on the polarization characteristics of the reflected wave, and static and dynamic types based on whether the reflected beam can be electronically switched.

[0004] Currently, RIS schemes generally have poor performance. For example, RIS cannot yet meet the performance requirements for multi-bit multi-polarization. In addition, the performance of RIS is currently limited by factors such as the layout of the array elements and the dielectric substrate, resulting in high manufacturing costs and difficulties. Summary of the Invention [Problem to be solved by the invention]

[0005] The following is a summary of the subject matter described in detail herein, which does not limit the scope of protection of the claims.

[0006] Embodiments of the present application provide controllable electromagnetic array elements and intelligent surfaces. [Means for solving the problem]

[0007] In a first aspect, the present embodiment comprises: A controllable electromagnetic array element, Includes a reflective unit and a parasitic unit, The reflection unit is at least one reflective metal piece; at least one controllable element electrically connected to the reflective metal strip and configured to control an electromagnetic parameter of the electromagnetic array element in response to a control signal; The parasitic unit provides a controllable electromagnetic array element disposed around and coupled to the reflective metal strip.

[0008] In a second aspect, embodiments of the present application provide an intelligence surface comprising a plurality of controllable electromagnetic array elements according to the first aspect.

[0009] In order to more clearly explain the technical solutions in the embodiments of the present application, the drawings that need to be used in the embodiments or related technical descriptions are briefly described below. The drawings in the following description are only some examples of the embodiments of the present application, and those skilled in the art can derive other drawings from these drawings without any creative efforts. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 2 is a structural schematic diagram of a reflective circuit layer of a controllable electromagnetic array element according to an embodiment of the present application; [Figure 2] FIG. 2 is a structural schematic diagram of a bias circuit layer of a controllable electromagnetic array element according to an embodiment of the present application; [Figure 3]FIG. 2 is a schematic diagram of a layer structure of a controllable electromagnetic array element according to one embodiment of the present application. [Figure 4] FIG. 10 is a structural schematic diagram of a reflective circuit layer of a controllable electromagnetic array element according to another embodiment of the present application. [Figure 5] FIG. 10 is a structural schematic diagram of a bias circuit layer of a controllable electromagnetic array element according to another embodiment of the present application. [Figure 6] FIG. 1 is a structural schematic diagram of a conventional RIS according to another embodiment of the present application. [Figure 7] FIG. 1 is a structural schematic diagram of a parasitic metasurface according to another embodiment of the present application. [Figure 8] FIG. 10 is a phase response waveform diagram of a RIS according to another embodiment of the present application. [Figure 9] FIG. 10 is an amplitude response waveform diagram of a RIS according to another embodiment of the present application. [Figure 10] FIG. 10 is a cross-polarization suppression waveform diagram of the RIS according to another embodiment of the present application. [Figure 11] FIG. 10 is a waveform diagram corresponding to the multi-angle beam pointing amplitude of the RIS according to one embodiment of the present application. [Figure 12] FIG. 10 is a waveform diagram corresponding to the multi-angle beam steering amplitude of the RIS according to another embodiment of the present application. [Figure 13] FIG. 10 is a waveform diagram corresponding to the multi-angle beam steering amplitude of the RIS according to another embodiment of the present application. [Figure 14] FIG. 10 is a structural schematic diagram of a reflective circuit layer of a controllable electromagnetic array element according to another embodiment of the present application. [Figure 15] FIG. 10 is a structural schematic diagram of a parasitic circuit layer of a controllable electromagnetic array element according to another embodiment of the present application. [Figure 16] FIG. 1 is a schematic diagram of a front-side structure of a parasitic metasurface according to another embodiment of the present application. [Figure 17] FIG. 1 is a schematic diagram of the backside structure of a parasitic metasurface according to another embodiment of the present application. [Figure 18] FIG. 10 is a structural schematic diagram of a reflective circuit layer of a controllable electromagnetic array element according to another embodiment of the present application. [Figure 19]FIG. 1 is a schematic diagram of a front-face structure of a parasitic hyper-surface according to another embodiment of the present application. DETAILED DESCRIPTION OF THE INVENTION

[0011] In the following description, specific details, such as particular system configurations, techniques, etc., are provided for purposes of explanation and not limitation in order to thoroughly understand the embodiments of the present application. However, the embodiments of the present application may also be practiced in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the embodiments of the present application with unnecessary detail.

[0012] It should be noted that although a logical order is shown in the flowchart, the steps shown or described may, in some cases, be performed in an order different from that shown in the flowchart. Terms such as "first," "second," etc. in the specification and claims, as well as in the above drawings, are not used to describe a particular order or priority, but rather to distinguish between similar objects.

[0013] Additionally, a reference to "one embodiment" or "some embodiments" in the specification of an embodiment of the present application means that a particular feature, structure, or characteristic described with reference to that embodiment is included in one or more of the embodiments of the present application. Thus, unless specifically stated otherwise, phrases such as "in one embodiment," "in some embodiments," "in other embodiments," and "in other embodiments" appearing in different places throughout this specification do not necessarily all refer to the same embodiment, but rather mean "one or more, but not all, embodiments." The terms "include," "including," "having," and variations thereof mean "including, but not limited to," unless specifically stated otherwise.

[0014] An intelligent surface is a two-dimensional planar array consisting of a large number of passive electromagnetic array elements, arranged according to a set of rules and with negligible thickness. Because these specially designed electromagnetic array elements exhibit physical properties not found in natural materials, these two-dimensional arrays of artificial electromagnetic array elements are also known as metasurfaces. Each electromagnetic array element is made of a specific shaped metal or dielectric material and connected to electronic elements (controllable elements). The electronic elements are controlled by an intelligent controller on the panel, allowing for individual adjustment of the electromagnetic properties (e.g., average permeability, average permittivity) of the electromagnetic array element. By controlling the electromagnetic properties of the electromagnetic array element, electromagnetic signals incident on the surface of the electromagnetic array element can be reflected or transmitted with various amplitudes, phases, polarization directions, etc., thereby establishing a virtual direct radiation path between the base station and the user terminal, achieving the goal of intelligently controlling the spatial electromagnetic environment. The intelligent surface uses an intelligent controller to simultaneously send independent control commands to each electromagnetic array element, causing corresponding changes in amplitude, phase, or polarization direction when the electromagnetic waves incident on the surface of the electromagnetic array element are reflected or transmitted, and the electromagnetic waves reflected or transmitted by all the electromagnetic array elements are spatially superimposed to create a beamforming effect, and finally received by a specific terminal device. The introduction of intelligent surfaces into wireless communication systems can expand and efficiently utilize spatial resources, which is beneficial for improving wireless communication system channel capacity, improving communication reliability, extending coverage, reducing transmission power consumption, and saving costs.

[0015] Reconfigurable intelligence surfaces (RIS) are considered by the industry to be one of the key potential technologies for future mobile communications (e.g., 6G). RIS can create specific beam directionality by controlling the electrical parameters of the electromagnetic array elements, thereby filling or enhancing blind signals in desired areas. RIS can be divided into transmission and reflection types based on their functions. Transmission types create beam directionality in the direction of the incoming wave, while reflection types create beam directionality on the other side of the incoming wave direction. Reflection-type RIS can be hung on the surface of building walls and can cover signals within the line of sight of the base station, showing great potential for future applications.

[0016] Reflective RIS can be divided into single-bit and multi-bit types according to the number of phase states of the reflected electromagnetic wave, single-polarized and multi-polarized types according to the polarization characteristics of the reflected wave, and static and dynamic types according to whether the reflected beam can be switched electronically. Obviously, reflective RIS that supports multi-bit, dual-polarized, and dynamic functions has the most comprehensive functions and the highest application value.

[0017] Currently, research into RIS focuses on 1+1 (1 bit + single polarization), 2+1 (2 bit + single polarization), and 1+2 (1 bit + dual polarization) schemes. However, the performance of current RIS schemes is not ideal. The applicant has discovered that this situation arises due to the following technical challenges:

[0018] 1) Multi-bit requires more switching elements, which not only increases the complexity and power consumption of the control circuit, but also changes the electromagnetic characteristics of the electromagnetic array elements, causing a mismatch between the RIS and the spatial wave impedance, thereby reducing the reflection efficiency. 2) Multiple polarizations have an inter-polarization coupling effect, which deteriorates the phase condition of a single polarization and affects the independent electrical adjustment ability between different polarizations, resulting in the loss of the diversity gain brought by multiple polarizations. 3) The electromagnetic properties of the metasurface are closely related to the arrangement of the electromagnetic array elements and the spacing between the array elements. When the RIS polarization method or array layout is changed, the spatial sparseness of the electromagnetic array elements changes the RIS configuration parameters (equivalent permeability, equivalent permittivity), which causes a performance degradation. 4) Similarly, the loss of a RIS is closely related to the dielectric substrate. Generally, the thicker the dielectric substrate and the lower its dielectric constant, the smaller the reflection loss. For example, for a Sub-6G RIS, the lower the frequency, the thicker the substrate required, which results in increased cost and manufacturing difficulty.

[0019] Therefore, currently, RIS schemes generally have poor performance. Moreover, the performance of RIS is limited by factors such as the layout of the array elements and the dielectric substrate, resulting in high manufacturing costs and difficulties.

[0020] Based on this, an embodiment of the present application provides a controllable electromagnetic array element and an intelligent surface. The controllable electromagnetic array element includes a reflective unit 110 and a parasitic unit 120. The reflective unit 110 includes at least one reflective metal piece and at least one controllable element 112 electrically connected to the reflective metal piece and configured to control electromagnetic parameters of the electromagnetic array element in response to a control signal. The parasitic unit 120 is disposed around the reflective metal piece and coupled to the reflective metal piece. In this embodiment, the parasitic unit 120 is disposed around the reflective unit 110 of the controllable electromagnetic array element to form a parasitic intelligent surface. The coupling effect between the parasitic unit 120 and the electromagnetic array element is used to change the configuration parameters of the intelligent surface, thereby reducing the reflection loss of the intelligent surface and improving the stability of the phase response of the intelligent surface, breaking through the performance limitations of the array element layout and the dielectric substrate for the intelligent surface, and advantageously improving the reliability of multi-bit multi-polarization RIS schemes.

[0021] For example, in some embodiments of the present application, a parasitic metasurface multi-polarization multi-bit RIS technology is provided. This parasitic metasurface technology is used to design a dynamic 2+2 (2-bit + dual-polarization) reflective RIS based on a lattice-like parasitic metasurface with an orthogonal lattice layout, thereby suppressing cross-polarization reflections while reducing losses and realizing a ±45° dual-polarization 2-bit independently electrically tuned RIS. This technology and design scheme solves many important technical challenges in the design of dynamic multi-polarization multi-bit reflective RISs and fills the gap in this type of product.

[0022] Unless otherwise specified, the RIS below refers to a dynamic reflective RIS. This example is applicable to indoor and outdoor wireless communications, signal relay, and other scenarios, specifically to base stations, small stations, electromagnetic reflectors, and relay devices. This application can be used for indoor and outdoor wireless signal reinforcement and blind filling, as well as for passive relay between stations. Hereinafter, the intelligence surface may be composed of multiple controllable electromagnetic array elements. The multiple controllable electromagnetic array elements may be arranged in an M*N matrix or may adopt other arrangement methods, but this application is not limited thereto. The parasitic unit 120 may be a periodic parasitic unit 120, i.e., macroscopically, it may be a periodic extension of the parasitic unit 120 of each array element of the intelligence surface.

[0023] Referring to Figures 1 and 4, the controllable electromagnetic array elements include: a reflective unit 110 and a parasitic unit 120; The reflection unit 110 includes: at least one reflective metal piece; at least one controllable element 112 electrically connected to the reflective metal strip and configured to control an electromagnetic parameter of the electromagnetic array element in response to a control signal; The parasitic unit 120 is disposed around the reflective metal piece and is bonded to the reflective metal piece.

[0024] In some embodiments, this application proposes a technology for a multi-polarized, multi-bit reflective reconfigurable intelligent surface based on a parasitic metasurface. This technology involves nesting a periodic parasitic unit 120 around a conventional electromagnetic scattering unit to form a parasitic metasurface. The parasitic metasurface then utilizes the capacitive coupling effect between the reflective unit 110 and the periodic parasitic unit 120 to generate a traveling wave current and change the configuration parameters of the metasurface, thereby changing the matching characteristics of the reflective metasurface and the spatial wave impedance, thereby improving the reflection efficiency and phase response. This technology improves the impact of changes in the size, spatial layout (pitch, orientation, and position) of the electromagnetic array elements, switching elements, and dielectric substrate on the electromagnetic response characteristics of the metasurface, laying the foundation for a low-cost, low-profile, and highly stable multi-polarized, multi-bit RIS.

[0025] In some embodiments, the present application utilizes parasitic metasurface technology (a surface material with a periodic arrangement of periodic metallic unit structures) to design a multi-bit multi-polarization reflective RIS based on a lattice-like parasitic metasurface. By aligning the periodic parasitic units 120 in the lattice-like parasitic metasurface with the polarization direction of the reflective units 110, the reflective efficiency and phase response are improved, while the polarization current is strengthened and cross-polarization current is suppressed, ensuring independent electrical tuning between multi-polarization reflection wavelengths. For example, in some embodiments, the reflective RIS can support ±45° dual-polarization 2-bit independent control. Even with cross-polarized materials, the cross-sectional height (thickness) of the reflective surface can be designed to be as low as 0.05 wavelengths, the center frequency reflection loss is less than 3.4 dB, cross-polarization reflection waves are suppressed by more than 52 dB, and the operating bandwidth reaches more than 6%. These indicators are superior to those of current RIS schemes. In other words, compared to current RIS schemes, the technology of this application can reduce the cross-sectional height (thickness) of the RIS, lower losses, better suppress cross-polarized reflections, and increase the operating bandwidth, thereby reducing costs and fabrication difficulties while improving RIS performance. The better the materials, the greater the effect of this application.

[0026] In some embodiments, the length and width dimensions of the controllable electromagnetic array elements may be designed to be, for example, 0.2 to 1 central wavelength, or 0.7 to 0.8 central wavelength, as needed, but the present application is not limited thereto.

[0027] In some embodiments, the shape of the parasitic unit 120 is not limited, and any parasitic unit 120 that couples to the reflective unit 110 and provides adequate coupling strength is effective.

[0028] The embodiment of the present application configures a parasitic unit 120 around the reflective unit 110 of the controllable electromagnetic array element to configure a parasitic intelligent surface, and utilizes the coupling effect between the parasitic unit 120 and the electromagnetic array element to change the configuration parameters of the intelligent surface, thereby reducing the reflection loss of the intelligent surface, improving the stability of the phase response of the intelligent surface, breaking through the performance limitations of the array element layout and the dielectric substrate intelligent surface, and advantageously improving the reliability of the multi-bit multi-polarization RIS scheme.

[0029] In some embodiments, the parasitic unit 120 is coupled to the reflecting unit 110 and is provided in the same layer as the reflecting unit 110; Alternatively, the parasitic unit 120 is provided on an upper layer of the reflective unit 110 so as to be coupled to the reflective unit 110; Alternatively, the parasitic unit 120 is provided below the reflective unit 110 so as to be coupled to the reflective unit 110 .

[0030] In some embodiments, the parasitic intelligence surface technology of the present application involves nesting a periodic parasitic unit 120 around the reflective unit 110 of the electromagnetic array element of the related art, and the mounting position of the parasitic unit 120 may be on the same layer, an upper layer, or a lower layer. In the following description, the electromagnetic array element has a multi-layer structure, and the layer on which the reflective unit 110 is located is the reflective circuit layer 100.

[0031] In some embodiments, mounting on the same layer means that both the parasitic unit 120 and the reflective unit 110 are provided on the reflective circuit layer 100. For example, the parasitic unit 120 and the reflective unit 110 are provided on the same surface of a dielectric plate, and the parasitic unit 120 and the reflective unit 110 are coupled to each other by forming a coupling slot in the horizontal direction, or the parasitic unit 120 and the reflective unit 110 are coupled to each other by an element (such as a resistor). Here, both the parasitic unit 120 and the reflective unit 110 may include a metal piece, which may be a metal piece attached to the dielectric plate or a metal piece plated or coated on the dielectric plate, and the present application is not limited thereto.

[0032] In some embodiments, "mounted on the upper layer" means that the parasitic unit 120 is provided on the upper layer of the reflective unit 110. For example, the parasitic unit 120 may be supported by a bracket or a dielectric plate on the reflective circuit layer 100 on which the reflective unit 110 is located. When the parasitic unit 120 is supported by a bracket on the reflective circuit layer 100 on which the reflective unit 110 is located, an air gap is formed between the parasitic unit 120 and the reflective unit 110. When the parasitic unit 120 is supported by a dielectric plate on the reflective circuit layer 100 on which the reflective unit 110 is located, a dielectric plate is provided between the parasitic unit 120 and the reflective unit 110. The parasitic unit 120 and the reflective unit 110 are coupled to each other by forming a coupling slot in the vertical direction, or the parasitic unit 120 and the reflective unit 110 are coupled to each other by an element (such as a resistor).

[0033] In some embodiments, mounting on a lower layer means that the parasitic unit 120 is provided on a layer below the reflective unit 110. For example, the parasitic unit 120 may be provided below the reflective circuit layer 100 on which the reflective unit 110 is located, with a dielectric plate provided between the parasitic unit 120 and the reflective unit 110. The parasitic unit 120 and the reflective unit 110 are coupled to each other by forming a coupling slot in the vertical direction, or the parasitic unit 120 and the reflective unit 110 are coupled to each other by an element (such as a resistor).

[0034] In practical design, the same layer mounting, upper layer mounting or lower layer mounting of the parasitic unit 120 can be selected as needed to achieve better reflected wave amplitude and phase response.

[0035] In some embodiments, a coupling slot is formed between the parasitic unit 120 and the reflective unit 110, the parasitic unit 120 and the reflective unit 110 are connected by electric field coupling, or the parasitic unit 120 and the reflective unit 110 are coupled by an element.

[0036] In some embodiments, the parasitic metasurface of the present application includes, in terms of coupling scheme, electric field coupling between the parasitic unit 120 and the reflective unit 110 and element coupling between the parasitic unit 120 and the reflective unit 110.

[0037] In some embodiments, the electric field coupling between the parasitic unit 120 and the reflective unit 110 means forming a coupling slot between the parasitic unit 120 and the reflective unit 110, i.e., the coupling slot separates the parasitic unit 120 from the reflective unit 110. In terms of the circuit, in the case of a direct current, there is a disconnection between the parasitic unit 120 and the reflective unit 110, and in the case of a high-frequency RF signal, there is one coupling, i.e., an electric field coupling, between the direct current parasitic unit 120 and the reflective unit 110.

[0038] In some embodiments, the element coupling between the parasitic unit 120 and the reflective unit 110 means that the parasitic unit 120 and the reflective unit 110 are connected by an element (such as a resistor), i.e., the parasitic unit 120 and the reflective unit 110 are connected in a DC manner to realize the element coupling.

[0039] In some embodiments, the reflecting unit 110 is disposed at the center of the controllable electromagnetic array element, and the parasitic unit 120 is disposed at the periphery of the controllable electromagnetic array element and is coupled to the reflecting unit 110 so as to be in the polarization direction of the reflecting unit 110.

[0040] In some embodiments, the reflecting unit 110 may be provided on the surface of the controllable electromagnetic array element, ie, in the center of the reflecting circuit layer 100, to perform signal reflection.

[0041] In some embodiments, the parasitic unit 120 is arranged in the polarization direction of the reflecting unit 110. For example, in the case of a cross-shaped dual-polarization reflecting unit 110 as shown in FIG. 1 , the parasitic unit 120 is arranged to extend in four directions of the cross-shaped reflecting unit 110 and is coupled to the reflecting unit 110.

[0042] In some embodiments, the reflective metal piece comprises: a first metal piece 111 configured to be electrically connected to ground; a bias voltage strip 113 electrically connected to the first metal strip 111 by the controllable element 112 and configured to receive a control signal and transmit the control signal to the controllable element 112.

[0043] 3, in some embodiments, the electromagnetic array element is a multi-layer structure including a reflective circuit layer 100, a base layer, and a bias circuit layer 200, where the reflective circuit layer 100 and the base layer are separated by a first dielectric plate 510, and the base layer and the bias circuit layer 200 are separated by a second dielectric plate 520. A first metal piece 111 on the reflective circuit layer 100 is located at the center of the reflective unit 110, and the first metal piece 111 can be electrically connected to the base layer through a metal via that penetrates the first dielectric plate 510 to achieve grounding.

[0044] In some embodiments, the number of bias voltage strips 113 corresponds to the number of controllable elements 112. The bias voltage strips 113 are electrically connected to the bias circuit layer 200 through metal vias that sequentially pass through the first dielectric plate 510 and the second dielectric plate 520, and can receive control signals from the bias circuit layer 200.

[0045] In some embodiments, the shape of the first metal piece 111 is not limited. For example, the first metal piece 111 may be a polygonal metal piece or a circular metal piece. The polygonal metal piece may be a square metal piece, a rectangular metal piece, or a trapezoidal metal piece, but the present application is not limited thereto.

[0046] In some embodiments, the first metal piece 111 is a polygonal metal piece, and the parasitic unit 120 is disposed along a corresponding edge of the polygonal metal piece, such that at least one edge of the parasitic unit 120 forms a strip-shaped coupling slot with at least one edge of the polygonal metal piece; or, The first metal piece is a circular metal piece, and the parasitic unit 120 is correspondingly provided along the circumference of the circular metal piece, such that the edge of the parasitic unit 120 forms an annular coupling slot with the edge of the polygonal metal piece.

[0047] In some embodiments, when the first metal piece 111 is a polygonal metal piece, one side of the parasitic unit 120 forms a strip-shaped coupling slot with one side of the first metal piece 111. In another embodiment, N sides of the parasitic unit 120 may form N strip-shaped coupling slots with N sides of the first metal piece 111, but this application is not limited thereto.

[0048] In some embodiments, a second metal piece 114 is further provided between the first metal piece 111 and the bias voltage piece 113, the bias voltage piece 113 is electrically connected to the second metal piece 114, and the second metal piece 114 is electrically connected to the first metal piece 111 by the controllable element 112; The parasitic unit 120 is provided along a corresponding edge of the second metal piece 114 such that at least one edge of the parasitic unit 120 forms a coupling slot with at least one edge of the second metal piece 114 .

[0049] In some embodiments, the second metal piece 114 is a polygonal metal piece, and one side of the parasitic unit 120 forms a strip-shaped coupling slot with one side of the second metal piece 114. In another embodiment, N sides of the parasitic unit 120 may form N strip-shaped coupling slots with N sides of the second metal piece 114, but this application is not limited thereto.

[0050] 1 and 4 , in some embodiments, the first metal piece 111 is a generally rectangular metal piece, and four groove structures configured to accommodate one end of the controllable element 112 are formed in the center of each of the four sides of the first metal piece 111. Four second metal pieces 114 are provided extending along the four sides of the rectangular first metal piece 111, and each of the four second metal pieces 114 is an elongated polygonal metal piece. The second metal piece 114 has chamfered edges on both ends of the edge closest to the first metal piece 111, allowing the four second metal pieces 114 to be arranged around the first metal piece 111. The second metal piece 114 has a groove formed on the long edge closest to the first metal piece 111, configured to accommodate one end of the controllable element 112. The second metal piece 114 has a groove formed on the long edge away from the first metal piece 111, configured to accommodate one end of the inductance element 115. Four bias voltage pieces 113 are provided on the outer sides of the four second metal pieces 114 correspondingly, and four parasitic units 120 are provided along the outer edges of the four second metal pieces 114, i.e., the parasitic units 120 are provided in the polarization direction of the reflective unit 110, forming a cross-shaped dual-polarized reflective electromagnetic array element. The bias voltage pieces 113 are electrically connected to the second metal pieces 114, and the second metal pieces 114 are electrically connected to the first metal pieces 111 by the controllable elements 112, allowing the bias voltage pieces 113 to electrically transmit control signals to the controllable elements 112.

[0051] In some embodiments, the reflecting unit 110 further includes an inductance element 115 that electrically connects the bias voltage strip 113 to the second metal strip 114 .

[0052] In some embodiments, the RF current in the first metal piece 111 and the second metal piece 114 may interfere with the control signal of the controllable element 112. In this case, by adding an inductance element 115 to the line of the control signal, AC isolation can be achieved, and the RF current in the first metal piece 111 and the second metal piece 114 can be prevented from flowing into the bias circuit layer 200, which is advantageous for protecting the control signal circuit and realizing accurate, effective and reliable control of the control signal.

[0053] In some embodiments, when the parasitic unit 120 is provided in the same layer as the reflective unit 110, the parasitic unit 120 has a U-shaped groove at a position corresponding to the bias voltage piece 113, the U-shaped groove being configured to accommodate the bias voltage piece 113.

[0054] In some embodiments, referring to Figures 1 and 4, the rectangular metal patch of the parasitic unit 120 has a U-shaped groove etched on the side facing the reflective unit 110, which can avoid coupling between the parasitic unit 120 and the bias voltage strip 113 and prevent energy from bypassing the inductance element 115 and flowing to the bias circuit layer 200.

[0055] In some embodiments, the electromagnetic array element may be a single-polarized electromagnetic array element, in which case the formed intelligence surface is a single-polarized intelligence surface, and the electromagnetic array element may be a multi-polarized electromagnetic array element, in which case the formed intelligence surface is a multi-polarized intelligence surface, and the present application is not limited thereto.

[0056] For example, the reflective unit 110 may be linear, in which case the electromagnetic array element is a single-polarization electromagnetic array element. Referring to Figures 14 and 15, the reflective unit 110 includes a first metal piece 111, which is a rectangular metal piece located at the center of the reflective circuit layer 100, a fourth metal piece 3112, and a fifth metal piece 3113. The fourth metal piece 3112 includes a trapezoidal portion 3112B whose short side is located close to the first metal piece 111 and whose long side is located away from the first metal piece 111, and a rectangular portion 3112A to which the long side of the trapezoidal portion 3112B is connected. The fifth metal piece 3113 is located opposite the fourth metal piece 3112. The fifth metal piece 3113 includes a trapezoidal portion 3113B whose short side is located close to the first metal piece 111 and whose long side is located away from the first metal piece 111, and a rectangular portion 3113A to which the long sides of the trapezoidal portion 3113B are connected. The fourth metal piece 3112 and the fifth metal piece 3113 are distributed above and below the first metal piece 111 so that the reflection unit 110 is linear. The first metal piece 111 and the fourth metal piece 3112 are electrically connected by a first controllable element 3114, and the first metal piece 111 and the fifth metal piece 3113 are electrically connected by a second controllable element 3115.

[0057] 1 or 4, the reflective circuit layer 100 is a cross-shaped reflector made up of metal patches, and includes a reflective unit 110 and a parasitic unit 120. As shown in FIG. 4, the reflective unit 110 has a cross shape and includes a first metal piece 111 that is generally substantially rectangular and located in the center, a controllable element 112, four second metal pieces 114, an inductance element 115, and a bias voltage piece 113, arranged from the inside to the outside, to form a ±45-degree dual-polarized electromagnetic unit.

[0058] Also, for example, the reflecting unit 110 may be circular, in which case the electromagnetic array element is a circularly polarized electromagnetic array element. Referring to FIG. 18 , the reflecting circuit layer 100, which is the main body of the reflector, includes a reflecting unit 110 and a parasitic unit 120. The reflecting unit 110 and the parasitic unit 120 are located on the same layer. The reflecting unit 110 includes a first metal piece 111, two bias voltage pieces 113, and two controllable elements 4113. The controllable elements 4113 are located between the first metal piece 111 and the bias voltage piece 113. The two controllable elements 4113 are arranged orthogonal to each other, and various reflected wave amplitude and phase responses can be obtained by controlling the electrical parameters of the controllable elements 4113. The parasitic unit 120 is octagonal and fitted to the outside of the reflecting unit 110. Optimal coupling can be achieved by controlling the inner distance of the parasitic unit 120 from the first metal piece 111 of the reflecting unit 110.

[0059] In addition, multiple polarizations can be realized by adjusting the structure of the reflecting unit 110, and this application is not limited to this. For example, by shaping the metal patch of the reflecting unit 110 so that the cross angle is 60 degrees, a triple-polarized electromagnetic array element can be formed.

[0060] In some embodiments, the controllable element 112 may be a varactor diode, a PIN diode, a liquid crystal, a Micro-Electro-Mechanical System (MEMS), or the like.

[0061] In some embodiments, the controllable element 112 may be a varactor diode, and various reflected wave amplitude and phase responses can be obtained by controlling the capacitance of the controllable element 112. A varactor diode is a device whose voltage can be continuously adjusted. Different voltages can cause the capacitance of the varactor diode to have N different states, where N is a positive integer greater than or equal to 2. In this case, a multi-bit electromagnetic array element can be realized. If the varactor diode is replaced with an element such as a PIN diode or liquid crystal, the parasitic metasurface of the present application can have similar functions and effects.

[0062] In some embodiments, the technology of the present application is not only applied to 2+2 (2-bit + dual polarization) RIS, but also has similar effects and advantages on 1+1 (1-bit + single polarization), 2+1 (2-bit + single polarization), 1+2 (1-bit + dual polarization), and other multi-bit multi-polarization RIS.

[0063] In some embodiments, the electromagnetic array element is a multi-layer structure; a reflective circuit layer 100 configured to provide a reflective unit 110; a first dielectric plate (510) provided below the reflective circuit layer (100) and having at least one metal via electrically connected to the reflective circuit layer (100); and a bias circuit layer 200 including a bias line 210 and a bias contact 220 configured to receive a control signal, the bias line 210 being electrically connected to the bias contact 220, and the bias contact 220 being electrically connected to the controllable element 112 through a metal via.

[0064] In some embodiments, the controllable electromagnetic array element comprises: It further includes at least one base layer disposed below the bias circuit layer 200 and / or disposed above the bias circuit layer 200 and electrically connected to the reflective unit 110 through metal vias.

[0065] 3, in some embodiments, the electromagnetic array element has a multi-layer structure, and includes, from top to bottom, a reflective circuit layer 100, a first dielectric plate 510, a first base layer 300, a second dielectric plate 520, a bias circuit layer 200, a third dielectric plate 530, and a second base layer 400. The reflective circuit layer 100 is electrically connected to the first base layer 300 through a first metal via 610, and the reflective circuit layer 100 is electrically connected to the bias circuit layer 200 through two second metal vias 620, respectively.

[0066] In some embodiments, the bias lines 210 in the bias circuit layer 200 have an external interface that is electrically connected to an external controller and configured to receive control signals from the external controller.

[0067] In some embodiments, the bias circuit layer 200 includes: It further includes a sheet-like branch 230 electrically connected to the bias contact 220 and configured to form a filter capacitor with the base layer.

[0068] In some embodiments, referring to FIGS. 2 and 5 , the sheet-shaped branch 230 may be a fan-shaped branch or a branch of another shape, but the present application is not limited thereto. The sheet-shaped branch 230 functions as a short-circuit capacitor. That is, the sheet-shaped branch 230 forms a capacitor between the first base layer 300 or the second base layer 400 and can filter AC. In actual operation, a portion of the RF signal (AC) from the reflective circuit layer 100 flows to the bias circuit layer 200 through the metal via and the bias contact 220, and the equivalent capacitor formed between the sheet-shaped branch 230 and the base layer can separate the RF current from the DC (control signal current). Multiple sheet-shaped branches 230 and the base layer (metal ground) form a parallel capacitor, blocking DC and shorting AC.

[0069] In some embodiments, the bias line 210 is a bent wiring and is configured to form a filter inductor. Referring to Figures 2 and 5, in the bias circuit layer 200, the bias line 210 is formed into a bent thin wire to form a filter inductor, and an LC filter circuit is configured together with the capacitor formed by the sheet-like branch 230, thereby achieving better separation between RF current and DC (current of the control signal). In some embodiments, the filter inductor of the bias circuit layer 200, the capacitor formed by the sheet-like branch 230, and the inductance element 115 provided in the reflection circuit layer 100 configure an LC filter circuit to achieve better separation between RF current and DC (current of the control signal).

[0070] In the embodiment of the present application, a parasitic unit 120 is provided around the reflective unit 110 of the controllable electromagnetic array element to form a parasitic intelligent surface, and the coupling effect between the parasitic unit 120 and the electromagnetic array element is used to change the configuration parameters of the intelligent surface, thereby reducing the reflection loss of the intelligent surface, improving the stability of the phase response of the intelligent surface, breaking through the performance limitations of the array element layout and the dielectric substrate intelligent surface, and advantageously improving the reliability of the multi-bit multi-polarization RIS scheme.

[0071] The present application also provides an intelligent surface including a plurality of the above-described controllable electromagnetic array elements. The intelligent surface may include a plurality of controllable electromagnetic array elements arranged in an M*N matrix, or may employ other arrangements, but the present application is not limited thereto. The parasitic units 120 may be periodic parasitic units 120, i.e., may be macroscopically periodic extensions of the parasitic units 120 of each array element of the intelligent surface.

[0072] Further embodiments of the present application will now be described with reference to three examples.

[0073] (Example 1) Referring to Figures 1 to 7, Example 1 shows a specific embodiment (hereinafter referred to as this example) of a 4.9 GHz dynamic 2+2 (2-bit + dual polarization) reflective RIS 1000. Referring to Figures 6 and 7, Figure 6 shows a 10x10 conventional metasurface 2000 (a metasurface of the related art), and Figure 7 shows a 10x10 parasitic metasurface 1000 according to this example. It has been found that the parasitic metasurface 1000 is constructed by nesting a parasitic unit 120 on the conventional metasurface 2000. The parasitic metasurface 1000 includes 10x10 electromagnetic array elements 1100.

[0074] The electromagnetic array element 1100 of this example includes two sections: a reflecting section with a microstrip structure and a biasing section with a stripline structure.

[0075] The reflective section includes, from top to bottom, a reflective circuit layer 100, a first dielectric plate 510, and a first base layer 300, and the bias section includes, from top to bottom, a first base layer 300, a second dielectric plate 520, a bias circuit layer 200, a third dielectric plate 530, and a second base layer 400, with the first base layer 300 being used in common as the boundary surface between the reflective section and the bias section.

[0076] 1 and 4, the reflective circuit layer 100 is a cross-shaped reflective unit 110 made of metal patches, and includes the reflective unit 110 and a parasitic unit 120.

[0077] In this example, referring to Figures 1 and 4, the reflection unit 110 of the electromagnetic array element is cross-shaped as shown in Figure 4, and includes, from the inside to the outside, a first metal piece 111 that is approximately rectangular overall and located in the center, a varactor diode (controllable element 112), four second metal pieces 114, an inductance element 115, and a bias voltage piece 113. A first metal via 610 is provided in the center of the first metal piece 111, which is approximately rectangular as a whole, and is connected to the first base layer 300 to ensure zero potential. Four second metal pieces 114 extend from the first metal piece 111, corresponding to its four sides. The four sides of the first metal piece 111 and the four second metal pieces 114 are connected by four varactor diodes (controllable elements 112). Four bias voltage pieces 113 are provided on the outer sides of the four second metal pieces 114, corresponding to each other. The four second metal pieces 114 are connected to the bias voltage pieces 113 by inductance elements 115, functioning as series inductors. The bias voltage pieces 113 are connected to the bias circuit layer 200 through second metal vias 620, and supply a forward bias voltage, enabling adjustment of the capacitance values ​​of the varactor diodes (controllable elements 112). The inductance element 115 functions as isolation to prevent RF current on the reflection unit 110 from flowing to the bias circuit layer 200. The four bias voltage pieces 113 are controlled by two bias lines 210, and each bias line 210 controls two bias voltage pieces 113, which will be described in detail in the bias section below.

[0078] The four parasitic units 120 are arranged to extend in four directions of the cross-shaped reflecting unit 110 and are coupled to the reflecting unit 110. That is, the four parasitic units 120 are arranged at the four corners of the reflecting circuit layer 100 and form couplings corresponding to the four second metal pieces 114. Each parasitic unit 120 includes two parts: a square parasitic patch 122 and a rectangular parasitic patch 121. The square parasitic patch 122 is arranged to extend outward along the rectangular parasitic patch 121 and form a coupling slot between it and the rectangular parasitic patch 121. By adjusting the pitch and size of the second metal pieces 114 of the parasitic unit 120 and the second metal pieces 114 of the reflecting unit 110, it is possible to provide optimal proximity coupling between two adjacent reflecting units 110, thereby changing the wave impedance of the RIS and achieving low reflection loss and stable phase response.

[0079] The second metal piece 114 of the parasitic unit 120 has a U-shaped groove etched on the side facing the reflecting unit 110 to avoid coupling between the parasitic unit 120 and the bias voltage piece 113, thereby preventing energy (e.g., RF current energy) from bypassing the inductance element 115 and flowing to the bias circuit layer 200.

[0080] 2 and 5, the bias circuit layer 200 includes two bias lines 210, four bias contacts 220, and four sheet-like branches 230. The sheet-like branches 230 are fan-shaped, and the four sheet-like branches 230 extend outward from the four bias contacts 220 to form a fan shape. The four sheet-like branches 230 are electrically connected to the four bias contacts 220, respectively, and the four bias contacts 220 are connected to four second metal vias 620 that form coupling capacitors in the first base layer 300 and / or the second base layer 400, respectively, and act as parallel short circuits for RF current. One bias line 210 connects two bias contacts 220 of a single polarization (two diagonal bias contacts 220) to achieve voltage synchronization control. By forming the bias line 210 in a bent thin wire shape, a filter inductor is formed, which, together with the coupling capacitor formed by the sheet-like branch 230, constitutes an LC filter circuit, thereby achieving better separation between the RF current and DC (current of the control signal). More specifically, the filter inductor of the bias circuit layer 200, the capacitor formed by the sheet-like branch 230, and the inductance element 115 provided in the reflection circuit layer 100 cooperate to constitute an LC filter circuit, thereby achieving better separation between the RF current and DC (current of the control signal).

[0081] The intelligence surface of this example has good amplitude and phase response characteristics. Figures 8, 9, and 10 show the phase response, amplitude response, and cross-polarization suppression in four states, respectively.

[0082] Figure 8 shows a phase response diagram. The 2-bit intelligent surface has four states: 00, 01, 10, and 11. These represent the four different phases of the intelligent surface's reflected waves, i.e., the four different phase states. The horizontal axis of the waveform diagram represents frequency, and the vertical axis represents angle. Ideally, there is a 90-degree difference between the four phase states. Referring to Figure 8, the curves in the diagram show that of the four lines representing the four phase states, at a frequency of 4.9 GHz, the difference between every two adjacent lines is approximately 90 degrees, which is an ideal situation.

[0083] Figure 9 shows an amplitude response diagram. The 2-bit intelligent surface has four states: 00, 01, 10, and 11. These represent the four different phases of the intelligent surface's reflected waves, i.e., the four different phase states. The horizontal axis of the waveform diagram represents frequency, and the vertical axis represents return loss. In the diagram, the four phase states correspond to four curves, showing the return loss for each of the four phase states. Generally, the closer the return loss is to zero, the better. In this example, a standard substrate is used, and even when evaluated at the worst value within the band, a relatively ideal return loss can be achieved. For example, in the diagram, the return loss for the 00 and 01 states is greater than -1 dB, which is a very ideal return loss. The return loss for the 01 and 10 states is approximately -3.3 dB at 4.9 GHz, which is also ideal.

[0084] Figure 10 shows the ±45° cross-polarization suppression diagram. The 2-bit intelligent surface has four states: 00, 01, 10, and 11. These represent the four different phases of the intelligent surface's reflected waves, i.e., the four different phase states. The horizontal axis of the waveform diagram represents frequency, and the vertical axis represents cross-polarization suppression. In the diagram, the four phase states correspond to four curves, showing the cross-polarization suppression status for each of the four phase states. While it is desirable for the two polarizations to not affect each other, the cross-polarization suppression index is used to evaluate the degree of influence between the two ±45° polarization directions. The smaller the cross-polarization suppression index, the less influence there is between the two polarizations. All four curves in the diagram show that the cross-polarization suppression is suppressed to below -55 dB at 4.9 GHz, which is ideal.

[0085] This example can support independent electrical control of dual-polarized electromagnetic waves. Table 1 shows the dual-polarized reflected wave phase difference matrix, where 00, 01, 10, and 11 represent the four reflected wave phase states, respectively.

[0086] [Table 1]

[0087] From Table 1, it can be seen that the four phase states are in two polarization directions of ±45 degrees, and the phase difference between each pair of phase states is approximately 90 degrees, which is an ideal situation.

[0088] The intelligent surface in this example supports a beam directionality of ±60°. Figure 11 shows the directivity patterns of the reflected wave at 0°, 15°, 30°, 45°, and 60° when the 10x10 array is incident at 0° (i.e., perpendicular to the surface of the intelligent surface, with 0° as the reference angle for each angle below). Here, the horizontal axis represents the angle of the reflected wave, and the vertical axis represents the amplitude (also known as wave strength, measured in dB). As can be seen from the figure, the amplitude at each angle reaches -10 dB or higher, and the reflected wave has the best beam directionality amplitude response waveform at 0°.

[0089] As shown in Fig. 11, when all incident waves are incident from 0°, various beam directivities of the reflected waves can be realized by adjusting the electromagnetic characteristics of the electromagnetic array elements for each RIS, and the maximum beam directivities are 0°, 15°, 30°, 45°, and 60°, respectively.

[0090] In this example, the incident and reflected beam reciprocity is supported within ±45°. Figure 12 shows the reflected wave patterns of a 10x10 array at 0° and 30° incidence using the same codebook. The horizontal axis represents the angle of the reflected wave, and the vertical axis represents the amplitude. From this figure, we can see that good amplitude responses can be achieved at both 0° and 30° incidence.

[0091] This example supports independent beam directivity of dual-polarized reflected waves. Figure 13 shows the +45° polarized reflected wave +30° directivity pattern and the -45° polarized reflected wave -30° directivity pattern of a 10x10 array. The horizontal axis represents the angle of the reflected wave, and the vertical axis represents the amplitude. This figure shows that good amplitude responses are obtained in both the +45° polarized reflected wave +30° directivity direction and the -45° polarized reflected wave -30° directivity direction.

[0092] (Example 2) Example 2 shows a specific implementation of a strip-shaped single-polarized dynamic 2+1 (2-bit + single-polarized) reflective RIS 3000, as shown in Figures 14 to 17, where the electromagnetic array element in this example is a single-polarized electromagnetic array element 3100. Figures 16 and 17 show schematic diagrams of the front and back structures of a 10x10 single-polarized dynamic 2+1 reflective RIS 3000 based on a strip-shaped parasitic metasurface. The parasitic metasurface includes 10x10 single-polarized electromagnetic array elements 3100.

[0093] The electromagnetic array element of this example is a single-polarized electromagnetic array element 3100 including a reflector section and a bias section. The reflector circuit layer, which is the main body of the reflector section, includes a reflector unit 110 and a parasitic unit 120. The reflector unit 110 and the parasitic unit 120 are located on both sides of a dielectric plate. That is, the parasitic unit 120 may be mounted by bottom mounting, and the parasitic unit 120 may be located below the reflector circuit layer where the reflector unit 110 is located, or a dielectric plate may be provided between the parasitic unit 120 and the reflector unit 110. The specific layer structure may refer to FIG. 3 of Example 1, but a parasitic circuit layer configured to support the parasitic unit 120 may be added between the reflector circuit layer and the first base layer.

[0094] The reflection unit 110 includes a first metal piece 111, a controllable element, a fourth metal piece 3112, and a fifth metal piece 3113. The controllable element includes a first PIN diode 3114 and a second PIN diode 3115. The first PIN diode 3114 is located between the first metal piece 111 and the fifth metal piece 3113, and the second PIN diode 3115 is located between the first metal piece 111 and the fourth metal piece 3112. By controlling the conduction states of the first PIN diode 3114 and the second PIN diode 3115, various combinations of the first metal piece 111, the fourth metal piece 3112, and the fifth metal piece 3113 can be obtained, thereby achieving various reflection amplitude and phase responses. The parasitic unit 120 includes a first parasitic patch 3121 and a second parasitic patch 3122. By adjusting the lengths of the first parasitic patch 3121 and the second parasitic patch 3122, the coupling strength between the parasitic unit 120 and the reflecting unit 110 is increased, and the reflection loss of the RIS 3000 is reduced.

[0095] The bias section of Example 2 may be provided in the bias circuit layer with reference to Example 1, and the bias section may include two bias lines, two bias contacts, and two fan-shaped branches, the bias lines and the bias contacts are electrically connected correspondingly, and the bias contacts and the fan-shaped branches are electrically connected correspondingly. The specific structural design, functions, and effects are similar to those of Example 1, and will not be further described here.

[0096] (Example 3) Example 3 shows a specific implementation of a circularly polarized dynamic 2-bit reflective RIS 4000, as shown in Figures 18 and 19, where the electromagnetic array element in this example is a circularly polarized electromagnetic array element 4100. Figure 19 shows a schematic diagram of a 10x10 circularly polarized dynamic 2-bit reflective RIS 4000 structure based on a honeycomb parasitic metasurface. The parasitic metasurface includes 10x10 circularly polarized electromagnetic array elements 4100.

[0097] The electromagnetic array element in this example is a circularly polarized electromagnetic array element 4100, which also includes a reflecting section and a bias section.

[0098] Referring to FIG. 18, the reflecting circuit layer, which is the main body of the reflector, includes a reflecting unit 110 and a parasitic unit 120. The reflecting unit 110 and the parasitic unit 120 are located on the same layer of the dielectric plate. The reflecting unit 110 includes a first metal piece 111, two bias voltage pieces 113, and two controllable elements 112. Here, the first metal piece 111 is a circular metal patch, and the controllable element 112 is a varactor diode located between the first metal piece 111 and the bias voltage piece 113. The two controllable elements 112 are arranged orthogonally to each other, and various reflected wave amplitude and phase responses can be obtained by controlling the capacitance values ​​of the controllable elements 112. The parasitic unit 120 is octagonal and fitted to the outside of the reflecting unit 110. Optimal coupling can be achieved by controlling the inner distance of the parasitic unit 120 from the first metal piece 111 of the reflecting unit 110.

[0099] The layer structure of the circularly polarized electromagnetic array element 4100 and the circuit design of the bias section may refer to the corresponding design example in Example 1, and will not be further mentioned here.

[0100] A first aspect of the present invention provides a controllable electromagnetic array element, the controllable electromagnetic array element including a reflecting unit and a parasitic unit, the reflecting unit including at least one reflecting metal piece and at least one controllable element electrically connected to the reflecting metal piece and configured to control electromagnetic parameters of the electromagnetic array element in response to a control signal, the parasitic unit being disposed around the reflecting metal piece and coupled to the reflecting metal piece. The present invention provides a parasitic unit disposed around the reflecting unit of the controllable electromagnetic array element to form a parasitic intelligent surface, and utilizes the coupling effect between the parasitic unit and the electromagnetic array element to change the configuration parameters of the intelligent surface, thereby reducing the reflection loss of the intelligent surface, improving the stability of the phase response of the intelligent surface, and breaking through the performance limitations of the array element layout and the dielectric substrate for the intelligent surface, which is advantageous for improving the reliability of multi-bit multi-polarization RIS schemes. This can effectively improve the performance of the RIS and reduce manufacturing costs.

[0101] The beneficial effects of the second aspect compared to the related art are the same as the beneficial effects of the first aspect compared to the related art, and reference may be made to the relevant description of the first aspect, and no further mention will be made here.

[0102] The embodiments of the present application have the following advantages over the related art: 1) We propose the concept of periodic parasitic units and the parasitic metasurface technology using periodic parasitic units. This technology involves nesting periodic parasitic units on a conventional reflective metasurface to form a parasitic metasurface, thereby changing the matching characteristics of the reflective metasurface and the spatial wave impedance, thereby improving the reflection efficiency and phase response. This technology improves the influence of the size, layout, switching elements, and dielectric substrate of the electromagnetic scattering unit on the electromagnetic response characteristics of the metasurface, thereby improving the reflection efficiency and widening the phase tuning range, laying the foundation for the development of polarization-multibit reflective RIS. 2) We designed a dynamic multi-bit multi-polarization reflective metasurface based on a lattice-like parasitic metasurface. This reflective metasurface adopts a lattice-like parasitic metasurface architecture design to improve the reflection efficiency and widen the phase tuning range, while suppressing orthogonal polarization direction currents and avoiding cross-coupling between the multi-polarized reflection wavelengths of the metasurface, ensuring the independent electrical tuning of various polarizations in the multi-polarization RIS.

[0103] The embodiments of the present application configure a parasitic intelligent surface by providing a parasitic unit around the reflective unit of a controllable electromagnetic array element, and by utilizing the coupling effect between the parasitic unit and the electromagnetic array element to change the configuration parameters of the intelligent surface, thereby reducing the reflection loss of the intelligent surface, improving the stability of the phase response of the intelligent surface, breaking through the performance limitations of the array element layout and the dielectric substrate intelligent surface, and advantageously improving the reliability of the multi-bit multi-polarization RIS scheme.

[0104] The above has specifically described some implementations of the embodiments of the present application, but the embodiments of the present application are not limited to the above embodiments. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of the embodiments of the present application, and these equivalent modifications or substitutions are intended to be included in the scope defined by the claims of the embodiments of the present application.

Claims

1. A controllable electromagnetic array element, Includes a reflective unit and a parasitic unit, The reflection unit is at least one reflective metal piece; at least one controllable element electrically connected to the reflective metal strip and configured to control an electromagnetic parameter of the electromagnetic array element in response to a control signal; the parasitic unit is disposed around the reflective metal piece and is coupled to the reflective metal piece; The reflective metal piece is a first metal piece configured to be electrically connected to ground; a bias voltage strip electrically connected to the first metal strip by the controllable element and configured to receive a control signal and transmit the control signal to the controllable element; Controllable electromagnetic array elements.

2. The parasitic unit is provided in the same layer as the reflecting unit so as to be coupled to the reflecting unit, or the parasitic unit is disposed on an upper layer of the reflective unit so as to be coupled to the reflective unit; or the parasitic unit is provided below the reflective unit so as to be coupled to the reflective unit; 10. The electromagnetic array element of claim 1.

3. a coupling slot is formed between the parasitic unit and the reflecting unit, and the parasitic unit and the reflecting unit are coupled together by an electric field; or the parasitic unit and the reflective unit are coupled together by a resistor; 10. The electromagnetic array element of claim 1.

4. the reflecting unit is provided at a central position of the controllable electromagnetic array element, and the parasitic unit is provided at an outer periphery of the controllable electromagnetic array element and is arranged in a polarization direction of the reflecting unit to be coupled to the reflecting unit; 10. The electromagnetic array element of claim 1.

5. The first metal piece is a polygonal metal piece, and the parasitic unit is provided along a corresponding side of the polygonal metal piece, such that at least one side of the parasitic unit forms a strip-shaped coupling slot with at least one side of the polygonal metal piece; or the first metal piece is a circular metal piece, and the parasitic unit is provided along the circumference of the circular metal piece so that an edge of the parasitic unit forms an annular coupling slot with an edge of the circular metal piece; 10. The electromagnetic array element of claim 1.

6. a second metal piece is further provided between the first metal piece and the bias voltage piece, the bias voltage piece being electrically connected to the second metal piece, and the second metal piece being electrically connected to the first metal piece by the controllable element; the parasitic unit is provided along a corresponding edge of the second metal piece such that at least one edge of the parasitic unit forms a coupling slot with at least one edge of the second metal piece; 10. The electromagnetic array element of claim 1.

7. The reflection unit further includes an inductance element, and the bias voltage piece is electrically connected to the second metal piece by the inductance element.

7. The electromagnetic array element of claim 6.

8. When the parasitic unit is provided in the same layer as the reflective unit, the parasitic unit is provided with a U-shaped groove configured to accommodate the bias voltage piece at a position corresponding to the bias voltage piece.

10. The electromagnetic array element of claim 1.

9. the reflecting unit is linear, in which case the electromagnetic array elements are single-polarized electromagnetic array elements; or the reflecting unit is cross-shaped, in which case the electromagnetic array elements are dual-polarized electromagnetic array elements; or the reflecting unit is circular, and in that case the electromagnetic array element is a circularly polarized electromagnetic array element; 10. The electromagnetic array element of claim 1.

10. the controllable element is a varactor diode, a PIN diode, or a liquid crystal; 10. The electromagnetic array element of claim 1.

11. the electromagnetic array element is a multi-layer structure; a reflective circuit layer configured to provide the reflective unit; and a first dielectric plate provided under the reflective circuit layer, the first dielectric plate is provided with at least one first metal via electrically connected to the first metal piece in the reflective circuit layer and at least one second metal via electrically connected to the bias voltage piece in the reflective circuit layer; a bias circuit layer including a bias line and a bias contact configured to receive the control signal, the bias line electrically connected to the bias contact, and the bias contact electrically connected to the controllable element through the second metal via; 10. The electromagnetic array element of claim 1.

12. and further comprising at least one base layer disposed below the bias circuit layer and / or above the bias circuit layer, and electrically connected to the reflective unit through a metal via.

12. The electromagnetic array element of claim 11.

13. The bias circuit layer includes: and a sheet-like branch electrically connected to the bias contact and configured to form a filter capacitor with the base layer.

13. The electromagnetic array element of claim 12.

14. The bias line is a bent wiring and is configured to form a filter inductor.

12. The electromagnetic array element of claim 11.

15. A controllable electromagnetic array element, comprising: Includes a reflective unit and a parasitic unit, the reflecting unit includes at least one reflective metal piece and at least one controllable element electrically connected to the reflective metal piece and configured to control an electromagnetic parameter of the electromagnetic array element in response to a control signal; the parasitic unit is disposed around the reflective metal piece and is coupled to the reflective metal piece; the reflecting unit is linear, in which case the electromagnetic array elements are single-polarized electromagnetic array elements; or the reflecting unit is cross-shaped, in which case the electromagnetic array elements are dual-polarized electromagnetic array elements; or the reflecting unit is circular, and in that case the electromagnetic array element is a circularly polarized electromagnetic array element; Controllable electromagnetic array elements.

16. comprising a plurality of controllable electromagnetic array elements according to any one of claims 1 to 15. Intelligence Surface.

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