Microcontroller

Abstract

To provide a microcontroller which operates in a low power consumption mode.SOLUTION: A microcontroller 100 includes a CPU110, a RAM112, and a peripheral circuit such as a timer circuit 145. A register in the peripheral circuit is provided in an interface with bus lines 161 to 163. A power gate unit 130 for controlling power supply is provided, and which causes the microcontroller to operate not only in a normal operation mode where all circuits are active, but also in a low power consumption mode where only some of the circuits are active. A volatile memory and a nonvolatile memory are provided in a register to which power is not supplied when in the low power consumption mode, such as a register 185 of the CPU. When shifting to the low power consumption mode, data in the volatile memory is backed up in the nonvolatile memory before the power supply is stopped. In the case where it returns to the normal operation mode, when power supply to the register is started again, the data in the nonvolatile memory is written back into the volatile memory.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a microcontroller and a method for manufacturing the same. A controller is a type of semiconductor device, and is also known as a "microcontroller unit," "MCU," or It is sometimes called "μC".

[0002] In this specification, a semiconductor device is a device that can function by utilizing semiconductor characteristics. The term "semiconductor device" refers to devices in general, and electro-optical devices, semiconductor circuits, and electronic equipment are all semiconductor devices. [Background technology]

[0003] With the advancement of semiconductor device miniaturization technology, the integration level of microcontrollers is increasing year by year. Accordingly, various semiconductor elements (e.g., transistors) installed inside the microcontroller This increases the leakage current of the transistors, etc., and significantly increases the power consumption of the microcontroller. For this reason, reducing power consumption has become an important issue for microcontrollers in recent years. It is one of the.

[0004] One of the ways to achieve low power consumption in microcontrollers is to Among the circuit blocks that make up the controller, those that are not required for operation are put into low-power mode. There is a technology for doing this (Patent Document 1). [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Publication No. 10-301659 Summary of the Invention [Problem to be solved by the invention]

[0006] In the circuit block where the power is cut off, all nodes in the integrated circuit are Since the logic of the code is volatile, the timing of power shutdown is after the current process has been completed. Limited to.

[0007] In view of the above problem, one aspect of the present invention is to reduce power consumption by cutting off power to circuits that are not required for operation. One objective is to provide a microcontroller with reduced force.

[0008] Another object is to provide a highly reliable microcontroller. [Means for solving the problem]

[0009] One aspect of the invention disclosed in the present application is a semiconductor memory device including a terminal to which a power supply potential is input, a CPU, a nonvolatile memory, and a a first peripheral circuit having a memory and a function for measuring time and outputting a first interrupt signal; a second peripheral circuit that is an interface with the external device and outputs a second interrupt signal; a third peripheral that processes an analog signal input from the outside and outputs a third interrupt signal; a circuit for determining the priority of the first to third interrupt signals and outputting a fourth interrupt signal; an interrupt controller, first to third peripheral circuits, a CPU, and an interrupt controller; the first to fifth registers for the first to third peripheral circuits, the CPU, the memory, the interrupt controller, The power supply voltage is supplied to and stopped from the controller and the first, fourth, and fifth registers. a power gate, a controller for controlling the power gate, and a sixth level for the controller. and a microcontroller having a

[0010] In the microcontroller of the above embodiment, at least first to third operation modes are provided. The first mode of operation is to activate all the circuits of the microcontroller. The second operating mode is a mode in which the controller, the first peripheral circuit, and the In this mode, the first, second and sixth registers are activated and the other circuits are deactivated. The third operating mode activates the controller and the sixth register, and This is the mode in which the circuit is inactive. The first operating mode is switched to the second mode by the instruction of the CPU. The transition process to the second or third operation mode is started. When the input to the controller is made, the transition process from the second operation mode to the first operation mode is performed. In addition, when an external interrupt signal is input to the controller, the The process of transitioning from the third operation mode to the first operation mode is started.

[0011] The first, fourth and fifth registers have a volatile storage section and a non-volatile storage section, and are connected to the power gate. When the power supply is cut off, the data in the volatile storage unit before the power supply is cut off is When the power supply is resumed by the power gate, The data saved in the nonvolatile storage unit is written to the volatile storage unit.

[0012] Similarly to the first register, other registers, for example, a third register, may also contain volatile A memory unit and a non-volatile memory unit can also be provided. In this case, the power supply is also controlled by the power gate. When the power supply is cut off, the data in the volatile memory unit is transferred to the non-volatile memory unit before the power supply is cut off. When the power supply is resumed by the power gate, the data is saved in the volatile memory. The data saved in the volatile storage unit is written to the volatile storage unit.

[0013] In the above-described embodiment, a transistor using an oxide semiconductor layer is used in a memory cell of the memory. A transistor using silicon and a resistor can be provided. A transistor using an oxide semiconductor layer in a photo-sensitive memory section and a transistor using silicon A register can be provided.

[0014] In the above embodiment, a multilayer film including an oxide semiconductor layer is used in a memory cell of the memory. By using such a transistor, reliability can be improved.

[0015] A transistor using a multilayer film including an oxide semiconductor layer has a first oxide layer, a second oxide layer, and a a multilayer film including a semiconductor layer and an oxide semiconductor layer; and a gate insulating film provided in contact with the multilayer film; a gate electrode provided on the multilayer film via a gate insulating film; and an oxide semiconductor layer The oxide semiconductor layer contains indium, and the oxide semiconductor layer is provided in contact with the first oxide layer. The oxide semiconductor layer has a larger energy gap than the oxide semiconductor layer, contains indium, and is an oxide The oxide semiconductor layer is provided between the first oxide layer and the second oxide layer, and the second oxide layer The semiconductor layer has a larger energy gap than the oxide semiconductor layer and is a semiconductor containing indium. It is a body device.

[0016] To provide stable electrical characteristics to a transistor in which a channel is formed in an oxide semiconductor layer To achieve this, it is effective to reduce the impurity concentration in the oxide semiconductor layer to make it highly purified and intrinsic. The term "purifying an oxide semiconductor layer to an intrinsic state" means making the oxide semiconductor layer intrinsic or substantially intrinsic. When it is qualitatively intrinsic, the carrier density of the oxide semiconductor layer is 1×10 17 / cm 3 less than, 1×10 15 / cm 3 Less than or equal to 1 x 10 13 / cm 3 The oxide semiconductor layer In this case, hydrogen, nitrogen, carbon, silicon, and metal elements other than the main components are considered impurities. In order to reduce the impurity concentration in the oxide semiconductor layer, the impurity concentration in the adjacent first oxide layer and the second oxide layer is It is also preferable to reduce the impurity concentration in the oxide layer.

[0017] For example, silicon in an oxide semiconductor layer forms an impurity level. These oxides can become traps and degrade the electrical characteristics of transistors. The silicon concentration in the semiconductor layer is 1×10 19 atoms / cm 3 Less than 5 x 10 1 8 atoms / cm 3 less than 1×10 18 atoms / cm 3 Less than The gate insulating film of the transistor may be formed of silicon oxide, silicon oxynitride, or nitride. Since insulating films containing silicon, such as silicon oxide and silicon nitride oxide, are often used, It is preferable that the compound semiconductor layer is not in contact with the gate insulating film.

[0018] In addition, hydrogen and nitrogen in the oxide semiconductor layer form donor levels and increase the carrier density. It makes them do it.

[0019] In addition, when a channel is formed at the interface between the gate insulating film and the oxide semiconductor layer, Surface scattering occurs, and the field-effect mobility of the transistor decreases. The compound semiconductor layer is formed so as not to come into contact with the gate insulating film, and the channel is separated from the gate insulating film. It is preferable.

[0020] Therefore, by separating the transistor channel from the gate insulating film, stable electrical characteristics can be achieved. This allows the transistor to have high field-effect mobility. When used as a switching element in a display device, the transistor has stable electrical characteristics. Therefore, a highly reliable display device can be obtained. It has effect mobility.

[0021] In order to separate the channel of the transistor from the gate insulating film, for example, a The multilayer film including the above-mentioned layer may have the following structure.

[0022] The multilayer film including the oxide semiconductor layer is formed by forming at least an oxide semiconductor layer (for convenience, a second oxide layer and a second oxide layer). The first oxide layer (called a barrier layer) is formed between the second oxide layer and the gate insulating film. The first oxide layer is made of one of the elements constituting the second oxide layer. The energy of the conduction band minimum is 0.05 eV or more higher than that of the second oxide layer. 0.07 eV or more, 0.1 eV or more, 0.15 eV or more and 2 eV or less, 1 eV or more The oxide layer is close to the vacuum level, 0.5 eV or less, or 0.4 eV or less. The oxide layer preferably contains at least indium, as this increases the carrier mobility. When an electric field is applied to the gate electrode, the oxide semiconductor layer in the multilayer film is A channel is formed in the second oxide layer, which has a small edge energy. By having a first oxide layer between the gate insulating film and the semiconductor substrate, the channel of the transistor It is possible to form the second oxide layer in a layer that is not in contact with the gate insulating film. Since the first oxide layer is composed of one or more elements that compose the second oxide layer, At the interface between the oxide layer and the first oxide layer, interfacial scattering is unlikely to occur. Since the movement of carriers is not hindered in the It is possible.

[0023] The first oxide layer may be made of, for example, aluminum, titanium, silicon, gallium, or germanium. , yttrium, zirconium, tin, lanthanum, cerium or hafnium in the second oxide Specifically, the first oxide layer and the second oxide layer may be an oxide layer containing a higher atomic ratio than the oxide layer. The above-mentioned elements are contained in the second oxide layer at a concentration of 1.5 times or more, preferably 2 times or more, more preferably 1.5 times or more, more ...2.5 times or more, more preferably 3 times or more, more preferably 3 times or more, more preferably 4 times or more, more preferably 4 times or more, Preferably, an oxide layer containing the elements at an atomic ratio three times higher is used. The elements mentioned above bond strongly with oxygen. Therefore, the first oxide layer has a function of suppressing oxygen deficiency from occurring in the oxide layer. The layer is an oxide layer that is less susceptible to oxygen vacancies than the second oxide layer.

[0024] Alternatively, the second oxide layer is an In-M-Zn oxide and the first oxide layer is also an In-M-Zn oxide. When the first oxide layer is an n-oxide, the first oxide layer is In:M:Zn=x1:y1:z1 [atomic ratio] If the second oxide layer has an atomic ratio of In:M:Zn=x2:y2:z2, then y1 / x The first oxide layer and the second oxide layer are selected such that 1 is greater than y2 / x2. The element M is a metal element that has a stronger bond with oxygen than In, such as Al, Ti, Ga, Examples include Y, Zr, Sn, La, Ce, Nd, and Hf. Preferably, y1 / x Select the first oxide layer and the second oxide layer such that 1 is 1.5 times or more larger than y2 / x2. More preferably, the first acid is selected such that y1 / x1 is at least twice as large as y2 / x2. Preferably, y1 / x1 is greater than y2 / x2. The first oxide layer and the second oxide layer are selected so that the thickness of the second oxide layer is three times larger than that of the first oxide layer. In the oxide layer, when y1 is equal to or greater than x1, stable electrical characteristics can be imparted to the transistor. However, if y1 is three times or more of x1, the field effect transition of the transistor becomes Since the mobility decreases, it is preferable that y1 is less than three times x1.

[0025] The thickness of the first oxide layer is 3 nm or more and 100 nm or less, preferably 3 nm or more and 50 nm or less. The thickness of the second oxide layer is 3 nm or more and 200 nm or less, preferably 3 nm or less. The thickness is preferably from m to 100 nm, more preferably from 3 nm to 50 nm.

[0026] The multilayer film including the oxide semiconductor layer has an insulating film and a second oxide semiconductor layer on the side opposite to the gate insulating film. The oxide layer is in contact with the first oxide layer and is composed of one or more elements that make up the second oxide layer. The energy is 0.05 eV or more, 0.07 eV or more, or 0.1 eV or more than the second oxide layer. or 0.15 eV or more and 2 eV or less, 1 eV or less, 0.5 eV or less, or 0.4 eV A third oxide layer (hereinafter also referred to as a barrier layer) close to the vacuum level may be included. It is preferable that the oxide layer contains at least indium, since this increases carrier mobility. At this time, even if an electric field is applied to the gate electrode, no channel is formed in the third oxide layer. In addition, since the third oxide layer is composed of one or more elements that compose the second oxide layer, The interface between the second oxide layer and the third oxide layer is unlikely to form an interface state. By using the interface as a channel, a second transistor having a different threshold voltage is formed. This can cause the apparent threshold voltage of the transistor to fluctuate. By providing a material layer, variations in electrical characteristics such as the threshold voltage of transistors are reduced. It is possible.

[0027] Specifically, the third oxide layer contains 1.5 times or more of the above elements than the second oxide layer. Preferably, an oxide layer containing at least two times, more preferably at least three times as many atoms as the oxide layer is used. The aforementioned elements strongly bond with oxygen, which prevents oxygen vacancies from occurring in the oxide layer. That is, the third oxide layer is an oxide layer in which oxygen vacancies are less likely to occur than in the second oxide layer. is.

[0028] Alternatively, the second oxide layer is an In-M-Zn oxide and the third oxide layer is also an In-M-Zn oxide. When the second oxide layer is an n-oxide, the second oxide layer is In:M:Zn=x2:y2:z2 [atomic ratio] , the third oxide layer is In:M:Zn=x 3: y 3: If z3 [atomic ratio], then y3 / x The second oxide layer and the third oxide layer are selected such that 3 is greater than y2 / x2. The element M is a metal element that has a stronger bond with oxygen than In, such as Al, Ti, Ga, Examples include Y, Zr, Sn, La, Ce, Nd, and Hf. Preferably, y3 / x Select the second oxide layer and the third oxide layer such that 3 is 1.5 times or more larger than y2 / x2. More preferably, the second acid is selected such that y3 / x3 is at least twice as large as y2 / x2. Preferably, y3 / x3 is greater than y2 / x2. The second oxide layer and the third oxide layer are selected so that the thickness of the second oxide layer is three times larger than that of the third oxide layer. In the oxide layer, when y2 is equal to or greater than x2, stable electrical characteristics can be imparted to the transistor. However, if y2 is three times or more of x2, the field effect transition of the transistor becomes Since the mobility decreases, it is preferable that y2 is less than three times x2.

[0029] The thickness of the third oxide layer is 3 nm or more and 100 nm or less, preferably 3 nm or more and 50 nm or less. Below.

[0030] When the first oxide layer is an In-M-Zn oxide, the atomic ratio of In to M is preferably Preferably, In is less than 50 atomic % and M is 50 atomic % or more, and more preferably In is less than 25 atomic % and M is 75 atomic % or more. When the compound layer is an In-M-Zn oxide, the atomic ratio of In to M is preferably 25%. atomic % or more, M is less than 75 atomic %, and more preferably In is 34 atomic % or more % or more and M is less than 66 atomic %. In the case of Zn oxide, the atomic ratio of In to M is preferably less than 50 atomic %. M is 50 atomic % or more, and more preferably In is less than 25 atomic %. is 75 atomic % or more.

[0031] The first oxide layer or the third oxide layer is a layer for forming the source electrode and the drain electrode of the transistor. However, the gate electrode is not connected to the source electrode and the drain electrode of the transistor. When the first oxide layer, the second oxide layer, or the third oxide layer is provided as a source Depending on the materials used for the electrode and drain electrode, the first oxide layer, the second oxide layer, or or oxygen vacancies in the region of the third oxide layer near the contact with the source electrode and the drain electrode. The n-type region becomes the source of the transistor. The source and drain electrodes can be used as When the material is a conductive material that easily bonds with oxygen, such as tungsten, the oxide semiconductor layer When the oxide semiconductor layer is brought into contact with the conductive material, oxygen in the oxide semiconductor layer diffuses toward the conductive material, which easily bonds with oxygen. The manufacturing process of a transistor involves several heating steps, so the above phenomenon As a result, oxygen vacancies are formed in the regions of the oxide semiconductor layer in the vicinity of the contact points with the source and drain electrodes. Loss occurs and the region becomes n-type. [Effects of the Invention]

[0032] By using one embodiment of the present invention, it is possible to cut off power to circuits that are not necessary for operation. This makes it possible to reduce the power consumption of the microcontroller.

[0033] In addition, by providing a non-volatile memory unit in the register that is powered off in low power consumption mode, , it is possible to increase the degree of freedom in the timing of power cutoff, and also to restore the state before power cutoff. It is possible to provide a microcontroller that can be restored quickly.

[0034] In addition, a transistor using a multilayer film including an oxide semiconductor layer is being used in a microcontroller. By using this, high reliability can be achieved. [Brief explanation of the drawings]

[0035] [Figure 1] FIG. 1 is a block diagram showing an example of the configuration of a microcontroller. [Figure 2] FIG. 1 is a diagram showing an example of a layout of a microcontroller. [Figure 3] 10 is a flowchart showing an example of processing when power is turned on. [Figure 4] 10 is a flowchart showing an example of a process for transitioning from an Active mode to an Noff1 or Noff2 mode. [Figure 5] 10 is a flowchart showing an example of a process for transitioning from the Noff1 or Noff2 mode to the Active mode. [Figure 6] FIG. 2 is a circuit diagram showing an example of a configuration of a register. [Figure 7] FIG. 2 is a circuit diagram showing an example of the configuration of a memory cell of a RAM. [Figure 8] FIG. 1 is a cross-sectional view showing an example of the configuration of a microcontroller. [Figure 9] FIG. 1 is a block diagram showing an example of the configuration of a microcontroller. [Figure 10] Optical microscope image of a microcontroller. [Figure 11] FIG. 1 is a cross-sectional view showing a multilayer film including an oxide semiconductor layer. [Figure 12] FIG. 1 illustrates a band structure of a multilayer film according to one embodiment of the present invention. [Figure 13] FIG. 1 illustrates a band structure of a multilayer film according to one embodiment of the present invention. [Figure 14] FIG. 1 illustrates a band structure of a multilayer film according to one embodiment of the present invention. [Figure 15] FIG. 1 is a top view showing an example of a film forming apparatus. [Figure 16] FIG. 2 is a cross-sectional view showing an example of a film formation chamber. [Figure 17] FIG. 3 is a cross-sectional view showing an example of a heat treatment chamber. [Figure 18] 1A and 1B are a top view and a cross-sectional view illustrating a transistor according to one embodiment of the present invention. [Figure 19] 1A to 1C are cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 20] 1A to 1C are cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 21]1A to 1C illustrate electronic devices. [Figure 22] 1 is a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 23] Signal waveform diagram of the input / output terminals of a microcontroller measured to check the operation of the CPU register. [Figure 24] FIG. 24 is an enlarged view of the signal waveforms in FIG. 23, showing the signal waveforms during operation in active mode. [Figure 25] 10A and 10B show measurement results of off-state current of a transistor including a multilayer film. DETAILED DESCRIPTION OF THE INVENTION

[0036] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The present invention is not limited to the following description, and various modifications in form and details are possible by those skilled in the art. The present invention should not be construed as being limited to the description of the following embodiments. It is not something that can be done.

[0037] (Embodiment 1) The configuration and operation of the microcontroller will be explained using Figure 1. FIG. 1 is a block diagram of a cross controller 100.

[0038] The microcontroller 100 includes a CPU (Central Processing Unit) 110, a bus bridge 111, RAM (Random Access Memory) 112, memory interface 113, controller 120, interrupt controller 121, I / O interface (input / output interface The power gate unit 130 includes a power gate base 122 and a power gate unit 130.

[0039] The microcontroller 100 further includes a crystal oscillator circuit 141, a timer circuit 145, an I / O O interface 146, I / O port 150, comparator 151, I / O interface interface 152, bus line 161, bus line 162, bus line 163, and data The microcontroller 100 also has a bus line 164. In addition, the microcontroller 100 has a connection to an external device. Each of the connection terminals 170-176 has at least one connection terminal 170-176. , represents a terminal group consisting of one terminal or multiple terminals.

[0040] FIG. 2 shows an example of the layout of each circuit block of the microcontroller 100. In the layout diagram, some of the circuit blocks in FIG. 1 are given reference numerals.

[0041] In the layout diagram of Figure 2, the transistors that make up each circuit are made from a silicon substrate. There are transistors made from a silicon dioxide layer and transistors made from an oxide semiconductor layer. The layout is based on the 0.35μm process technology for transistors made from silicon. The process technology for transistors made from oxide semiconductor layers is set to 0.8 μm. It was designed with this in mind.

[0042] The CPU 110 has a register 185 and is connected to the bus lines 161- 163 and a data bus line 164.

[0043] The RAM 112 is a nonvolatile storage device that functions as the main memory of the CPU 110. The RAM 112 stores instructions executed by the CPU 110. It is a device that stores data required for executing instructions and data processed by the CPU 110. Data is written to and read from the RAM 112 according to instructions from the CPU 110. do.

[0044] In the microcontroller 100, the power supply to the RAM 112 is cut off in the low power consumption mode. Therefore, non-volatile memory that can retain data even when power is not supplied is used. The RAM 112 is configured with memory.

[0045] The memory interface 113 is an input / output interface with an external storage device. The PU 110 processes an instruction, and the connection terminal 1 Data is written to and read from an external storage device connected to 76 .

[0046] The clock generation circuit 115 generates a clock signal MCLK (hereinafter referred to as MCLK) used by the CPU 110. CLK.) and has an RC oscillator. MCLK is a control The signal is also output to the interrupt controller 120 and the interrupt controller 121.

[0047] The controller 120 is a circuit that performs control processing for the entire microcontroller 100. For example, the power supply control of the microcontroller 100, the clock generation circuit 115 and the water The control circuit 141 also controls the power gate unit 130, which will be described later. The controller 120 receives an external interrupt signal INT1 via a connection terminal 170. The connection terminal 170 is a terminal for inputting an external interrupt signal. The controller 120 receives an interrupt signal (T0I) from the peripheral circuits (145, 150, 151). RQ, P0IRQ, C0IRQ) are input without going through the buses (161-164).

[0048] The interrupt controller 121 receives the bus line 16 via the I / O interface 122. 1 and data bus line 164. The interrupt controller 121 is The interrupt controller 121 has the function of assigning priority to external requests. Interrupt signal INT1 and interrupt signals ( The interrupt controller 121 receives the interrupts T0IRQ, P0IRQ, and C0IRQ. When an interrupt signal is detected, it checks whether the interrupt request is valid. If so, an internal interrupt signal INT2 is output to the controller 120.

[0049] When an external interrupt signal INT1 is input, the controller 120 sends an internal The CPU 110 outputs an external interrupt signal INT2 to cause the CPU 110 to execute the interrupt process.

[0050] The register 180 of the controller 120 is provided in the controller 120 and is The register 186 of the controller 121 is provided in the I / O interface 122 .

[0051] The peripheral circuits of the microcontroller 100 will be described below. The timer circuit 145, the I / O port 150, and the comparator 151 are included. These peripheral circuits are merely examples, and may vary depending on the electronic device in which the microcontroller 100 is used. , the necessary circuitry can be provided.

[0052] The timer circuit 145 uses a clock signal TCLK (hereinafter referred to as TCLK) to calculate the time. The timer circuit 145 also has a function to measure the time between the allocation and the time. The interrupt controller 120 and the interrupt controller 121 respectively receive the input signal T0IRQ. The timer circuit 145 has a function of outputting to the interrupt request terminal of the I / O interface. The interface 146 is connected to the bus line 161 and the data bus line 164. do.

[0053] The TCLK used in the timer circuit 145 is generated by the clock generation circuit 140. TCLK is a clock signal with a lower frequency than MCLK. For example, The frequency is set to several MHz (for example, 8 MHz), and TCLK is set to several tens of kHz (for example, 3 The clock generation circuit 140 is built into the microcontroller 100. The crystal oscillator circuit 141 is connected to the connection terminal 172 and the oscillator 142 is connected to the connection terminal 173. A crystal oscillator 143 is used as the oscillator of the oscillator 142. By configuring the clock generation circuit 140 with an R oscillator or the like, all of the clock generation circuit 140 The above modules can be integrated into the microcontroller 100.

[0054] The I / O port 150 is configured to connect an external device to a connection terminal 174 in a state where information can be input and output. It is an interface for digital signal input / output. / O port 150 controls the interrupt signal P0IRQ according to the input digital signal. The interrupt request terminals of the interrupt controller 120 and the interrupt controller 121 are output. do.

[0055] As a peripheral circuit for processing an analog signal input from a connection terminal 175, a comparator 1 The comparator 151 receives an analog signal input from a connection terminal 175. The potential (or current) of the signal is compared with the potential (or current) of the reference signal, and the value is either 0 or generates a digital signal of 1. Furthermore, the comparator 151 detects the value of this digital signal When is 1, the interrupt signal C0IRQ is generated. The signals are output to the interrupt request terminals of the interrupt controller 120 and the interrupt controller 121. .

[0056] The I / O port 150 and the comparator 151 are connected via a common I / O interface 152. The I / O is connected to a bus line 161 and a data bus line 164. Port 150 and comparator 151 each have a circuit that can be shared. Therefore, it is configured with one I / O interface 152, but of course, the I / O port The I / O interfaces of the comparator 150 and the comparator 151 can be provided separately.

[0057] The registers of the peripheral circuits are provided in the corresponding input / output interfaces. The register 187 of the marker circuit 145 is provided in the I / O interface 146. The register 183 of the port 150 and the register 184 of the comparator 151 are respectively / O interface 152.

[0058] The microcontroller 100 includes a power gate unit to cut off the power supply to the internal circuitry. The power gate unit 130 supplies power to the circuits required for operation. By performing the above, the power consumption of the entire microcontroller 100 can be reduced.

[0059] As shown in FIG. 1, the units 101-104 of the microcontroller 100 are enclosed by a dashed line. This circuit is connected to a connection terminal 171 via a power gate unit 130. The connection terminal 171 is a power supply terminal for supplying a high power supply potential VDD (hereinafter referred to as VDD).

[0060] The power gate unit 130 is controlled by the controller 120. The unit 130 is a switch circuit for cutting off the supply of VDD to the units 101-104. The switch circuit 131 and the switch circuit 132 are The on / off is controlled by the controller 120. Specifically, the request of the CPU 110, An external interrupt signal INT1 and an interrupt signal TOIR from the timer circuit 145 Using Q as a trigger, the controller 120 controls the power gate unit 130 to It outputs control signals for the circuit 131 and the switch circuit 132 .

[0061] In FIG. 1, the power gate unit 130 includes two switch circuits 131 and 132. However, it is sufficient to provide as many switch circuits as necessary to cut off the power supply. Now, for the timer circuit 145 and the I / O interface 146 (unit 101), Therefore, a switch circuit may be provided so that the power supply can be controlled independently of other circuits.

[0062] In addition, in FIG. 1, the power supply to the units 102-104 is cut off by a common switch circuit 132. However, the present invention is not limited to such a power supply path. For example, a switch circuit other than the switch circuit 132 for the CPU 110 may be used to It is possible to control the power supply. Also, multiple switches can be used for one circuit. A latch circuit may be provided.

[0063] In addition, the controller 120 is always connected to the connection terminal 130 without going through the power gate unit 130. VDD is supplied from 171. In addition, to reduce the influence of noise, the clock generation circuit The oscillation circuit of the circuit 115 and the crystal oscillation circuit 141 are provided with an external power supply different from the VDD power supply circuit. The power supply potential is supplied from the power supply circuit in the part.

[0064] By providing the controller 120 and the power gate unit 130, The controller 100 can be operated in three different operating modes. This is the normal operating mode, where all the circuits of the microcontroller 100 are active. This operating mode is called "Active mode."

[0065] The second and third operating modes are low power consumption modes, in which some circuits are active. On the other hand, in the low power consumption mode, the controller 120 and the timer circuit 14 5 and its related circuits (crystal oscillator circuit 141, I / O interface 146) are active. In the other low power consumption mode, only the controller 120 is active. Here, the former low power consumption mode is called "Noff1 mode" and the latter is called "Noff2 mode." We will call it "Grade".

[0066] Table 1 below shows the relationship between each operation mode and the active circuit. As shown in Table 1, in Noff1 mode, The controller 120 and some of the peripheral circuits (circuits necessary for timer operation) are running, and the Noff2 In this mode, only the controller 120 is operating.

[0067] [Table 1]

[0068] The oscillator of the clock generation circuit 115 and the crystal oscillation circuit 141 operate regardless of the operation mode. The clock generation circuit 115 and the crystal oscillation circuit 141 are kept inactive. To activate it, input an enable signal from the controller 120 or externally. This is done by stopping the oscillation of the clock generation circuit 115 and the crystal oscillation circuit 141.

[0069] In the Noff1 and Noff2 modes, the power gate unit 130 supplies power. Therefore, the I / O port 150 and I / O interface 152 are inactive. However, in order to operate the external device connected to the connection terminal 174 properly, Power is supplied to the O port 150 and part of the I / O interface 152. is the output buffer of the I / O port 150, and is a register 183 for the I / O port 150. In Noff1 and Noff2 modes, the actual function of I / O port 150 is I / O interface 152 and data transmission function with external devices, interrupt signal generation function Similarly, the communication function of the I / O interface 152 is also stopped. do.

[0070] In this specification, a circuit being inactive means that the power supply is cut off and the circuit is stopped. In addition to the state where the main functions in Active mode (normal operation mode) are stopped, This includes operating in a power-saving mode, or in a more power-efficient mode than Active mode.

[0071] In addition, the microcontroller 100 can switch from Noff1 and Noff2 modes to Acti To speed up the return to VE mode, registers 185-187 store data during power down. In other words, the registers 185-187 are In Active mode, the volatile data storage section and the non-volatile data storage section are The volatile storage of registers 185-187 is accessed to write and read data. The procedure will be carried out.

[0072] It should be noted that the data in the register 184 of the comparator 151 does not need to be retained when the power is turned off. Therefore, the register 184 does not include a nonvolatile storage unit. Even in Noff1 / Noff2 mode, the output buffer is enabled for I / O port 150. Since the register 183 for storing the data is also operated, a nonvolatile memory unit is set in the register 183. It has not been installed.

[0073] When switching from Active mode to Noff1 / Noff2 mode, the power is turned off. Thus, the data in the volatile storage of the registers 185-187 is written to the nonvolatile storage. The data in the volatile storage unit is reset to the initial value.

[0074] When returning from Noff1 / Noff2 mode to Active mode, register 18 When power is supplied to the 5-187 again, the data in the volatile memory is first reset to its initial value. Then, the data in the nonvolatile storage unit is written to the volatile storage unit.

[0075] Therefore, even in the low power consumption mode, the data required for the processing of the microcontroller 100 is recorded. Registers 185-187 are held in place to keep the microcontroller 100 low power. This allows immediate return from active mode to active mode.

[0076] The operation mode is switched under the control of the CPU 110 and the controller 120. The operation mode switching process will be described below with reference to FIGS.

[0077] FIG. 3 shows the process of the controller 120 when power is applied to the microcontroller 100. First, the external power supply is supplied to a part of the circuit of the microcontroller 100. Power is supplied (steps 309 and 310). In step 309, VDD is The clock is supplied only to the control unit of the power gate unit 130 of the roller 120. Power is also supplied to the oscillator of the generating circuit 115 and the crystal oscillator circuit 141. In step 20, the control unit of the power gate unit 130 is initialized (step 302).

[0078] The controller 120 causes the clock generation circuit 115 and the crystal oscillation circuit 141 to start oscillating. The controller 120 outputs an enable signal to enable the power supply (step 303). A control signal is output to the gate unit 130, and all the switch circuits ( 131, 132) are turned on (step 304). In step 303, the clock generation The circuit 115 generates MCLK, and the clock generation circuit 140 generates TCLK. In addition, in step 304, VDD is supplied to all circuits connected to the connection terminal 171. Then, the input of MCLK to the controller 120 is started. All 20 circuits are activated (step 305).

[0079] The controller 120 releases the reset of each circuit of the microcontroller 100 ( The CPU 110 starts receiving MCLK (step 306) and the CPU 110 starts receiving MCLK (step 307). When CLK is input, the CPU 110 starts operation and the microcontroller 100 outputs AC tive mode (step 308).

[0080] The transition from Active mode to low power consumption mode (Noff1, Noff2 mode) The operation mode is determined by the execution of a program by the CPU 110. A request to enter the low power mode is sent to the controller 120 via the low power mode register 180. Write to the address for power mode request (hereinafter referred to as Noff_TRIG). The CPU 110 determines whether to switch to the Noff1 or Noff2 mode. Also, write the value to a predetermined address (hereinafter referred to as Noff_MODE) of the register 180. .

[0081] The controller 120 triggers writing data to Noff_TRIG of the register 180. This triggers the transition process to Noff1 or Noff2 mode.

[0082] In the register 180, the data storage unit for operation mode transition is only a volatile storage unit. Therefore, when the power is turned off, Noff_TRIG and Noff_MODE are Here, the initial value of Noff_MODE is Active mode. With this setting, the CPU 110 is stopped and the Noff_TRIG write is executed. It can return to Active mode from Low Power Consumption mode even if the .

[0083] Figure 4 shows the flow chart of the transition process from Active mode to Noff1 and Noff2 modes. In Active mode, the Noff_TRIG When the controller 120 detects a write to Noff (steps 320, 321), The operation mode to be transitioned to is determined from the value of N_MODE (step 322). The process in Figure 4 will be explained using the example of transitioning to off1 mode. The same is true for

[0084] The controller 120 stores in the registers 185 and 186 that the power is turned off in the Noff1 mode. Then, a control signal requesting data saving is output (step 323). When the control signal from the controller 120 is received, the volatile memory 6 is The data in the memory is saved to the non-volatile memory.

[0085] The controller 120 then resets the circuits that are powered down in the Noff1 mode. A control signal is output (step 324) to stop the supply of MCLK to the CPU 110 (step (Step 325) The controller 120 outputs a control signal to the power gate unit 130. Then, the switch circuit 132 is turned off (step 326). The power supply to the ports 102-104 is then cut off. An enable signal is output to the generating circuit 115 to stop oscillation (step 327). This causes a transition to the Noff1 mode (step 328).

[0086] If it is determined in step 322 that the mode is to be changed to the Noff2 mode, In step 3, data is also saved in the register 187 of the timer circuit 145. In step 326, the switch circuit 131 is also turned off. In step 327, the oscillation is stopped. An enable signal to stop the crystal oscillation circuit 141 is also output to the crystal oscillation circuit 141 .

[0087] When switching from Noff1 or Noff2 mode to Active mode, the controller The process is executed when the controller 120 receives an interrupt signal. In ff1 mode, the external interrupt signal INT1 or the interrupt from the timer circuit 145 is used. In Noff2 mode, the external interrupt signal INT 1 is the trigger.

[0088] Figure 5 shows the flow of the process of returning from Noff1 or Noff2 mode to Active mode. This is a chart showing how to return from No off1 mode to Active mode. As explained below, the same applies to Noff2 mode.

[0089] In the Noff1 or Noff2 mode, the controller 120 detects an interrupt signal. When the clock signal is output, an enable signal is output to the oscillator of the clock generating circuit 115 to restart oscillation. Then, the clock generation circuit 115 outputs MCLK to the controller 120 (step 350-353).

[0090] The controller 120 determines the operation mode to be transitioned from the value of Noff_MODE in the register 180. In Noff1 or Noff2 mode, Noff_ Since the MODE data is reset to the initial value, Active mode is determined. .

[0091] The controller 120 controls the power gate unit 130 to turn on the switch circuit 132. Then, the controller 120 restarts the unit to which the power supply has been resumed (step 355). The reset of the ports 102-104 is released (step 356), and the MCLK to the CPU 110 is Then, the supply is resumed (step 357). Then, a control signal is output to the registers 185 and 186. The data backed up in the non-volatile memory is written back to the volatile memory (step By the above process, the microcontroller 100 is in the Active mode. (step 359).

[0092] As mentioned above, in the No off1 mode, the controller 120 receives the The interrupt signal T0IRQ causes the microcontroller 100 to enter Active mode. Therefore, by using the timer function of the timer circuit 145, In other words, the microcontroller 100 can be operated intermittently. By outputting the signal T0IRQ at regular intervals, the system can be switched from No off mode to Act mode periodically. In Active mode, the controller When the microcontroller 120 determines that the processing in the microcontroller 100 is completed, the microcontroller 120 executes the above-described control Processing is performed and the microcontroller 100 is put into Noff1 mode.

[0093] In the microcontroller 100, signals input from the connection terminals 174 and 175 are processed. To operate the CPU 110, it is necessary to set it to Active mode. The time required for the calculation process by the CPU 110 is extremely short. This allows the microcontroller 100 to operate in low power consumption mode except when processing external signals. It is possible to operate it in Noff1 mode.

[0094] Therefore, the microcontroller 100 can be used for intermittent control of sensing devices, monitoring devices, etc. For example, the microcontroller 100 is well suited to devices that operate under dynamic control. It is suitable for control devices such as disaster alarms, smoke detectors, and secondary battery management devices. In order to operate the device for a long period of time, power consumption becomes an issue. The majority of the time the controller 100 is in operation, the required cycles to return to Active mode are Since only the path is operating, power consumption during operation can be reduced.

[0095] Therefore, this embodiment provides low power consumption operation by introducing a low power consumption mode and low power consumption. To provide a microcontroller capable of quickly returning from a power mode to a normal operation mode is possible.

[0096] In addition, necessary data can be saved in the non-volatile memory of the register before power is cut off. Therefore, the process for power shutdown can be started even before the CPU process is completed. This increases the degree of freedom in determining the timing of power cutoff.

[0097] This embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0098] (Embodiment 2) A register having both nonvolatile and volatile storage units will be described with reference to FIG.

[0099] Figure 6 is a circuit diagram of a register with both non-volatile and volatile storage. The register 200 has a memory circuit 201 and a memory The memory circuit 201 is a volatile memory unit of 1 bit. The register 200 stores, as necessary, a 1-bit nonvolatile memory. Other elements such as diodes, resistors, inductors, etc. may be provided.

[0100] The memory circuit 201 is supplied with a low power supply potential VSS (hereinafter referred to as VSS) and a high power supply potential VDD. (hereinafter referred to as VDD) is input as a power supply potential. Data is held during the period when the potential difference with VSS is supplied as the power supply voltage.

[0101] The memory circuit 202 includes a transistor 203, a transistor 204, a capacitor 205, a transistor transmission gate 206, transistor 207, inverter 208 and inverter 2 It has 09.

[0102] The potential reflecting the data in the memory circuit 201 is transmitted via a transmission gate 206. The potential is input to the memory circuit 202. The transistor 203 prevents this potential from being supplied to the node FN. The transistor 203 controls the supply of the potential V1 to the node FN. In FIG. 6, the signal WE1 controls the on / off of the transistor 203. The potential V1 may be the same as VSS or the same as VDD. Good too.

[0103] The node FN is a data storage portion of the memory circuit 202. The transistor 203 and the capacitor The potential of the node FN is maintained by the transistor 205. When transistor 204 is on, transistor 204 A potential V1 is supplied to the memory circuit 201 via

[0104] The signal WE2 controls the on / off of the transmission gate 206. The transmission gate 206 receives a signal with the polarity of the signal WE2 inverted and a signal with the same polarity as the signal WE2. Here, the transmission gate 206 receives a signal of the polarity of the signal WE2. When the potential is at a high level, the transistor is turned off, and when the potential is at a low level, the transistor is turned on.

[0105] The signal WE2 controls the on / off of the transistor 207. Here, the signal WE2 When the potential of the signal WE2 is at a high level, the transistor 207 is turned on, and the potential of the signal WE2 is low. When the level is high, the transistor 207 is turned off. , a transmission gate, or other switch other than the transistor 207 may be used. can be done.

[0106] In order to improve the charge retention characteristics of the memory circuit 202, the off-state current of the transistor 203 However, it is desirable that the off-state current of the transistor 203 is extremely small. This is because the amount of charge leaking from the FN can be reduced. Compared to capacitor transistors, it has a lower leakage current than silicon transistors. It is made of a thin film of oxide semiconductor with a wide band gap and a lower intrinsic carrier density than silicon. Examples of such transistors include:

[0107] In oxide semiconductors, impurities such as moisture or hydrogen, which act as electron donors, The oxide semiconductor (pu) is highly purified by reducing the oxygen vacancy. Rized OS) is an i-type (intrinsic semiconductor) or is as close to i-type as possible. A transistor having a channel formation region in a highly-degraded oxide semiconductor layer has a significant off-state current. It is very small, highly reliable, and suitable for the transistor 203.

[0108] Here, the “low To explain the off-state current, the results of determining the off-state current of a transistor using a multilayer film are shown below. Explain the results.

[0109] <Measurement of off-state current of a transistor using a multilayer film> First, the measurement sample will be described.

[0110] First, an insulating film was formed on a silicon substrate. A 300 nm thick silicon oxynitride film was formed.

[0111] Next, a first oxide film was formed on the insulating base film. The first oxide film was made of In-Ga-Z A target made of n-oxide (In:Ga:Zn=1:3:2 [atomic ratio]) was used. A 5 nm film was formed by sputtering. The film formation gas was argon gas at 30 sccm. 15 sccm of oxygen gas was used, the pressure was 0.4 Pa, and the substrate temperature was 200°C. The film was formed by applying a power of 0.5 kW.

[0112] Next, an oxide semiconductor film was formed on the first oxide film. - Using a target made of Zn oxide (In:Ga:Zn=1:1:1 [atomic ratio]) A 15 nm film was formed by sputtering. Argon gas was used as the film forming gas for 30 s. ccm, oxygen gas 15sccm, pressure 0.4Pa, substrate temperature 300℃ Then, a DC power of 0.5 kW was applied to form a film.

[0113] Next, a second oxide film was formed over the oxide semiconductor film. -Zn oxide (In:Ga:Zn=1:3:2 [atomic ratio]) target was used. The film was formed to a thickness of 5 nm by sputtering. The film-forming gas was argon gas at 30 sc The pressure was 0.4 Pa and the substrate temperature was 200°C. The film was formed by applying a DC power of 0.5 kW.

[0114] Next, heat treatment was performed to release water, hydrogen, and the like from the oxide semiconductor film. After heat treatment in a nitrogen atmosphere at 450°C for 1 hour, Heat treatment was carried out for 1 hour.

[0115] Next, a conductive film is formed on the base insulating film and the second oxide film, and a photolithography process is performed. forming a mask on the conductive film by etching a part of the conductive film using the mask; A source electrode and a drain electrode were formed. The conductive film formed was a tungsten film with a thickness of 100 nm.

[0116] Next, a gate insulating film was formed on the second oxide film, the source electrode, and the drain electrode. As a gate insulating film, a silicon oxynitride film was formed to a thickness of 30 nm by the CVD method.

[0117] Next, a gate electrode was formed on the gate insulating film. A tantalum nitride film was formed, and a tungsten film with a thickness of 135 nm was deposited on the tantalum nitride film by sputtering. A tungsten film was formed. A mask was formed on the tungsten film by photolithography. Then, the tantalum nitride and a portion of the tungsten film are etched using the mask. A gate electrode was formed.

[0118] Next, an interlayer insulating film was formed to cover each component. An aluminum oxide film with a thickness of 70 nm was formed by CVD. A silicon oxynitride film having a thickness of 300 nm was formed by this method.

[0119] The transistor channel length L = 0.73 μm, the channel width W = 1 cm, and the gate electrode and The length Loff between the source electrodes (or drain electrodes) is 0.67 μm.

[0120] Through the above steps, a sample transistor was fabricated.

[0121] Next, the measurement results of leakage current of the fabricated transistor will be described.

[0122] The measurement conditions were a dry atmosphere, Vgs=-4V, Vds=1V in the dark, 85°C and 1 The experiment was carried out under two conditions at 25°C.

[0123] As shown in Figure 25, even after time has passed at 85°C and 125°C, the - 21 A / μm or less, 1×10 -19 It shows a low off-state current of A / μm or less.

[0124] From the above, it was confirmed that the off-state current of the transistor using a multilayer film is extremely low.

[0125] In this way, a transistor in which a channel is formed in an oxide semiconductor film in a multilayer film is used. This makes it possible to realize a transistor with extremely low off-state current. In a register using a stator, the charge retention characteristics of the memory circuit can be improved. .

[0126] Next, an example of the operation of the register 200 will be described.

[0127] To transition from the active mode to the low power consumption mode, the memory circuit 201 The data is saved to the memory circuit 202. Before saving the data, the memory circuit 202 is reset. To do this, the transmission gate 206 is turned off, the transistor 207 is turned on, and the transistor The transistor 203 is turned on to apply a potential V1 to the node FN. The potential is set to an initial state.

[0128] Next, the data is saved from the memory circuit 201 to the memory circuit 202. The transistor 206 is turned on, the transistor 207 is turned off, and the transistor 203 is turned on. As a result, a potential reflecting the amount of charge held in the memory circuit 201 is applied to the node FN. That is, when the data in the memory circuit 201 is written to the memory circuit 202, After writing the data, the transistor 203 is turned off, and the potential of the node FN is By the above operation, the data in the memory circuit 201 is stored in the memory circuit 202. can be.

[0129] Then, the power supply to the register 200 is cut off. VSS is applied to the node to which VDD is applied under the control of unit 130. Since the off-current of the resistor 203 is extremely small, the resistor 200 is not supplied with VDD. Even in this state, the charge held in the capacitor 205 or the gate capacitance of the transistor 204 remains for a long time. Therefore, the memory circuit 202 can retain the data for a certain period of time even when the power supply is cut off. It is possible to retain data for a period of time.

[0130] To return from low power consumption mode to active mode, first set VDD Then, the memory circuit 201 is reset to the initial state. This is done by setting the potential of the node holding the charge in the memory circuit 201 to VSS.

[0131] Next, the data held in the memory circuit 202 is written to the memory circuit 201. When the transistor 204 is turned on, the potential V1 is applied to the memory circuit 201. In the memory circuit 201, when a potential V1 is applied, a potential V When transistor 204 is off, data is transferred to memory circuit 201. The potential of the node where the data is held remains at the initial state potential. The data 202 is stored in the memory circuit 201.

[0132] Register 200 determines which microcontrollers are powered down in low power mode. By configuring the registers of the microcontroller 100, data can be stored while the microcontroller 100 is running. Furthermore, after power supply is resumed, the data can be quickly evacuated. Therefore, in the microcontroller 100, Whether it is for a long period like 0 seconds or a short period like milliseconds, the power supply is interrupted. This makes it possible to provide a microcontroller with low power consumption. do.

[0133] In the register 200, the memory circuit 202 stores the potential held at the node FN. , the operating state (on or off) of transistor 204 is selected, and the operating state Therefore, the data held at node FN during the power-off period is Even if the amount of charge stored in the memory cell fluctuates slightly, the original data can still be read accurately.

[0134] In the memory circuit 202, the node FN stores the voltage stored in the memory circuit 201. VDD or VSS is applied depending on the amount of charge. If the potential of node FN when the gate voltage becomes equal to the threshold voltage is V0, then the potential V0 is The transistor 204 is in an operating state when the node FN is at a potential V However, when the potential V0 becomes 0, it switches between VDD and VSS. For example, the potential difference between VDD and potential V0 is smaller than the potential between V0 and VS If the potential difference between VSS and S is greater than the potential difference between VSS and S, VSS is applied to the node FN where VDD is held. When applying VDD to node FN where VSS is held, the It takes a long time for N to reach the potential V0. The transition becomes slower.

[0135] Therefore, in the register 200, the data in the memory circuit 201 is written to the memory circuit 202. Before this, the potential of the node FN is set to an initial state by applying a potential V1 to the node FN. This operation allows the voltage V0 to be lower than the midpoint between VDD and VSS. Even in this case, by applying a potential V1 equal to the potential VSS to the node FN in advance, the node FN As a result, the time required to apply the potential VSS to the memory circuit 202 can be shortened. This allows data to be written at high speed.

[0136] Furthermore, the resistor 200 having the transistor 203 with a significantly small off-state current is Compared to non-volatile memory such as As a comparative example, a magnetoresistive memory (MRAM: Magnetoresistive Random Access Memory) Examples of such memory include: Generally, the current required for writing to MRAM is said to be 50μA to 500μA. In the register 200, data is saved by supplying charge to the capacitance element. The current required for writing data can be reduced to about 1 / 100 of that required for MRAM. In register 200, the overhead is equal to the power saved by shutting down the power supply. Break-Even Time (BET) can be made shorter than when configuring a register with MRAM. By applying 00 to the register of the microcontroller 100, the register This reduces power consumption due to data backup in the register.

[0137] This embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0138] (Embodiment 3) The memory cell structure of the RAM 112 will be described with reference to FIG. 7. This is a circuit diagram of memory cell 400. Memory cell 400 consists of three transistors 401-403. and a capacitor 404. The memory cell 400 is connected to a bit line BL, a word line RWL, and The word line RWL is connected to the word line WWL. The line WWL is a word line for writing. The memory cell 400 is also connected to a power supply line 405. If VSS is at a potential higher than 0V, The potential of the feed line 405 can be set to 0V.

[0139] The bit lines BL are connected to the read and write circuits of the RAM 112. The row lines RWL and WWL are connected to the row driver.

[0140] To enable the memory cell 400 to function as a nonvolatile memory circuit, the transistor 401 Similar to the transistor 203 of the resistor 200, This is because in the memory cell 400, the node FN (transistor) is used as data. This is because the charge on the gate of the transistor 403 is held.

[0141] The read and write operations will be described below. To write data, the potential of the word line RWL is set to low level and the potential of the word line WWL is set to high level. The node FN is connected to the potential of the bit line BL. After the word line WWL is maintained at a high level potential for a certain period of time, The write operation is completed by returning the potential to a low level.

[0142] To perform a read operation, first the potential of the bit line BL is set to a high level (precharge). Then, the potential of the word line WWL is set to a low level, and the potential of the word line RWL is set to a high level. This turns on the transistor 402. The source and drain of the transistor 403 are connected as follows: A current corresponding to the potential of the gate (node ​​FN) flows. The read circuit detects the amount of change in the potential of the bit line BL and It is determined whether the data held in rule 400 is 0 or 1.

[0143] The memory cell 400 of this embodiment uses one transistor for both read and write operations. This provides a non-volatile RAM that can operate at high speeds, since all that is required is to control the on / off of the It is possible to provide

[0144] This embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0145] (Fourth embodiment) Each circuit of the microcontroller 100 can be fabricated on the same semiconductor substrate. 8 shows an example of a cross-sectional structure of a part of the microcontroller 100. The main elements constituting the circuit of the microcontroller 100 are formed by channeling the oxide semiconductor layer. a transistor 860 having a channel forming region in a silicon substrate; 1 and 2. A n-channel transistor 861 and an n-channel transistor 862 are shown. .

[0146] The transistor 860 is connected to a memory cell of the RAM 112 (transistor 401 in FIG. 7), and applied to resistors 185-187 (see transistor 203 in FIG. 6). 861, 862 apply to other transistors.

[0147] As shown in FIG. 8, a transistor 861 and a transistor 862 are formed on a semiconductor substrate 800. The semiconductor substrate 800 is formed of, for example, a single crystal having n-type or p-type conductivity. Silicon substrates, compound semiconductor substrates (GaAs substrates, InP substrates, GaN substrates, SiC substrates) In FIG. 8, a single crystal silicon substrate having n-type conductivity can be used. This shows an example in which a silicon substrate is used.

[0148] The transistors 861 and 862 are electrically isolated by an insulating film 801 for element isolation. The element isolation insulating film 801 is formed by a selective oxidation method (LOCOS (Local Oxidation Scheme)). Oxidation of Silicon (Oxidation of Silicon) method or trench isolation method It should be noted that an SOI type semiconductor substrate may be used as the semiconductor substrate 800. In this case, the elements may be separated by dividing the semiconductor layer into individual elements by etching.

[0149] An impurity element that imparts p-type conductivity is selectively introduced into the region where the transistor 862 is to be formed. A p-well 802 is formed by introducing ions into the semiconductor substrate 801.

[0150] The transistor 861 includes an impurity region 803, a low-concentration impurity region 804, and a gate electrode 8 805 and a gate insulating film 806 provided between the semiconductor substrate 800 and the gate electrode 805. A sidewall 836 is formed around the gate electrode 805.

[0151] The transistor 862 includes an impurity region 807, a low-concentration impurity region 808, a gate electrode 809, and a gate insulating film 806. A sidewall 835 is provided around the gate electrode 809. It is formed.

[0152] An insulating film 816 is provided over the transistor 861 and the transistor 862. An opening is formed in the insulating film 816, and a wiring is inserted in the opening in contact with the impurity region 803. 810 and wiring 811 are formed, and wiring 812 and wiring 813 are formed in contact with the impurity region 807. is formed.

[0153] The wiring 810 is connected to a wiring 817 formed on an insulating film 816. The wiring 811 is connected to a wiring 818 formed on an insulating film 816, and the wiring 812 is connected to an insulating film 818. The wiring 813 is connected to a wiring 819 formed on the insulating film 816. 8. The wiring 820 is connected to the wiring 820 formed in the

[0154] An insulating film 821 is formed over the wirings 817 to 820. The insulating film 821 has an opening. On the insulating film 821, a wiring 820 is formed. Wiring 822 and wiring 823 are formed. An insulating film 824 is formed on the insulating film 824 .

[0155] A transistor 860 including an oxide semiconductor layer 830 is formed over the insulating film 824. The transistor 860 has a gate insulating film formed over the oxide semiconductor layer 830 as a source electrode or a drain electrode. The conductive film 832 and the conductive film 833, the gate insulating film 831, and the gate electrode 83 The conductive film 832 is connected to the wiring 822 in an opening provided in the insulating film 824. is connected.

[0156] The wiring 823 is provided at a position overlapping with the oxide semiconductor layer 830 with an insulating film 824 interposed therebetween. The wiring 823 functions as a back gate of the transistor 860. 823 is provided as needed.

[0157] The transistor 860 is covered with an insulating film 844 and an insulating film 845. Specifically, the insulating film 845 has a function of preventing hydrogen released from the insulating film 845 from entering the oxide semiconductor layer 830. An insulating film having such a function is preferable. An example of such an insulating film is a silicon nitride film.

[0158] A conductive film 846 is provided over the insulating film 844. The insulating film 844, the insulating film 845, and the gate insulating film 846 are In the opening provided in the gate insulating film 831, the conductive film 846 is in contact with the conductive film 832. do.

[0159] The thickness of the oxide semiconductor layer 830 may be greater than or equal to 2 nm and less than or equal to 40 nm. The conductor layer 830 is an i-type (intrinsic semiconductor) layer that forms a channel forming region of the transistor 860. It is desirable that the electron donor is water or water. The oxide semiconductor layer in which impurities such as silicon are reduced and oxygen vacancies are reduced is an i-type (intrinsic) oxide semiconductor layer. In this paper, we will explain how to purify such an oxide semiconductor layer. The transistor made of a highly purified oxide semiconductor layer is called a highly purified oxide semiconductor layer. The transistor has an extremely small off-state current and is highly reliable.

[0160] In order to manufacture a transistor with low off-state current, the carrier density of the oxide semiconductor layer 830 is , 1×10 17 / cm 3 Preferably, it is less than 1×10 16 / cm 3 Below, 1 x10 15 / cm3 Below, 1×10 14 / cm 3 or less, or 1×10 13 / cm 3 below is.

[0161] The oxide semiconductor layer 830 is used to form the source-drain region of the transistor 860 in an off state. The current is 1×10 at room temperature (approximately 25°C). -18 A or less. Room temperature (25℃ The off-state source-drain current at about 1×10 -21 A or below and more preferably 1×10 -24 A or less. Or, at 85°C, this current value 1×10 -15 A or less, preferably 1×10 -18 A or lower, and Preferably 1 x 10 -21 A or less. Note that the transistor is in the off state when the n-channel In the case of a gate-type transistor, this refers to a state in which the gate voltage is sufficiently smaller than the threshold voltage. Specifically, if the gate voltage is 1V or more, 2V or more, or 3V or more less than the threshold voltage, For example, the transistor is in an off state.

[0162] The off-state current of a transistor using an oxide semiconductor layer has been extremely reduced in various experiments. For example, if the channel width is 1×10 6 μm and channel length is 10 μm In this transistor, the source-drain voltage (drain voltage) is 1V to 10V. The off-state current in the range is below the measurement limit of the semiconductor parameter analyzer, that is, 1×10 - 13 In this case, the channel width of the transistor is The normalized off-state current is 100 zA / μm or less.

[0163] In another experiment, a transistor is connected to the capacitor, and the capacitance is injected into or removed from the capacitor. There is a method for measuring the off-state current using a circuit that uses a transistor to control the charge discharged from the In this case, the off-state current of the transistor is calculated from the change in the amount of charge per unit time of the capacitor. As a result, the off-current of the transistor was measured at several tens of yA under the condition of a drain voltage of 3V. Therefore, it was confirmed that the channel formation was achieved in the highly purified oxide semiconductor layer. The transistor in which the region is formed has an off-state current that is higher than that of a transistor using crystalline silicon. It becomes significantly smaller than the

[0164] The oxide semiconductor layer 830 may contain at least indium (In) or zinc (Zn). For example, the oxide semiconductor may be indium oxide, zinc oxide, or an In-Zn oxide. In-Ga-Zn oxides, In-Al-Zn oxides, In-Sn-Zn oxides etc.

[0165] The crystal structure of the oxide semiconductor layer 830 may be single crystal or polycrystalline (also called polycrystalline). The oxide semiconductor layer 830 is typically a CAAC-OS ( C Axis Aligned Crystalline Oxide Semicon A ductor membrane is preferred.

[0166] The CAAC-OS film is neither completely single crystalline nor completely amorphous. is one of the oxide semiconductor films having a plurality of crystal parts aligned along the c-axis. Microscope (TEM: Transmission Electron Microscope) ), the boundary between the crystals, that is, the grain boundary (grain boundary) Therefore, the CAAC-OS film is not characterized by the grain boundary. In addition, cross-sectional TEM observation and planar TEM observation showed that the electron mobility is less likely to decrease. The observation shows that the crystals in the CAAC-OS film have an orientation. Most of the crystals in the C-OS film are large enough to fit within a cube with a side length of less than 100 nm. Therefore, the crystal part contained in the CAAC-OS film has a side length of less than 10 nm and a side length of 5 nm. This includes cases where the size is less than 1 m or less than 3 nm. -When multiple crystals in the OS film are connected to form a single large crystal region, For example, in a planar TEM image, 2 Over 5μm 2 Greater than or equal to 1 000μm 2 Crystal regions with more than this size may be observed.

[0167] The crystal part included in the CAAC-OS film has a c-axis that is the normal vector of the surface on which the CAAC-OS film is formed. The triangle is aligned parallel to the normal vector of the hole or surface and perpendicular to the ab plane. The metal atoms are arranged in a layered or hexagonal shape when viewed perpendicular to the c-axis. Metal atoms and oxygen atoms are arranged in layers. The orientation of the b-axis may be different. In this specification, when simply referring to a vertical axis, it means that the This also includes the range of -5° to 95°. This also includes the range of 5° or less.

[0168] In the CAAC-OS film, the distribution of the crystal parts may not be uniform. In the process of forming the C-OS film, when crystal growth is performed from the surface side of the oxide semiconductor layer, The proportion of crystalline parts may be higher near the surface than near the growth surface. By adding impurities to the AC-OS film, the crystalline part in the impurity-doped region becomes amorphous. It may also be pawned.

[0169] The c-axis of the crystalline part in the CAAC-OS film is the normal vector of the surface on which the CAAC-OS film is formed. The CAAC-OS film shape (on which the film is formed) is Depending on the cross-sectional shape of the surface or the cross-sectional shape of the surface, they may face in different directions. The direction of the c-axis of the crystal is the normal vector of the surface on which the CAAC-OS film is formed. The direction of the crystal is parallel to the normal vector of the film or surface. is formed by carrying out a crystallization treatment such as a heat treatment after the film formation.

[0170] The electrical characteristics of transistors using CAAC-OS are stable when exposed to visible or ultraviolet light. Since the size can be reduced, the reliability of the transistor can be improved.

[0171] A method for forming a CAAC-OS film will be described below. There is a sputtering method using an oxide semiconductor sputtering target. When ions collide with the sputtering target, the The crystal region to be formed is cleaved from the ab plane and forms a plate or pellet with a plane parallel to the ab plane. In this case, the sputtered particles may peel off as flat sputtered particles. The CAAC-OS film can be formed by reaching the substrate while maintaining its crystalline state. do.

[0172] The flat sputtered particles have a circular equivalent diameter of 3 nm to 10 nm on a plane parallel to the ab plane. Hereinafter, the thickness (length in the direction perpendicular to the ab plane) is 0.7 nm or more and less than 1 nm. The flat sputtered particles may have a plane parallel to the ab plane that is an equilateral triangle or a regular hexagon. Here, the circle-equivalent diameter of a surface refers to the diameter of a perfect circle that is equal to the area of ​​the surface.

[0173] In addition, the following conditions are preferably applied to form the CAAC-OS film.

[0174] By increasing the substrate temperature during film formation, migration of sputtered particles occurs after reaching the substrate. Specifically, the substrate temperature is set to 100°C or higher and 740°C or lower, preferably 200°C or higher and 500°C or lower. By increasing the substrate temperature during film formation, the plate-shaped sputtered particles are deposited on the substrate. When the particle reaches the substrate, migration occurs on the substrate and the flat surface of the sputtered particle touches the substrate. At this time, the sputtered particles are positively charged, so they do not repel each other. Since the sputtered particles adhere to the substrate without unevenly overlapping, the thickness is uniform. Therefore, a CAAC-OS film can be formed.

[0175] By reducing the amount of impurities mixed in during film formation, it is possible to prevent the crystal state from being destroyed by impurities. For example, the concentration of impurities (hydrogen, water, carbon dioxide, nitrogen, etc.) present in the film formation chamber can be reduced. In addition, the impurity concentration in the deposition gas can be reduced. A deposition gas having a temperature of 80° C. or less, preferably −100° C. or less, is used.

[0176] In addition, increasing the oxygen ratio in the deposition gas and optimizing the power reduces plasma damage during deposition. The oxygen ratio in the deposition gas is preferably 30% by volume or more, and more preferably 100% by volume or more. The product is %.

[0177] After the CAAC-OS film is formed, heat treatment may be performed. The temperature is set to 740°C or higher, preferably 200°C or higher and 500°C or lower. The heating time is from 1 minute to 24 hours, preferably from 6 minutes to 4 hours. The heat treatment may be carried out in an active atmosphere or an oxidizing atmosphere. Preferably, the heat treatment is carried out in an inert atmosphere. After that, heat treatment is performed in an oxidizing atmosphere. The impurity concentration of the OS film can be reduced in a short time. In this case, oxygen vacancies may be generated in the CAAC-OS film in an oxidizing atmosphere. The heat treatment can reduce the oxygen vacancies. The crystallinity of the CAAC-OS film can be further improved. The reaction may be carried out under reduced pressure of 100 Pa or less, 10 Pa or less, or 1 Pa or less. In this case, the impurity concentration of the CAAC-OS film can be reduced in an even shorter time.

[0178] As an example of a sputtering target, we will look at an In-Ga-Zn oxide target. As shown below.

[0179] InO X powder, GaO Y Powder and ZnO Z The powders are mixed in a specified number of moles, and after pressure treatment, By heat treatment at temperatures between 1000℃ and 1500℃, polycrystalline In-Ga- The target is a Zn-oxide target. Note that X, Y, and Z are arbitrary positive numbers. The mole ratio of InO X powder, GaO Y Powder and ZnO Z Powder is 2:2:1 , 8:4:3, 3:1:1, 1:1:1, 1:3:2, 1:6:4, 4:2:3 or 3 The powder type and the molar ratio of the powder to be mixed depend on the sputtering conditions. This can be changed as appropriate depending on the ring target.

[0180] Alternatively, the CAAC-OS film can be formed by depositing the film multiple times. An example of such a method is shown below.

[0181] First, a first oxide semiconductor layer is formed to a thickness of 1 nm or more and less than 10 nm. The semiconductor layer is formed by sputtering. Specifically, the substrate temperature is set to 100°C or higher for 5 minutes. 00℃ or less, preferably 150℃ or more and 450℃ or less, and the oxygen ratio in the deposition gas is 30 The film is formed at a volume percentage of at least 100%, preferably 100%.

[0182] Next, heat treatment is performed to convert the first oxide semiconductor layer into a first CAAC-OS film with high crystallinity. The temperature of the heat treatment is 350°C or higher and 740°C or lower, preferably 450°C or higher and 650°C or lower. The heat treatment time is 1 minute to 24 hours, preferably 6 minutes to 4 hours. The heat treatment may be carried out in an inert atmosphere or an oxidizing atmosphere. Or, after heat treatment in an inert atmosphere, heat treatment is performed in an oxidizing atmosphere. By the heat treatment in air, the impurity concentration of the first oxide semiconductor layer can be reduced in a short time. On the other hand, oxygen vacancies are generated in the first oxide semiconductor layer by heat treatment in an inert atmosphere. In this case, the oxygen deficiency can be reduced by heat treatment in an oxidizing atmosphere. Heat treatment can be carried out at a pressure of 1000 Pa or less, 100 Pa or less, 10 Pa or less, or The treatment may be performed under reduced pressure of 1 Pa or less. It can be reduced in an even shorter time.

[0183] The first oxide semiconductor layer has a thickness of 1 nm or more and less than 10 nm. Compared with nanometers or larger, it can be easily crystallized by heat treatment.

[0184] Next, a second oxide semiconductor layer having the same composition as the first oxide semiconductor layer is formed to a thickness of 10 nm to 50 nm. The second oxide semiconductor layer is formed by sputtering. Specifically, the substrate temperature is set to 100°C or higher and 500°C or lower, preferably 150°C or higher and 450°C or lower. The film is formed by setting the oxygen ratio in the film forming gas to 30% by volume or more, preferably 100% by volume. .

[0185] Next, heat treatment is performed to form a second oxide semiconductor layer from the first CAAC-OS film by solid phase growth. The heat treatment temperature was 350°C. The temperature is set to 450°C or higher and 740°C or lower, preferably 450°C or higher and 650°C or lower. The heating time is from 1 minute to 24 hours, preferably from 6 minutes to 4 hours. The heat treatment may be carried out in an active atmosphere or an oxidizing atmosphere. Preferably, the heat treatment is carried out in an inert atmosphere. After that, heat treatment is performed in an oxidizing atmosphere. The impurity concentration of the compound semiconductor layer can be reduced in a short time. Oxygen vacancies may be generated in the second oxide semiconductor layer by the treatment. The oxygen deficiency can be reduced by heat treatment in a 10 atmosphere. The pressure may be reduced to 00 Pa or less, 100 Pa or less, 10 Pa or less, or 1 Pa or less. Under reduced pressure, the impurity concentration of the second oxide semiconductor layer can be reduced in a shorter time. do.

[0186] The oxide semiconductor layer disclosed in the above embodiment can be formed by sputtering or plasma CVD (Chemical Vapor Deposition). It can be formed by the (chemical vapor deposition) method, but other The film may be formed by a method such as a thermal CVD method. An example of the thermal CVD method is MOCVD (Modular Organic Chemical Vapor Deposition). etal Organic Chemical Vapor Deposition) method Alternatively, an atomic layer deposition (ALD) method may be used.

[0187] The thermal CVD method is a film formation method that does not use plasma, so defects are generated by plasma damage. This has the advantage that it will not be

[0188] In the thermal CVD method, the chamber is kept at atmospheric pressure or reduced pressure, and the source gas and oxidant are simultaneously mixed in the chamber. The film is formed by sending the gas into the chamber, reacting it near or on the substrate, and depositing it on the substrate. It is also possible.

[0189] In the ALD method, the chamber is kept at atmospheric pressure or reduced pressure, and the source gases for the reaction are introduced in sequence. Next, the gas is introduced into the chamber, and the film may be formed by repeating this gas introduction sequence. For example, by switching between two or more switching valves (also called high-speed valves), The source gases are supplied to the chamber in order, and the first source gas is supplied to the chamber in order to prevent the mixture of the source gases. Inert gas (argon, nitrogen, etc.) is introduced simultaneously with or after the fuel gas. In case of simultaneously introducing an inert gas, the inert gas is The second source gas may be introduced as a carrier gas, and an inert gas may be introduced at the same time as the second source gas is introduced. Also, instead of introducing an inert gas, the first source gas is discharged by evacuation. The first source gas may be adsorbed on the surface of the substrate to form the first single source gas. The second monoatomic layer is formed by reacting with the second source gas introduced later, and the second monoatomic layer is formed by A thin film is formed by stacking atomic layers one after another. The order of gas introduction is controlled to achieve the desired thickness. By repeating this process several times until the thin film is completely covered, a thin film with excellent step coverage can be formed. The thickness can be adjusted by changing the number of times the gas introduction sequence is repeated, allowing for precise film thickness adjustment. This allows for fine tuning and is suitable for fabricating miniaturized FETs.

[0190] The thermal CVD method such as the MOCVD method or the ALD method can be used in the above-described embodiments. It is possible to form various films such as metal films, semiconductor films, and inorganic insulating films that make up the device. For example, InGaZnO X When forming a (X>0) film, trimethylindium, trime Trimethylindium is made of diethylgallium and diethylzinc. The chemical formula of trimethylindium is ( The chemical formula for trimethylgallium is (CH3)3Ga. The chemical formula of diethylzinc is (CH3)2Zn. Not limited to, triethylgallium (chemical formula (C2H5)3 Ga) can also be used, and dimethyl zinc (chemical formula (C2H5)2 Zn) can also be used.

[0191] For example, when forming a hafnium oxide film, a solution containing a solvent and a hafnium precursor compound is used. Hafnium alkoxide solution, typically tetrakisdimethylamidohafnium (T Two types of gases are used: vaporized DMAH) as a raw material gas and ozone (O3) as an oxidizing agent. The chemical formula for tetrakisdimethylamidohafnium is Hf[N(CH3)2]4 Other liquid materials include tetrakis(ethylmethylamido)hafnium. There is.

[0192] For example, when forming an aluminum oxide film, a solvent and an aluminum precursor compound are used. Two types of gases are used: a raw material gas made by vaporizing a liquid containing methyl methacrylate (TMA, etc.), and H2O as an oxidizing agent. The chemical formula for trimethylaluminum is Al(CH3)3. The solution includes tris(dimethylamido)aluminum, triisobutylaluminum, Aluminum tris(2,2,6,6-tetramethyl-3,5-heptanedionate) There are some.

[0193] For example, when forming a silicon oxide film, hexachlorodisilane is adsorbed on the surface to be formed. This removes the chlorine contained in the adsorbed material and provides radicals of oxidizing gases (O2, nitrous oxide). is fed to react with the adsorbate.

[0194] For example, when forming a tungsten film using a film forming device that uses ALD, WF6 gas is used. The initial tungsten film is formed by repeatedly introducing WF6 and B2H6 gases. The tungsten film is formed by simultaneously introducing B2H6 gas and H2 gas. Alternatively, SiH4 gas may be used.

[0195] For example, an oxide semiconductor film, such as InGaZnO, can be formed using a film formation device that uses ALD. X (X >0) film, In(CH3)3 gas and O3 gas are introduced in sequence and repeatedly. After forming an InO2 layer, Ga(CH3)3 gas and O3 gas are introduced simultaneously to form GaO Then, Zn(CH3)2 and O3 gases are introduced simultaneously to form a ZnO layer. The order of these layers is not limited to this example. Mixed compounds such as O2 layer, InZnO2 layer, GaInO layer, ZnInO layer, GaZnO layer Alternatively, a layer may be formed by bubbling H2 with an inert gas such as Ar instead of O3 gas. Although O gas may be used, it is preferable to use O gas that does not contain H. Instead of Ga(CH3)3 gas, In(C2H5)3 gas may be used. Instead of gas In(CH3)3, gas Ga(C2H5)3 may be used. Alternatively, In(C2H5)3 gas may be used. That's fine.

[0196] This embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0197] (Embodiment 5) In this embodiment, another example of the configuration of the microcontroller will be described.

[0198] FIG. 9 is a block diagram of the microcontroller 190.

[0199] Similar to the microcontroller 100 of FIG. 10, bus bridge 111, RAM 112, memory interface 113, controller 120, interrupt controller 121, I / O interface (input / output interface The power gate unit 130 includes a power gate base 122 and a power gate unit 130.

[0200] The microcontroller 190 further includes a crystal oscillator circuit 141, a timer circuit 145, an I / O O interface 146, I / O port 150, comparator 151, I / O interface interface 152, bus line 161, bus line 162, bus line 163, and data The microcontroller 190 also has a bus line 164. In addition, the microcontroller 190 has a connection to an external device. The oscillator has at least connection terminals 170-176. The pendulum 142 is connected to the microcontroller 19 via the connection terminals 172 and 173. It is connected to 0.

[0201] Each block of the microcontroller 190 corresponds to a block of the microcontroller 100 in FIG. Table 2 shows the functions of the microcontroller 100 and the microcontroller The role of each circuit in the microcontroller 190 is also shown. As with the roller 100, the operation mode is switched according to the flowcharts shown in FIGS. Replace.

[0202] [Table 2]

[0203] The microcontroller 190 receives an interrupt request signal from the microcontroller 100. There are some differences in the lineage, which will be explained below.

[0204] The connection terminal 170, which is a terminal for inputting an external interrupt signal, receives the external interrupt signal INT The external interrupt signal NMI1 is input to the non-master This is a scabble interrupt signal.

[0205] The external interrupt signal NMI1 input via the connection terminal 170 is When an external interrupt signal NMI1 is input to the controller 120, The controller 120 immediately outputs an internal interrupt signal NMI2 to the CPU 110. 10 to execute the interrupt processing.

[0206] The external interrupt signal INT1 is input to the interrupt controller 121 via the connection terminal 170. The interrupt controller 121 receives signals from the peripheral circuits (145, 150, 151). These interrupt signals (T0IRQ, P0IRQ, C0IRQ) are also transmitted via buses (161-164). It is entered without going through .

[0207] When an external interrupt signal INT1 is input, the controller 120 sends an internal The CPU 110 outputs an external interrupt signal INT2 to cause the CPU 110 to execute the interrupt process.

[0208] In addition, the interrupt signal T0IRQ is directly transmitted to the controller without going through the interrupt controller 121. The controller 120 may receive the interrupt signal T0IRQ. When this occurs, an internal interrupt signal NMI2 is output to the CPU 110, causing an interrupt to the CPU 110. Execute the read process.

[0209] Similar to the microcontroller 100, the power gate unit of the microcontroller 190 The controller 120 controls the output 130. As described above, the controller 120 indicates a part of the switch circuit of the power gate unit 130 at the request of the CPU 110. Or it outputs a signal to turn off all of them (stopping the power supply). 20 is an external interrupt signal NMI1 or an interrupt signal T from the timer circuit 145. 0IRQ is used as a trigger to turn on the switch circuit 132 of the power gate unit 130. Outputs a signal to turn on the device (starts power supply).

[0210] In addition, by providing the controller 120 and the power gate unit 130, Like the microcontroller 100, the microcontroller 190 also has three operating modes: (Active mode, Noff1 mode and Noff2 mode) The active and inactive circuits in each operating mode can be controlled by the controller 190. The active circuitry is the same as that of the microcontroller 100 (see Table 1). The microcontroller 190 also switches between operating modes in the same way as the microcontroller 100. This is performed under the control of the controller 120. The controller 120 controls the flow charts shown in FIGS. Switches the operating mode according to the logic.

[0211] Also, in the microcontroller 190, from Noff1 / Noff2 mode, To speed up the return to VE mode, registers 185-187 are volatile data retention registers. and a non-volatile data storage unit for backing up data when the power is cut off. Furthermore, the microcontroller 190 has a register 1 of the comparator 151. 84, like registers 185-187, is divided into a volatile data storage section and a non-volatile data storage section. It has a structure with a holding part.

[0212] In the microcontroller 100, the register 184 is provided with a nonvolatile storage unit. Although not shown, in the microcontroller 100, register 184 also stores the As with 5-187, a non-volatile memory unit may also be provided.

[0213] When switching from Active mode to Noff1 / Noff2 mode, the power is turned off. The data in the volatile storage of the registers 184-187 is written to the nonvolatile storage. The data in the volatile memory is reset to the initial value. Then, the registers 184-187 The power supply is cut off.

[0214] To return from Noff1 / Noff2 mode to Active, set registers 184-18 When power supply to the EEPROM 7 is resumed, the data in the volatile memory is first reset to its initial value. Then, the data in the nonvolatile storage unit is written to the volatile storage unit.

[0215] Therefore, even in the low power consumption mode, the data required for processing by the microcontroller 190 is recorded. Registers 184-187 are used to maintain the microcontroller 190 in a low power state. This allows immediate return from active mode to active mode.

[0216] Therefore, this embodiment provides low power consumption operation by introducing a low power consumption mode and low power consumption. To provide a microcontroller capable of quickly returning from a power mode to a normal operation mode is possible.

[0217] Therefore, the microcontroller 190 also controls the intermittent operation of the sensing device, monitoring device, etc. For example, the microcontroller 100 and 190 is suitable for control devices such as fire alarms, smoke detectors, and secondary battery management devices. For devices that are battery-powered, power consumption becomes an issue when trying to operate them for a long period of time. Like the microcontroller 100, the cross-controller 190 operates in a state where N Since it is operating in off1 mode, the circuit required to return it to Active mode Since only the power supply is in operation, power consumption during operation can be reduced.

[0218] (Sixth embodiment) 11, 12, 13, and 14, oxides that can be used in transistors will be described. The structure of the multilayer film including the compound semiconductor layer will be described with reference to FIG.

[0219] The multilayer film 706 shown in FIG. 11 includes an oxide layer 706a and a an oxide semiconductor layer 706b; and an oxide layer 706c provided over the oxide semiconductor layer 706b. In the following, the case where the multilayer film 706 has three layers will be described. The multilayer film 706 may be two layers or four or more layers. For example, the multilayer film 706 may be an oxide layer 706. The oxide semiconductor layer 706b is provided over the oxide layer 706a. The multilayer film 706 includes an oxide semiconductor layer 706b and a thin film provided on the oxide semiconductor layer 706b. and an oxide layer 706c.

[0220] Here, the band structure of the multilayer film 706 will be described with reference to FIGS.

[0221] The oxide layer 706a is made of In-Ga- The oxide semiconductor layer 706b is formed using Zn oxide and has an energy gap of 2.8 eV. The oxide layer 706c is made of the same material as the oxide layer 706a. In addition, the interface between the oxide layer 706a and the oxide semiconductor layer 706b was The energy gap near the surface is set to 3 eV, and the oxide layer 706c and the oxide semiconductor layer 706b The energy gap near the interface with the ion beam was set to 3 eV. Measurement was carried out using a meter (HORIBA JOBIN YVON UT-300). The oxide layer 706a has a thickness of 10 nm, the oxide semiconductor layer 706b has a thickness of 10 nm, The oxide layer 706c had a thickness of 10 nm.

[0222] FIG. 12(A) shows the multilayer film 706 being etched from the oxide layer 706c while each layer is vacuum-etched. The energy difference between the vacuum level and the top of the valence band is measured and plotted. The energy difference between the top of the valence band and the top of the valence band is measured by ultraviolet photoelectron spectroscopy (UPS). et Photoelectron Spectroscopy) equipment (PHI Ve Measurements were performed using rsaProbe.

[0223] Figure 12(B) shows the energy gap of each layer from the energy difference between the vacuum level and the top of the valence band. By subtracting the energy gap, the energy difference between the vacuum level and the bottom of the conduction band is calculated and plotted. do.

[0224] A part of the band structure shown in FIG. 12(B) is shown in FIG. 13(A). ) In the case where a silicon oxide film is provided in contact with the oxide layer 706a and the oxide layer 706c, Here, EcI1 represents the energy at the bottom of the conduction band of the silicon oxide film. , EcS1 indicates the energy of the bottom of the conduction band of the oxide layer 706a, and EcS2 indicates the energy of the oxide semiconductor. EcS3 represents the energy of the bottom of the conduction band of the oxide layer 706b, and EcS4 represents the energy of the bottom of the conduction band of the oxide layer 706c. EcI2 indicates the energy of the bottom of the conduction band of the silicon oxide film.

[0225] As shown in FIG. 13A, the oxide layer 706a, the oxide semiconductor layer 706b, and the oxide semiconductor layer 706c are In the layer 706c, the energy of the conduction band minimum changes continuously. The oxide semiconductor layer 706a, the oxide semiconductor layer 706b, and the oxide layer 706c are mutually diffused. This is the case.

[0226] In this way, the multilayer film of oxide semiconductor layers that are stacked with a common main component is not simply stacked. The energy of the bottom of the conduction band is not continuous but is continuous between each layer. The structure is fabricated so that a transitional U-shaped well is formed. Defect levels such as trap centers and recombination centers, or those that block the flow of carriers The stacked structure is formed so that there are no impurities that would form a barrier to the When impurities are mixed between the layers of the oxide semiconductor layer, the continuity of the energy band is lost. At the interface, carriers are trapped or disappear due to recombination.

[0227] To form continuous junctions, a multi-chamber deposition system equipped with a load lock chamber is required. Each layer is laminated in succession using a sputtering device without being exposed to the atmosphere. Each chamber in the sputtering apparatus is preferably free of impurities for the oxide semiconductor. To remove as much moisture as possible, an adsorption type vacuum pump such as a cryopump is used. High vacuum pumping (1×10 -4 Pa~5×10 -7 It is preferable to Alternatively, a turbomolecular pump and cold trap can be combined to evacuate the chamber from the exhaust system. It is preferable to prevent gas containing carbon, moisture, etc. from flowing back into the container.

[0228] To obtain a highly purified intrinsic oxide semiconductor, the chamber must be evacuated to a high vacuum. It is also important to increase the purity of the sputtering gas. Gongas has a dew point of -40°C or less, preferably -80°C or less, more preferably -100°C or less. By using a gas that is highly purified to the following level, moisture and the like are taken into the oxide semiconductor film. can be prevented as much as possible.

[0229] In FIG. 13A, the oxide layer 706a and the oxide layer 706c have similar physical properties. However, the oxide layer 706a and the oxide layer 706c are different. For example, an oxide layer having EcS1 higher than EcS3 is preferable. In this case, a part of the band structure has a high energy. In the band structure shown in FIG. 13(B), for example, when EcI2 is used as the gate insulator, Assuming a structure in which the gate electrode is located to the left of the insulating film, EcI2, as shown in Figure 13(B), A structure having the energy of the bottom of the conduction band where EcS1>EcS3 is preferable. This is because the current mainly flows through EcS2 near Ecs3 on the gate electrode side.

[0230] In addition, when the oxide layer 706c and the gate are disposed with a silicon oxide film sandwiched therebetween, the silicon oxide The oxide semiconductor layer 706b functions as a gate insulating film, and indium contained in the oxide semiconductor layer 706b forms a gate insulating film. The oxide layer 706c can prevent the diffusion of the silicon dioxide into the insulating film. In order to prevent the diffusion of indium, the oxide layer 706c is formed on the oxide semiconductor layer 706. It is preferable that the amount of indium contained in b is less than that contained in b.

[0231] 12 and 13, the oxide semiconductor layer 706b of the multilayer film 706 forms a well. In the transistor using the multilayer film 706, the channel is formed in the oxide semiconductor layer 706b. It can be seen that the multilayer film 706 is formed in such a way that the energy at the bottom of the conduction band changes continuously. Because it is shaped like a U-shaped well, it can also be called a U-shaped well.

[0232] As shown in FIG. 14, the oxide layer 706a and the oxide layer 706c are Trap levels due to impurities and defects can be formed near the interface with insulating films such as silicon films. The oxide layers 706a and 706c prevent the oxide semiconductor layer 706 from being damaged. b can be separated from the trap level. When the energy difference between EcS2 and EcS3 is small, the electrons in the oxide semiconductor layer 706b When an electron is captured in a trap level, This results in a negative fixed charge, and the threshold voltage of the transistor shifts in the positive direction. cormorant.

[0233] Therefore, the energy difference between EcS1 and EcS3 and EcS2 is 0.1e V or more, preferably 0.15 eV or more, the fluctuation of the threshold voltage of the transistor is small. This is preferable because it reduces the electrical resistance and provides stable electrical properties.

[0234] Next, a method for forming the oxide semiconductor layer 706b with high crystallinity will be described.

[0235] By sputtering using a target containing a highly oriented polycrystalline oxide semiconductor, It is possible to produce crystals with aligned axes. The oxide semiconductor layer obtained by deposition has a uniform thickness. The oxide semiconductor layer 706b has a uniform crystal orientation. , resulting in a CAAC-OS film.

[0236] By reducing the localized level in the multilayer film 706, the transistor using the multilayer film 706 can be stabilized. The localized level of the multilayer film 706 can be given a constant photocurrent. Measurement method (CPM: Constant Photocurrent Method) It can be evaluated based on this.

[0237] In order to provide stable electrical characteristics to the transistor, the CPM measurement in the multilayer film 706 The absorption coefficient due to the localized level obtained by measurement is 1×10 -3 cm -1 Less than 3x1 0 -4 cm -1 It is sufficient to set it to less than.

[0238] Next, a deposition apparatus for depositing the oxide semiconductor layer 706b having high crystallinity will be described with reference to FIG. 5, 16, and 17. In addition, the oxide semiconductor layer formed using the film formation apparatus The film formation method will be described.

[0239] First, let us use Figure 15 to explain the structure of a film formation system that minimizes the intrusion of impurities into the film during film formation. and explain.

[0240] Figure 15(A) is a schematic top view of a multi-chamber film forming apparatus. The apparatus comprises an atmospheric substrate supply chamber 71 having three cassette ports 74 for accommodating substrates; a lock chamber 72a, an unload lock chamber 72b, a transfer chamber 73, and a transfer chamber 73a; The chamber includes a transfer chamber 73b, a substrate heating chamber 75, a film forming chamber 70a, and a film forming chamber 70b. The side substrate supply chamber 71 is connected to the load lock chamber 72a and the unload lock chamber 72b. The load lock chamber 72a and the unload lock chamber 72b are connected to the transfer chamber 73a and the transfer chamber 73b. 3b. The substrate heating chamber 75, the film forming chamber 70a, and the film forming chamber 70b are connected to the transfer chamber 73 via the b is connected only to the transfer chamber 73.

[0241] Furthermore, gate valves (hatched with diagonal lines in the figure) are provided at the connections of each chamber. Each chamber can be independently maintained in a vacuum state except for the air-side substrate supply chamber 71. The side substrate supply chamber 71 and the transfer chamber 73 have one or more substrate transfer robots 76, Here, it is preferable that the substrate heating chamber 75 also serves as a plasma processing chamber. The single-wafer multi-chamber deposition equipment exposes the substrate to the atmosphere between processes. This prevents impurities from adsorbing on the substrate, and also prevents film formation and heat treatment. The order of the transfer chamber, deposition chamber, load lock chamber, and The number of load lock chambers and substrate heating chambers is not limited to the above number, and may vary depending on the installation space. This can be decided as appropriate based on the source and process.

[0242] FIG. 15(B) shows a multi-chamber film forming apparatus with a different configuration from that shown in FIG. 15(A). The film forming apparatus has an atmosphere-side substrate supply chamber 81 having a cassette port 84 and a load / unload A lock chamber 82, a transfer chamber 83, a substrate heating chamber 85, a film formation chamber 80a, and a film formation chamber 80b. The film forming chamber 80c and the film forming chamber 80d are provided. The heat chamber 85, the film forming chamber 80a, the film forming chamber 80b, the film forming chamber 80c, and the film forming chamber 80d are connected to the transfer chamber 8. 3.

[0243] Furthermore, gate valves (hatched with diagonal lines in the figure) are provided at the connections of each chamber. Each chamber can be independently maintained in a vacuum state except for the air-side substrate supply chamber 81. The side substrate supply chamber 81 and the transfer chamber 83 have one or more substrate transfer robots 86, and the glass substrates can be transported.

[0244] Here, the details of the film formation chamber (sputtering chamber) shown in FIG. 15(B) will be explained with reference to FIG. 16. The film forming chamber 80b shown in FIG. 16(A) includes a target 87, a shield plate 88, and a substrate. The substrate stage 90 has a glass substrate 89. The substrate stage 90 is a substrate support (not shown) that holds the glass substrate 89. A holding mechanism, a backside heater for heating the glass substrate 89 from the backside, etc. may also be provided. The deposition shield 88 prevents particles sputtered from the target 87 from accumulating in unwanted areas. This can be suppressed.

[0245] The film forming chamber 80b shown in FIG. 16(A) is connected to the transfer chamber 83 via a gate valve. The transfer chamber 83 is connected to the load / unload lock chamber 82 via a gate valve. The transfer chamber 83 is provided with a substrate transfer robot 86, which transfers the film forming chamber 80b and the The glass substrate can be transferred to and from the load / unload lock chamber 82. The load / unload lock chamber 82 is divided into upper and lower parts within a single vacuum chamber. One of them can be used as a load chamber and the other as an unload chamber. Such a structure is preferable because it reduces the installation area of ​​the sputtering device. It is suitable.

[0246] 16(A) is a film-forming chamber 80b. The refiner 94 and the mass flow controller 97 are connected to the Although several gases are provided, only one gas is shown for simplicity. A gas with a dew point of -80°C or less, preferably -100°C or less, is used. By using gases, rare gases (such as argon gas), etc., the amount of moisture mixed in during film formation can be reduced. It is possible.

[0247] The film forming chamber 80b shown in FIG. 16(A) is connected to a cryopump 95a via a valve. The transfer chamber 83 is connected to a cryopump 95b via a valve, and the load / unload The load lock chamber 82 is connected to a vacuum pump 96 via a valve. The load lock chamber 82 and the unload lock chamber are vacuum-sealed independently. The film forming chamber 80b and the transfer chamber 83 may be connected to a pump. and connected to a vacuum pump 96 .

[0248] The vacuum pump 96 may be, for example, a dry pump or a mechanical booster pump. By using such a configuration, the film forming chamber 80b and The transfer chamber 83 is vacuumed from atmospheric pressure to low vacuum (approximately 0.1 Pa to 10 Pa) by a vacuum pump 96. The vacuum was then evacuated from low to high vacuum (1×10) by switching the valve. -4 Pa~1×10 - 7 The cryopump 95a or the cryopump 95b is used to pump down to a pressure of 1000 kJ / cm2 (Pa).

[0249] Next, with reference to FIG. 16(B), the example of the film forming chamber shown in FIG. 15(B) will be described. ) will be explained.

[0250] The film forming chamber 80b shown in FIG. 16(B) is connected to the transfer chamber 83 via a gate valve. The transfer chamber 83 is connected to the load / unload lock chamber 82 via a gate valve. .

[0251] The film-forming chamber 80b shown in FIG. 16(B) is a gas-heating chamber. The gas heating mechanism 98 is connected to the refiner 94 via the mass flow controller 97. The gas heating mechanism 98 heats the gas introduced into the film forming chamber 80b to a temperature of 40°C or higher. The temperature can be increased to 00°C or less, preferably 50°C to 200°C. The number of heating mechanisms 98, refiners 94 and mass flow controllers 97 is the same as the number of gas species. However, for simplicity, only one is shown.

[0252] The film-forming chamber 80b shown in FIG. 16(B) is connected to a turbo molecular pump 95c and a vacuum pump 96b via a valve. The turbo molecular pump 95c is connected to the air pump 96b. The vacuum pump 96a is connected to the vacuum pump 96b. The same configuration as the vacuum pump 96 may be used.

[0253] Further, a film formation chamber 80b shown in FIG. 16(B) is provided with a cryotrap 99.

[0254] The turbo molecular pump 95c stably pumps large molecules (or atoms), and Low maintenance frequency makes it highly productive, but it has a low ability to exhaust hydrogen and water. Therefore, the pumping ability for molecules (or atoms) with a relatively high melting point, such as water, is high. The cryotrap 99 is connected to the film forming chamber 80b. The temperature of the cryocooler in the cryostat 99 is set to 100 K or less, preferably 80 K or less. If the wrap 99 has multiple freezers, changing the temperature for each freezers will improve the efficiency of exhaust. For example, the temperature of the first stage refrigerator is set to 100 K or less, The temperature of the second stage refrigerator should be set to 20K or less.

[0255] The transfer chamber 83 shown in FIG. 16(B) includes a vacuum pump 96b, a cryopump 95d, and and cryopump 95e via valves. In this case, pumping is not possible while the cryopump is regenerating. By connecting two or more cryopumps in parallel, even if one is regenerating, the remaining cryopumps It is possible to use a cryopump to pump the gas. This refers to the process of releasing molecules (or atoms) stored inside the pump. If too many molecules (or atoms) accumulate, the exhaust capacity will decrease, so it is necessary to periodically regenerate will be carried out.

[0256] The load / unload lock chamber 82 shown in FIG. 16(B) is equipped with a cryopump 95f and vacuum pump 96c via valves. may have the same configuration as the vacuum pump 96.

[0257] Next, the substrate heating chamber 85 shown in FIG. 15(B) will be described in detail with reference to FIG.

[0258] The substrate heating chamber 85 shown in FIG. 17 is connected to the transfer chamber 83 via a gate valve. The transfer chamber 83 is connected to the load / unload lock chamber 82 via a gate valve. The load / unload lock chamber 82 is evacuated as shown in FIG. 16(A) or FIG. 16(B). ) can be configured in the same way.

[0259] The substrate heating chamber 85 shown in FIG. 17 is connected to a refiner 94 via a mass flow controller 97. The number of refiners 94 and mass flow controllers 97 provided is equal to the number of gas species. The substrate heating chamber 85 is connected to a vacuum pump via a valve. The amplifier 96b is connected to the amplifier 96c.

[0260] The substrate heating chamber 85 also includes a substrate stage 92. The substrate stage 92 includes at least It is sufficient if only one substrate can be placed on the stage, but the stage may also be capable of placing multiple substrates. The substrate heating chamber 85 also includes a heating mechanism 93. The heating mechanism 93 may be, for example, a resistor. The heating mechanism may be a heating mechanism using a heating element or a medium such as a heated gas. The heating mechanism may be one that heats by heat conduction or heat radiation from the (Gas Rapid Thermal Anneal), LRTA (Lamp Rap RTA (Rapid Thermal Anneal) LRTA can be used with halogen lamps, metal halide lamps, etc. lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, high-pressure mercury lamps The material to be treated is heated by the radiation of light (electromagnetic waves) emitted from a lamp such as a GRTA. In this method, heat treatment is performed using high-temperature gas, which is an inert gas.

[0261] The back pressure of the film forming chamber 80b and the substrate heating chamber 85 is 1×10 -4 Pa or less, preferably is 3 x 10 -5 Pa or less, more preferably 1×10 -5 Pa or less.

[0262] The film-forming chamber 80b and the substrate heating chamber 85 are filled with a gas having a mass-to-charge ratio (m / z) of 18. The partial pressure of the molecules (atoms) is 3 x 10 -5 Pa or less, preferably 1×10 -5 Pa or less, and Preferably 3 x 10 -6 Pa or less.

[0263] The film forming chamber 80b and the substrate heating chamber 85 are also equipped with a gas molecule (atom) having an m / z of 28. The partial pressure is 3×10 -5 Pa or less, preferably 1×10 -5 Pa or less, more preferably 3× 10 -6 Pa or less.

[0264] The film forming chamber 80b and the substrate heating chamber 85 are also equipped with a gas molecule (atom) having an m / z of 44. The partial pressure is 3×10 -5 Pa or less, preferably 1×10 -5 Pa or less, more preferably 3× 10 -6 Pa or less.

[0265] The film forming chamber 80b and the substrate heating chamber 85 have a leak rate of 3×10 -6 Pa·m 3 / s or less, preferably 1×10 -6 Pa·m 3 / s or less.

[0266] The film forming chamber 80b and the substrate heating chamber 85 are also equipped with a gas molecule (atom) having an m / z of 18. Leak rate is 1×10 -7 Pa·m 3 / s or less, preferably 3 × 10 -8 Pa·m 3 / s or less.

[0267] The film forming chamber 80b and the substrate heating chamber 85 are also equipped with a gas molecule (atom) having an m / z of 28. Leak rate is 1×10 -5 Pa·m 3 / s or less, preferably 1×10 -6 Pa·m 3 / s or less.

[0268] The film forming chamber 80b and the substrate heating chamber 85 are also equipped with a gas molecule (atom) having an m / z of 44. Leak rate is 3 x 10 -6 Pa·m 3 / s or less, preferably 1×10 -6 Pa·m 3 / s or less.

[0269] The total and partial pressures in the vacuum chamber can be measured using a mass spectrometer. For example, the quadrupole mass spectrometer (also called Q-mass) manufactured by ULVAC, Inc. The leak rate is calculated based on the mass distribution mentioned above. It can be derived from the total pressure and partial pressure measured using an analyzer.

[0270] The leak rate depends on external and internal leaks. External leaks occur due to small holes or An internal leak is when gas enters the vacuum system from outside due to a seal defect. This is caused by leaks from internal valves or other partitions or by gas released from internal components. In order to keep the leak rate below the above-mentioned values, it is necessary to take measures against both external and internal leaks. There is a need.

[0271] For example, it is advisable to seal the opening and closing parts of the deposition chamber with a metal gasket. is achieved by using metals coated with iron fluoride, aluminum oxide, or chromium oxide. Metal gaskets have better adhesion than O-rings and can reduce external leakage. It also protects the passivation of metals coated with iron fluoride, aluminum oxide, chromium oxide, etc. By using this, the gas released from the metal gasket containing impurities is suppressed, and the internal Leaks can be reduced.

[0272] The materials that make up the film deposition equipment are aluminum and chromium, which emit less gas and contain impurities. , titanium, zirconium, nickel or vanadium. It may be used by coating an alloy containing chromium and nickel. The alloy containing titanium is rigid, heat-resistant, and easy to process. To make it smaller, reducing the surface roughness of the component by polishing or other methods can reduce the amount of gas released. Cut.

[0273] Alternatively, the components of the aforementioned film forming device are coated with iron fluoride, aluminum oxide, chromium oxide, etc. You may do so.

[0274] It is preferable that the members of the film forming apparatus are made of metal only, for example, quartz. Even when installing a viewing window, the surface should be coated with iron fluoride or aluminum oxide to suppress gas emissions. It is recommended to thinly coat it with aluminum or chromium oxide.

[0275] In addition, if a refiner is installed just before introducing the deposition gas, the piping from the refiner to the deposition chamber The length of the pipe is 10 m or less, preferably 5 m or less, and more preferably 1 m or less. By setting the length to 10m or less, 5m or less, or 1m or less, the effect of gas released from the piping can be reduced can be reduced accordingly.

[0276] Furthermore, the inside of the film-forming gas piping is filled with iron fluoride, aluminum oxide, chromium oxide, etc. It is recommended to use coated metal piping. The above piping is, for example, SUS316L-EP piping. Compared to conventional gases, the amount of gas containing impurities released is smaller, reducing the amount of impurities entering the deposition gas. In addition, if high-performance ultra-small metal gasket fittings (UPG fittings) are used for piping fittings, In addition, by constructing the piping entirely from metal, the amount of emissions that occurs is less than when resin or other materials are used. This is preferable as it can reduce the influence of gas and external leaks.

[0277] The adsorbates present in the film deposition chamber are adsorbed to the inner walls, etc., and do not affect the pressure in the film deposition chamber. This causes gas emission when the deposition chamber is evacuated. Although there is no correlation, it is recommended to use a pump with high exhaust capacity to remove as much of the adsorbed matter as possible from the deposition chamber. It is important to desorb the adsorbed material and evacuate the gas beforehand. The deposition chamber may be baked. Baking increases the desorption rate of adsorbed substances by about 10 times. Baking can be performed at a temperature between 100°C and 450°C. When removing adsorbed substances while introducing an inert gas into the deposition chamber, the adsorbed substances cannot be removed by simply evacuating the chamber. The desorption rate of water, which is difficult to remove, can be further increased. Heating to the same temperature as baking can further increase the desorption rate of adsorbed substances. Here, it is preferable to use a rare gas as the inert gas. Alternatively, oxygen or the like may be used instead of an inert gas. In some cases, it may be preferable to use oxygen, which is the main component.

[0278] Alternatively, an inert gas such as a heated rare gas or oxygen may be introduced into the film formation chamber. It is preferable to increase the pressure and then evacuate the film formation chamber again after a certain period of time has elapsed. By introducing gas, it is possible to desorb adsorbed substances in the film formation chamber, and impurities present in the film formation chamber can be removed. This treatment can be carried out 2 to 30 times, preferably 5 to 15 times. It is effective to repeat this process within the range of 40°C to 400°C. Inert gas or oxygen, etc., preferably at a temperature of 50°C or higher and 500°C or lower, is introduced. The pressure in the deposition chamber is set to 0.1 Pa or more and 10 kPa or less, preferably 1 Pa or more and 1 kPa or less. More preferably, the pressure is set to 5 Pa or more and 100 Pa or less, and the pressure is maintained for 1 minute or more and 300 minutes or less. The time is preferably 5 minutes or more and 120 minutes or less. The air is evacuated for a period of time of not more than 10 minutes and not more than 120 minutes.

[0279] Furthermore, the desorption rate of the adsorbed substances can be further increased by forming a dummy film. - Film formation is performed on a dummy substrate by sputtering or other methods. A film is deposited on the substrate and the inner wall of the film deposition chamber, and impurities in the film deposition chamber and substances adsorbed on the inner wall of the film deposition chamber are removed by the film. The dummy substrate is preferably one that emits less gas. By forming a dummy film, the impurity concentration in the film to be formed later can be reduced. The film formation may be performed simultaneously with baking.

[0280] By forming an oxide semiconductor layer using the above-described film formation apparatus, impurities in the oxide semiconductor layer can be removed. Furthermore, by using the above film formation apparatus, it is possible to form a film in contact with the oxide semiconductor layer. By forming a film having a thickness of 1000 nm, impurities are prevented from entering the oxide semiconductor layer from the film in contact with the oxide semiconductor layer. This can suppress noise.

[0281] Next, a method for forming a CAAC-OS film using the above-described film formation apparatus will be described.

[0282] The target surface temperature is 100°C or less, preferably 50°C or less, and more preferably room temperature. The temperature is set to about 20°C or 25°C (typically 20°C or 25°C). In many cases, large-area targets are used in these devices. It is difficult to fabricate a seamless target. Although they are arranged as close to each other as possible to create a large shape, small gaps inevitably occur. The surface temperature of the target rises through these small gaps, causing Zn and other elements to volatilize. If the gap widens, it may cause problems with the backing plate or adhesive. The metals used may be sputtered, which increases the impurity concentration. Therefore, it is preferable that the target is sufficiently cooled.

[0283] Specifically, a metal having high electrical conductivity and high heat dissipation properties (e.g., In particular, Cu is used. In addition, a water channel is formed in the backing plate, and a sufficient amount of By flowing cooling water of this amount, the target can be cooled efficiently. It depends on the size of the target, but for example, for a circular target with a diameter of 300 mm, In this case, the flow rate should be 3 L / min or more, 5 L / min or more, or 10 L / min or more.

[0284] CAAC-OS is a substrate heating temperature of 100°C or higher and 600°C or lower, preferably 150°C or higher. Film formation is performed in an oxygen gas atmosphere at 550°C or less, more preferably 200°C to 500°C. The thickness of the CAAC-OS is 1 nm or more and 40 nm or less, preferably 3 nm or more and 20 nm or less. The higher the heating temperature during film formation, the lower the impurity concentration of the resulting CAAC-OS. In addition, migration of sputtered particles is more likely to occur on the surface where the film is to be formed. Therefore, the atomic arrangement is well-ordered, the density is high, and it becomes easy to form a CAAC-OS film with high crystallinity. Furthermore, by forming the film in an oxygen gas atmosphere, plasma damage is reduced, and the rare gas Since no unnecessary atoms such as these are included, it is easy to form a highly crystalline CAAC-OS film. However, a mixture of oxygen gas and rare gas may be used, in which case the ratio of oxygen gas is 3. 0% by volume or more, preferably 50% by volume or more, more preferably 80% by volume or more, and even more preferably Or 100% by volume.

[0285] When the target contains Zn, the plasma damage is reduced by forming the film in an oxygen gas atmosphere. Therefore, CAAC-OS can be obtained, in which the image is reduced and Zn volatilization is less likely to occur.

[0286] CAAC-OS is formed under a film-forming pressure of 0.8 Pa or less, preferably 0.4 Pa or less. The distance between the nozzle and the substrate is set to 40 mm or less, preferably 25 mm or less, during film formation. By depositing CAAC-OS under these conditions, the sputtering particles and the other sputtering particles can be separated. It is possible to reduce the frequency of collisions with particles, gas molecules or ions. The distance between the target and the substrate is adjusted accordingly to the mean average particle size of the sputtered particles, gas molecules, or ions. By making it smaller than the through-path, the concentration of impurities taken into the film can be reduced.

[0287] For example, the mean free path at a pressure of 0.4 Pa and a temperature of 25°C (absolute temperature of 298 K) The hydrogen molecule (H2) is 48.7 mm, the helium atom (He) is 57.9 mm, and the water molecule ( H2O) is 31.3 mm, methane molecule (CH4) is 13.2 mm, neon atom (Ne) 42.3mm, nitrogen molecules (N2) 23.2mm, carbon monoxide molecules (CO) 16.0m m, oxygen molecule (O2) 26.4 mm, argon atom (Ar) 28.3 mm, carbon dioxide The elementary molecule (CO2) is 10.9 mm, the krypton atom (Kr) is 13.4 mm, and the xenon atom The electron (Xe) is 9.6 mm. If the pressure is doubled, the mean free path will be halved. Therefore, if the absolute temperature doubles, the mean free path doubles.

[0288] The mean free path is determined by pressure, temperature, and the diameter of the molecule (atom). When the diameter of a molecule (atom) is fixed, the mean free path becomes shorter. The diameter of the atom is 0.218 nm for H2, 0.200 nm for He, and 0.27 nm for H2O. 2nm, CH4 0.419nm, Ne 0.234nm, N2 0.316nm, CO is 0.380nm, O2 is 0.296nm, Ar is 0.286nm, CO2 is 0.460 nm, Kr is 0.415 nm, and Xe is 0.491 nm.

[0289] Therefore, the larger the diameter of the molecule (atom), the shorter the mean free path and the easier it is to incorporate into the film. When it is mixed, the crystallinity decreases due to the large diameter of the molecule (atom). For example, molecules (atoms) with a diameter equal to or larger than that of Ar are likely to become impurities.

[0290] Next, a heat treatment is performed under reduced pressure in an inert atmosphere or an oxidizing atmosphere. The heat treatment can reduce the impurity concentration in the CAAC-OS.

[0291] Heat treatment is carried out under reduced pressure or in an inert atmosphere, and then the temperature is maintained while the material is heated in an oxidizing atmosphere. It is preferable to switch the atmosphere to a reduced pressure or an inert atmosphere and then carry out further heat treatment. The impurity concentration in CAAC-OS can be reduced by heat treatment at low temperature. This is because oxygen deficiency may occur at times, and the oxygen deficiency that occurs at this time is corrected by the oxidation of the This can be reduced by heat treatment.

[0292] CAAC-OS not only heats the substrate during film formation, but also performs heat treatment to reduce the impurity concentration in the film. It is possible to reduce

[0293] Specifically, the hydrogen concentration in the CAAC-OS was 2×10 20 atom s / cm 3 Less than or equal to 5 x 10 19 atoms / cm 3Less than or equal to 1× 10 19 atoms / cm 3 Less than 5 × 10, more preferably 18 atoms / cm 3 Below It can be below.

[0294] The nitrogen concentration in the CAAC-OS was 5×10 19 atoms / c m 3 Less than 5 x 10 18 atoms / cm 3 Less than 1×10, more preferably 1 8 atoms / cm 3 Less than 5 × 10, more preferably 17 atoms / cm 3 The following It is possible.

[0295] The carbon concentration in the oxide semiconductor layer was measured by SIMS and found to be 5×10 19 atoms / c m 3 Less than 5 x 10 18 atoms / cm 3 Less than or equal to 1×10 1 8 atoms / cm 3 Less than 5 × 10, more preferably 17 atoms / cm 3 The following It is possible.

[0296] In addition, CAAC-OS can detect gas molecules with m / z of 2 (such as hydrogen molecules) by TDS analysis. (atom), gas molecule (atom) with m / z 18, gas molecule (atom) with m / z 28 and m / z 44 gas molecules (atoms) are released at 1 × 10 19 pieces / cm 3 Less than 1 × 1018 pieces / cm 3 It can be as follows:

[0297] For details on how to measure the amount of released oxygen atoms using TDS analysis, see the section on measuring the amount of released oxygen atoms below. See description of method.

[0298] In this manner, a CAAC-OS film with high crystallinity can be formed.

[0299] Next, we developed a top-gate top-contact structure (T A transistor with a GTC structure will be described with reference to FIG.

[0300] FIG. 18A shows a top view and a cross-sectional view of a transistor having a TGTC structure. 18A shows a top view of the transistor. A cross-sectional view of the above is shown in FIG. 18(B). In FIG. 18(A), the cross-sectional view of the above is taken along the dashed line B3-B4. The corresponding cross section is shown in FIG.

[0301] The transistor shown in FIG. 18B includes a base insulating film 602 provided on a semiconductor substrate 600. an oxide layer 606a provided on the base insulating film 602; an oxide semiconductor layer 606b formed on the oxide semiconductor layer 606b; A multilayer film 606 including 6c, a source provided on the base insulating film 602 and the multilayer film 606 The multilayer film 606, the source electrode 616a and the drain electrode 616b, A gate insulating film 612 provided on the drain electrode 616b and a gate insulating film 616c provided on the gate insulating film 612 a gate electrode 604 formed on the gate insulating film 612 and a gate electrode 604; and a protective insulating film 618. Note that the transistor has a base insulating film 602 and / or The protective insulating film 618 may not be provided.

[0302] The source electrode 616a and the drain electrode 616b are disposed on the oxide semiconductor layer 606b side. It is provided in contact with the end portion.

[0303] As shown in FIG. 18(B), the source electrode 616a and the drain electrode 616b are Depending on the type of conductive film used, oxygen may be taken from a part of the oxide layer 606c, forming an n-type region. The n-type region may be formed by oxidizing the silicon dioxide to form the source and drain regions. The oxide layer has a large amount of oxygen vacancies, and the oxide layer has a large amount of oxygen vacancies. When a tungsten film is used as 616a, tungsten elements are mixed in the n-type region. Although not shown, an oxide layer is introduced into the region in contact with the oxide layer on the source electrode 616a side. The oxygen in the oxide layer may penetrate into the n-type region, forming a mixed layer. The n-type region described above is also formed on the side of the drain electrode 616b. In the figure, the boundary of the n-type region is indicated by a dotted line.

[0304] In FIG. 18A, in the region overlapping with the gate electrode 604, the source electrode 616a and The distance between the drain electrode 616b and the source region is called the channel length. When the gate electrode 604 includes a source region and a drain region, the gate electrode 604 overlaps the source region. The distance between the source and drain regions may be called the channel length.

[0305] The channel forming region is a region in the multilayer film 606 that overlaps with the gate electrode 604 and The region between the source electrode 616a and the drain electrode 616b. refers to the region in the channel formation region where current mainly flows. indicates a portion of the oxide semiconductor layer 606b in the channel formation region.

[0306] For the multilayer film 606, please refer to the description of the multilayer film 706 shown in FIG. The oxide semiconductor layer 606a is described in the description of the oxide layer 706c. The oxide layer 606c is the same as the oxide semiconductor layer 706a. Please refer to the description about.

[0307] The oxide layer 606c is composed of one or more elements that constitute the oxide semiconductor layer 606b. The energy of the conduction band minimum is 0.05 eV or more and 0. 07 eV or more, 0.1 eV or more, or 0.15 eV or more and 2 eV or less, 1 eV or less, It is an oxide layer with a potential of 0.5 eV or less or 0.4 eV or less, close to the vacuum level. The layer 606b preferably contains at least indium, since this increases carrier mobility. At this time, when an electric field is applied to the gate electrode 604, the conduction band minimum of the multilayer film 606 is A channel is formed in the oxide semiconductor layer 606b having low energy. By providing the oxide layer 606c between the dielectric layer 606b and the gate insulating film 612, The channel of the transistor is formed in the oxide semiconductor layer 606b that is not in contact with the gate insulating film 612. In addition, one or more elements forming the oxide semiconductor layer 606b can be used. Since the oxide layer 606c is formed, the boundary between the oxide semiconductor layer 606b and the oxide layer 606c is Therefore, the movement of carriers is not hindered at the interface. This increases the field effect mobility of the transistor.

[0308] The thickness of the oxide layer 606c is 3 nm to 100 nm, preferably 3 nm to 50 nm. The thickness of the oxide semiconductor layer 606b is preferably greater than or equal to 3 nm and less than or equal to 200 nm. The thickness is preferably 3 nm or more and 100 nm or less, and more preferably 3 nm or more and 15 nm or less. The thickness of the oxide layer 606a is 3 nm to 100 nm, preferably 3 nm to 50 nm. The following applies.

[0309] The oxide layer 606a contains one or more elements forming the oxide semiconductor layer 606b. and the energy of the conduction band minimum is 0.05 eV higher than that of the oxide semiconductor layer 606b. or more, 0.07 eV or more, 0.1 eV or more, or 0.15 eV or more and 2 eV or less, 1 eV or less, 0.5 eV or less, or 0.4 eV or less, which is close to the vacuum level. The oxide layer 606a is composed of one or more elements that compose the semiconductor layer 606b. Therefore, an interface state is unlikely to be formed at the interface between the oxide semiconductor layer 606b and the oxide layer 606a. If the interface has an interface state, a second transistor with a different threshold voltage will be generated using the interface as a channel. This can cause a transistor to form, which can cause the apparent threshold voltage of the transistor to fluctuate. By providing the oxide layer 606a, the electrical characteristics of the transistor, such as the threshold voltage, can be improved. This can reduce the variation in sex.

[0310] For example, the oxide layer 606a and the oxide layer 606c may have the same element as the oxide semiconductor layer 606b. The oxide semiconductor layer 606b is made of a material containing elements (indium, gallium, and zinc) as main components, and gallium is contained in the oxide semiconductor layer 606b. Specifically, the oxide layer 606a and the oxide layer 606b may be formed as oxide layers containing a higher atomic ratio than the oxide layer 606a. The oxide semiconductor layer 606c preferably contains 1.5 times more gallium than the oxide semiconductor layer 606b. The oxide layer contains gallium at an atomic ratio that is at least two times, more preferably at least three times higher than that of gallium. Since it strongly bonds with oxygen, it has the function of suppressing the occurrence of oxygen vacancies in the oxide layer. That is, the oxide layer 606a and the oxide layer 606c have a smaller oxygen deficiency than the oxide semiconductor layer 606b. This is an oxide layer that is less likely to develop cracks.

[0311] Note that the oxide layer 606a, the oxide semiconductor layer 606b, and the oxide layer 606c are amorphous. Preferably, the oxide layer 606a is amorphous or crystalline, and the oxide The semiconductor layer 606b is crystalline, and the oxide layer 606c is amorphous. Since the oxide semiconductor layer 606b is crystalline, the transistor has stable electrical characteristics. can be granted.

[0312] Other configurations of the transistor will be described below.

[0313] For the semiconductor substrate 600, refer to the description of the semiconductor substrate 800.

[0314] The source electrode 616a and the drain electrode 616b are made of aluminum, titanium, chromium, Cobalt, nickel, copper, yttrium, zirconium, molybdenum, ruthenium, silver, A conductive film containing one or more of tantalum and tungsten may be used in a single layer or a multilayer structure. The source electrode 616a and the drain electrode 616b may have the same composition or different compositions. For example, a laminate of a tungsten film and a tantalum nitride film may be used.

[0315] In FIG. 18(A), the multilayer film 606 is formed to the outside of the gate electrode 604. However, in order to suppress the generation of carriers by light in the multilayer film 606, A multilayer film 606 may be formed on the inner side of the electrode 604 .

[0316] The base insulating film 602 is made of aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, or the like. Silicon, silicon oxide nitride, silicon nitride, gallium oxide, germanium oxide, gallium oxide Thorium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide and oxide An insulating film containing one or more types of tantalum may be used as a single layer or a stacked layer.

[0317] The base insulating film 602 has, for example, a first layer made of silicon nitride and a second layer made of silicon oxide. In this case, the silicon oxide layer may be a silicon oxynitride layer. The silicon nitride layer may be a silicon nitride oxide layer. It is preferable to use a silicon oxide layer with a low degree of conductivity. The spin density of the spins originating from the signal of 1 is 3×10 17 spins / cm 3 The following is preferred: Kuha 5 x 10 16 spins / cm 3 A silicon oxide layer is used, which is: silicon nitride The layer uses a silicon nitride layer that releases less hydrogen and ammonia. The amount of released oxygen can be measured by TDS analysis. A thin or almost opaque silicon nitride layer is used.

[0318] Alternatively, the base insulating film 602 may have a first silicon nitride layer as a first layer and a second silicon nitride layer as a second layer. A multilayer film may be formed by using a first silicon oxide layer as the first layer and a third silicon oxide layer as the second layer. In this case, the first silicon oxide layer and / or the second silicon oxide layer is silicon oxynitride. The silicon nitride layer may be a silicon oxide nitride layer. The silicon layer is preferably a silicon oxide layer with a low defect density. The spin density of the spin originating from the signal with a g value of 2.001 at R is 3×10 17 spins / cm 3 Less than or equal to 5 x 10 16 spins / cm 3 A silicon oxide layer having a thickness of: The second silicon oxide layer is a silicon oxide layer having excess oxygen. The silicon nitride layer is a silicon nitride layer that releases less hydrogen and ammonia. The silicon layer uses a silicon nitride layer that is impermeable or almost impermeable to oxygen.

[0319] The silicon oxide layer containing excess oxygen is a layer that can release oxygen by heat treatment or the like. When the silicon oxide layer is expanded to an insulating film, it becomes an insulating film with excess oxygen. The film is an insulating film that has the function of releasing oxygen when subjected to a heat treatment.

[0320] Here, the film that releases oxygen by heat treatment has a TDS analysis of 1 × 10 18 at oms / cm 3 That's it, 1×10 19 atom / cm 3 or more than 1×10 20 atoms / cm 3 It may release more than 10 ...

[0321] Here, a method for measuring the amount of released oxygen using TDS analysis will be described below.

[0322] The total amount of gas released when the measurement sample is subjected to TDS analysis is calculated by the integral value of the ion intensity of the released gas. By comparison with a standard sample, the total amount of gas released can be calculated.

[0323] For example, the TDS analysis results of a silicon wafer containing hydrogen at a given density as a standard sample, From the results of the TDS analysis of the measurement sample, the amount of released oxygen molecules (N O2 ) is a mathematical expression ( 1) Here, the gas detected at mass number 32 obtained by TDS analysis is It is assumed that all of these are derived from oxygen molecules. There is also CH3OH, which has a mass number of 32. It is not considered here as it is unlikely to exist. Oxygen molecules containing oxygen atoms with mass numbers 17 and 18 also occur in nature. It is not taken into consideration because its abundance is extremely small.

[0324]

number

[0325] N H2 is the density converted value of hydrogen molecules desorbed from the standard sample. H2 is the standard This is the integrated value of the ion intensity when the sample is subjected to TDS analysis. Here, the reference value of the standard sample is N H2 / S H2 Let's say S O2 is the integral value of the ion intensity when the measurement sample is subjected to TDS analysis. α is a coefficient that affects the ion intensity in TDS analysis. Details of formula (1) For details, see Japanese Patent Application Laid-Open No. 6-275697. A thermal desorption analyzer EMD-WA1000S / W manufactured by Kagaku Co., Ltd. was used as a standard sample. 1×10 16 atoms / cm 2 The measurement is performed using a silicon wafer containing hydrogen atoms.

[0326] In addition, some of the oxygen is detected as oxygen atoms in TDS analysis. The atomic ratio can be calculated from the ionization rate of oxygen molecules. Since it includes the ionization rate of the molecules, evaluating the amount of released oxygen molecules can be used to estimate the amount of released oxygen atoms. It is also possible to estimate.

[0327] In addition, N O2 is the amount of released oxygen molecules. The amount of released oxygen atoms is This is twice the amount of offspring released.

[0328] Alternatively, the film that releases oxygen upon heat treatment may contain peroxide radicals. Specifically, the spin density due to peroxide radicals is 5×10 17 spins / cm 3 Below In addition, the film containing peroxide radicals has an ESR g value of approximately 2.01. It may also have asymmetric signals nearby.

[0329] Alternatively, the insulating film containing excess oxygen may be formed by converting silicon oxide (SiO X (X>2) Silicon oxide (SiO X (X>2) is the number of silicon atoms It contains more than twice as many oxygen atoms per unit volume as silicon per unit volume. The number of atoms and the number of oxygen atoms are values ​​measured by RBS.

[0330] At least one of the gate insulating film 612 and the base insulating film 602 is an insulating film containing excess oxygen. When the oxide semiconductor layer 606b contains the fluorine atom, oxygen vacancies in the oxide semiconductor layer 606b can be reduced.

[0331] The protective insulating film 618 is made of aluminum oxide, magnesium oxide, silicon oxide, or Silicon nitride, silicon oxynitride, silicon nitride, gallium oxide, germanium oxide, oxide yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide and An insulating film containing one or more of tantalum oxide and tantalum oxide may be used as a single layer or a stacked layer.

[0332] The transistor configured as described above has a structure in which the oxide semiconductor layer 606b of the multilayer film 606 The formation of a channel provides stable electrical properties and high field-effect mobility. do.

[0333] Here, a method for manufacturing a transistor will be described with reference to FIGS.

[0334] First, a semiconductor substrate 600 on which an insulating base film 602 is formed is prepared. As the method for forming the silicon oxide layer, a sputtering apparatus is used to form a silicon oxide layer containing excess oxygen.

[0335] Next, an oxide layer that will become the oxide layer 606a is formed. A 0 nm thick IGZO (In:Ga:Zn=1:3:2) film is used. The film was formed using a sputtering device under the conditions of: Temperature 200℃, Ar / O2=30 / 15sccm, deposition pressure=0.4Pa, deposition power (DC ) = 0.5 kW, and the substrate-target distance (TS distance) = 60 mm.

[0336] Next, an oxide semiconductor layer to be the oxide semiconductor layer 606b is formed. For b, a 15 nm thick IGZO (In:Ga:Zn=1:1:1) film is used. The deposition conditions for the IGZO (In:Ga:Zn=1:1:1) film are sputtering. The substrate temperature was 300°C, Ar / O2=30 / 15sccm, and the deposition pressure was 0.4P. a, deposition power (DC) = 0.5 kW, substrate-target distance (TS distance) = 60 m Let m.

[0337] Next, an oxide layer that will become the oxide layer 606c is formed. The IGZO (In:Ga:Zn=1:3:2) film with a thickness of 1000 nm is used. The conditions for forming the Ga:Zn=1:3:2) film were as follows: a sputtering device was used; the substrate temperature was 200℃, Ar / O2=30 / 15sccm, deposition pressure=0.4Pa, deposition power (DC) = 0.5 kW, substrate-target distance (TS distance) = 60 mm.

[0338] Next, first heat treatment is preferably performed at a temperature of 250° C. or higher and 650° C. or lower. The first heat treatment is preferably performed at a temperature of 300° C. or higher and 500° C. or lower. oxidizing gas atmosphere, atmosphere containing 10 ppm or more, 1% or more, or 10% or more of oxidizing gas, Alternatively, the first heat treatment is carried out under reduced pressure. Alternatively, the first heat treatment is carried out under an inert gas atmosphere. After the treatment, oxidizing gas is added at 10 ppm or more, 1% or more, or 1% or more to replace the oxygen that has been removed. The heat treatment may be performed in an atmosphere containing 0% or more of the oxide semiconductor. The crystallinity of the oxide semiconductor layer 606b is improved, and the base insulating film 602 and the oxide layer 606 are formed. an oxide layer to be the oxide semiconductor layer 606a, an oxide semiconductor layer to be the oxide semiconductor layer 606b, and / or an oxide semiconductor layer Impurities such as hydrogen and water can be removed from the oxide layer that will become the oxide layer 606c.

[0339] Next, an oxide layer to be the oxide layer 606a and an oxide semiconductor layer to be the oxide semiconductor layer 606b are A part of the oxide layer that will become the oxide layer 606c is etched, and the oxide layer 606a and the oxide layer 606b are removed. A multilayer film 606 including an oxide semiconductor layer 606b and an oxide layer 606c is formed (FIG. 19(A) )reference.).

[0340] Next, a conductive film that will become the source electrode 616a and the drain electrode 616b is formed.

[0341] Next, a part of the conductive film that will become the source electrode 616a and the drain electrode 616b is etched. Then, a source electrode 616a and a drain electrode 616b are formed (see FIG. 19(B)). .

[0342] Next, it is preferable to carry out a second heat treatment. For the second heat treatment, refer to the description of the first heat treatment. The second heat treatment removes impurities such as hydrogen and water from the multilayer film 606. can be removed.

[0343] Next, a gate insulating film 612 is formed (see FIG. 19(C)). The gate insulating film 612 is For example, the first layer is a first silicon oxide layer, and the second layer is a second silicon oxide layer 418b. The first silicon oxide layer is a silicon nitride layer, and the third layer is a silicon nitride layer. The layer and / or the second silicon oxide layer may be a silicon oxynitride layer. The silicon layer may be a silicon nitride oxide layer. The first silicon oxide layer has a low defect density. It is preferable to use a small silicon oxide layer. The spin density of the spins originating from the number is 3×10 17 spins / cm 3 Below, preferably 5 x10 16 spins / cm 3 The following silicon oxide layers are used: The layer is a silicon oxide layer with excess oxygen. The silicon nitride layer is a layer containing hydrogen and ammonia. The silicon nitride layer has a low oxygen emission rate. A thin or almost opaque silicon nitride layer is used.

[0344] Next, a conductive film that will become the gate electrode 604 is formed.

[0345] Next, a part of the conductive film that will become the gate electrode 604 is etched to form the gate electrode 604. (See Figure 20(A)).

[0346] Next, a protective insulating film 618 is formed (see FIG. 20(B)).

[0347] In the above manner, the transistor shown in FIG. 18 can be manufactured.

[0348] In the transistor, oxygen vacancies in the oxide semiconductor layer 606b of the multilayer film 606 are reduced. Therefore, it has stable electrical properties.

[0349] (Embodiment 7) The microcontroller disclosed in this specification is suitable for various electronic devices (including gaming machines). The electronic devices can be used in a variety of applications, including televisions, monitors, and other display devices, lighting devices, and desks. A desktop or laptop personal computer, a word processor, a DVD (Di Still images or images stored on recording media such as Digital Versatile Disc Video playback devices, portable CD players, radios, tape recorders, headsets Cordless phone stereos, stereos, cordless phone handsets, transceivers, mobile phones, car phones , portable game consoles, calculators, personal digital assistants, electronic organizers, e-books, electronic translators, voice input devices appliances, video cameras, digital still cameras, electric shavers, IC chips, microwave ovens, etc. High frequency heating devices, electric rice cookers, electric washing machines, electric vacuum cleaners, air conditioners, etc. Cooking equipment, dishwashers, dish dryers, clothes dryers, futon dryers, electric refrigerators, electric freezers, Examples include electric refrigerator-freezers, freezers for DNA storage, radiation detectors, dialysis machines, and other medical equipment. Other examples include alarm devices such as smoke detectors, gas alarms, and burglar alarms. Furthermore, guide lights, traffic lights, conveyor belts, elevators, escalators, and industrial robots and industrial equipment such as power storage systems. Mobile bodies propelled by electric motors using power from secondary batteries are also included in the category of electrical equipment. The above-mentioned moving body may be, for example, an electric vehicle (EV), which has an internal combustion engine and an electric motor. Hybrid electric vehicles (HEVs), plug-in hybrid electric vehicles (PHEVs), Tracked vehicles that have wheels replaced with endless tracks, motorized bicycles including electrically assisted bicycles, Motorcycles, electric wheelchairs, golf carts, small or large boats, submarines, helicopters , aircraft, rockets, satellites, space probes, planetary probes, and spacecraft. A specific example of such an electronic device is shown in FIG.

[0350] In FIG. 21(A), an alarm device 8100 is a residential fire alarm, and includes a detection unit and an oxidation It has a microcomputer 8101 that uses semiconductors.

[0351] In FIG. 21(A), an air conditioner having an indoor unit 8200 and an outdoor unit 8204 is shown. The core is an example of an electrical device that uses a microcomputer that uses an oxide semiconductor. Specifically, the indoor unit 8200 includes a housing 8201, an air outlet 8202, a microcomputer 82 21A, the microcomputer 8203 controls the indoor unit 82 8. The microcomputer 8203 is installed in the outdoor unit 8 Alternatively, both the indoor unit 8200 and the outdoor unit 8204 may be provided with a A microcomputer 8203 may be provided. Power saving by using a computer as the microcomputer of an air conditioner This will help to strengthen our capabilities.

[0352] In FIG. 21A, an electric refrigerator-freezer 8300 is a microcomputer using an oxide semiconductor. Specifically, the electric refrigerator-freezer 8300 is an example of an electric device equipped with a computer. 301, refrigerator door 8302, freezer door 8303, microcomputer 8304, etc. In FIG. 21A, a microcomputer 8304 is installed inside a housing 8301. The transistor described in the above embodiment is used in the microphone of the electric refrigerator-freezer 8300. By using it in the microcomputer 8304, power saving can be achieved.

[0353] FIG. 21(B) shows an example of an electric vehicle, which is an example of an electric device. The power of the secondary battery 9701 is supplied to the control circuit 97 The output is adjusted by the control circuit 9702 and supplied to the driving device 9703. Controlled by a microcomputer 9704 with ROM, RAM, CPU, etc. not shown The microcomputer using oxide semiconductors will be used as the microcomputer for the electric vehicle 9700. By using it in the computer 9704, power saving can be achieved.

[0354] The drive unit 9703 is a DC motor or an AC motor alone, or a motor and an internal combustion engine. The microcomputer 9704 controls the operation of the electric vehicle 9700. Operation information of the cyclist (acceleration, deceleration, stopping, etc.) and information during driving (uphill and downhill slopes, driving Based on input information (such as load information on the driving wheels), a control signal is output to the control circuit 9702. The control circuit 9702 controls the secondary battery 9 The output of the drive unit 9703 is controlled by adjusting the electrical energy supplied from 701. If a DC motor is installed, an inverter (not shown) that converts DC to AC is also installed. Built-in.

[0355] (Embodiment 8) In this embodiment, the switch of the microcomputer described in the previous embodiment is The first transistor 902 has a channel formation region formed using an oxide semiconductor. Example of cross-sectional structure when a single crystal silicon wafer is used for the channel formation region as the sintered body 901 This is shown in FIG. 22, and an example of the manufacturing method thereof will be described below.

[0356] However, the second transistor 901 of the switch is made of single crystal silicon or germanium. Semiconductor materials such as silicon, silicon germanium, and silicon carbide may also be used. For example, a silicon transistor is made of a silicon thin film fabricated by the SOI method. The insulating film can be formed by using a silicon thin film produced by vapor phase growth.

[0357] In this embodiment, a cross section of only a part of the structure of the switch is shown. The stacked structure can be used to fabricate logic elements and other circuit configurations.

[0358] The second transistor 901 is fabricated using a substrate 900 containing a semiconductor material. N-channel transistor (NMOSFET), p-channel transistor (PMOSFET) In the example shown in FIG. 22, the second transistor 901 is equipped with STI (Shallow Trench Isolation) 905 The element is isolated from the STI905. This can suppress bird's beaks in the element isolation area that occur during isolation, and reduces the size of the element isolation area. On the other hand, in semiconductor devices where miniaturization of the structure is not required, the STI905 The formation of the insulating film is not necessarily required, and an element isolation means such as LOCOS may be used. The substrate 900 on which the transistor 901 is formed is doped with conductive material such as boron, phosphorus, or arsenic. A well 904 is formed in which impurities are added to provide the desired conductivity.

[0359] The second transistor 901 in FIG. 22 is a channel-forming transistor provided in a substrate 900. and impurity regions 906 (source and drain regions) provided so as to sandwich the channel forming region. a gate insulating film 907 provided on the channel forming region; a gate electrode layer 908 provided on the gate insulating film 907 so as to overlap with the channel forming region; The gate electrode layer is made of a first material for improving processing accuracy. The gate electrode layer is made of a second material and is laminated to reduce the resistance of the wiring. For example, crystalline silicon doped with impurities such as phosphorus to provide conductivity and nickel However, it is not limited to this structure and can be made as required. The material, number of layers, shape, etc. can be adjusted according to the specifications.

[0360] In addition, the impurity region 906 provided in the substrate 900 is provided with contact plugs 913 and 9 Here, the contact plugs 913 and 915 are connected to the second transistor. The impurity region 906 also functions as a source electrode and a drain electrode of the transistor 901. An impurity region different from the impurity region 906 may be provided between the impurity region and the channel region. The material region can be configured as an LDD region or an extension region depending on the concentration of the introduced impurities. It functions to control the electric field distribution in the vicinity of the channel forming region. The insulating film 909 has a sidewall insulating film 909 interposed therebetween. By using the insulating film 909, it is possible to form an LDD region and an extension region. .

[0361] The second transistor 901 is covered with an insulating film 910. The 0 can function as a protective film, preventing impurities from entering the channel formation region from the outside. In addition, the insulating film 910 can be formed by nitriding silicon by the PE-CVD method. When single crystal silicon is used for the channel formation region, The insulating film 910 can be hydrogenated by the treatment. By using an insulating film having such a property, strain can be applied to the semiconductor material that constitutes the channel formation region. In the case of an n-channel transistor, the silicon material that becomes the channel formation region is In the case of a p-channel transistor, tensile stress is applied to the silicon that forms the channel region. By applying compressive stress to the silicon material, the field-effect mobility of each transistor can be improved. can be done.

[0362] Furthermore, an insulating film 911 is provided on the insulating film 910, and its surface is planarized by CMP. As a result, the second transistor 901 is The device layers can be stacked with high precision.

[0363] An oxide semiconductor film is formed in a channel formation region above the layer including the second transistor 901. A layer including a first transistor 902 and a capacitor 903 used in the region is formed.

[0364] The first transistor 902 includes a multilayer film 926, a source electrode layer 927, and a drain electrode A top gate structure including a layer 928, a gate insulating film 929, and a gate electrode layer 930. The first transistor 902 is the same as the transistor shown in FIG. 20 of the previous embodiment. Since the same configuration as that of the transistor can be used, it can be formed by taking the above description into consideration. Therefore, other configurations will be described below.

[0365] The insulating film 924 is formed using an oxygen-releasing oxide insulating film that releases oxygen by heat treatment. It is suitable.

[0366] The oxide insulating film from which some oxygen is released by heating is Oxygen can be diffused into the oxide semiconductor film in the multilayer film 926 formed in the above manner. When a silicon oxide film is used as the insulating film 924, SiO 2+α (However, α> 0) By using such an insulating film 924, oxygen can be supplied to the oxide semiconductor film. By supplying oxygen to the oxide semiconductor film, oxygen vacancies in the oxide semiconductor film can be reduced. can be compensated for.

[0367] The insulating film 924 may be formed by sputtering, PE-CVD, or the like. For example, when the insulating film 924 is formed by the PE-CVD method, water derived from the source gas Therefore, when the PE-CVD method is used to form the insulating film 924, the insulating film 924 may be contaminated with oxygen or water. After forming 924, it is preferable to perform heat treatment for dehydrogenation or dehydration. The temperature of the heat treatment is preferably a temperature at which hydrogen or water is released from the insulating film 924. The heat treatment can be performed using an electric furnace, an RTA device, or the like. Heat treatment can be performed at temperatures above the strain point of the substrate for a short period of time. The time for hydrogen or water to be released from the film 924 can be reduced.

[0368] The heat treatment can dehydrogenate or dehydrate the insulating film 924. The diffusion of hydrogen or water into the oxide semiconductor film in the multilayer film 926 can be suppressed. Cut.

[0369] Furthermore, by introducing oxygen into the insulating film 924, the amount of oxygen desorbed by heating is increased. Oxygen can be introduced into the insulating film 924 by ion implantation, ion irradiation, or the like. There are doping methods, plasma treatments, etc.

[0370] The multilayer film 926 includes a first oxide layer formed in contact with the insulating film 924 side, and a second oxide layer formed on the first oxide layer. forming an oxide semiconductor layer in contact with the oxide semiconductor layer; and forming a second oxide layer in contact with the oxide semiconductor layer. Use structure.

[0371] The gate electrode layer 930 and the upper electrode layer 931 have a thickness of 10 nm to 400 nm, preferably In this embodiment, a film thickness of 30 nm is formed by a sputtering method. A 135 nm thick tungsten film was laminated on a 100 nm thick tantalum nitride film to form a conductive film for the gate electrode. After forming the film, the conductive film is processed (patterned) into a desired shape by etching. Thus, a gate electrode layer 930 and an upper electrode layer 931 are formed. If the resist mask is formed by the ink jet method, the photoresist Since no mask is used, manufacturing costs can be reduced.

[0372] The first transistor 902 is provided with a back gate electrode layer 923. When the gate electrode layer 923 is provided, the normally-off state of the first transistor 902 is further increased. For example, the potential of the back gate electrode layer 923 can be set to GND or a fixed voltage. By making the threshold voltage of the first transistor 902 more positive, In this way, the first transistor 902 can be an off-state transistor. Alternatively, a transistor having a multi-gate structure having a plurality of channel formation regions may be used.

[0373] The second transistor 901, the first transistor 902, and the capacitor 903 In order to electrically connect these layers to form an electrical circuit, wiring layers for connection between each layer and upper layers are are laminated in a single layer or multiple layers.

[0374] In FIG. 22, either the source or the drain of the second transistor 901 is connected to a contact. The wiring layer 914 is electrically connected to the logic layer 914 via the plug 913. The source of the second transistor 901 is electrically connected to the output terminal of the The other of the drains is electrically connected to a wiring layer 916 via a contact plug 915. There are.

[0375] The wiring layer 916 is electrically connected to the input terminals of other logic elements. The gate of the transistor 901 is connected to a contact plug 917, a wiring layer 918, a contact The first transistor 90 is connected to the first electrode 921 via the plug 921, the wiring layer 922, and the contact plug 925. The second drain electrode layer 928 is electrically connected to the second drain electrode layer 928.

[0376] The drain electrode layer 928 extends rightward in FIG. The drain electrode layer 928 functions as a gate insulating layer of the first transistor 902. The gate insulating film 929 is formed on the capacitor element 903. In this region, it functions as an inter-electrode dielectric film of the capacitance element 903. The upper electrode layer 931 is connected to the semiconductor substrate 900 via a contact plug 935. It is electrically connected to the wiring layer 936 .

[0377] The wiring layers 914, 916, 918, 922, 936 and the back gate electrode layer 923 are These wiring layers are made of low resistance materials such as copper and aluminum. It is preferable to use a conductive material with high conductivity. Graphene can also be used as a conductive material to form wiring layers. 2 join A sheet of carbon molecules of 1 atomic layer having Graphene is a material made up of stacks of metals. Thermal CVD is used to form graphene on the substrate, and ultraviolet light is used to generate plasma locally. One example is the PE-CVD method, which uses methane to form graphene without using a catalyst by heating the material.

[0378] By using such low-resistance conductive materials, the RC delay of signals propagating through the wiring layer can be reduced. When copper is used for the wiring layer, the copper diffusion into the channel forming region can be prevented. To prevent this, a barrier film is formed. For example, tantalum nitride or tantalum nitrate is used as the barrier film. and tantalum lamination, titanium nitride, titanium nitride and titanium lamination, etc. However, the function of preventing the diffusion of wiring materials and adhesion to wiring materials and base films, etc. are ensured. The barrier film is not limited to a film made of these materials in terms of the degree of insulation. Alternatively, a material that will become a barrier film may be contained in the wiring material, and the insulating film may be formed by heat treatment. It may be formed by deposition on the inner wall of an opening provided in the film.

[0379] The insulating films 911, 912, 919, 920, 933, and 934 are made of silicon oxide, oxynitride, or the like. Silicon nitride, silicon oxide nitride, BPSG (Boron Phosphorus Sil icate Glass), PSG(Phosphorus Silicate Gla ss), carbon-doped silicon oxide (SiOC), fluorine-doped silicon oxide (S iOF, TEOS (Tetra), a silicon oxide made from Si(OC2H5)4 ethyl orthosilicate), HSQ(Hydrogen Silses) quioxane), MSQ(MethylSilsesquioxane), OSG( Organo Silicate Glass, organic polymer-based materials, etc. In particular, when semiconductor devices are miniaturized, the parasitic capacitance between wirings becomes significant. This increases the signal delay, so the relative dielectric constant of silicon oxide (k=4.0 to 4.5) is high. It is preferable to use a material having k of 3.0 or less. The insulating film must have sufficient mechanical strength to undergo CMP processing. As long as the dielectric constant is low, these can be made porous to reduce the dielectric constant. The coating is made by the sputtering method, CVD method, and spin-on glass (Spin On Glass) method. It is formed by a coating method including SOG.

[0380] The insulating films 911, 912, 919, 920, 933, and 934 are used to insulate wiring materials. After being embedded in the film, it functions as an etching stopper when performing planarization processing such as CMP. An insulating film for enhancing the function may be provided separately.

[0381] On the wiring layers 914, 916, 918, 922, 936 and the back gate electrode layer 923 A barrier film is provided on the insulating film, and a protective film is provided on the barrier film. The barrier film is a film intended to prevent the diffusion of wiring materials. It can be made of insulating materials such as iC and SiBON. However, the barrier film is thick. In this case, it is a factor that increases the capacitance between wirings, so a material with barrier properties and low dielectric constant is required. It is preferable to select

[0382] The contact plugs 913, 915, 917, 921, 925, and 935 are formed by applying high adhesion to the insulating film. By forming an opening (via hole) with the desired aspect ratio and filling it with a conductive material such as tungsten, It is preferable to form the opening by dry etching, which is highly anisotropic. It is preferable to use the ion etching method (RIE method). The inner wall of the opening is made of a titanium film and a nitrogen film. A barrier film (diffusion prevention film) made of a titanium dioxide film or a laminated film thereof is provided, and the barrier film The inside of the hole is filled with a material such as polysilicon doped with tungsten or phosphorus. By using the blanket CVD method, tungsten can be embedded in the via hole, and CM The upper surface of the contact plug is flattened by P.

[0383] A protective insulating film 937 is provided on the top layer to prevent moisture and contaminants from entering the semiconductor device from the outside. The protective insulating film 937 is made of a silicon nitride film, a silicon oxynitride film, ... The insulating film 10 can be formed using a material such as silicon dioxide, and may be a single layer or a multilayer.

[0384] By configuring the semiconductor device as described above, the first semiconductor material having high speed operation performance can be obtained. and a transistor using a second semiconductor material with extremely low off-state current. By combining this with a microcomputer, it is possible to create a microcomputer that can consume less power. .

[0385] This embodiment mode can be implemented in appropriate combination with other embodiment modes. [Example]

[0386] FIG. 10 is an optical microscope image of a microcontroller 500 fabricated using a silicon substrate. The microcontroller 500 is the microcontroller described with reference to FIG. 190. In addition, in FIG. 10, the circuit block shown in FIG. Some of the reference numerals corresponding to the circuit blocks are added.

[0387] The process technology of the microcontroller 500 in FIG. 10 is also the same as that of the microcontroller in FIG. Like the Controller 100, the transistors are made from silicon and are 0.35 μm thick. The transistor made from the oxide semiconductor layer is 0.8 μm. The size of the roller 500 is 11.0 mm x 12.0 mm.

[0388] Operate the microcontroller 500 and switch it from Active mode to Power OFF mode. Even if the mode is changed to the Noff2 mode, the data in the register 185 of the CPU 110 is maintained. Using the signal waveform diagrams in Figures 23 and 24, the results were as follows: explain.

[0389] To check whether data is retained, check the HL The data is stored in the register, and the power supply is stopped in Nooff2 mode. This was done by reading the data in the HL register after returning to ve mode.

[0390] 23, 24A, and 24B show the Tektronix TLA7P pattern generator. The signal generated by G2 is input to the microcontroller 500. The signal generated at the input / output terminal (connection terminal) of the 500 is measured by the company's logic analyzer TLA7AA. The results of measurements using 2 are shown. "ADDR", "DATA", and "CPU_VDD" shown in FIGS. 23, 24A, and 24B "MREQ_B", "RD_B", "WR_B", and "NMI_B" are the logic These are the names of the input and output terminals measured by the analyzer.

[0391] The "ADDR" terminal receives the step number (sequentially according to the number of processes) counted by the CPU 110. It is possible to detect the value (value that changes) or the address that the CPU 110 accesses. In addition, the "DATA" terminal receives the data executed by the CPU 110 in the microcontroller 500. It is possible to detect instruction codes and data input and output by the microcontroller 500. Also, the "CPU_VDD" terminal detects the VDD voltage supplied to the CPU 110. It is possible.

[0392] In addition, the "MREQ_B" terminal detects a signal that determines whether or not to access external memory. When the "MREQ_B" terminal is at low potential, access to the external memory is permitted. When the "MREQ_B" terminal is at a high potential, access to the external memory is denied. Also, when the "MREQ_B" terminal is at low potential and the "RD_B" terminal is at low potential, Reading data from external memory is permitted and the "MREQ_B" terminal is set to Low. When the "WR_B" terminal is at a low potential, writing data to external memory is permitted. .

[0393] In addition, the "NMI_B" terminal can detect non-maskable interrupt signals. Normally, a high potential is supplied to the "NMI_B" terminal. When a low potential is supplied, an interrupt process is executed.

[0394] Note that a high potential is a potential higher than the reference potential, and a low potential is a potential lower than the reference potential. When the reference potential is 0V, the high potential is a positive potential and the low potential is a negative potential. In addition, either the high potential or the low potential can be It may also be set to the same potential as the reference potential.

[0395] 23. Furthermore, the period 511 and the period 515 shown in FIG. 23 are periods when the microcontroller 500 is in Act mode. In addition, the period 512 is a period during which the microcontroller 5 operates in the active mode. Before 00 transitions from Active mode to Noff2 mode, the volatile This is a period of time during which data is saved from the storage unit to the nonvolatile storage unit. is the period during which the microcontroller 500 operates in the Noff2 mode. A period 514 is when the microcontroller 500 transitions from the No.off2 mode to the Active mode. Before returning to the normal mode, the data in each register is written back to the volatile storage. This is the recovery processing period.

[0396] Also, a portion of the signal measured during period 511 operating in Active mode is enlarged, 24A as a signal during period 591. Also, during the period when the device is operating in Active mode, A portion of the signal measured at 515 during period 515 is enlarged and shown as the signal during period 592 in FIG. 24B. Shown below.

[0397] During period 511 (active mode period), the HL register, which is part of the register 185, This process is called process 596. (See Figure 24A.) During process 596, when the "ADDR" terminal is "0007", The "21" detected at the " terminal is the instruction code to store data in the HL register. In addition, the "55" and "AA" detected at the "DATA" terminal are then stored in the HL register. The microcontroller 500 stores data in 1-byte units. In order to process the data, the lower byte "55" is detected first, and then the upper byte "AA" was detected (see Figures 23 and 24A).

[0398] Next, the microprocessor in the transition process from Active mode to Noff2 mode shown in Figure 4 The operation check of the controller 500 will be described.

[0399] To check this operation, the signal to switch the operation mode to Noff2 mode is sent to the microcomputer. The signal to switch to Noff2 mode is input to the microcontroller 500. When the data is input to the microcontroller 500, the microcontroller 500 reads the data in registers (184-187). The data stored in the volatile memory must be retained even after the power supply is stopped. The data is transferred to the nonvolatile storage unit and stored in the nonvolatile storage unit (period 512). The data "AA55" stored in the HL register, which is a volatile memory unit, is also transferred to the non-volatile memory unit. and stored in the nonvolatile storage unit.

[0400] When the transfer and storage of data to the nonvolatile storage unit is completed, the microcontroller 500 , the power gate unit 130 is operated, the power supply to each circuit block is cut off, and No In the period 513 in FIG. 23, the "CPU_VDD" terminal This indicates that the power supply to the child has been stopped.

[0401] Next, the microprocessor in the transition process from Nooff2 mode to Active mode shown in Figure 5 The operation check of the controller 500 will be described.

[0402] To return from Noff2 mode to Active mode, set the "NMI_B" terminal to Low potential. When a low potential is supplied to the "NMI_B" terminal, the power The gate unit 130 operates to restart the power supply to each circuit block. The data stored in the nonvolatile storage unit is transferred to the volatile storage unit and stored in the volatile storage unit. At this time, the data "AA55" stored in the nonvolatile memory is also transferred to the HL register. The data is stored back in the register (period 514).

[0403] When the data recovery from the non-volatile memory to the volatile memory is completed, the microcontroller 5 00 resumes operation in the Active mode based on the restored data (period 515).

[0404] Subsequently, in the period 515, the process 597 and the process 598 are performed, and the HL register is restored. The data was then verified.

[0405] During process 597, when the "ADDR" terminal is "0023", The "22" is the instruction code to transfer the data stored in the HL register to external memory. In addition, the "FD" and "7F" detected at the "DATA" terminal are The address of the external memory to which the data is to be transferred is "7FFD" (see Figure 23 and Figure 24). 24B).

[0406] In step 598 following step 597, the microcontroller 500 reads the data in the HL register. As mentioned above, the microcontroller 500 transfers the data to the external memory. In addition, external memory stores 1 byte of data at one address. Therefore, the microcontroller 500, which has received the command of process 597, performs process 598. First, the lowest byte of data in the HL register is read from the external memory address "7F FD”, then transfer the upper byte of data to address “7FFE” in external memory. Send.

[0407] Referring to FIG. 24B, in process 598, the microcontroller 500 first reads "ADDR" "7FFD" is output to the terminal, and the data for the lower byte of the HL register is output to the "DATA" terminal. At this time, the "MREQ_B" terminal and the "W By supplying a low potential to the "R_B" terminal, "5FFD" is written to the address "7FFD" in the external memory. 5" is written.

[0408] Next, the microcontroller 500 outputs "7FFE" to the "ADDR" terminal, DATA terminal as the upper byte of data in the HL register. At this time, the "MREQ_B" terminal and the "WR_B" terminal are By supplying the w potential, "AA" is written to address "7FFE" in the external memory. .

[0409] Measurement results of "ADDR" terminal and "DATA" terminal in process 597 and process 598 From this, it can be seen that the data "AA55" is stored in the HL register during the period 515. Therefore, the microcontroller 500 is in the Active mode and the power supply is cut off. Even if the mode is switched to Noff2 mode, the data in register 185 is retained. It was also confirmed that even after returning from Nooff2 mode to Active mode, It was confirmed that the Microcontroller 500 was operating normally.

[0410] In addition, necessary data can be saved in the non-volatile memory of the register before power is cut off. That is, the microcontroller 500 is powered off even before the CPU processing is completed. Since it is possible to start processing for the power supply, there is a high degree of freedom in the timing of power cutoff. Provide a microcontroller that can quickly return to normal operation mode from a power-saving mode It was confirmed that this is possible. [Explanation of symbols]

[0411] MCLK, TCLK clock signals T0IRQ, P0IRQ, C0IRQ, INT, NMI interrupt signals 100, 190, 500 microcontrollers Units 101-104 110 CPU 111 Bus Bridge 112 RAM 113 Memory Interface 115 Clock Generation Circuit 120 Controller 121 Interrupt Controller 122, 146, 152 I / O interfaces 130 Power gate unit 131, 132 Switch circuit 140 Clock Generation Circuit 141 Crystal Oscillator Circuit 142 Oscillator 143 Crystal Oscillator 145 Timer Circuit 150 I / O ports 151 Comparator 161-163 Bus Line 164 data bus lines 170-176 Connection terminal 180, 183-187 register FN node 200 Registers 201, 202 memory circuit 203, 204, 207 Transistors 205 Capacitor 206 Transmission Gate 208 Inverter 209 Inverter BL bit line RWL Word Line WWL Word Line 400 memory cells 401-403 Transistor 404 Capacitor 405 Power supply line 511-515, 591, 592 period 596-598 Processing 800 semiconductor substrates 801 Element isolation insulating film 802 p-well 803, 807 Impurity region 804, 808 Low concentration impurity region 805, 809 Gate electrodes 806, 831 Gate insulating film 810-813, 817-820, 822, 823 wiring 816, 821, 824, 844, 845 Insulating film 830 Oxide semiconductor layer 832, 833, 846 Conductive film 834 gate electrode 835, 836 sidewall 860-862 transistor

Claims

1. a terminal to which a power supply potential is input; a CPU that executes instructions; a non-volatile memory for storing the instructions; a first peripheral circuit having a function of measuring time and outputting a first interrupt signal; a second peripheral circuit that is an interface with an external device and outputs a second interrupt signal; a third peripheral circuit that processes an analog signal input from the outside and outputs a third interrupt signal; an interrupt controller having a function of assigning priorities to the first to third interrupt signals; first to fifth registers for the first to third peripheral circuits, the CPU, and the interrupt controller; a power gate that supplies and stops the power supply potential to the first to third peripheral circuits, the CPU, the memory, the interrupt controller, and the first, fourth, and fifth registers; a controller for controlling the power gate; a sixth register for the controller, the interrupt controller determines whether the first to third interrupt signals are valid, and if the first to third interrupt signals are valid, outputs a fourth interrupt signal to the controller; a memory cell of the memory including a transistor using a multilayer film including an oxide semiconductor layer and a transistor using silicon; The operation modes include at least first to third operation modes, the first operating mode is a mode in which all circuits of the microcontroller are active; the second operation mode is a mode in which the controller, the first peripheral circuit, and the first, second, and sixth registers are activated and other circuits are deactivated; the third operation mode is a mode in which the controller and the sixth register are activated and other circuits are deactivated; A transition process from the first operation mode to the second or third operation mode is initiated by an instruction from the CPU, a transition process from the second operation mode to the first operation mode is initiated by inputting the first interrupt signal to the controller; a transition process from the third operation mode to the first operation mode is initiated when an external interrupt signal is input to the controller; the first, fourth, and fifth registers each have a volatile memory unit and a non-volatile memory unit, and when the power supply is cut off by the power gate, data in the volatile memory unit is saved to the non-volatile memory unit before the power supply is cut off, and when the power supply is resumed by the power gate, the data saved in the non-volatile memory unit is written to the volatile memory unit.

2. In claim 1, the first peripheral circuit outputs the first interrupt signal at regular intervals; The microcontroller is characterized in that the controller switches from the second operation mode to the first operation mode based on the first interrupt signal.

3. In claims 1 and 2, the power gate supplies and stops the power supply potential to the third register; the third register has a volatile memory unit and a nonvolatile memory unit, and when the power supply is cut off by the power gate, data in the volatile memory unit is saved to the nonvolatile memory unit before the power supply is cut off, and when the power supply is resumed by the power gate, the data saved in the nonvolatile memory unit is written to the volatile memory unit.

4. 4. The microcontroller according to claim 1, wherein the nonvolatile memory unit includes a transistor using a multilayer film including an oxide semiconductor layer and a transistor using silicon.

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