Semiconductor device and power conversion device

Abstract

To provide a highly-reliable semiconductor device capable of suppressing corrosion of a metal layer connected to a guard ring.SOLUTION: A semiconductor device comprises: a guard ring 215 formed on a principal surface of a semiconductor substrate 209 so as to surround an active region 103 formed on the principal surface; an inter-layer insulation film 202 formed on the semiconductor substrate so as to cover the guard ring; a field plate 217 arranged on the inter-layer insulation film and electrically connected to the guard ring via a contact 203 penetrating the inter-layer insulation film; and a protection film 221 covering the field plate. The field plate is composed of a lamination structure of a first metal 219 in contact with the guard ring, and a second metal 220 arranged in contact with the first metal and having a lower standard potential than that of the first metal. A ratio of a contact area with the protection film of the first metal to a contact area with the protection film of the second metal is lower than or equal to 0.05.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to the structure of a semiconductor device, and more particularly to a technique that is effective when applied to a semiconductor device having a termination structure in which a semiconductor active region is surrounded by a guard ring. [Background technology]

[0002] Semiconductor devices are used in a wide range of fields, including system LSIs (Large Scale Integration), power conversion devices, and control devices for hybrid and electric vehicles. For example, IGBT modules (Insulated Gate Bipolar Transistors, hereafter abbreviated as IGBT), which are key components of power conversion devices such as inverters, are used in railways, electric power, and electric vehicles, and there is a demand for power modules that are not only low-cost and compact, but also highly reliable even in high-temperature, high-humidity environments. Similarly, there is a demand for new technologies for power device chips within power modules that not only achieve low-cost and compact size, but also high reliability in high-temperature, high-humidity environments.

[0003] Against this background, Patent Document 1, for example, proposes a technology for miniaturizing the termination structure surrounding the active area of ​​a power device chip. This technology has a layered structure of a barrier metal layer and a field electrode connected to a guard ring, and is characterized by a portion of the barrier metal layer extending beyond both sides of the field electrode in a direction crossing the termination area.

[0004] This makes it possible to achieve both high voltage resistance and miniaturization.

[0005] Furthermore, Figure 19 of Patent Document 2 proposes a technology for forming an anode electrode and a field plate electrode from a multilayer aluminum-based metal consisting of a lower aluminum-based metal film, an aluminum diffusion barrier metal film, an upper aluminum-based metal film, etc., in an SBD element having an active region of a Schottky barrier diode (hereinafter referred to as SBD) provided on the main surface of a semiconductor substrate and a PSG (Phosphorus Silicate Glass) film-coated region provided on the outer periphery from the edge of the SBD active region. The technology includes an organic final passivation film and a UBM (Under Bump Metal) layer provided complementary to the aluminum-based metal film that forms the anode electrode.

[0006] This makes it possible to suppress the occurrence of cracks.

[0007] Furthermore, Patent Document 3 proposes a structure in which an edge termination region surrounding the active region has an electric field relaxation mechanism including a guard ring, a first field plate in contact with the guard ring, and a second field plate provided on the first field plate with an interlayer insulating film sandwiched therebetween, the second field plate being thicker than the first field plate, the spacing between the second field plates being wider than the spacing between the first field plates, a barrier metal film being provided between the second field plate and the interlayer insulating film and in conductive contact with the second field plate, and the spacing between the barrier metal films being equal to the spacing between the first field plates.

[0008] This can improve the shielding effect against extraneous charges. [Prior art documents] [Patent documents]

[0009] [Patent Document 1] Japanese Patent Application Laid-Open No. 2010-251404 [Patent Document 2] Japanese Patent Application Laid-Open No. 2011-100811 [Patent Document 3] International Publication No. 2014 / 084124 Summary of the Invention [Problem to be solved by the invention]

[0010] However, the inventors of the present application have found that when part of the barrier metal layer protrudes from both sides of the field electrode in a direction crossing the termination region, as in Patent Documents 1 and 3, there is a problem of galvanic corrosion in which dissimilar metals form a local battery and corrode under high temperature and humidity.

[0011] Galvanic corrosion is localized corrosion caused by a standard potential difference between dissimilar metals, and is related by the following equation (1):

[0012]

number

[0013] where P is the amount of corrosion, P0 is the amount of corrosion when the metal is alone, A is the area of ​​the metal with a higher standard potential, and B is the area of ​​the metal with a lower standard potential. Note that the area in this formula is the surface area.

[0014] In Patent Documents 1 and 3, the standard potential of the barrier metal layer is high and the standard potential of the field electrode made of an aluminum alloy is low, which increases A / B (area of ​​the barrier metal layer / area of ​​the field electrode) in the above formula (1), accelerating galvanic corrosion and leaving reliability issues under high temperature and humidity.

[0015] Furthermore, in a three-layer structure of Al / barrier metal film / Al, as in Patent Document 2, where the barrier metal film does not protrude and the edges are aligned, the surface area of ​​the upper Al layer is the top and side surfaces, whereas the surface area of ​​the barrier metal film and the lower Al layer is only the side surfaces, so the lower Al layer has a smaller surface area than the upper Al layer. Therefore, the A / B ratio (area of ​​barrier metal film / area of ​​field electrode) in equation (1) above is larger for the lower Al layer than for the upper Al layer, which creates the problem of the lower Al layer being more susceptible to galvanic corrosion than the upper Al layer.

[0016] Therefore, an object of the present invention is to provide a semiconductor device having a termination structure in which a guard ring surrounds a semiconductor active region, While suppressing cracks caused by stress during the deposition of inorganic passivation films, The present invention provides a highly reliable semiconductor device capable of suppressing corrosion of a metal layer connected to a guard ring, and a power converter using the same. [Means for solving the problem]

[0017] In order to achieve the above object, the present invention provides a semiconductor device comprising: an active region formed on a main surface of a semiconductor substrate; and a guard ring region formed on the main surface to surround the active region, wherein the guard ring region has a guard ring formed on the semiconductor substrate; an interlayer insulating film formed on the semiconductor substrate to cover the guard ring; a field plate disposed on the interlayer insulating film and electrically connected to the guard ring via a contact penetrating the interlayer insulating film; and a protective film covering the field plate, wherein the field plate has a laminated structure of a first metal in contact with the guard ring and a second metal disposed on the first metal in contact with the guard ring and having a lower standard potential than the first metal, wherein a ratio of a contact area of ​​the first metal with the protective film to a contact area of ​​the second metal with the protective film is 0.05 or less, and 90% or more of an area of ​​an upper surface of the first metal is covered with the second metal which is an alloy mainly composed of Al, thereby suppressing corrosion of the first metal due to a standard potential difference between the first metal and the second metal, When the field plate is viewed in cross section, an end of the first metal protrudes from an end of the second metal, and the protective film is formed in the following order from the bottom: Inorganic passivation film andOrganic passivation film stacked laminated film is It is characterized by:

[0018] The present invention also provides a power conversion device comprising a pair of DC terminals, AC terminals in the same number as the number of AC phases, and two parallel circuits connected in series between the pair of DC terminals, each parallel circuit having a switching element and a diode of opposite polarity connected in parallel, and power conversion units in the same number as the number of AC phases, the interconnection points of the parallel circuits being connected to different AC terminals, characterized in that the switching elements are the above-mentioned semiconductor devices. [Effects of the Invention]

[0019] According to the present invention, in a semiconductor device having a termination structure in which a guard ring surrounds a semiconductor active region, While suppressing cracks caused by stress during the deposition of inorganic passivation films, It is possible to provide a highly reliable semiconductor device capable of suppressing corrosion of the metal layer connected to the guard ring.

[0020] This can contribute to improving the reliability and extending the life of the semiconductor device and the power conversion device using the same.

[0021] Problems, configurations, and effects other than those described above will become apparent from the following description of the embodiments. [Brief explanation of the drawings]

[0022] [Figure 1] 1 is a top view of a semiconductor device (IGBT semiconductor chip) according to a first embodiment of the present invention. [Figure 2] 1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention. [Figure 3] 3 is a schematic diagram showing a first metal and a second metal in a cross section of a main part of a guard ring portion. FIG. [Figure 4] FIG. 10 is a diagram illustrating the effect of the present invention. [Figure 5] 3 is a schematic diagram showing a first metal and a second metal in a cross section of a main part of a guard ring portion. FIG. [Figure 6]FIG. 10 is a diagram illustrating the effect of the present invention. [Figure 7] 1A to 1C are cross-sectional views showing a manufacturing process of a semiconductor device according to a first embodiment of the present invention. [Figure 8] FIG. 10 is a cross-sectional view of a semiconductor device according to a second embodiment of the present invention. [Figure 9] FIG. 10 is a cross-sectional view of a semiconductor device according to a third embodiment of the present invention. [Figure 10] FIG. 10 is a circuit block diagram of a power conversion device according to a fourth embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0023] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In each drawing, the same reference numerals indicate the same components or components with similar functions. Furthermore, p-, p, and p+ indicate that the conductivity type of the semiconductor layer is p-type, and the relative impurity concentration increases in this order. Similarly, n-, n, and n+ indicate that the conductivity type of the semiconductor layer is n-type, and the relative impurity concentration increases in this order. [Example]

[0024] A semiconductor device and a manufacturing method thereof according to a first embodiment of the present invention will be described with reference to FIGS.

[0025] 1 is a top view of an IGBT semiconductor chip 101, which is a semiconductor device of this embodiment. An IGBT active region 103 is provided in the center of the chip. A gate electrode PAD 104 for applying a gate voltage to the IGBT is also provided. A chip terminal guard ring region 102 is provided on the periphery of the IGBT semiconductor chip 101.

[0026] 2 is a cross-sectional view of the active region 103 and chip terminal guard ring region 102 of the IGBT semiconductor chip 101. Trench gates 207 are periodically arranged within the active region 103, and contacts 203 are provided between adjacent trench gates 207. The contacts 203 penetrate the insulating layer (interlayer insulating film 202) and are connected to the emitter electrode 201, which is a first metal layer.

[0027] The trench gate 207 is made of a gate insulating film 208 and polysilicon (Poly-Si) embedded in the trench, and a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) is configured with a p-base layer 206 and an n+ source layer 204 formed on the surface of an n-semiconductor substrate 209, and has the function of turning on and off the IGBT semiconductor chip 101. In addition, a p+ layer 205 is provided in the p-base layer 206 to reduce contact resistance with the contact 203.

[0028] The trench gate 207 is connected to a polysilicon gate wiring 214 on the field oxide film 222 by polysilicon (Poly-Si) buried in the trench, and is connected to a gate electrode 213 by a contact 203 via an insulating layer (interlayer insulating film 202).

[0029] In the chip end guard ring region 102, multiple second conductivity type (p type) guard rings 215 are arranged on the surface of the n-semiconductor substrate 209, and at the chip end, a first conductivity type (n type) channel stopper 216 is arranged on the surface of the n-semiconductor substrate 209.

[0030] Each of the multiple second conductivity type (p-type) guard rings 215 is connected to a corresponding second metal layer 217 by a corresponding contact 203 via a field oxide film 222 and an insulating layer (interlayer insulating film 202). The first conductivity type (n-type) channel stopper 216 is connected to a third metal layer 218 by a contact 203 via an insulating layer (interlayer insulating film 202).

[0031] The second metal layer 217 covers the surface of the corresponding guard ring 215 of the second conductivity type (p-type) and is composed of a laminated structure of at least two or more types of dissimilar metals, and this laminated structure of dissimilar metals is formed such that a first metal 219 is formed in contact with the corresponding guard ring 215 of the second conductivity type (p-type), and a second metal 220 having a standard potential lower than that of the first metal 219 is formed in contact with the first metal 219.

[0032] In addition, the second metal layer 217 connected to the second conductivity type (p-type) guard ring 215 and the third metal layer 218 connected to the first conductivity type (n-type) channel stopper 216 are covered with an organic passivation film (protective film) 221.

[0033] Here, the laminated structure of the first metal 219 and the second metal 220 is formed so that the ratio of the contact area of ​​the first metal 219 with the organic passivation film (protective film) 221 to the contact area of ​​the second metal 220 with the organic passivation film (protective film) 221 is 0.05 or less.

[0034] On the back surface of n-semiconductor substrate 209, i.e., the main surface (back surface) opposite to the main surface (front surface) of n-semiconductor substrate 209 on which trench gate 207 is formed, n-type buffer layer 210, p-type collector layer 211, and collector electrode 212 are formed in this order.

[0035] The relationship between the first metal 219 and the second metal 220 will be described in detail with reference to Figures 3 to 6. For ease of understanding, Figures 3 and 5 show the state before the second metal layer 217 is covered with the organic passivation film (protective film) 221, i.e., the state in which the top and side surfaces of the second metal 220 and the top and side surfaces of the first metal 219 that are not covered with the second metal 220 are exposed.

[0036] 3 is a schematic diagram showing the relationship between the exposed surface area A of the first metal 219 and the exposed surface area B of the second metal 220 in a cross section of a main part of the guard ring portion. The left diagram (a) of FIG. 3 shows a case where the ratio of the exposed surface area A of the first metal 219 to the exposed surface area B of the second metal 220 is large, and the right diagram (b) of FIG. 3 shows a case where the ratio of the exposed surface area A of the first metal 219 to the exposed surface area B of the second metal 220 is small.

[0037] 4 is a characteristic diagram showing the relationship between the amount of corrosion of the first metal 219 and the ratio of the exposed surface area A of the first metal 219 to the exposed surface area B of the second metal 220. According to the study by the present inventors, since the above-mentioned galvanic reaction has the relationship of formula (1), it was found that corrosion of the first metal 219 can be suppressed when the ratio of the exposed surface area A of the first metal 219 to the exposed surface area B of the second metal 220 is 0.05 or less, as shown in FIG.

[0038] Fig. 5 is a schematic diagram showing the proportion of the area Ts1 of the upper surface of the first metal 219 covered by the area Bs1 of the second metal 220 in a cross section of a main part of the guard ring part. The left diagram (a) of Fig. 5 shows a case where the proportion of the upper surface of the first metal 219 (area: Ts1) covered by the second metal 220 (area: Bs1) is small, and the right diagram (b) of Fig. 5 shows a case where the proportion of the upper surface of the first metal 219 (area: Ts1) covered by the second metal 220 (area: Bs1) is large.

[0039] FIG. 6 is a characteristic diagram showing the relationship between the amount of corrosion of the first metal 219 and the proportion of the upper surface (area: Ts1) of the first metal 219 covered by the second metal 220 (area: Bs1). Under high temperature and humidity conditions, bromine ions (Br - ) and chloride ions (Cl - ), fluorine ion (F - ) dissolve in moisture, and these halogen components migrate to the positive potential side of the chip end guard ring region 102, which can cause leakage paths and corrosion. In addition, dissimilar metals can become local batteries, which can accelerate corrosion.

[0040] According to the study by the inventors of the present application, it was found that corrosion of the first metal 219 can be suppressed when the proportion of the top surface (area: Ts1) of the first metal 219 that is covered with the second metal 220 (area: Bs1) is 90% or more, as shown in Fig. 6. Note that in Fig. 5, Bs1 is defined as the portion excluding the contact 203, but in Fig. 5, the contact 203 is formed continuously in the depth direction of the page, and even if there is a broken portion of the contact 203, it is only about 1% of the whole, so it is within the margin of error in the calculation results shown in Fig. 6.

[0041] FIG. 7 is a diagram showing a manufacturing process of the IGBT semiconductor chip 101 of this embodiment (FIG. 2).

[0042] <(a) P-well formation> First, an n-semiconductor substrate 209 (for example, a semiconductor wafer such as a Si wafer) is prepared.

[0043] Next, an insulating film (for example, an SiO 2 film) is formed on the main surface (front surface) of n-semiconductor substrate 209, and after applying photoresist onto the insulating film, the photoresist is patterned by photolithography to form P well 301.

[0044] Next, using patterned photoresist as a mask, p-type impurities (e.g., boron) are implanted into n-semiconductor substrate 209 by ion implantation, and after removing the photoresist, the p-type impurities are diffused by annealing to form P-well 301. P-well 301 constitutes guard ring 215 of the second conductivity type (p-type) in chip end guard ring region 102, and constitutes a p-type layer for potential stabilization below polysilicon gate wiring 214 in active region 103.

[0045] (b) Trench gate formation Next, an insulating film (e.g., an SiO2 film) is formed on the main surface (surface) of n-semiconductor substrate 209, and after applying a photoresist to the insulating film, the photoresist is patterned by photolithography to form field oxide film 222. After removing the photoresist, the main surface (surface) of n-semiconductor substrate 209 is subjected to a thermal oxidation treatment using the patterned insulating film as a mask, and field oxide film 222 is selectively formed on the main surface (surface) of n-semiconductor substrate 209.

[0046] After removing the patterned insulating film, an insulating film (e.g., SiO2 film) is formed on the main surface (front surface) of n-semiconductor substrate 209, and after applying photoresist to the insulating film, the photoresist and insulating film are patterned by photolithography to form trenches. After removing the photoresist, trenches are formed by anisotropic etching using the patterned insulating film as a mask.

[0047] Next, after forming a gate insulating film 208 in the trench, a polysilicon film is deposited so as to fill the trench, and a trench gate 207 and a polysilicon gate wiring 214 are processed and formed by photolithography.

[0048] <(c) p base layer, n + Source layer and channel stopper formation≫ Next, using a photoresist patterned for forming the p-base layer 206 as a mask, p-type impurity ions are implanted, and then heat treatment is performed, thereby forming the p-base layer 206.

[0049] Next, n + Using a photoresist patterned for forming the source layer 204 and the first conductivity type (n-type) channel stopper 216 as a mask, n-type impurity ions are implanted to form the n+ source layer 204 and the first conductivity type (n-type) channel stopper 216.

[0050] (d) Contact formation Next, an interlayer insulating film 202 is deposited on the main surface (front surface) of the n-semiconductor substrate 209, and a planarization process is performed on the interlayer insulating film 202. For the planarization, a planarization method such as reflow of a BPSG (Boron-Phosphors Silicate Glass) film or CMP (Chemical Mechanical Polishing) is used.

[0051] After planarizing the interlayer insulating film 202, contact holes are formed by photolithography and anisotropic etching. At this time, the contact holes penetrate the interlayer insulating film 202 and reach the p-base layer 206, the P-well 301, the polysilicon gate wiring 214, and the first conductivity type (n-type) channel stopper 216. As a result, when the p-base layer 206 is viewed in cross section, a pair of n+ source layers 204 are formed, and a groove portion with which a contact metal layer formed in a later process will come into contact is also formed.

[0052] Subsequently, using the interlayer insulating film 202 with the contact holes formed therein as a mask, ap+ layer 205 is formed at the bottom of the contact holes by ion implantation of p-type impurities.

[0053] Next, a metal that serves as a barrier layer for the Al electrode and that can undergo a silicide reaction with Si, such as Mo, TiW, TiN, Ti, Co, or Ni, to reduce the resistance of the Si contact surface, is deposited by, for example, sputtering, and then annealed to form a silicide layer.

[0054] Next, the contact holes are filled with a metal film made of a metal with high hardness and high melting point, such as W, and then planarized by etching or CMP to form a contact metal layer (contact 203). At this time, the portions other than the contact holes are not removed even after planarization of the W, and remain on the interlayer insulating film 202.

[0055] Here, in order to suppress galvanic reactions, it is desirable for the metal that forms the barrier layer of the Al electrode to have a small potential difference from the standard potential of Al (-1.66 V). For example, the standard potential of Ti is -1.63 V, Co is -0.277 V, Ni is -0.23 V, and Mo is -0.2 V.

[0056] <(e) Surface electrode, organic passivation formation> Thereafter, a metal layer mainly composed of aluminum (Al) is deposited, and photolithography and etching are used to form the first metal layer, emitter electrode 201, second metal layer 217, and gate electrode 213. The aluminum is etched by anisotropic dry etching, and a barrier layer is also processed and formed at the same time.

[0057] As a result, the proportion of the area Ts1 of the top surface of the first metal 219 (e.g., Ti) that is the barrier layer that is covered by the area Bs1 of the second metal 220 (Al) increases, thereby suppressing galvanic reactions and corrosion of the barrier layer (first metal 219).

[0058] In addition, the ratio of the exposed surface area A of the first metal 219 (barrier layer: e.g., Ti) to the exposed surface area B of the second metal 220 (Al) becomes smaller, which similarly suppresses galvanic reactions and corrosion of the barrier layer (first metal 219).

[0059] In addition, the second metal layer 217 is structured to cover the surface of the second conductivity type (p-type) guard ring 215, which can enhance the shielding effect against external charges such as moisture, ionic substances, and mobile ions. This stabilizes the potential of the n-semiconductor substrate 209 during application of a high voltage, making electric field fluctuations less likely to occur and stabilizing the blocking voltage.

[0060] Thereafter, an organic passivation film 221 made of polyimide or the like is formed and patterned so that the emitter electrode 201 is exposed.

[0061] The above steps (a) to (e) are the surface treatment of the n-semiconductor substrate 209.

[0062] <(f) Formation of rear n-type buffer, p-type collector layer, and collector electrode> Next, n-semiconductor substrate 209 is ground from the back surface side by back grinding to a desired thickness. Thereafter, n-type and p-type impurity ions are implanted into n-semiconductor substrate 209 from the back surface side of n-semiconductor substrate 209, and further laser annealing is performed to form n-type buffer layer 210 and p-type collector layer 211.

[0063] By appropriately adjusting the acceleration energy during ion implantation, n-type buffer layer 210 and p-type collector layer 211 can be formed at different depths from the rear surface of n-semiconductor substrate 209.

[0064] Thereafter, a laminated metal layer of, for example, Al—Ti—Ni—Au or the like is formed on the back surface of n-semiconductor substrate 209 by sputtering, thereby forming collector electrode 212 .

[0065] In the semiconductor device of this embodiment, second metal layer 217 covers the surface of second conductivity type (p-type) guard ring 215, enhancing the shielding effect against external charges such as moisture, ionic substances, mobile ions, etc. Therefore, the potential of n-semiconductor substrate 209 is stabilized during application of a high voltage, making it difficult for the electric field to fluctuate and enabling stabilization of the blocking voltage.

[0066] Furthermore, the second metal layer 217 is composed of a laminated structure of dissimilar metals, in which a first metal 219 is formed in contact with a guard ring 215 of a second conductivity type (p-type), a second metal 220 having a lower standard potential than the first metal 219 is formed in contact with the first metal 219, 90% or more of the area of ​​the top of the first metal 219 is covered with the second metal 220, and the proportion of the area Ts1 of the top surface of the first metal 219 (barrier layer: for example, Ti) that is covered by the area Bs1 of the second metal 220 (Al) increases, thereby suppressing galvanic reactions and corrosion of the barrier layer (first metal 219).

[0067] In addition, the ratio of the exposed surface area A of the first metal 219 (barrier layer: e.g., Ti) to the exposed surface area B of the second metal 220 (Al) becomes smaller, which similarly suppresses galvanic reactions and corrosion of the barrier layer (first metal 219).

[0068] Furthermore, the chip end guard ring region 102 is covered with an organic passivation film 221 to mechanically protect the surface and also to protect against external charges such as moisture, ionic substances, and mobile ions.

[0069] As described above, the semiconductor device of this embodiment includes active region 103 formed on the main surface of n-semiconductor substrate 209, and chip end guard ring region 102 formed on the main surface of n-semiconductor substrate 209 so as to surround active region 103. Chip end guard ring region 102 includes guard ring 215 of second conductivity type (p type) formed on n-semiconductor substrate 209, interlayer insulating film 202 formed on n-semiconductor substrate 209 so as to cover guard ring 215 of second conductivity type (p type), and contact 203 disposed on interlayer insulating film 202 and penetrating interlayer insulating film 202, and is electrically connected to guard ring 215 of second conductivity type (p type). The field plate (second metal layer 217) has a layered structure including a first metal 219 in contact with a guard ring 215 of a second conductivity type (p-type), and a second metal 220 that is disposed on and in contact with the first metal 219 and has a lower standard potential than the first metal 219, and is configured such that the ratio of the contact area of ​​the first metal 219 with the organic passivation film (protective film) 221 to the contact area of ​​the second metal 220 with the organic passivation film (protective film) 221 is 0.05 or less.

[0070] Moreover, 90% or more of the area of ​​the top surface of the first metal 219 is covered with the second metal 220.

[0071] Chip end guard ring region 102 also has a channel stopper 216 of the first conductivity type (n type) formed in n- semiconductor substrate 209 so as to surround guard ring 215 of the second conductivity type (p type).

[0072] This makes it possible to suppress corrosion of the metal layer connected to the guard ring under high temperature and humidity conditions, thereby realizing a highly reliable semiconductor device that suppresses deterioration in breakdown voltage and increases in leakage current during long-term operation under high temperature and humidity conditions, and a power conversion device using the same.

[0073] It is more desirable that substantially the entire top surface (approximately 100%) of first metal 219 is covered with second metal 220, and that when the field plate (second metal layer 217) is viewed in cross section, the edge of first metal 219 is aligned with the edge of second metal 220. This makes it possible to reliably suppress galvanic corrosion of the field plate (second metal layer 217).

[0074] Furthermore, when the IGBT semiconductor chip 101 is viewed in cross section, it is preferable that both ends of the field plate (second metal layer 217) protrude beyond both ends of the second conductivity type (p-type) guard ring 215. This is because the electric field relaxation effect of the field plate (second metal layer 217) at the chip termination can be enhanced.

[0075] Furthermore, in this embodiment (FIG. 2), an example has been shown in which a plurality of second conductivity type (p type) guard rings 215 are formed on n-semiconductor substrate 209, and each of the plurality of second conductivity type (p type) guard rings 215 is individually connected to a plurality of field plates (second metal layers 217) via a plurality of contacts 203, but the number of combinations of second conductivity type (p type) guard rings 215 and field plates (second metal layers 217) is not limited to this.

[0076] For example, one second conductivity type (p type) guard ring 215 and one field plate (second metal layer 217) may be formed in the chip terminal guard ring region 102, or multiple second conductivity type (p type) guard rings 215 may be formed on the n-semiconductor substrate 209, and connected via multiple contacts 203 to a single field plate (second metal layer 217) with a large area that covers the entire multiple second conductivity type (p type) guard rings 215.

[0077] In either case, by configuring the area of ​​the first metal 219 and the area of ​​the second metal 220 that make up the field plate (second metal layer 217) as described above, galvanic corrosion of the field plate (second metal layer 217) can be suppressed. [Example]

[0078] Second Embodiment A semiconductor device according to a second embodiment of the present invention will be described with reference to Fig. 8. Fig. 8 is a cross-sectional view of an IGBT semiconductor chip 101 according to this embodiment, which corresponds to a modification of the first embodiment (Fig. 2).

[0079] Whereas the chip end guard ring region 102 in Example 1 (FIG. 2) is covered with an organic passivation film 221, which is a protective film, the chip end guard ring region 102 in this Example (FIG. 8) is covered with an inorganic passivation film 801, which is different from Example 1. The rest of the configuration is the same as Example 1 (FIG. 2). Because the organic passivation film 221 is hygroscopic and has little effect in suppressing the diffusion of moisture and ionic substances, by using an inorganic passivation film 801 made of SiN, SiON, SiO2, or the like as the protective film for the chip end guard ring region 102, it is possible to suppress the penetration of moisture and the diffusion of ionic substances.

[0080] In the semiconductor device of this embodiment, compared to the first embodiment, the intrusion of moisture, ionic substances, and the like can be further prevented, thereby suppressing corrosion of the metal layer connected to the guard ring under high temperature and humidity conditions, and suppressing deterioration in breakdown voltage and increase in leakage current during long-term operation under high temperature and humidity conditions, thereby realizing a more reliable semiconductor device and a power conversion device using the same. [Example]

[0081] A semiconductor device according to a third embodiment of the present invention will be described with reference to Fig. 9. Fig. 9 is a cross-sectional view of an IGBT semiconductor chip 101 according to the third embodiment, which corresponds to a modification of the first embodiment (Fig. 2) and the second embodiment (Fig. 8).

[0082] The chip end guard ring region 102 of this embodiment differs from those of the first and second embodiments in that it is covered with a laminated film of an inorganic passivation film 801 and an organic passivation film 221. The other configurations are the same as those of the first and second embodiments.

[0083] The inorganic passivation film 801 is formed on the second metal layer 217. The passivation film serves to mechanically protect the surface as well as to protect against external charges such as moisture, ionic substances, and mobile ions. For mechanical surface protection, it is effective to make the passivation film thicker.

[0084] However, the surface of the second metal layer 217 is uneven, and if SiN is used as the inorganic passivation film 801 and made thick, cracks may occur due to stress during film formation. The cracks become a path for moisture and ionic substances to penetrate, which can cause a decrease in the withstand voltage against external charges and an increase in leakage current, leading to corrosion of the barrier layer (first metal 219).

[0085] Therefore, in this embodiment, the second metal layer 217 is covered with a laminated film of an inorganic passivation film 801 and an organic passivation film 221, and by thinning the inorganic passivation film 801, the occurrence of cracks is prevented, mechanical surface protection is achieved, and the intrusion of moisture, ionic substances, etc. is prevented. Furthermore, corrosion of the metal layer connected to the guard ring under high temperature and humidity is suppressed, and a highly reliable semiconductor device and a power conversion device using the same can be realized, which suppresses deterioration in breakdown voltage and increase in leakage current during long-term operation under high temperature and humidity. [Example]

[0086] An example of an embodiment in which the semiconductor device of the present invention is applied to a power conversion device will be described with reference to Fig. 10. Fig. 10 is a circuit block diagram showing a power conversion device 600 that employs the semiconductor devices according to Examples 1 to 3 of the present invention as components. Fig. 10 shows the circuit configuration of the power conversion device 600 of this example and the connection relationship between a DC power supply and a three-phase AC motor (AC load).

[0087] In a power conversion device 600 of this embodiment, the semiconductor devices of Examples 1 to 3 are used as power switching elements 601 to 606. The power switching elements 601 to 606 are, for example, IGBTs.

[0088] As shown in FIG. 10, the power conversion device 600 of this embodiment includes a pair of DC terminals, namely, a P terminal 631 and an N terminal 632, and AC terminals, namely, a U terminal 633, a V terminal 634, and a W terminal 635, the number of which is the same as the number of phases of the AC output.

[0089] The inverter also includes a switching leg consisting of a pair of power switching elements 601 and 602 connected in series, with a U-terminal 633 connected to their series connection point as its output. Another switching leg with a similar configuration consists of power switching elements 603 and 604 connected in series, with a V-terminal 634 connected to their series connection point as its output. Another switching leg with a similar configuration consists of power switching elements 605 and 606 connected in series, with a W-terminal 635 connected to their series connection point as its output.

[0090] Three-phase switching legs consisting of power switching elements 601 to 606 are connected between DC terminals P-terminal 631 and N-terminal 632, and DC power is supplied from a DC power supply (not shown). Three-phase AC terminals of power conversion device 600, namely U-terminal 633, V-terminal 634, and W-terminal 635, are connected to a three-phase AC motor (not shown) as a three-phase AC power supply.

[0091] Diodes 621 to 626 are connected in anti-parallel to the power switching elements 601 to 606, respectively. Gate input terminals of the power switching elements 601 to 606, which are IGBTs, are connected to gate drive circuits 611 to 616, and the power switching elements 601 to 606 are driven and controlled by the gate drive circuits 611 to 616, respectively.

[0092] That is, the power conversion device 600 of this embodiment is a power conversion device that receives DC power from the outside, converts the input DC power into AC power, and outputs the AC power. The power conversion device 600 includes a pair of DC terminals 631, 632 for receiving the DC power, and AC terminals 633 to 635 for outputting the AC power, the number of which is the same as the number of phases of the AC power. For each of the AC terminals 633 to 635, the number of which is equal to the number of phases, a switching element (for example, a power switching element 601) is connected between one terminal (P terminal 631) and the other terminal (N terminal 632) of the pair of DC terminals 631, 632. A series circuit (for example, a parallel circuit of the power switching element 601 and the diode 621, and a parallel circuit of the power switching element 602 and the diode 622) is configured in which two parallel circuits (for example, a parallel circuit of the power switching element 601 and the diode 621) each formed by connecting in parallel a diode (for example, the diode 621) of opposite polarity to the switching element are connected to each other, and the interconnection point of the two parallel circuits that make up the series circuit is connected to an AC terminal (for example, the U terminal 633) of the phase (for example, the U phase) corresponding to the series circuit.

[0093] As in this embodiment, by applying the IGBT semiconductor chip 101 described in the above embodiments 1 to 3 to the power switching element of the power converter, the reliability and life of the power converter can be improved.

[0094] The present invention is not limited to the above-described embodiments and includes various modifications. For example, the above-described embodiments have been described in detail to clearly explain the present invention, and are not necessarily limited to those including all of the described configurations. It is possible to replace part of the configuration of one embodiment with the configuration of another embodiment, and it is also possible to add the configuration of another embodiment to the configuration of one embodiment. Furthermore, it is also possible to add, delete, or replace part of the configuration of each embodiment with other configurations. [Explanation of symbols]

[0095] 101...IGBT semiconductor chip 102...Chip end guard ring area 103...Active area 104...gate electrode pad 201...Emitter electrode (first metal layer) 202...Interlayer insulating film 203...Contact 204...n+ source layer 205…p+ layer 206...p base layer 207...Trench Gate 208...Gate insulating film 209...n-semiconductor substrate 210...n-type buffer layer 211...p-type collector layer 212...Collector electrode 213...gate electrode 214...Polysilicon gate wiring 215...Second conductivity type (p-type) guard ring 216...First conductivity type (n-type) channel stopper 217...Second metal layer 218...Third metal layer 219...First Metal 220...Second metal 221...Organic passivation film (protective film) 222...Field oxide film 301...P well 600...Power conversion device 601 to 606...Power switching elements 621~626...Diodes 611~616...Gate drive circuit 631,632…DC terminal 633~635…AC terminal 801...Inorganic passivation film

Claims

1. an active region formed on a main surface of a semiconductor substrate; a guard ring region formed on the main surface so as to surround the active region, The guard ring region includes a guard ring formed on the semiconductor substrate. an interlayer insulating film formed on the semiconductor substrate so as to cover the guard ring; a field plate disposed on the interlayer insulating film and electrically connected to the guard ring via a contact penetrating the interlayer insulating film; a protective film covering the field plate, The field plate includes a first metal in contact with the guard ring; a laminated structure of a second metal that is disposed on and in contact with the first metal and has a standard potential lower than that of the first metal; a ratio of a contact area of ​​the first metal with the protective film to a contact area of ​​the second metal with the protective film being 0.05 or less, and 90% or more of an area of ​​an upper surface of the first metal is covered with the second metal, which is an alloy mainly composed of Al, thereby suppressing corrosion of the first metal due to a standard potential difference between the first metal and the second metal; When the field plate is viewed in cross section, an end of the first metal protrudes from an end of the second metal, The semiconductor device is characterized in that the protective film is a laminated film in which an inorganic passivation film and an organic passivation film are laminated in this order from the bottom.

2. 2. The semiconductor device according to claim 1, When the semiconductor device is viewed in cross section, both ends of the field plate protrude beyond both ends of the guard ring.

3. 2. The semiconductor device according to claim 1, a plurality of the guard rings are formed on the semiconductor substrate; a contact and a field plate formed for each of the plurality of guard rings;

4. 2. The semiconductor device according to claim 1, The semiconductor device is characterized in that the guard ring region has a channel stopper formed in the semiconductor substrate so as to surround the guard ring.

5. 2. The semiconductor device according to claim 1, 1. A semiconductor device, wherein the first metal is any one of Mo, TiW, TiN, Ti, Co, and Ni.

6. 2. The semiconductor device according to claim 1, A semiconductor device characterized in that it is an IGBT in which a plurality of trench gates are periodically arranged within the active region.

7. A pair of DC terminals; The same number of AC terminals as the number of AC phases, a power conversion device including: two parallel circuits connected in series, each parallel circuit having a switching element and a diode of opposite polarity connected in parallel, connected between the pair of DC terminals; and power conversion units, the number of which is equal to the number of AC phases, each of which has interconnection points of the parallel circuits connected to different AC terminals; A power conversion device, wherein the switching element is a semiconductor device according to any one of claims 1 to 6.

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