Chip parts

Abstract

To provide a chip part capable of ensuring a larger capacitance for a capacitor portion, maintaining stability of wall portions, and enhancing stability of components.SOLUTION: A chip part 1 includes: a substrate 2 having a first main surface 5 and a second main surface 6 opposite thereto; a capacitive film 22 formed on the first main surface 5; a first external electrode 3 formed on the capacitive film 22; a second external electrode 4 formed on the second main surface 6; and a conductive layer 21 formed between the capacitive film 22 and the substrate 2. Consequently, a vertical capacitor 25 having a laminated structure of an upper electrode 23 (the first external electrode 3) / the capacitive film 22 / a lower electrode 24 (the substrate 2) is formed in a lengthwise direction along a thickness direction of the substrate 2.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present disclosure relates to chip components. [Background technology]

[0002] Patent Document 1 discloses a chip capacitor including a substrate, a first conductive film and a first pad film formed on the substrate, a dielectric film formed on the first conductive film and the first pad film, and a second conductive film formed on the dielectric film and including a second connection region and a second capacitor formation region. The first conductive film includes the first connection region and the first capacitor formation region. A first external electrode is bonded to the first connection region of the first conductive film, and a second external electrode is bonded to the second connection region of the second conductive film. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2017-195322 Summary of the Invention [Problem to be solved by the invention]

[0004] An embodiment of the present disclosure provides a chip component that can effectively utilize the lateral space of a semiconductor substrate and ensure a large capacitance of the capacitor.

[0005] Moreover, one embodiment of the present disclosure provides a chip component that can ensure a large capacitance of the capacitor, maintain the stability of the wall portion, and improve the reliability of the element. [Means for solving the problem]

[0006] A chip component according to one embodiment of the present disclosure includes a semiconductor substrate having a first main surface and a second main surface opposite to the first main surface, a capacitive film formed on the first main surface, a first electrode formed on the capacitive film, a second electrode formed on the second main surface, and a conductive layer formed between the capacitive film and the semiconductor substrate. [Effects of the Invention]

[0007] In a chip component according to an embodiment of the present disclosure, a first electrode and a semiconductor substrate (second electrode) face each other with a capacitive film sandwiched between them. This forms a vertical capacitor having a stacked structure of an upper electrode, a capacitive film, and a lower electrode in the vertical direction along the thickness direction of the semiconductor substrate. Because it is a vertical capacitor, the first electrode can be disposed on the first main surface side and the second electrode can be disposed on the second main surface side, eliminating the need to arrange these external electrodes side by side in the horizontal direction along the first main surface of the semiconductor substrate. This allows for effective use of the horizontal space of the semiconductor substrate, thereby providing a compact chip component.

[0008] Furthermore, a conductive layer is formed between the capacitive film and the semiconductor substrate. This allows the resistance value of the first main surface of the semiconductor substrate to be replaced by the resistance value of the conductive layer, thereby reducing the resistance value on the second electrode side. As a result, the loss of the capacitor can be reduced. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a schematic perspective view of a chip part according to an embodiment of the present disclosure. [Figure 2] FIG. 2 is a schematic plan view of the chip part. [Figure 3] FIG. 3 is a schematic bottom view of the chip part. [Figure 4] FIG. 4 is a schematic cross-sectional view of the chip part. [Figure 5A] FIG. 5A is a schematic cross-sectional view showing a part of the manufacturing process of the chip component. [Figure 5B] FIG. 5B is a diagram showing the next step of FIG. 5A. [Figure 5C] FIG. 5C shows the next step in FIG. 5B. [Figure 5D] FIG. 5D shows the next step in FIG. 5C. [Figure 5E] FIG. 5E shows the next step of FIG. 5D. [Figure 5F] FIG. 5F shows the next step of FIG. 5E. [Figure 6] FIG. 6 is a schematic plan view of the chip part. [Figure 7] FIG. 7 is a schematic bottom view of the chip part. [Figure 8] FIG. 8 is a schematic cross-sectional view of the chip part. [Figure 9A] FIG. 9A is a schematic cross-sectional view showing a part of the manufacturing process of the chip component. [Figure 9B] FIG. 9B is a diagram showing the next step of FIG. 9A. [Figure 9C] FIG. 9C shows the next step in FIG. 9B. [Figure 9D] FIG. 9D shows the next step in FIG. 9C. [Figure 10] FIG. 10 is a schematic plan view of the chip part. [Figure 11] FIG. 11 is a schematic bottom view of the chip part. [Figure 12] FIG. 12 is a schematic cross-sectional view of the chip part. [Figure 13] FIG. 13 is a schematic plan view of the chip part. [Figure 14] FIG. 14 is a schematic bottom view of the chip part. [Figure 15] FIG. 15 is a schematic cross-sectional view of the chip part. [Figure 16] FIG. 16 is a schematic plan view of the chip part. [Figure 17] FIG. 17 is a schematic bottom view of the chip part. [Figure 18] FIG. 18 is a schematic cross-sectional view of the chip part. [Figure 19A] FIG. 19A is a schematic cross-sectional view showing a part of the manufacturing process of the chip component. [Figure 19B] FIG. 19B shows the next step in FIG. 19A. [Figure 19C] FIG. 19C shows the next step in FIG. 19B. [Figure 19D] FIG. 19D shows the next step in FIG. 19C. [Figure 19E] FIG. 19E shows the next step in FIG. 19D. [Figure 19F] FIG. 19F shows the next step in FIG. 19E. [Figure 19G] FIG. 19G shows the next step in FIG. 19F. [Figure 19H] FIG. 19H shows the next step in FIG. 19G. [Figure 19I] FIG. 19I shows the next step in FIG. 19H. [Figure 20] FIG. 20 is a schematic plan view of the chip part. [Figure 21] FIG. 21 is a schematic bottom view of the chip part. [Figure 22] FIG. 22 is a schematic cross-sectional view of the chip part. [Figure 23] FIG. 23 is a schematic cross-sectional view of the chip part. [Figure 24] FIG. 24 is a schematic cross-sectional view of the chip part. DETAILED DESCRIPTION OF THE INVENTION

[0010] Next, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. [ Appearance of chip part 1 ] FIG. 1 is a schematic perspective view of a chip component 1 according to an embodiment of the present disclosure. FIG. 2 is a schematic plan view of the chip component 1. FIG. 3 is a schematic bottom view of the chip component 1. In FIGS. 1 to 3, the longitudinal direction of the rectangular parallelepiped chip component 1 is defined as a first direction X, the width direction of the chip component 1 is defined as a second direction Y, and the thickness direction of the chip component 1 is defined as a third direction Z. In addition, in FIGS. 2 and 3, the first external electrode 3 and the second external electrode 4 are hatched for clarity.

[0011] The chip component 1 is formed in a rectangular parallelepiped shape, and has a length L along the first direction X, a width W along the second direction Y, and a thickness T along the third direction Z. The length L may be, for example, 0.4 mm or more and 2 mm or less. The width W may be, for example, 0.2 mm or more and 2 mm or less. The thickness T may be, for example, 0.1 mm or more and 0.5 mm or less.

[0012] The chip component 1 may be a small electronic component designated by its size (length L (mm) × width W (mm)), such as a 1608 (1.6 mm × 0.8 mm) chip, a 1005 (1.0 mm × 0.5 mm) chip, a 0603 (0.6 mm × 0.3 mm) chip, a 0402 (0.4 mm × 0.2 mm) chip, or a 03015 (0.3 mm × 0.15 mm) chip.

[0013] The chip component 1 includes a substrate 2 , a first external electrode 3 , and a second external electrode 4 .

[0014] The substrate 2 forms the base of the chip component 1. The chip component 1 is configured by supporting a plurality of insulating films, metal films, etc. stacked on top of each other on the substrate 2. The substrate 2 has a rectangular parallelepiped shape and is approximately the same size as the chip component 1. In this embodiment, the substrate 2 may be a semiconductor substrate such as a silicon substrate. The thickness of the substrate 2 may be, for example, 80 μm or more and 150 μm or less.

[0015] The substrate 2 has a first main surface 5, a second main surface 6, and four side surfaces 7 to 10. The first main surface 5 is the so-called front surface of the chip component 1, and the second main surface 6 is the back surface of the chip component 1. The four side surfaces 7 to 10 surround the first main surface 5 in a plan view seen from the normal direction n of the first main surface 5 (hereinafter simply referred to as a "plan view"). The four side surfaces 7 to 10 may include a pair of first side surfaces 7 and second side surfaces 8 facing each other in the first direction X, and a pair of third side surfaces 9 and fourth side surfaces 10 facing each other in the second direction Y. In other words, the side surfaces extending parallel to each other along the second direction Y may be the first side surfaces 7 and second side surfaces 8 on the short side sides of the substrate 2, and the side surfaces extending parallel to each other along the first direction X may be the third side surfaces 9 and fourth side surfaces 10 on the long side sides of the substrate 2. The first side surface 7, the second side surface 8, the third side surface 9, and the fourth side surface 10 may alternatively be referred to as the first end surface, the second end surface, the third end surface, and the fourth end surface, respectively.

[0016] The first external electrode 3 is formed to cover almost the entire first main surface 5. The first external electrode 3 has side surfaces 11 to 14 formed at intervals inward from the side surfaces 7 to 10. The four side surfaces 11 to 14 may be a pair of first side surfaces 11 and second side surfaces 12 that face each other in the first direction X and are parallel to the pair of first side surfaces 7 and second side surfaces 8, and a pair of third side surfaces 13 and fourth side surfaces 14 that face each other in the second direction Y and are parallel to the pair of third side surfaces 9 and fourth side surfaces 10. The region between the side surfaces 11 to 14 of the first external electrode 3 and the side surfaces 7 to 10 of the substrate 2 may be an insulating space 15 in which an insulating portion on the first main surface 5 of the substrate 2 is exposed. The side surfaces 11 to 14 of the first external electrode 3 may also be referred to as the edge or end face of the first external electrode 3.

[0017] A notch 16 is formed in the periphery of the first external electrode 3. The notch 16 may function as a mark for checking the orientation of the chip component 1 when mounting the chip component 1 on a mounting board or the like. For example, by visually checking the position of the notch 16, it is possible to determine from outside the chip component 1 the orientation of the longitudinal direction (first direction X) and lateral direction (second direction Y) of the chip component 1. In this embodiment, the notch 16 is formed by selectively removing a corner of the first external electrode 3 that faces a corner of the substrate 2. Two notches 16 may be formed in total, corresponding to each of a pair of corners on the first side surface 7 side of the substrate 2 in the first direction X. However, from the viewpoint of serving as an indicator for the orientation of the chip component 1, it is preferable to form the notch 16 corresponding to one corner, as shown in FIGS. 1 and 2 . This allows the chip component 1, which has a rectangular shape in a plan view, to have asymmetry in terms of both line symmetry (for example, line symmetry with a line along the first direction X and the second direction Y as the axis of symmetry) and point symmetry.

[0018] The second external electrode 4 is formed on the second main surface 6 side. The second external electrode 4 is formed so as to cover the entire second main surface 6. The second external electrode 4 has a shape that matches the shape of the second main surface 6 and has side surfaces 17-20 that match the side surfaces 7-10 of the substrate 2. The four side surfaces 17-20 may be a pair of first side surfaces 17 and second side surfaces 18 that face each other in the first direction X and match the pair of first side surfaces 7 and second side surfaces 8, and a pair of third side surfaces 19 and fourth side surfaces 20 that face each other in the second direction Y and match the pair of third side surfaces 9 and fourth side surfaces 10. The second external electrode 4 is in direct contact with the substrate 2 and is electrically and mechanically connected to the substrate 2. The first external electrode 3 and the second external electrode 4 are selectively formed on the first main surface 5 side and the second main surface 6 side of the substrate 2, respectively. Therefore, in this embodiment, the side surfaces 7 to 10 of the substrate 2 may be exposed surfaces that are not covered with electrode films such as the first external electrode 3 and the second external electrode 4, and where the semiconductor surface of the substrate 2 is exposed. [ Cross-sectional structure of chip component 1 ] 4 is a schematic cross-sectional view of the chip component 1. Fig. 4 is a diagram that schematically shows the layer structure on the first main surface 5 of the chip component 1, and does not show a cross section taken along a specific cutting line in Fig. 2.

[0019] Referring to FIG. 4, on the first main surface 5 of the substrate 2, a conductive layer 21 and a capacitive film 22 are laminated.

[0020] The conductive layer 21 is formed so as to cover the entire flat first main surface 5 of the substrate 2. Therefore, the conductive layer 21 has end faces that coincide with the side surfaces 7 to 10 of the substrate 2. The flat first main surface 5 may be defined, for example, as meaning that no recesses such as trenches are intentionally formed in the first main surface 5 by etching, and the surface state of the device formation surface of the semiconductor wafer is maintained as a flat surface. The thickness of the conductive layer 21 may be, for example, 0.1 μm or more and 2.0 μm or less.

[0021] The conductive layer 21 may be, for example, a metal layer or a polysilicon layer, or may be a laminated film of these. In this embodiment, the conductive layer 21 is formed of a single metal layer. The conductive layer 21 as a metal layer may be, for example, an Al layer, an Au layer, or the like. The conductive layer 21 as a polysilicon layer may be, for example, a polysilicon layer containing impurities.

[0022] The capacitive film 22 is formed to cover the entire conductive layer 21. Therefore, the capacitive film 22 has end faces that coincide with the side surfaces 7 to 10 of the substrate 2. The thickness of the capacitive film 22 may be, for example, not less than 2 μm and not more than 8 μm.

[0023] The capacitance film 22 may be, for example, an SiO2 film or an SiN film, or may be a laminated film of these. For example, it may be an SiO2 / SiN laminated film or an SiO2 / SiN / SiO2 laminated film. The capacitance film 22 may also be an ON film or an ONO film, or may be a laminated film of these. Furthermore, the capacitance film 22 may be an insulating film made of a high-dielectric material (High-k material). Examples of high-dielectric materials include aluminum oxide (Al2O3), tantalum pentoxide (Ta2O5), titanium pentoxide (Ti3O5), hafnium oxide (HfO2), strontium titanate (SrTiO3), barium strontium titanate (Ba x Sr 1-x Examples of suitable materials include perovskite compounds such as TiO3. In this embodiment, the capacitance film 22 is formed of an SiO2 film.

[0024] The first external electrode 3 is formed on the capacitive film 22. The first external electrode 3 faces the substrate 2 with the capacitive film 22 sandwiched therebetween. In the chip component 1, a capacitor 25 is formed by the capacitive film 22 and the first external electrode 3 (upper electrode 23) and substrate 2 (lower electrode 24) that sandwich the capacitive film 22. Note that in FIG. 4, the substrate 2 is shown as the lower electrode 24, but the laminated structure including the second external electrode 4, substrate 2, and conductive layer 21 may also be defined as the lower electrode. In other words, the lower electrode may be formed by a conductive laminated structure having a pair of metal layers (conductive layer 21 and second external electrode 4) that sandwich a semiconductor layer made of the substrate 2 from above and below.

[0025] The first external electrode 3 may be a laminated film including multiple conductive layers. For example, the first external electrode 3 may include a first layer 26, a second layer 27, and a third layer 28, stacked in this order from the substrate 2 side. The first layer 26 may be referred to as a barrier layer containing Ti, for example. The second layer 27 may be referred to as a sputtered layer containing Au, and the third layer 28 may be referred to as a plated layer containing Au. If the second layer 27 and the third layer 28 are made of the same material, there may be no boundary between them. The third layer 28 may be thicker than the first layer 26 and the second layer 27. For example, the first layer 26 may be 1000 Å to 3000 Å thick, the second layer 27 may be 300 Å to 1000 Å thick, and the third layer 28 may be 1 μm to 3 μm thick.

[0026] The second external electrode 4 is connected to the second main surface 6 of the substrate 2. The second external electrode 4 is electrically connected to the lower electrode 24. The second external electrode 4 may be, for example, a Ni / Pd / Au laminated film including a Ni film, a Pd film, and an Au film laminated in this order from the substrate 2 side.

[0027] In this embodiment, the first external electrode 3 and the second external electrode 4 form both terminals of the vertical chip component 1. The vertical chip component 1 can be used, for example, by bonding it to a mounting substrate via the second external electrode 4 and joining a joining member such as a bonding wire 29 to the first external electrode 3.

[0028] In this chip component 1, the upper electrode 23 and the lower electrode 24 (substrate 2) face each other with the capacitive film 22 sandwiched therebetween. This forms a vertical capacitor 25 having a laminated structure of the upper electrode 23-capacitive film 22-lower electrode 24 in the vertical direction along the thickness direction of the substrate 2. Because it is a vertical capacitor 25, the first external electrode 3 for the upper electrode 23 can be arranged on the first main surface 5 side, and the second external electrode 4 for the lower electrode 24 can be arranged on the second main surface 6 side, so there is no need to form these external electrodes 3, 4 side by side in the horizontal direction along the first main surface 5 of the substrate 2. This makes it possible to effectively utilize the horizontal space of the substrate 2, thereby providing a compact chip component 1.

[0029] While miniaturization can be achieved, because the lower electrode 24 includes the substrate 2 (semiconductor substrate), there is a concern about loss due to the resistance of the substrate 2, compared to when the lower electrode is composed of a single metal layer. In this regard, in the chip component 1, the conductive layer 21 is formed between the capacitive film 22 and the substrate 2. This allows the resistance value on the first main surface 5 of the substrate 2 to be replaced by the resistance value of the conductive layer 21 instead of the resistance value of the substrate 2 (semiconductor resistance value), thereby reducing the resistance value on the lower electrode 24 side. As a result, loss in the capacitor 25 can be reduced. Furthermore, because the thickness of the substrate 2 is 80 μm or more and 150 μm or less, the resistance of the substrate 2 can be reduced. As a result, loss in the capacitor 25 can be further reduced.

[0030] Furthermore, since the substrate 2 of the chip component 1 is not a ceramic substrate but a semiconductor substrate (a silicon substrate in this embodiment), it can be suitably used as a chip component to be used in a relatively high temperature environment of, for example, about 200°C. [ Manufacturing method of chip component 1 ] 5A to 5F are diagrams showing the manufacturing process of the chip part 1 in the order of steps, and correspond to the cross section of FIG. 4 described above.

[0031] To manufacture the chip component 1, first, referring to FIG. 5A, a wafer 30 that will become the substrate 2 is prepared. Then, a metallic conductive layer 21 is formed on the first main surface 5 of the wafer 30 by, for example, sputtering. When the conductive layer 21 is made of polysilicon, the conductive layer 21 may be formed by CVD. The conductive layer 21 is formed so as to cover the entire first main surface 5 of the wafer 30.

[0032] 5B, a capacitive film 22 made of SiO 2 is formed on the conductive layer 21 by, for example, a CVD method. The capacitive film 22 is formed to cover the entire first main surface 5 of the wafer 30.

[0033] 5C, the first external electrode 3 is formed. For example, after the first layer 26 and the second layer 27 are formed in this order by sputtering, the third layer 28 is formed by plating growth from the second layer 27.

[0034] 5D, the wafer 30 is ground from the side of the second main surface 6. As a result, the wafer 30 is thinned.

[0035] Next, with reference to FIG. 5E, the second external electrode 4 is formed on the second main surface 6 of the substrate 2 by, for example, sputtering.

[0036] 5F, a dicing blade is inserted into the wafer 30 from the side of the second main surface 6, thereby cutting (dividing) the wafer 30. This cuts out the individual chip components 1. Through the above steps, the chip components 1 are obtained. [ Embodiment of chip component 31 ] Next, the structure of the chip part 31 will be described with reference to Figures 6 to 8. In Figures 6 to 8, structures corresponding to those described with reference to Figures 1 to 4 are given the same reference numerals, and descriptions thereof will be omitted.

[0037] 6 and 7, the chip component 31 further includes through conductive layers 32. In this embodiment, the plurality of through conductive layers 32 are arranged in a matrix across the entire first main surface 5 of the substrate 2 in a plan view. The plurality of through conductive layers 32 face both the first external electrode 3 and the second external electrode 4 in the thickness direction (third direction Z) of the substrate 2. Therefore, the plurality of through conductive layers 32 overlap the first external electrode 3 and the second external electrode 4 in a plan view. In addition, some of the plurality of through conductive layers 32 are formed in positions directly below bonding regions 33 for bonding wires 29 formed on the first external electrode 3, and overlap the bonding regions 33 in a plan view.

[0038] 8, the through conductive layer 32 penetrates the substrate 2 in the thickness direction (third direction Z) and electrically connects the conductive layer 21 and the second external electrode 4. In this embodiment, a plurality of through holes 34 are formed penetrating the substrate 2 in the thickness direction, and the conductive vias 35 that fill up each of the through holes 34 may be the through conductive layer 32. The conductive vias 35 may have a lower resistance than the substrate 2, and may be, for example, metal vias (e.g., aluminum vias, tungsten vias, etc.).

[0039] The conductive vias 35 are embedded in each through hole 34 and have a first surface 36 that is flush with the first main surface 5 of the substrate 2 and a second surface 37 that is flush with the second main surface 6 of the substrate 2. Therefore, on the first main surface 5 side of the substrate 2, in a plan view, island-shaped (dot-like) metal surfaces (first surfaces 36) are selectively formed on the substantially rectangular semiconductor surface (first main surface 5), and the semiconductor surface and the metal surface are smoothly connected without any steps, thereby forming a flat surface. Similarly, on the second main surface 6 side of the substrate 2, island-shaped (dot-like) metal surfaces (second surfaces 37) are selectively formed on the substantially rectangular semiconductor surface (second main surface 6) in a plan view, and the semiconductor surface and the metal surface are smoothly connected without any steps, thereby forming a flat surface.

[0040] In a cross-sectional view, the conductive layer 21 is in contact with the first main surface 5 of the substrate 2 and the first surfaces 36 of the conductive vias 35 alternately along the first direction X, and is connected to both the substrate 2 and the conductive vias 35. In addition, the second external electrode 4 is in contact with the second main surface 6 of the substrate 2 and the second surfaces 37 of the conductive vias 35 alternately along the first direction X, and is connected to both the substrate 2 and the conductive vias 35.

[0041] The through-hole conductive layer 32 does not need to be a conductive via 35, and may be, for example, a conductive film having one side and the other side opposite thereto, formed along the inner surface of the through-hole 34. In other words, when the through-hole conductive layer 32 is a conductive film, the through-hole 34 does not need to be completely filled with the through-hole conductive layer 32.

[0042] As described above, according to the chip component 31, the second external electrode 4 and the conductive layer 21 can be connected by the through conductive layer 32, which has a lower resistance than the substrate 2, and therefore the loss of the capacitor 25 can be further reduced. [ Manufacturing method of chip component 31 ] 9A to 9D are views showing some of the manufacturing steps of the chip part 31 in the order of steps, and correspond to the cross section of FIG. 8 described above.

[0043] 5A to 5D are first carried out to manufacture the chip component 31. That is, the same manufacturing steps as those for the chip component 1 are carried out up to the step of thinning the wafer 30.

[0044] 9A, the wafer 30 is selectively removed from the side of the second main surface 6. In this embodiment, the wafer 30 is selectively dry etched to form the through holes .

[0045] 9B, the material of the conductive vias 35 is deposited on the second main surface 6 of the wafer 30. After the deposition, the material outside the through holes 34 is removed by, for example, a CMP process, and a flat surface is formed where the second surfaces 37 of the conductive vias 35 and the second main surface 6 of the wafer 30 are continuous.

[0046] Next, with reference to FIG. 9C, second external electrode 4 is formed on second main surface 6 of substrate 2 by, for example, sputtering.

[0047] 9D, a dicing blade is inserted into the wafer 30 from the second main surface 6 side, thereby cutting (dividing) the wafer 30. This cuts out the individual chip components 1. Through the above steps, chip components 31 are obtained. [ Embodiment of chip component 41 ] Next, the structure of the chip part 41 will be described with reference to Figures 10 to 12. In Figures 10 to 12, structures corresponding to those described with reference to Figures 1 to 4 and Figures 6 to 8 are given the same reference numerals, and descriptions thereof will be omitted.

[0048] In the chip component 41, the through conductive layer 32 is not formed over the entire first main surface 5 of the substrate 2, but is formed in a concentrated manner directly below the bonding region 33. On the other hand, most of the region of the substrate 2 that does not overlap with the bonding region 33 in a plan view is a semiconductor region that maintains the state of the wafer 30. For example, as shown in FIGS. 10 and 11 , the substrate 2 may include, in the center in the first direction X, a first region 42 in which the through conductive layer 32 is formed, and a pair of second regions 43 consisting of semiconductor regions formed on both sides of the first region 42 in the first direction X. The first region 42 is sandwiched between the pair of second regions 43 in the first direction X.

[0049] In the chip component 41, a plurality of conductive through layers 32 are concentrated directly below the bonding region 33 where the current density is relatively high and which is in direct contact with the bonding wire 29. This allows the capacitor 25 to efficiently store electric charge. [ Embodiment of chip component 51 ] Next, the structure of the chip part 51 will be described with reference to Figures 13 to 15. In Figures 13 to 15, structures corresponding to those described with reference to Figures 1 to 4, 6 to 8, and 10 to 12 are given the same reference numerals, and descriptions thereof will be omitted.

[0050] In the chip component 51, the through conductive layer 32 is not formed over the entire first main surface 5 of the substrate 2, but is selectively formed near the side surfaces 7 to 10 of the substrate 2, avoiding the position directly below the bonding region 33. On the other hand, the region of the substrate 2 that overlaps with the bonding region 33 in a plan view is a semiconductor region that maintains the state of the wafer 30. For example, as shown in FIGS. 13 and 14 , the substrate 2 may include first regions 42 near the first side surface 7 and the second side surface 8, respectively, and the region sandwiched between the pair of first regions 42 in the first direction X may be the second region 43. The widths W2 and W3 occupied by the first regions 42 from the first side surface 7 and the second side surface 8 of the substrate 2 may be, for example, 10% to 30% of the length L of the substrate 2 in the first direction X (see FIG. 1 ). [ 1. An embodiment according to a chip component 61 ] Next, the structure of the chip part 61 will be described with reference to Figures 16 to 18. In Figures 13 to 15, structures corresponding to those described with reference to Figures 1 to 4 are given the same reference numerals, and descriptions thereof will be omitted.

[0051] In the chip component 61, capacitor trenches 62 are formed in the first main surface 5 of the substrate 2. In this embodiment, the plurality of capacitor trenches 62 are arranged in a stripe pattern across the entire first main surface 5 of the substrate 2 in a plan view. The plurality of capacitor trenches 62 may be stripes extending parallel to one another in the short-side direction (second direction Y) of the substrate 2. Some of the plurality of capacitor trenches 62 are formed directly below the bonding regions 33 for the bonding wires 29 and overlap the bonding regions 33 in a plan view. Each capacitor trench 62 has an inner surface 65 including a bottom surface 63 located midway in the thickness direction of the substrate 2 and side surfaces 64 extending from the bottom surface 63 to the first main surface 5. Each capacitor trench 62 is formed linearly extending in the second direction Y. Each capacitor trench 62 does not have to be linear and may be, for example, wavy or zigzag.

[0052] The conductive layer 21 and the capacitive film 22 form a laminated structure 67 having a boundary surface 66 that is aligned with the inner surface 65 of the capacitor trench 62. The laminated structure 67 has one surface 74 that contacts the first main surface 5 and another surface 75 on the opposite side, with both the one surface 74 and the other surface 75 aligned with the inner surface 65 of the capacitor trench 62. As a result, a space 68 surrounded by the laminated structure 67 is formed within the capacitor trench 62. The space 68 is formed by the capacitive film 22.

[0053] A buried electrode 69 is formed on the capacitive film 22. The buried electrode 69 is embedded in the space 68 and is formed along the first main surface 5 of the substrate 2. In other words, the buried electrode 69 is embedded in the capacitor trench 62 via the stacked structure 67. The buried electrode 69 integrally includes a buried portion 70 embedded in the capacitor trench 62 and a flat portion 71 connected to the upper end of the buried portion 70 and formed flat along the first main surface 5 of the substrate 2. The buried electrode 69 may be made of a semiconductor material such as polysilicon, or a metal material containing Cu or Al. In the case of a metal material, the buried electrode 69 may be made of, for example, Cu, Al, AlSi, or AlCu. The thickness of the buried electrode 69 (flat portion 71) may be, for example, 4000 Å or more and 10000 Å or less (400 nm or more and 1000 nm or less).

[0054] A surface insulating film 72 is formed on the substrate 2. The surface insulating film 72 covers the embedded electrode 69. The surface insulating film 72 may be, for example, an SiO2 film or an SiN film. The thickness of the surface insulating film 72 may be, for example, 10,000 Å to 15,000 Å (1 μm to 1.5 μm). A contact hole 73 is formed in the surface insulating film 72 to expose a portion of the embedded electrode 69. The first external electrode 3 is electrically connected to the embedded electrode 69 within the contact hole 73 in the surface insulating film 72. As a result, the upper electrode 23 of the capacitor 25 may be defined by a stacked structure of the embedded electrode 69 and the first external electrode 3.

[0055] According to the chip component 61, the capacitor trench 62 is formed, so that the opposing area between the embedded electrode 69 (upper electrode 23) and the conductive layer 21 (lower electrode 24) can be increased, thereby ensuring a large capacitance of the capacitor 25. [ Manufacturing method of chip component 61 ] 19A to 19I are diagrams showing the manufacturing process of the chip part 61 in the order of steps, and correspond to the cross section of the above-mentioned FIG.

[0056] To manufacture the chip component 61, first, referring to FIG. 19A, a wafer 76, which is the base of the substrate 2, is prepared. Then, a hard mask (not shown) made of SiO2 is formed by, for example, thermally oxidizing the first main surface 5 of the wafer 76. Next, openings are formed in the hard mask, and the wafer 76 is selectively etched from the first main surface 5 side through the hard mask. As a result, capacitor trenches 62 are formed in the removed portions of the wafer 76. As the etching method, dry etching is preferably used.

[0057] 19B, a conductive layer 21 is formed on the first main surface 5 of the wafer 76 and the inner surface 65 of the capacitor trench 62. The conductive layer 21 may be formed by, for example, a sputtering method.

[0058] 19C, a capacitive film 22 is formed on the conductive layer 21 on the first main surface 5 of the wafer 76 and on the inner surface 65 of the capacitor trench 62. The capacitive film 22 may be formed by, for example, a CVD method. This forms a stacked structure 67 of the conductive layer 21 and the capacitive film 22. A space 68 surrounded by the capacitive film 22 is formed in the capacitor trench 62.

[0059] 19D, a conductive film (not shown) that will become the embedded electrode 69 is formed on the capacitance film 22, for example, by CVD. The conductive film is formed to fill the capacitor trench 62 (space 68) and cover the entire first main surface 5 of the wafer 76. The conductive film is then patterned to form the embedded electrode 69 (upper electrode 23). This forms a capacitor 25 that includes the lower electrode 24 (wafer 76), capacitance film 22, and upper electrode 23.

[0060] 19E, a surface insulating film 72 is formed by, for example, a CVD method. Thereafter, the surface insulating film 72 is patterned to form a contact hole 73.

[0061] 19F, the first external electrode 3 is formed. For example, after the first layer 26 and the second layer 27 are formed in this order by sputtering, the third layer 28 is formed by plating growth from the second layer 27.

[0062] 19G, wafer 76 is ground from the side of second main surface 6. As a result, wafer 76 is thinned.

[0063] Next, referring to FIG. 19H, second external electrodes 4 are formed on second main surface 6 of wafer 76 by, for example, sputtering.

[0064] 19I, a dicing blade is inserted into the wafer 76 from the side of the second main surface 6, thereby cutting (dividing) the wafer 76. As a result, the individual chip components 61 are cut out. [ 1. An embodiment relating to a chip component 81 ] Next, the structure of the chip part 81 will be described with reference to Figures 20 to 22. In Figures 20 to 22, structures corresponding to those described with reference to Figures 1 to 4 and Figures 16 to 18 are given the same reference numerals, and descriptions thereof will be omitted.

[0065] In the chip component 81, the capacitor trench 62 is not formed over the entire first main surface 5 of the substrate 2, but is selectively formed near the side surfaces 7 to 10 of the substrate 2, avoiding the position directly below the bonding region 33. Meanwhile, the region of the substrate 2 that overlaps with the bonding region 33 in a plan view is a semiconductor region that maintains the state of the wafer 76. For example, as shown in FIGS. 20 and 21 , the substrate 2 may include a first region 82 formed near the first side surface 7 and the second side surface 8 and in which the capacitor trench 62 is formed, and a second region 83 consisting of a semiconductor region sandwiched between the pair of first regions 82 in the first direction X. Widths W4 and W5 of the substrate 2 from the first side surface 7 and the second side surface 8 to the first region 82 may be, for example, 20% to 40% of the length L of the substrate 2 in the first direction X (see FIG. 1 ). [ 1. An embodiment relating to a chip component 91 ] Next, the structure of the chip part 91 will be described with reference to Fig. 23. In Fig. 23, structures corresponding to those described with reference to Figs. 1 to 4, 6 to 8, and 16 to 18 are given the same reference numerals, and descriptions thereof will be omitted.

[0066] The chip component 91 has a structure in which the chip component 61 shown in FIG. 18 further includes a through-hole conductive layer 32. The through-hole conductive layer 32 of the chip component 91 is formed to avoid the areas where the multiple capacitor trenches 62 are formed. In FIG. 23, the through-hole conductive layer 32 is formed on the periphery of the substrate 2 outside the multiple capacitor trenches 62. As a result, the through-hole conductive layer 32 is connected to the conductive layer 21 on the first main surface 5 of the substrate 2.

[0067] In addition to the effect of ensuring a large capacitance of the capacitor 25, the chip component 91 can connect the second external electrode 4 and the conductive layer 21 via the through conductive layer 32, which has a lower resistance than the substrate 2, thereby further reducing the loss of the capacitor 25. [ Embodiment of chip component 101 ] Next, the structure of the chip part 101 will be described with reference to Fig. 24. In Fig. 24, structures corresponding to those described with reference to Figs. 1 to 4, 6 to 8, and 16 to 18 are given the same reference numerals, and descriptions thereof will be omitted.

[0068] The chip part 101 has a structure in which the chip part 61 shown in FIG. 18 further includes a through conductive layer 32. The through conductive layer 32 of the chip part 101 is formed in a position directly below the region in which a plurality of capacitor trenches 62 are formed. In FIG. 24, the through conductive layer 32 is formed in a position directly below the bottom of each capacitor trench 62. As a result, the through conductive layer 32 is connected to the conductive layer 21 at the bottom surface 63 of the capacitor trench 62.

[0069] According to the chip component 101, in addition to the effect of ensuring a large capacitance of the capacitor 25, the second external electrode 4 and the conductive layer 21 can be connected by the through conductive layer 32, which has a lower resistance than the substrate 2, thereby further reducing the loss of the capacitor 25.

[0070] Although embodiments of the present disclosure have been described, the present disclosure may be embodied in other forms.

[0071] The embodiments of the present disclosure are to be considered as illustrative in all respects and not restrictive, and are intended to include modifications in all respects.

[0072] The following characteristics can be extracted from the description of this specification and the drawings. [Appendix 1-1] a semiconductor substrate (2) having a first main surface (5) and a second main surface (6) opposite to the first main surface; a capacitive film (22) formed on the first main surface (5); a first electrode (3) formed on the capacitance film (22); a second electrode (4) formed on the second main surface (6); A chip component (1, 31, 41, 51, 61, 81, 91, 101) including a conductive layer (21) formed between the capacitive film (22) and the semiconductor substrate (2).

[0073] According to this configuration, the first electrode (3) and the semiconductor substrate (2) (second electrode (4)) face each other with the capacitive film (22) sandwiched therebetween. This results in a vertical capacitor (25) having a stacked structure of the upper electrode (23), the capacitive film (22), and the lower electrode (24) in the vertical direction along the thickness direction of the semiconductor substrate (2). Because the capacitor (25) is vertical, the first electrode (3) can be disposed on the first main surface (5) side, and the second electrode (4) can be disposed on the second main surface (6) side. This eliminates the need to arrange these external electrodes (3, 4) side by side in the horizontal direction along the first main surface (5) of the semiconductor substrate (2). This allows for effective use of the horizontal space of the semiconductor substrate (2), thereby providing a compact chip component (1, 31, 41, 51, 61, 81, 91, 101).

[0074] Furthermore, a conductive layer (21) is formed between the capacitive film (22) and the semiconductor substrate (2). This allows the resistance value of the first main surface (5) of the semiconductor substrate (2) to be replaced by the resistance value of the conductive layer (21) instead of the resistance value of the semiconductor, thereby reducing the resistance value on the second electrode (4) side. As a result, the loss of the capacitor (25) can be reduced. [Appendix 1-2] A chip component (31, 41, 51, 91, 101) according to Appendix 1-1, further including a through conductive layer (32) that penetrates the semiconductor substrate (2) in the thickness direction, electrically connects the conductive layer (21) and the second electrode (4), and has a lower resistance than the semiconductor substrate (2).

[0075] According to this configuration, the second electrode (4) and the conductive layer (21) can be connected by the through conductive layer (32) which has a lower resistance than the semiconductor substrate (2), so that the loss of the capacitor (25) can be further reduced. [Appendix 1-3] The chip part (31, 41, 51, 91, 101) according to Supplementary Note 1-2, wherein a plurality of the through conductive layers (32) are formed on the semiconductor substrate (2). [Appendix 1-4] The chip component (31) according to appendix 1-3, wherein the plurality of through conductive layers (32) are arranged in a matrix across the entire first main surface (5) of the semiconductor substrate (2) in a plan view. [Appendix 1-5] The first electrode (3) has a bonding region (33) to which a bonding member (29) is bonded, The chip component (41) according to appendix 1-3, wherein the plurality of through-hole conductive layers (32) are formed in a concentrated manner at a position directly below the bonding region (33).

[0076] According to this configuration, the plurality of conductive through layers 32 are concentrated directly below the joining region 33 where the current density is relatively high and which is in direct contact with the joining member 29. This allows efficient charge storage in the capacitor 25. [Appendix 1-6] The first electrode (3) has a bonding region (33) to which a bonding member (29) is bonded, A chip component (51) according to appendix 1-3, wherein the plurality of through conductive layers (32) are selectively formed in the vicinity of the end faces (7-10) of the semiconductor substrate (2), avoiding the position directly below the junction region (33).

[0077] According to this configuration, the through conductive layer 32 is formed so as to avoid a position directly below the bonding region 33. This prevents the force acting on the first electrode 3 when the bonding member 29 is bonded from being directly transmitted to the through conductive layer 32. As a result, the strength of the semiconductor substrate 2 can be improved. [Appendix 1-7] The chip part (31, 41, 51, 91, 101) according to any one of Supplementary Notes 1-2 to 1-6, wherein the through conductive layer (32) includes a conductive via (35) embedded in a through hole (34) that penetrates the semiconductor substrate (2) in the thickness direction. [Appendix 1-8] a capacitor trench (62) formed in the first main surface (5) of the semiconductor substrate (2); the conductive layer (21) and the capacitive film (22) form a laminated structure (67) having a boundary surface (66) along the inner surface (65) of the capacitor trench (62); A chip component (61, 81, 91, 101) according to any one of Appendices 1-1 to 1-4, further including an embedded electrode (69) embedded in the capacitor trench (62) via the laminated structure (67) and connected to the first electrode (3).

[0078] According to this configuration, the formation of the capacitor trench 62 increases the opposing area between the embedded electrode 69 and the conductive layer 21, thereby ensuring a large capacitance of the capacitor 25. [Appendix 1-9] The first electrode (3) has a bonding region (33) to which a bonding member (29) is bonded, A chip component (81) according to appendix 1-8, wherein the capacitor trench (62) is selectively formed in the vicinity of the end face (7-10) of the semiconductor substrate (2), avoiding a position directly below the junction region (33). [Appendix 1-10] The chip part (1, 31, 41, 51, 61, 81, 91, 101) according to any one of Supplementary Notes 1-1 to 1-9, wherein the conductive layer (21) is formed so as to cover the entire first main surface (5) of the semiconductor substrate (2). [Appendix 1-11] The chip part (1, 31, 41, 51, 61, 81, 91, 101) according to any one of Supplementary Notes 1-1 to 1-10, wherein the conductive layer (21) includes at least one of a metal layer and a polysilicon layer. [Appendix 1-12] The chip part (1, 31, 41, 51, 61, 81, 91, 101) according to any one of Supplementary Notes 1-1 to 1-11, wherein the semiconductor substrate (2) has a thickness of 80 μm or more and 150 μm or less.

[0079] According to this configuration, the thickness of the semiconductor substrate 2 is 80 μm or more and 150 μm or less, so that the resistance of the semiconductor substrate 2 can be reduced, thereby reducing the loss of the capacitor 25. [Appendix 1-13] The chip part (1, 31, 41, 51, 61, 81, 91, 101) according to any one of Supplementary Notes 1-1 to 1-12, wherein the semiconductor substrate (2) includes a silicon substrate. [Appendix 1-14] The chip part (1, 31, 41, 51, 61, 81, 91, 101) according to any one of Supplementary Notes 1-1 to 1-13, wherein the capacitive film (22) has a thickness of 2 μm or more and 8 μm or less. [Appendix 1-15] The chip part (1, 31, 41, 51, 61, 81, 91, 101) according to any one of Supplementary Notes 1-1 to 1-14, wherein the capacitive film (22) includes at least one selected from the group consisting of an SiO2 film, a SiN film, an ON film, an ONO film, an Al2O3 film, and a Ti3O5 film. [Explanation of symbols]

[0080] 1: Chip parts 2: Circuit board 3 :1st external electrode 4: 2nd external electrode 5: First main surface 6: Second main surface 7 :1st side 8:Second side 9:Third side 10: 4th side 11 :1st side 12:Second side 13:Third side 14: 4th side 15: Insulating space 16: Notch 17 :1st side 18:Second side 19:Third side 20: 4th side 21: Conductive layer 22: Capacitive membrane 23: Upper electrode 24: Lower electrode 25: Capacitor 26 :1st layer 27: 2nd layer 28:Third layer 29: Bonding wire 30: Wafer 31: Chip parts 32: Through conductive layer 33:Joint area 34:Through hole 35: Conductive via 36: 1st page 37:Second side 41: Chip parts 42:First area 43:Second area 51: Chip parts 61: Chip parts 62: Capacitor trench 63: Bottom 64: Side 65: Inner 66: Boundary 67: Laminated structure 68: Space 69: Buried electrode 70: Embedded part 71: Flat part 72: Surface insulating film 73: Contact hole 74: One side 75: Other side 76: Wafer 81: Chip parts 82: 1st area 83:Second area 91: Chip parts 101: Chip parts T: Thickness W: Width W2: Width W3: Width W4: Width W5:Width X: 1st direction Y: Second direction Z: 3rd direction n:Normal direction

Claims

1. a semiconductor substrate having a first main surface and a second main surface opposite to the first main surface; a capacitive film formed on the first main surface; a first electrode formed on the capacitance film; a second electrode formed on the second major surface; a conductive layer formed between the capacitance film and the semiconductor substrate; a plurality of through-hole conductive layers that penetrate the semiconductor substrate in a thickness direction, electrically connect the conductive layer and the second electrode, and have a lower resistance than the semiconductor substrate; A chip component, wherein, in a plan view, the semiconductor substrate has a portion where the plurality of through-hole conductive layers are collectively formed and a portion where the plurality of through-hole conductive layers are not formed.

2. the first electrode has a bonding region to which a bonding member is bonded; 2. The chip part according to claim 1, wherein the plurality of through-hole conductive layers are formed in a concentrated manner at a position directly below the bonding region.

3. The first electrode has a bonding area to which a bonding member is bonded, 2. The chip component according to claim 1, wherein the plurality of through-hole conductive layers are formed at positions that avoid positions directly below the bonding region.

4. the first electrode has a bonding region to which a bonding member is bonded; 4. The chip component according to claim 3, wherein said plurality of through-hole conductive layers are selectively formed in the vicinity of the end face of said semiconductor substrate, avoiding positions directly under said junction regions.

5. 5. The chip part according to claim 2, wherein the through conductive layer includes a conductive via embedded in a through hole that penetrates the semiconductor substrate in the thickness direction.

6. a capacitor trench formed in the first major surface of the semiconductor substrate; the conductive layer and the capacitive film form a laminated structure having a boundary surface along the inner surface of the capacitor trench; 6. The chip part according to claim 1, further comprising a buried electrode that is buried in the capacitor trench via the laminated structure and connected to the first electrode.

7. the first electrode has a bonding region to which a bonding member is bonded; 7. The chip component according to claim 6, wherein said capacitor trench is selectively formed in the vicinity of an end face of said semiconductor substrate, avoiding a position directly below said junction region.

8. A chip component as described in claim 6 or 7, wherein the multiple penetrating conductive layers are formed to avoid the formation area of ​​the capacitor trench.

9. A chip component as described in claim 6 or 7, wherein the plurality of through conductive layers are formed at a position directly below the formation area of ​​the capacitor trench.

10. 10. The chip part according to claim 1, wherein the conductive layer is formed so as to cover the entire first main surface of the semiconductor substrate.

11. 11. The chip part according to claim 1, wherein the conductive layer includes at least one of a metal layer and a polysilicon layer.

12. The chip part according to any one of claims 1 to 11, wherein the semiconductor substrate has a thickness of 80 µm or more and 150 µm or less.

13. The chip part according to any one of claims 1 to 12, wherein the semiconductor substrate includes a silicon substrate.

14. The chip part according to any one of claims 1 to 13, wherein the capacitive film has a thickness of 2 µm or more and 8 µm or less.

15. The capacitance film is made of SiO ２ film, SiN film, ON film, ONO film, Al ２ O ３ film, and Ti ３ O ５ The chip part according to any one of claims 1 to 14, comprising at least one selected from the group consisting of films.

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