Semiconductor device, display device, and semiconductor integrated circuit

Abstract

This semiconductor device comprises: a first gate electrode; a first gate insulating film disposed on the first gate electrode; a semiconductor film disposed on the first gate insulating film so as to overlap the first gate electrode; a first terminal which is in contact with the semiconductor film and is electrically connected to the semiconductor film and to the first gate electrode; a second terminal which is disposed so as to be in contact with the semiconductor film but to be separated from the first terminal; a second gate insulating film disposed on the semiconductor film, the first terminal, and the second terminal; and a second gate electrode which is disposed on the second gate insulating film so as to overlap the semiconductor film and is electrically connected to the second terminal.

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a semiconductor device or a display device including a semiconductor device. [Background technology]

[0002] Recently, liquid crystal display devices using liquid crystal elements or display devices using light-emitting elements have become known as display devices. The light-emitting elements are, for example, light-emitting diodes (LEDs), micro-light-emitting diodes (micro LEDs), or organic electroluminescence (EL) elements. The display devices also include a protection circuit (semiconductor device) for protecting transistors, capacitors, resistors, and circuits including these from surges or electrostatic discharge (ESD). The protection circuit is composed of, for example, two transistors (see Patent Document 1 or Patent Document 2). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2019-212855 [Patent Document 2] Japanese Patent Application Laid-Open No. 2017-147385 Summary of the Invention [Problem to be solved by the invention]

[0004] For example, in order to operate a protection circuit at a desired voltage, it may be necessary to connect multiple protection circuits. Also, in order to pass a current corresponding to a surge or ESD through the protection circuit, it may be necessary to increase the size of the transistors that make up the protection circuit. As a result, the circuit scale of the protection circuit may increase.

[0005] An object of one embodiment of the present invention is to provide a semiconductor device that suppresses an increase in circuit size, and a display device including the semiconductor device. [Means for solving the problem]

[0006] A semiconductor device according to one embodiment of the present invention comprises a first gate electrode, a first gate insulating film disposed on the first gate electrode, a semiconductor film disposed on the first gate insulating film and overlapping the first gate electrode, a first terminal in contact with the semiconductor film and electrically connected to the semiconductor film and the first gate electrode, a second terminal in contact with the semiconductor film and disposed spaced apart from the first terminal, a second gate insulating film disposed on the semiconductor film, the first terminal, and the second terminal, and a second gate electrode disposed on the second gate insulating film, overlapping the semiconductor film, and electrically connected to the second terminal.

[0007] A display device according to one embodiment of the present invention comprises a semiconductor device including a first gate electrode, a first gate insulating film disposed on the first gate electrode, a semiconductor film disposed on the first gate insulating film and overlapping the first gate electrode, a first terminal in contact with the semiconductor film and electrically connected to the semiconductor film and the first gate electrode, a second terminal in contact with the semiconductor film and disposed spaced apart from the first terminal, a second gate insulating film disposed on the semiconductor film, the first terminal, and the second terminal, and a second gate electrode disposed on the second gate insulating film, overlapping the semiconductor film, and electrically connected to the second terminal; a display unit including a plurality of pixels electrically connected to a plurality of the semiconductor devices; and a control circuit electrically connected to the plurality of pixels and controlling the plurality of pixels.

[0008] A semiconductor integrated circuit according to one embodiment of the present invention includes a semiconductor device including: a first gate electrode; a first gate insulating film disposed on the first gate electrode; a semiconductor film disposed on the first gate insulating film and overlapping the first gate electrode; a first terminal in contact with the semiconductor film and electrically connected to the semiconductor film and the first gate electrode; a second terminal in contact with the semiconductor film and disposed spaced apart from the first terminal; a second gate insulating film disposed on the semiconductor film, the first terminal, and the second terminal; and a second gate electrode disposed on the second gate insulating film, overlapping the semiconductor film, and electrically connected to the second terminal; and an electronic device electrically connected to the semiconductor device. [Brief explanation of the drawings]

[0009] [Figure 1] 1A is a plan view showing the configuration of a semiconductor device according to one embodiment of the present invention, and FIG. 1B is an end cross-sectional view showing the configuration of a semiconductor device according to one embodiment of the present invention. [Figure 2] 1A and 1B are circuit diagrams showing the circuit configuration of a semiconductor device according to one embodiment of the present invention. [Figure 3] 1 is a plan view showing a configuration of a display device according to an embodiment of the present invention. [Figure 4] 1 is a circuit diagram showing a configuration of a semiconductor device and a pixel circuit according to an embodiment of the present invention; [Figure 5] 1 is an end cross-sectional view showing the configuration of a semiconductor device and a pixel circuit according to an embodiment of the present invention. [Figure 6] 1A is a plan view showing the configuration of a semiconductor device according to a second embodiment of the present invention, and FIG. 1B is an end cross-sectional view showing the configuration of a semiconductor device according to the second embodiment of the present invention. [Figure 7] 10(A) and 10(B) are circuit diagrams showing the circuit configuration of a semiconductor device according to a second embodiment of the present invention. [Figure 8] FIG. 10 is an end cross-sectional view showing the configuration of a semiconductor device and a pixel circuit according to a third embodiment of the present invention. [Figure 9]FIG. 10 is a plan view showing the configuration of a semiconductor integrated circuit according to a fourth embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, each embodiment of the present invention will be described with reference to the drawings. However, the present invention can be embodied in various forms without departing from the spirit of the present invention, and should not be construed as being limited to the description of the embodiments exemplified below. Furthermore, in the drawings, the width, thickness, shape, etc. of each part may be shown schematically compared to the actual form in order to make the explanation clearer, but these schematic drawings are merely examples and do not limit the interpretation of the present invention.

[0011] In the present invention, when a single film is processed to form multiple films, these multiple films may have different functions and roles. However, these multiple films originate from films formed as the same layer in the same process, and have the same layer structure and the same material. Therefore, these multiple films are defined as existing in the same layer.

[0012] In each embodiment of the present invention, expressions such as "above" and "below" when describing the drawings express the relative positional relationship between a structure of interest and another structure. In each embodiment of the present invention, in a side view, the direction from an insulating surface described below toward a bank is defined as "above," and the opposite direction is defined as "below." In each embodiment of the present invention, when expressing a mode in which another structure is disposed on top of another structure, the term "above" is used to include both a case in which another structure is disposed directly above the structure so as to be in contact with the structure, and a case in which another structure is disposed above the structure via another structure, unless otherwise specified.

[0013] Furthermore, in each embodiment of the present invention, unless otherwise specified, expressions such as "α includes A, B, or C," "α includes any one of A, B, and C," and "α includes one selected from the group consisting of A, B, and C" do not exclude cases where α includes multiple combinations of A to C. Furthermore, these expressions do not exclude cases where α includes other elements.

[0014] Furthermore, in each embodiment of the present invention, elements similar to those previously described with reference to the preceding drawings may be given the same reference numerals (or reference numerals with A, B, a, b, etc., suffixed thereto) and detailed descriptions thereof may be omitted as appropriate. Note that the letters "first" and "second" suffixed to each element are convenient labels used to distinguish between elements and have no further meaning unless otherwise specified.

[0015] First Embodiment In this embodiment, a semiconductor device 100 according to one embodiment of the present invention and a display device 20 using the semiconductor device 100 will be described. In this embodiment, the semiconductor device 100 is a protection circuit for protecting transistors, capacitors, resistors, and circuits including them from surges or ESD. The protection circuit is, for example, a bidirectional diode. In this embodiment, the semiconductor device 100 includes, for example, a thin film transistor (TFT) as the semiconductor film 112 (FIGS. 1A, 1B, 5, 6, and 8). In this embodiment, the semiconductor device 100 viewed from a direction perpendicular to the screen (display unit) is referred to as a "planar view," and the semiconductor device 100 cut along a plane or curved plane intersecting an insulating surface and the cut surface viewed from a direction parallel to the screen is referred to as a "cross-sectional view." In this embodiment, for example, an axis parallel or approximately parallel to the major axis of the first gate electrode or the second gate electrode is defined as a first axis D1, an axis intersecting the first axis D1 and parallel or approximately parallel to the minor axis of the first gate electrode or the second gate electrode is defined as a second axis D2, and an axis intersecting the first axis D1 and the second axis D2 and perpendicular or approximately perpendicular to a plane (D1-D2 plane) including the first axis D1 and the second axis D2 is defined as a third axis D3.

[0016] <1-1. Configuration of the semiconductor device 100> Fig. 1(A) is a plan view showing the configuration of the semiconductor device 100, and Fig. 1(B) is an end cross-sectional view showing a part of the cross section taken along line A1-A2 of the semiconductor device 100 shown in Fig. 1(A). Figs. 2(A) and 2(B) are circuit diagrams showing the circuit configuration of the semiconductor device 100. The configuration of the semiconductor device 100 is not limited to the configurations shown in Figs. 1(A), 1(B), 2(A), and 2(B).

[0017] 1A and 1B, the semiconductor device 100 includes a first rectifier circuit 306 and a second rectifier circuit 304. One of the first rectifier circuit 306 and the second rectifier circuit 304 is a diode-connected first transistor, and the other of the first rectifier circuit 306 and the second rectifier circuit 304 is a diode-connected second transistor.

[0018] In this embodiment, as an example, the first rectifier circuit 306 is a first transistor 370, and the second rectifier circuit 304 is a second transistor 350. The first transistor 370 is composed of a gate electrode 374, a first gate insulating film 106, a semiconductor film 112, a first terminal 108, and a second terminal 110, and the second transistor 350 is composed of a gate electrode 354, a second gate insulating film 114, a semiconductor film 112, the first terminal 108, and the second terminal 110.

[0019] The gate electrode 374 is formed using a first gate electrode layer 104 arranged to be in contact with the upper surface of the first substrate 102. The first gate insulating film 106 is in contact with the upper surface of the first substrate 102 and the first gate electrode layer 104, and is arranged to cover the upper surface and side surfaces of the gate electrode 374. The semiconductor film 112 is arranged to be in contact with the first gate insulating film 106 and is formed to overlap with the gate electrode 374. The first terminal 108 is arranged to be in contact with part of the upper surface and side surfaces of the semiconductor film 112 and the upper surface of the first gate insulating film 106, and is electrically connected to the gate electrode 374 through a contact hole 121. The contact hole 121 opens the first gate insulating film 106. The second terminal 110 is in contact with part of the upper surface and side surfaces of the semiconductor film 112 and the upper surface of the first gate insulating film 106, and is arranged spaced apart from the first terminal 108, and is electrically connected to the gate electrode 354 through a contact hole 122. The first terminal 108 and the second terminal 110 are formed in the same layer. A contact hole 122 opens the second gate insulating film 114. The second gate insulating film 114 is arranged so as to be in contact with the upper surface and part of the side surface of the semiconductor film 112, the upper surface and part of the side surface of the first terminal 108, and the upper surface and part of the side surface of the second terminal 110. The gate electrode 354 is formed using a second gate electrode layer 116 arranged so as to be in contact with the upper surface of the second gate insulating film 114. The gate electrode 354 is also formed so as to overlap the semiconductor film 112 and is electrically connected to the second terminal 110 through the contact hole 122.

[0020] In plan view and cross-sectional view, the arrangement of the gate electrode 374, first gate insulating film 106, semiconductor film 112, first terminal 108, second terminal 110, second gate insulating film 114, and gate electrode 354 allows at least one region (first region 120A) to be defined in the semiconductor film 112, which is sandwiched between the first terminal 108 and the second terminal 110. The length of the first region 120A parallel to the first axis D1 is length L1.

[0021] The first region 120A is a region sandwiched between the first terminal 108 and the second terminal 110, and is a region where the semiconductor film 112 overlaps with the gate electrode 374 and the first gate insulating film 106. The first region 120A functions as an active region (channel region) of the first transistor 370. The first region 120A is a region sandwiched between the first terminal 108 and the second terminal 110, and is a region where the semiconductor film 112 overlaps with the gate electrode 354 and the second gate insulating film 114. The first region 120A also functions as an active region (channel region) of the second transistor 350. In planar and cross-sectional views, the first region 120A of the first transistor 370 overlaps with the first region 120A of the second transistor 350, and the longitudinal position of the first region 120A of the first transistor 370 parallel to the first axis D1 is the same as or approximately the same as the longitudinal position of the first region 120A of the second transistor 350 parallel to the first axis D1.

[0022] That is, the channel region of the first transistor 370 is the same as the channel region of the second transistor 350. Meanwhile, in the first rectifier circuit 306, the first terminal 108 is electrically diode-connected to the gate electrode 374, the first terminal 108 is the source electrode 372 of the first transistor 370, and the second terminal 110 is the drain electrode 376 of the first transistor 370. Also, in the second rectifier circuit 304, the second terminal 110 is electrically diode-connected to the gate electrode 354, the second terminal 110 is the source electrode 352 of the second transistor 350, and the first terminal 108 is the drain electrode 356 of the second transistor 350.

[0023] In the first transistor 370, a current can flow in the semiconductor film 112 by applying a voltage to the gate electrode 374, the first terminal 108, and the second terminal 110. In the second transistor 350, a current can flow in the semiconductor film 112 by applying a voltage to the gate electrode 354, the second terminal 110, and the first terminal 108.

[0024] With respect to the third axis D3, the first rectifier circuit 306 (first transistor 370) is arranged (stacked) on top of the second rectifier circuit 304 (second transistor 350), and the first rectifier circuit 306 (first transistor 370) is arranged closer to the first substrate 102 than the second rectifier circuit 304 (second transistor 350).

[0025] For example, when the first rectifier circuit is not disposed (stacked) on the second rectifier circuit 304, the transistors of the first rectifier circuit and the second rectifier circuit 304 constituting the semiconductor device 100 are formed on a plane including the first axis D1 and the second axis D2. In this case, compared to when the first rectifier circuit is disposed (stacked) on the second rectifier circuit 304, the transistors of the first rectifier circuit 306 and the second rectifier circuit 304 constituting the semiconductor device 100 are larger on the plane including the first axis D1 and the second axis D2, and the circuit scale of the semiconductor device 100 is larger.

[0026] In the semiconductor device 100 of this embodiment, the first rectifier circuit 306 is arranged (stacked) on top of the second rectifier circuit 304, so the transistor size of the semiconductor device 100 can be made smaller and the circuit scale can also be made smaller than when the first rectifier circuit 306 is not arranged (stacked) on top of the second rectifier circuit 304.

[0027] Also, as shown in Figures 1(A), 1(B), 2(A), and 2(B), the gate electrode 374 and the source electrode 372 of the first transistor 370 are electrically connected to the drain electrode 356 of the second transistor 350, and the gate electrode 354 and the source electrode 352 of the second transistor 350 are electrically connected to the drain electrode 376 of the first transistor 370.

[0028] That is, the gate electrode 374 and the source electrode 372 of the first transistor 370 function as an anode (positive electrode) of the first rectifier circuit 306, and the drain electrode 376 of the first transistor 370 functions as a cathode (negative electrode) of the first rectifier circuit 306. Thus, the semiconductor device 100 can function as a bidirectional diode.

[0029] 2A and 2B, in the semiconductor device 100 according to one embodiment of the present invention, the gate electrode 374 and the source electrode 372 of the first transistor 370 and the drain electrode 356 of the second transistor 350 are electrically connected to the input terminal IN, and the gate electrode 354 and the source electrode 352 of the second transistor 350 and the drain electrode 376 of the first transistor 370 are electrically connected to the output terminal OUT. Note that in the semiconductor device 100, the gate electrode 374 and the source electrode 372 of the first transistor 370 and the drain electrode 356 of the second transistor 350 may be electrically connected to the output terminal OUT, and the gate electrode 354 and the source electrode 352 of the second transistor 350 and the drain electrode 376 of the first transistor 370 may be electrically connected to the input terminal IN.

[0030] For example, when a surge or ESD greater than the voltage supplied to the cathode of the first rectifier circuit 306 (the drain electrode 376 of the first transistor 370) enters the input terminal IN of the semiconductor device 100, a current flows from the anode of the first rectifier circuit 306 (the gate electrode 374 and the source electrode 372 of the first transistor 370) to the cathode of the first rectifier circuit 306. For example, the impedance of a transistor, resistor, capacitor, or circuit including these electrically connected to the input terminal IN is greater than that of the semiconductor device 100. As a result, the surge or ESD that has entered the input terminal IN of the semiconductor device 100 is prevented from entering the transistor, resistor, capacitor, or circuit including these electrically connected to the input terminal IN. At this time, since the voltage supplied to the anode of the second rectifier circuit 304 (the gate electrode 354 and source electrode 352 of the second transistor 350) is smaller than the voltage of the surge or ESD that has entered the input terminal IN, no current flows from the anode of the second rectifier circuit 304 to the cathode of the second rectifier circuit 304 (the drain electrode 356 of the second transistor 350).

[0031] For example, when a surge or ESD smaller than the voltage supplied to the anode of the second rectifier circuit 304 (the gate electrode 354 and the source electrode 352 of the second transistor 350) enters the input terminal IN of the semiconductor device 100, a current flows from the anode of the second rectifier circuit 304 to the cathode of the second rectifier circuit 304 (the drain electrode 356 of the second transistor 350). For example, the impedance of a transistor, resistor, capacitor, or circuit including these electrically connected to the input terminal IN is larger than that of the semiconductor device 100. As a result, the surge or ESD that has entered the input terminal IN of the semiconductor device 100 is prevented from entering the transistor, resistor, capacitor, or circuit including these electrically connected to the input terminal IN. At this time, since the voltage supplied to the anode of the first rectifier circuit 306 (the gate electrode 374 and the source electrode 372 of the first transistor 370) is smaller than the voltage supplied to the cathode of the first rectifier circuit 306 (the drain electrode 376 of the first transistor 370), no current flows from the anode of the first rectifier circuit 306 to the cathode of the first rectifier circuit 306.

[0032] Therefore, by using the semiconductor device 100, it is possible to prevent electrostatic breakdown of a transistor, a resistor, a capacitor, or a circuit including any of them electrically connected to the input terminal IN.

[0033] <1-2. Configuration of the display device 20 including the semiconductor device 100> Fig. 3 is a plan view showing the configuration of a display device 20 according to one embodiment of the present invention. Fig. 4 is a circuit diagram showing the configuration of a protection circuit 200 and a pixel circuit 400 including a semiconductor device 100 according to one embodiment of the present invention. Fig. 5 is an end cross-sectional view showing the configuration of a protection circuit 200 and a pixel circuit 400 including a semiconductor device 100 according to one embodiment of the present invention. The configuration of the display device 20 is not limited to the configuration shown in Figs. 3 to 5. In the configurations shown in Figs. 3 to 5, descriptions of configurations that are the same as or similar to those in Figs. 1 and 2 may be omitted.

[0034] 3, the display device 20 includes, for example, a plurality of protection circuits 200A, 200B, 200C, 200D, 200E, and 200F, a display unit 204 formed on an insulating surface, a peripheral unit 206, a data line driving circuit 207, a scanning line driving circuit 208, a driver IC 212, a terminal unit in which a plurality of terminals 214 are arranged, a flexible printed circuit board 216, and a sealing unit 222. The display device 20 according to this embodiment is, for example, a liquid crystal display device using a liquid crystal element 480. The display device 20 according to this embodiment may be a display device using an electrophoretic layer or a display device using an EL element, which is a light-emitting element.

[0035] The peripheral portion 206 surrounds the periphery of the display portion 204. The peripheral portion 206 includes a plurality of protection circuits 200, the display portion 204 formed on an insulating surface, the peripheral portion 206, a data line driving circuit 207, a scanning line driving circuit 208, a driver IC 212, a terminal portion in which a plurality of terminals 214 are arranged, a flexible printed circuit board 216, and a sealing portion 222. The array substrate 30 and the counter substrate 40 are bonded together by the sealing portion 222. Although details will be described later, the plurality of protection circuits 200A, 200B, 200C, 200D, 200E, and 200F comprise the semiconductor device 100.

[0036] The driver IC 212 is arranged on the flexible printed circuit board 216 using a COF (Chip on Film) method, but the arrangement of the driver IC 212 is not limited to the example shown here. The driver IC 212 may be provided on the first substrate 102. The flexible printed circuit board 216 is electrically connected to a terminal section in which a plurality of terminals 214 provided in the peripheral section 206 are arranged.

[0037] A plurality of protection circuits 200A are arranged between the scanning line driving circuit 208 and a plurality of scanning lines 218, and input terminals IN(I) of the plurality of protection circuits 200A are electrically connected between the scanning line driving circuit 208 and the plurality of scanning lines 218. Output terminals OUT(O) of the plurality of protection circuits 200A are electrically connected to wiring 243. The wiring 243 is electrically connected to the terminal 214. The scanning line driving circuit 208 is connected to the plurality of protection circuits 200A using a plurality of wirings 238. The plurality of protection circuits 200A are electrically connected to the plurality of scanning lines 218 in a one-to-one relationship.

[0038] The ends of the multiple scanning lines 218 opposite to the ends where the multiple protection circuits 200A are arranged are electrically connected to the input terminals IN(I) of the multiple protection circuits 200B in a one-to-one relationship. The output terminals OUT(O) of the multiple protection circuits 200B are electrically connected to wiring 242. The wiring 242 is electrically connected to the terminal 214. The multiple scanning lines 218 are arranged to extend parallel or approximately parallel to the X-axis of the display device 20.

[0039] The plurality of protection circuits 200D are disposed between the data line driving circuit 207 and the plurality of data lines 220, and input terminals IN(I) of the plurality of protection circuits 200D are electrically connected between the data line driving circuit 207 and the plurality of data lines 220. Output terminals OUT(O) of the plurality of protection circuits 200D are electrically connected to wiring 244. The wiring 244 is electrically connected to the terminal 214. The data line driving circuit 207 is connected to the plurality of protection circuits 200D using a plurality of wirings 236. The plurality of protection circuits 200D are electrically connected to the plurality of data lines 220 in a one-to-one relationship.

[0040] The ends of the multiple data lines 220 opposite to the ends where the multiple protection circuits 200D are arranged are electrically connected to the input terminals IN(I) of the multiple protection circuits 200C in a one-to-one relationship. The output terminals OUT(O) of the multiple protection circuits 200D are electrically connected to wiring 241. The wiring 241 is electrically connected to the terminal 214. The multiple data lines 220 are arranged to extend parallel or approximately parallel to the Y axis of the display device 20.

[0041] In this embodiment, for example, the plane including the X-axis and Y-axis (XY plane) may be the D1-D2 plane, the X-axis may be the D1 axis, and the Y-axis may be the D2 axis. Also, an axis perpendicular or approximately perpendicular to the XY plane may be the third axis D3.

[0042] The plurality of protection circuits 200E are disposed between the plurality of terminals 214 and the data line driving circuit 207, and input terminals IN(I) of the plurality of protection circuits 200E are electrically connected between the plurality of terminals 214 and the data line driving circuit 207. Output terminals OUT(O) of the plurality of protection circuits 200E are electrically connected to wiring 245. The wiring 245 is electrically connected to the terminals 214. The data line driving circuit 207 is electrically connected to the plurality of protection circuits 200E in a 1:1 ratio using a plurality of wirings 234. Each of the plurality of terminals 214 is electrically connected to the plurality of protection circuits 200E in a 1:1 ratio using a plurality of wirings 230 and a plurality of wirings 232. The plurality of wirings 230 and the plurality of wirings 232 may be electrically connected in a 1:1 ratio, and the plurality of wirings 230 may be the plurality of wirings 232.

[0043] The plurality of protection circuits 200F are disposed between the plurality of terminals 214 and the scanning line driving circuit 208, and input terminals IN (input terminals I) of the plurality of protection circuits 200F are electrically connected between the plurality of terminals 214 and the scanning line driving circuit 208. Output terminals OUT (output terminals O) of the plurality of protection circuits 200F are electrically connected to wiring 245. The wiring 245 is electrically connected to the terminals 214. Each of the plurality of terminals 214 electrically connected to the scanning line driving circuit 208 is electrically connected to the plurality of protection circuits 200F in a 1:1 relationship using the plurality of wirings 230 and the plurality of wirings 232. In the present embodiment, an example in which one plurality of protection circuits 200F is provided is shown as an example.

[0044] For example, the output terminals OUT(O) and wiring 243 of the multiple protection circuits 200A are supplied with the common voltage VCOM (FIG. 4) from the terminal 214. The output terminals OUT(O) and wiring 242 of the multiple protection circuits 200B are supplied with the common voltage VCOM (FIG. 4) from the terminal 214. The output terminals OUT(O) and wiring 241 of the multiple protection circuits 200C are supplied with the common voltage VCOM (FIG. 4) from the terminal 214. The output terminals OUT(O) and wiring 244 of the multiple protection circuits 200D are supplied with the common voltage VCOM (FIG. 4) from the terminal 214. The output terminals OUT(O) of the multiple protection circuits 200E and the output terminals OUT(O) and wiring 245 of the multiple protection circuits 200F are supplied with the common voltage VCOM (FIG. 4) from the terminal 214. In this embodiment, each of the multiple protection circuits 200A to 200E is supplied with the common voltage VCOM (FIG. 4) using a different wiring, but each of the multiple protection circuits 200A to 200E may be electrically connected to the same wiring (for example, wiring 241) and may be supplied with the common voltage VCOM (FIG. 4) from the same wiring.

[0045] The driver IC 212 is electrically connected to a plurality of terminals 214. The driver IC 212 functions as a control unit that supplies signals to the scanning line driving circuit 208 and the data line driving circuit 207. For example, the driver IC 212 may incorporate a circuit that includes the functions of the data line driving circuit 207 other than the sampling switch, the data line driving circuit 207 may include a sampling switch (not shown), or the driver IC 212 may incorporate the data line driving circuit 207. In this embodiment, the driver IC 212, parts of the scanning line driving circuit 208, and the data line driving circuit 207 may be referred to as control circuits, and the driver IC 212, the scanning line driving circuit 208, and the data line driving circuit 207 may be collectively referred to as control circuits.

[0046] In this embodiment, the insulating surface is the surface of the first substrate 102. The first substrate 102 supports each layer constituting a transistor, a liquid crystal element, and the like, which are provided on the surface of the first substrate 102. The first substrate 102 itself may be made of an insulating material, and the surface of the first substrate 102 itself may be the insulating surface, or the surface of an insulating film separately formed on the first substrate 102 may be the insulating surface. As long as an insulating surface can be obtained, the material of the first substrate 102 and the material forming the insulating film are not particularly limited.

[0047] A plurality of pixels 210 are arranged in a matrix in the display unit 204, parallel or substantially parallel to the X-axis and Y-axis. Each of the plurality of pixels 210 has a pixel circuit 400 (FIG. 4).

[0048] The plurality of pixels 210 are arranged, for example, in a stripe array. Each of the plurality of pixels 210 may correspond to, for example, sub-pixel R, sub-pixel G, or sub-pixel B. Three sub-pixels may form one pixel. Each sub-pixel is provided with a display element and a pixel circuit 400. The display element is, for example, a liquid crystal element 480. The color corresponding to the sub-pixel is determined by the characteristics of the liquid crystal element 480 or a color filter (not shown) provided on the sub-pixel.

[0049] In the stripe arrangement, the subpixels R, G, and B can be configured to provide different colors from one another. For example, the subpixels R, G, and B may be provided with color filter layers that emit the three primary colors of red, green, and blue, respectively.

[0050] Each of the plurality of pixels 210 is electrically connected to a corresponding scan line 218 and a corresponding data line 220. The plurality of pixels 210 may also be electrically connected to a power supply line that supplies power. As will be described in detail later, the elements that make up the pixel circuit 400 may be any elements that have a current control function.

[0051] For example, the driver IC 212 outputs a scan signal to the scan line 218 via the scan line drive circuit 208. The driver IC 212 outputs a data signal corresponding to image data (image data) to be displayed on the display unit 204 to the data line 220. The driver IC 212 also supplies voltages to the scan line drive circuit 208, the pixel circuit 400, and the power supply line. When the driver IC 212 inputs a voltage, a scan signal, and a data signal to the pixel circuits included in the plurality of pixels 210, the transistor 420 (FIG. 4) included in the pixel circuit 400 can use the voltage, scan signal, and data signal to supply a voltage corresponding to the image data to the pixel electrode 490A of the liquid crystal element 480. As a result, each of the plurality of pixels 210 can display a color and an image corresponding to the data signal. In this embodiment, the scan line 218 and the data line 220 may be referred to as a signal line.

[0052] In this embodiment, a plurality of protection circuits 200 including the semiconductor device 100 are arranged between each circuit and each signal line, between the terminal 214 and each circuit, etc. By using the protection circuit 200 including the semiconductor device 100, surges or ESD that enter the terminal 214, each circuit, or each signal line are mitigated, and electrostatic discharge (ESD) damage to the terminal 214, each circuit, or each signal line is suppressed. Furthermore, by using the configuration of the semiconductor device 100 for the protection circuit 200, the area in which the protection circuit 200 is formed can be reduced. Furthermore, by applying the protection circuit 200 using the semiconductor device 100 to a high-definition display device with an increased number of signal lines and a display device with a narrow frame, it is possible to sufficiently suppress electrostatic discharge damage while suppressing an increase in the frame width (periphery 206).

[0053] In the present embodiment, an example is shown in which a plurality of protection circuits 200 including the semiconductor device 100 are arranged between a circuit and each signal line, between the terminal 214 and each circuit, etc., but the arrangement of the plurality of protection circuits 200 including the semiconductor device 100 is not limited to the arrangement described here. For example, in the display device 20, the protection circuit 200 including the semiconductor device 100 may be arranged only between the scanning line driving circuit 208 and the plurality of scanning lines 218, or may be arranged in two locations: between the scanning line driving circuit 208 and the plurality of scanning lines 218 and between the data line driving circuit 207 and the plurality of data lines 220. The protection circuit 200 including the semiconductor device 100 may be arranged in three locations: between the scanning line driving circuit 208 and the plurality of scanning lines 218, between the data line driving circuit 207 and the plurality of data lines 220, and between the plurality of terminals 214 and each wiring, or may be arranged in four or more locations. The arrangement of the plurality of protection circuits 200 including the semiconductor device 100 may be appropriately determined depending on the application, specifications, etc. of the display device 20.

[0054] FIG. 4 is a diagram showing an example in which the protection circuit 200A is arranged between the scanning line driving circuit 208 and the scanning line 218 in the display device 20 shown in FIG. 3 and is electrically connected to the pixel circuit 400 that constitutes the pixel 210.

[0055] 4 shows, as an example, a protection circuit 200A including one semiconductor device 100. An input terminal I (FIG. 3) of the protection circuit 200A is electrically connected to a scanning line 218 and an input terminal IN of the semiconductor device 100, and an output terminal O (FIG. 3) of the protection circuit 200A is electrically connected to an output terminal OUT of the semiconductor device 100. The output terminal O of the protection circuit 200A is electrically connected to a wiring 243 (FIG. 3) and is supplied with a common voltage VCOM from a terminal 214. The configuration of the semiconductor device 100 is the same as that shown in FIGS. 1 and 2, and therefore a description thereof will be omitted here.

[0056] The protection circuit 200A may have a plurality of semiconductor devices 100 connected in series. By using a plurality of semiconductor devices 100, the resistance value between the scanning line 180 and the wiring 243 can be further increased. Therefore, by using the protection circuit 200 including the semiconductor device 100, electrostatic breakdown of the pixel circuit 400 is suppressed, and leakage current to the wiring 243 is also suppressed.

[0057] The pixel circuit 400 includes, for example, a transistor 420, a liquid crystal element 480, and a capacitor 490. The transistor 420 includes a gate electrode 410, a source electrode 430, and a drain electrode 440. The gate electrode 410 is electrically connected to a scan line 218. The source electrode 430 is electrically connected to a data line 220. The drain electrode 440 is electrically connected to a pixel electrode 490A. The liquid crystal element 480 and the capacitor 490 are electrically connected between the pixel electrode 490A and a common electrode 490B. The common electrode 490B is electrically connected to the terminal 214 using, for example, a wiring 246, and is supplied with a common voltage VCOM.

[0058] Fig. 5 is an end cross-sectional view of a portion of a pixel circuit 400 and a protection circuit 200A including the semiconductor device 100 shown in Fig. 4. The display device 20 has the semiconductor device 100 and the pixel circuit 400, each including a semiconductor film 112 formed using the same material on the same substrate.

[0059] 1B, the configuration of the semiconductor device 100 is similar to that shown in FIG. 1B, and therefore a description thereof will be omitted. Here, the configuration of the pixel circuit 400 and the layers or films disposed above the second gate electrode layer 116 of the semiconductor device 100 will be mainly described.

[0060] The first transistor 370 is a bottom-gate transistor containing a metal oxide as a material forming the semiconductor film 112. The second transistor 350 is a top-gate transistor containing a metal oxide as a material forming the semiconductor film 112. The transistor 420 included in the pixel circuit 400 is a bottom-gate transistor containing a metal oxide as a material forming the semiconductor film 112B. The transistors described here may be used in, for example, the data line driver circuit 207 or the scan line driver circuit 208.

[0061] The material forming the semiconductor film 112 may contain, for example, a Group 14 element such as silicon or germanium, or may contain a metal oxide. Examples of materials containing silicon include amorphous silicon and polycrystalline silicon. The metal oxide may contain a Group 13 element such as indium or gallium, for example, a mixed oxide of indium and gallium (IGO) or a mixed oxide containing indium, gallium, and zinc (IGZO). The metal oxide may also contain tin, titanium, zirconium, or the like. In this embodiment, the metal oxide is referred to as an oxide semiconductor.

[0062] The transistor 420 is a transistor formed on the first substrate 102. A gate electrode 410 is disposed on the first substrate 102. The gate electrode 410 is electrically connected to the gate electrode 374 and the scanning line 218, and is formed using the first gate electrode layer 104. A plurality of insulating layers may be disposed as base layers between the first substrate 102 and the first gate electrode layer 104. A semiconductor film 112B is disposed above the gate electrode 410. The gate electrode 410 faces the semiconductor film 112B. The semiconductor film 112B is disposed in the same layer as the semiconductor film 112. A first gate insulating film 106 is disposed between the gate electrode 410 and the semiconductor film 112B. The gate insulating film in the transistor 420 is the first gate insulating film 106. A first terminal 109 functioning as a source electrode 430 is disposed at one end of the pattern of the semiconductor film 112B, and a second terminal 111 functioning as a drain electrode 440 is disposed at the other end of the pattern of the semiconductor film 112B. The source electrode 430 and the drain electrode 440 are electrically connected to the semiconductor film 112B on the upper surface and side surface thereof, respectively. The first terminal 109 and the second terminal 111 are disposed in the same layer as the first terminal 108 and the second terminal 110. A second gate insulating film 114 is disposed so as to be in contact with parts of the upper surface and side surface of the semiconductor film 112B, parts of the upper surface and side surface of the first terminal 109, and parts of the upper surface and side surface of the second terminal 111.

[0063] An insulating film 316 is disposed on and in contact with the gate electrode 354 disposed on the second gate electrode layer 116 and the second gate insulating film 114. An insulating film 128 is disposed on and in contact with the gate electrode 354 disposed on the second gate electrode layer 116 and the second gate insulating film 114. The insulating film 128 is disposed on the insulating film 316. A contact hole 126 is formed in the insulating film 316 and the insulating film 128. A pixel electrode 490A is disposed on the insulating film 128 and inside the contact hole 126 using a pixel electrode layer 130. The pixel electrode 490A is electrically connected to the second terminal 111, which functions as the drain electrode 440. A first alignment film 132 is disposed on the pixel electrode layer 130. In this embodiment, for example, a portion including the first substrate 102 to the first alignment film 132 parallel to the third axis D3 is referred to as an array substrate 30.

[0064] In a cross-sectional view, the counter electrode layer 138 is disposed on the surface of the second substrate 140 on which the first substrate 102 is disposed, and the second alignment film 136 is disposed on the surface of the counter electrode layer 138 on which the first substrate 102 is disposed. In this embodiment, for example, a portion that is parallel to the third axis D3 and includes the second substrate 140, the counter electrode layer 138, and the second alignment film 136 is called the counter substrate 40.

[0065] In the display device 20, the first alignment film 132 of the array substrate 30 and the first alignment film 132 of the array substrate 30 are bonded together at the sealing portion 222 (Figure 3) so that they face each other, and a liquid crystal layer 134 including a liquid crystal element included in the liquid crystal element 480 is injected between the first alignment film 132 of the array substrate 30 and the first alignment film 132 of the array substrate 30.

[0066] When a voltage is supplied between the pixel electrode 490A and the counter electrode layer 138, an electric field is formed between the pixel electrode 490A and the counter electrode layer 138. This electric field causes the liquid crystal elements included in the liquid crystal element 480 to operate, thereby displaying a color and an image according to the data signal supplied to the pixel circuit 400.

[0067] TFTs using metal oxides as the material for forming the semiconductor film have extremely low leakage currents, and are used as switching elements in pixel circuits of display devices. As a result, the charge stored in the capacitive element included in the pixel circuit can be retained for a long time, allowing a desired voltage to be maintained for a long time. However, because the leakage current of the TFT is extremely low, surges or ESD that penetrate terminal 214, each circuit, or each signal line are difficult to remove, which can result in electrostatic damage to the TFT. While protection circuits (e.g., protection diodes) are available to protect against surges or ESD, there is a risk that the circuit scale and size would be too large to achieve the desired operation.

[0068] The display device 20 according to this embodiment includes a protection circuit 200 having a TFT using a metal oxide as a material for forming a semiconductor film, and the first rectifier circuit 306 is disposed (stacked) on the second rectifier circuit 304, thereby reducing the transistor size and circuit scale of the semiconductor device 100. Furthermore, by using the semiconductor device 100 according to this embodiment, it is possible to mitigate surges or ESD that enter the terminals 214, the circuits, or the signal lines, and to suppress electrostatic breakdown of the terminals 214, the circuits, or the signal lines.

[0069] The structures of the transistors, capacitors, resistors, and the like, as well as the films, layers, and materials of each part forming the transistors, capacitors, resistors, and the like, may be those known in the art. For example, the common electrode 490B shown in FIG. 4 may be the counter electrode layer 138 shown in FIG. 5. Furthermore, the common electrode 490B shown in FIG. 4 is not limited to the counter electrode layer 138 shown in FIG. 5. Alternatively, the common electrode 490B may be provided between the insulating film 128 and the insulating film 316, forming a capacitor element 490 between the pixel electrode 490A and the common electrode 490B and driving the liquid crystal element 480 (liquid crystal layer 134) by a lateral electric field. Furthermore, in the transistor 420, a second gate electrode may be provided between the insulating film 316 and the second gate insulating film 114 so as to overlap with the semiconductor film 112B formed using a metal oxide, and two gate electrodes may be provided so that the semiconductor film 112B is sandwiched between the gate electrode 410 and the second gate electrode.

[0070] Second Embodiment In the second embodiment, the configuration of a semiconductor device 100B will be described. In the semiconductor device 100B according to the second embodiment, a resistive element is added to the semiconductor device 100 according to the first embodiment. In all other respects, the semiconductor device 100B according to the second embodiment is similar to the semiconductor device 100 according to the first embodiment. Here, differences from the semiconductor device 100 will be mainly described.

[0071] FIG. 6(A) is a plan view showing the configuration of the semiconductor device 100B, and FIG. 6(B) is an end cross-sectional view showing a part of the cross section of the semiconductor device 100B shown in FIG. 6(A) taken along line B1-B2. FIGS. 7(A) and 7(B) are circuit diagrams showing the circuit configuration of the semiconductor device 100B. The configuration of the semiconductor device 100B is not limited to the configurations shown in FIGS. 6(A), 6(B), 7(A), and 7(B). In the configurations shown in FIGS. 6(A), 6(B), 7(A), and 7(B), descriptions of configurations that are the same as or similar to those in FIGS. 1 to 5 may be omitted.

[0072] In the semiconductor device 100B shown in Figures 6(A), 6(B), 7(A), and 7(B), the first rectifier circuit 306B, the first transistor 370B, the gate electrode 374B, the source electrode 372B, the drain electrode 376B, the second rectifier circuit 304B, the second transistor 350B, the gate electrode 354B, the source electrode 352B, and the drain electrode 356B correspond to the first rectifier circuit 306, the first transistor 370, the gate electrode 374, the source electrode 372, the drain electrode 376, the second rectifier circuit 304, the second transistor 350, the gate electrode 354, the source electrode 352, and the drain electrode 356, respectively, of the semiconductor device 100 in the first embodiment.

[0073] As shown in FIGS. 6A, 6B, 7A, and 7B, in a plan view or cross-sectional view of the first rectifier circuit 306B (first transistor 370), the arrangement of the gate electrode 374B, the first gate insulating film 106, the semiconductor film 112, the first terminal 108, the second terminal 110, the second gate insulating film 114, and the gate electrode 354B defines a first region 120B in the semiconductor film 112, sandwiched between the first terminal 108 electrically connected to the source electrode 372B and the gate electrode 374B. In the semiconductor device 100B, the first region 120B functions as an active region (channel region) of the first transistor 370B. The length of the first region 120B parallel to the first axis D1 is length L2. The length L2 of the first region 120B may be longer or shorter than the length L1 of the first region 120A shown in FIG.

[0074] The first region 120B is sandwiched between the first terminal 108 and the second terminal 110, and is provided closer to the first terminal 108 than the second region 120C. The first region 120B is a region provided between the second region 120C and the first terminal 108, where the semiconductor film 112 and the gate electrode 374B overlap.

[0075] Furthermore, a second region 120C can be defined in the semiconductor film 112, sandwiched between the gate electrode 374B and the second terminal 110 electrically connected to the drain electrode 376B. The length of the second region 120C parallel to the first axis D1 is length L3. The length L3 of the second region 120C is shorter than the length L2 of the first region 120B and the length L1 of the first region 120A.

[0076] The second region 120C is sandwiched between the first terminal 108 and the second terminal 110 and is located closer to the second terminal 110 than the first region 120B. The second region 120C is located between the first region 120B of the first transistor 370B and the second terminal 110, and serves as a first resistance region where the semiconductor film 112 and the gate electrode 374B do not overlap. The first resistance region functions as a resistance element 380B. The resistance value of the resistance element 380B is greater than the resistance value of the first region 120B of the first transistor 370B.

[0077] In a plan view or cross-sectional view of the second rectifier circuit 304B (second transistor 350B), the arrangement of the gate electrode 374B, the first gate insulating film 106, the semiconductor film 112, the first terminal 108, the second terminal 110, the second gate insulating film 114, and the gate electrode 354B defines a third region 120D in the semiconductor film 112, sandwiched between the second terminal 110 electrically connected to the source electrode 352B and the gate electrode 354B. In the semiconductor device 100B, the third region 120D functions as the active region (channel region) of the second transistor 350B. The length of the third region 120D parallel to the first axis D1 is a length L4. The length L4 of the third region 120D is different from the length L1 of the first region 120A, and may be longer or shorter than the length L1. The length L4 is equal to or approximately equal to the length L2 of the first region 120B.

[0078] The third region 120D is sandwiched between the first terminal 108 and the second terminal 110, and is provided closer to the second terminal 110 than the fourth region 120E. The third region 120D is a region provided between the fourth region 120E and the second terminal 110, and is a region where the semiconductor film 112 and the gate electrode 354B overlap. In plan view and cross-sectional view, the third region 120D overlaps with a part of the first region 120B and the second region 120C, and the position of the third region 120D in the longitudinal direction parallel to the first axis D1 differs from the position of the first region 120B in the longitudinal direction parallel to the first axis D1.

[0079] Furthermore, a fourth region 120E can be defined in the semiconductor film 112, sandwiched between the gate electrode 354B and the first terminal 108 electrically connected to the drain electrode 356B. The length of the fourth region 120E parallel to the first axis D1 is length L5. The length L5 of the fourth region 120E is shorter than the length L4 of the third region 120D, the length L2 of the first region 120B, and the length L1 of the first region 120A, and is equal to or approximately equal to the length L3 of the third region 120D.

[0080] The fourth region 120E is sandwiched between the first terminal 108 and the second terminal 110, and is provided closer to the first terminal 108 than the third region 120D. The fourth region 120E is a region provided between the third region 120D of the second transistor 350B and the first terminal 108, and is a second resistance region where the semiconductor film 112 and the gate electrode 354B do not overlap. The second resistance region functions as a resistance element 360B. The resistance value of the resistance element 360B is greater than the resistance value of the third region 120D of the second transistor 350B.

[0081] In the second embodiment, the second region 120C and the third region 120D are provided, so the resistance values ​​of the first transistor 370B and the second transistor 350B can be made larger than the resistance values ​​of the first transistor 370 and the second transistor 350 according to the first embodiment. Therefore, for example, when the resistance values ​​of the first transistor 370B and the second transistor 350B are made the same or substantially the same as the resistance values ​​of the first transistor 370 and the second transistor 350 according to the first embodiment, the lengths L2 and L4 can be made shorter than the length L1 according to the first embodiment. Therefore, the layout of the first transistor 370B and the second transistor 350B can be made smaller than the layout of the first transistor 370 and the second transistor 350 according to the first embodiment. As a result, the size of the semiconductor device 100B can be reduced, and the frame width (periphery 206) can be reduced, thereby realizing a display device with a narrow frame. Furthermore, for example, when multiple semiconductor devices 100B are connected in series, the resistance values ​​of the first transistor 370B and the second transistor 350B per unit length can be increased by making the lengths L2 and L4 longer than the length L1 in the first embodiment. Therefore, the number of semiconductor devices 100B connected in series can be reduced, thereby reducing the overall footprint of the semiconductor device 100B. As a result, the frame width (peripheral portion 206) can be reduced, resulting in a display device with a narrow frame. Furthermore, similar to the semiconductor device 100, the use of the semiconductor device 100B can suppress electrostatic breakdown of transistors, resistors, capacitors, or circuits including them electrically connected to the input terminal IN. Furthermore, the use of the semiconductor device 100B provides a first resistance region and a second resistance region between the input terminal IN and the output terminal OUT, further increasing the resistance value between the input terminal IN and the output terminal OUT. As a result, for example, leakage current to wiring, elements, or circuits arranged at the output terminal OUT can be further suppressed.

[0082] Third Embodiment 8 is an end cross-sectional view showing the configuration of a protection circuit 200 including a semiconductor device 100 and a pixel circuit 400 of a display device 20B according to one embodiment of the present invention. In the configuration shown in FIG. 8, descriptions of configurations that are the same as or similar to those in FIGS. 1 to 7 may be omitted.

[0083] The display device 20B shown in Fig. 8 is a display device having a pixel circuit 400 and a protection circuit 200A including a semiconductor device 100, which have different structures, on the same substrate. The structure of the pixel circuit 400 is different from that of the semiconductor device 100. The protection circuit 200A including the pixel circuit 400 and the semiconductor device 100 has the same structure as in the first embodiment, so a detailed description thereof will be omitted here. Here, the structure different from the first embodiment will mainly be described.

[0084] In the display device 20B, the first transistor 370 included in the semiconductor device 100 is a bottom-gate transistor containing polycrystalline silicon as the material for forming the semiconductor film 112, the second transistor 350 included in the semiconductor device 100 is a top-gate transistor containing polycrystalline silicon as the material for forming the semiconductor film 112, and the transistor 420 included in the pixel circuit 400 is a bottom-gate transistor containing metal oxide as the material for forming the semiconductor film 112B. The transistors described here may be used in, for example, the data line driver circuit 207 or the scanning line driver circuit 208.

[0085] The first transistor 370 and the second transistor 350 are transistors stacked in this order on the first substrate 102 with respect to the third axis D3, and constitute the semiconductor device 100. The gate electrode 374 is formed using a first gate electrode layer 104 arranged to be in contact with the upper surface of the first substrate 102. The first gate insulating film 106 is arranged to be in contact with the upper surface of the first substrate 102 and the first gate electrode layer 104, and to cover the upper surface and side surfaces of the gate electrode 374. Multiple insulating layers may be arranged as base layers between the first substrate 102 and the first gate electrode layer 104. The semiconductor film 112 is arranged to be in contact with the upper surface of the first gate insulating film 106 and to overlap with the gate electrode 374. The second gate insulating film 114 is arranged to be in contact with the upper surface and part of the side surfaces of the semiconductor film 112. The gate electrode 354 is formed using a second gate electrode layer 116 arranged to be in contact with the upper surface of the second gate insulating film 114. Furthermore, the gate electrode 354 is formed to overlap the semiconductor film 112. An insulating film 310 is disposed on the gate electrode 354 so as to be in contact with a portion of the upper surface and side surfaces of the gate electrode 354 and the upper surface of the second gate insulating film 114. An insulating film 312 is disposed on the insulating film 310 so as to be in contact with the upper surface of the insulating film 310. An insulating film 314 is disposed on the insulating film 312 so as to be in contact with the upper surface of the insulating film 312. A contact hole 121 is formed penetrating the first gate insulating film 106, the second gate insulating film 114, the insulating film 310, the insulating film 312, and the insulating film 314. Contact holes 121B and 122 are formed penetrating the second gate insulating film 114, the insulating film 310, the insulating film 312, and the insulating film 314. A contact hole 122B is formed penetrating the insulating film 310, the insulating film 312, and the insulating film 314. The first terminal 108 is disposed so as to be in contact with the upper surface of the insulating film 314, and is electrically connected to the gate electrode 374 through the contact hole 121, and is electrically connected to the semiconductor film 112 through the contact hole 121B. The portion of the first terminal 108 that is electrically connected to the semiconductor film 112 through the contact hole 121B is the source electrode 372, and the portion that is electrically connected to the gate electrode 374 through the contact hole 121 is the drain electrode 356.The second terminal 110 is disposed so as to be in contact with the upper surface of the insulating film 314, and is electrically connected to the gate electrode 354 via the contact hole 122B, and is electrically connected to the semiconductor film 112 via the contact hole 122B. The portion of the second terminal 110 electrically connected to the semiconductor film 112 via the contact hole 122B is the drain electrode 376, and the portion electrically connected to the gate electrode 354 via the contact hole 122B is the source electrode 352.

[0086] The transistor 420 is a transistor formed on the first substrate 102. A gate electrode 410 is disposed on an insulating film 310. The gate electrode 410 is electrically connected to the gate electrode 374, the source electrode 372, the drain electrode 356, and the scanning line 218. The gate electrode 410 may be formed of the same material as the first gate electrode layer 104, or may be formed of a material different from that of the first gate electrode layer 104. A semiconductor film 112B is disposed above the gate electrode 410. The gate electrode 410 faces the semiconductor film 112B. An insulating film 312 is disposed between the gate electrode 410 and the semiconductor film 112B. The insulating film 312 serves as the gate insulating film in the transistor 420. A first terminal 109 functioning as a source electrode 430 is disposed at one end of the pattern of the semiconductor film 112B, and a second terminal 111 functioning as a drain electrode 440 is disposed at the other end of the pattern of the semiconductor film 112B. The source electrode 430 and the drain electrode 440 are electrically connected to the semiconductor film 112B on the upper surface and side surface thereof, respectively. An insulating film 314 is disposed so as to be in contact with parts of the upper surface and side surface of the semiconductor film 112B, parts of the upper surface and side surface of the first terminal 109, and parts of the upper surface and side surface of the second terminal 111. Contact holes 311 and 313 are formed in the insulating film 314. The first terminal 109B is disposed on the insulating film 314 and is electrically connected to the first terminal 109 through the contact hole 311. The second terminal 111B is disposed on the insulating film 314 and is electrically connected to the second terminal 111 through the contact hole 313. The first terminal 109B and the second terminal 111B are disposed in the same layer as the first terminal 108 and the second terminal 110.

[0087] An insulating film 316 is disposed on the first terminal 109B, the second terminal 111B, the first terminal 108, and the second terminal 110. The configuration above the insulating film 316 with respect to the third axis D3 is similar to the configuration shown in FIG. 5, and therefore a detailed description thereof will be omitted here.

[0088] In the display device 20B according to the third embodiment, the pixel electrode 490A is electrically connected to the second terminal 111B through the contact hole 126. In addition, in the display device 20B according to the third embodiment, for example, a portion including the first substrate 102 to the first alignment film 132 parallel to the third axis D3 is called an array substrate 30B, and a portion including the second substrate 140, the counter electrode layer 138, and the second alignment film 136 is called a counter substrate 40B.

[0089] Similar to the case where the semiconductor device 100 includes a metal oxide as the material for forming the semiconductor film 112, the case where the semiconductor device 100 includes polycrystalline silicon as the material for forming the semiconductor film 112 also makes it possible to mitigate surges or ESD that enter the terminal 214, each circuit, or each signal line, and to suppress electrostatic breakdown of the terminal 214, each circuit, or each signal line.

[0090] <Fourth embodiment> Fig. 9 is a plan view showing the configuration of a semiconductor integrated circuit 500 according to one embodiment of the present invention. In the configuration shown in Fig. 9, the description of the same or similar configuration as in Figs. 1 to 8 may be omitted.

[0091] The semiconductor integrated circuit 500 has at least a semiconductor device 100, a plurality of wirings 502, a wiring 504, and an electronic device 506. Input terminals IN(I) of the plurality of semiconductor devices 100 are electrically connected between the electronic device 506 and terminals T1 to T3 electrically connected to the plurality of wirings 502, respectively. An output terminal OUT(O) of the plurality of semiconductor devices 100 is electrically connected to a terminal T4 connected to the wiring 504. The semiconductor device 100 has the same configuration and function as the semiconductor device 100, semiconductor device 100B, semiconductor device 100, or protection circuit 200 including the semiconductor device 100 described in any of the first to third embodiments. The configuration and function of the semiconductor device 100 have been described in the first to third embodiments, so a description thereof will be omitted here.

[0092] For example, signals for controlling the electronic device 506 are supplied to the terminals T1 to T3. The signals include voltages. For example, a constant voltage is supplied to the terminal T4. The constant voltage is, for example, a ground voltage, 0V, or VSS.

[0093] The electronic device 506 is, for example, an analog circuit, a memory circuit, an arithmetic circuit, or a device including any of them. The analog circuit is, for example, a backlight, a lighting device, an LED, a micro LED, or an amplifier circuit. The memory circuit is, for example, a volatile memory such as a DRAM or an SRAM, or a non-volatile memory. The arithmetic circuit is, for example, a CPU.

[0094] By using a semiconductor integrated circuit 500 including the semiconductor device 100, it is possible to mitigate surges or ESD that enter the electronic device 506 included in the semiconductor integrated circuit 500, and to suppress electrostatic damage to the electronic device 506.

[0095] The protection circuit 200 including the semiconductor device 100, the display device 20 including the protection circuit 200, the display device 20B, and the semiconductor integrated circuit 500 described above as embodiments of the present invention can be combined as appropriate to the extent that they are not mutually inconsistent. Furthermore, within the scope of the concept of the present invention, those skilled in the art will recognize that various modifications and alterations may occur, and these modifications and alterations also fall within the scope of the present invention. For example, those skilled in the art may appropriately add, delete, or change the design of components, or add, omit, or change the conditions of processes, as long as they comply with the gist of the present invention. These modifications and alterations are also within the scope of the present invention.

[0096] Furthermore, other effects and advantages brought about by the aspects in one embodiment of the present invention that are obvious from the description in this specification or that can be appropriately thought of by a person skilled in the art are naturally understood to be brought about by the present invention. [Explanation of symbols]

[0097] 10: display device, 20: display device, 20B: display device, 30: array substrate, 30B: array substrate, 40: counter substrate, 40B: counter substrate, 100: semiconductor device, 100B: semiconductor device, 102: first substrate, 104: first gate electrode layer, 106: first gate insulating film, 108: first terminal, 109: first terminal, 109B: first terminal, 110: second terminal, 111: second terminal, 111B: second terminal, 112: semiconductor film, 112B: semiconductor film, 114: second gate insulating film, 116: second gate electrode layer, 120A, 120B: first region, 120C: second region, 120D: third region, 120E: fourth region, 121: contact hole, 121B: contact hole, 122: contact hole, 122B: contact hole, 126: contact hole, 128: insulating film, 130: pixel electrode layer, 132: first alignment film, 134: liquid crystal layer, 136: second alignment film, 138: counter electrode layer, 140: second substrate, 180: scanning line, 200: protection circuit, 200A: protection circuit, 200B: protection circuit, 200C: protection circuit, 200D: protection circuit, 200E: protection circuit, 200F: protection circuit, 204: display unit, 20 6: peripheral portion, 207: data line driving circuit, 208: scanning line driving circuit, 210: pixel, 214: terminal, 216: flexible printed circuit board, 218: scanning line, 220: data line, 222: sealing portion, 230: wiring, 232: wiring, 234: wiring, 236: wiring, 238: wiring, 241: wiring, 242: wiring, 243: wiring, 244: wiring, 245: wiring, 246: wiring, 304: second rectifier circuit, 304B: second rectifier circuit, 306: first rectifier circuit, 306B: first rectifier circuit, 310: insulating film, 311: contact hole, 312: insulating film, 313: contact Contact hole, 314: insulating film, 316: insulating film, 350: second transistor, 350B: second transistor, 352: source electrode, 352B: source electrode, 354: gate electrode, 354B: gate electrode, 356: drain electrode, 356B: drain electrode, 360B: resistance element, 370: first transistor, 370B: first transistor, 372: source electrode, 372B: source electrode, 374: gate electrode, 374B: gate electrode, 376: drain electrode, 376B: drain electrode, 380B: resistance element, 400: pixel circuit, 410: gate electrode,420: transistor, 430: source electrode, 440: drain electrode, 480: liquid crystal element, 490: capacitance element, 490A: pixel electrode, 490B: common electrode, 500: semiconductor integrated circuit, 502: wiring, 504: wiring, 506: electronic device,

Claims

1. a first gate electrode; a first gate insulating film disposed on the first gate electrode; a semiconductor film disposed on the first gate insulating film and overlapping the first gate electrode; a first terminal in contact with the semiconductor film and electrically connected to the semiconductor film and the first gate electrode; a second terminal in contact with the semiconductor film and spaced apart from the first terminal; a second gate insulating film disposed on the semiconductor film, the first terminal, and the second terminal; a second gate electrode disposed on the second gate insulating film, overlapping the semiconductor film, and electrically connected to the second terminal; a first rectifier circuit; a second rectifier circuit; Equipped with one of the first rectifier circuit and the second rectifier circuit is a diode-connected first transistor, the other of the first rectifier circuit and the second rectifier circuit is a diode-connected second transistor; the first transistor includes the first gate electrode, the first gate insulating film, the semiconductor film, the first terminal, and the second terminal; the second transistor includes the second gate electrode, the second gate insulating film, the semiconductor film, the first terminal, and the second terminal; In plan view, the semiconductor film includes, between the first terminal and the second terminal, a channel region of the first transistor, a channel region of the second transistor, a first resistance region between the channel region of the first transistor and the second terminal and in which the first gate electrode does not overlap, and a second resistance region between the channel region of the second transistor and the first terminal and in which the second gate electrode does not overlap, the first gate insulating film and the first gate electrode overlap in a channel region of the first transistor; the second gate insulating film and the second gate electrode overlap in a channel region of the second transistor; Semiconductor device.

2. In the first rectifier circuit, the first terminal is a source electrode and the second terminal is a drain electrode; In the second rectifier circuit, the second terminal is a source electrode and the first terminal is a drain electrode. The semiconductor device according to claim 1 .

3. a position of the channel region of the first transistor is the same as a position of the channel region of the second transistor; The semiconductor device according to claim 1 .

4. a position of the channel region of the first transistor is different from a position of the channel region of the second transistor; The semiconductor device according to claim 1 .

5. the semiconductor film comprises amorphous silicon, polycrystalline silicon, or metal oxide; The semiconductor device according to claim 1 .

6. A semiconductor device according to any one of claims 1 to 5; a display unit including a plurality of pixels electrically connected to the plurality of semiconductor devices; a control circuit electrically connected to the plurality of pixels and controlling the plurality of pixels; having Display device.

7. the control circuit is electrically connected to the semiconductor device; The display device according to claim 6.

8. A semiconductor device according to any one of claims 1 to 5; an electronic device electrically connected to the semiconductor device; having Semiconductor integrated circuit.

Images