Interleave circuit and communication device

Abstract

To provide an interleaving circuit and a communication device that can suppress reduction in throughput and can be implemented with a practical circuit configuration.SOLUTION: An interleaving circuit includes a sorting circuit and an address calculation circuit. The sorting circuit inputs input data containing n bits (n is an integer greater than or equal to 2) in parallel every cycle, and rearranges n input data input in n cycles into n output data each containing n bits input in mutually different cycles. The address calculation circuit calculates a write address for writing n pieces of output data to a first storage device and a read address for reading n pieces of output data from the first storage device.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] FIELD OF THE INVENTION An embodiment of the present invention relates to an interleaving circuit and a communication device. [Background technology]

[0002] Error correction technology is essential for communications, including quantum key distribution (QKD), which uses photons. A technique called rate adaptation is effective for improving information transmission speeds and stabilizing error correction. However, the heterogeneity of error rates across a wide range of data and the occurrence of block errors increase the likelihood of error correction failure.

[0003] In order to ensure stable error correction and improve information transmission speed, it is effective to perform block interleaving, which rearranges the bit order within blocks divided by a predetermined number of bits. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent No. 4045017 [Patent Document 2] Patent No. 3549756 [Patent Document 3] Patent No. 3288262 [Non-patent literature]

[0005] [Non-Patent Document 1] AR Dixon and H. Sato, “High speed and adaptable error correction for megabit / s rate quantum key distribution”, Nature Scientific Reports, 2013. Summary of the Invention [Problem to be solved by the invention]

[0006] However, conventional techniques have had problems such as a decrease in throughput or difficulty in circuit implementation. The present invention aims to provide an interleave circuit and a communication device that can suppress the decrease in throughput and can be implemented with a practical circuit configuration. [Means for solving the problem]

[0007] The interleave circuit of the embodiment includes a rearrangement circuit and an address calculation circuit. The rearrangement circuit receives input data in parallel, each of which includes n bits (n is an integer equal to or greater than 2) per cycle, and rearranges the n input data input in the n cycles into n output data, each of which includes n bits input in different cycles. The address calculation circuit calculates write addresses for writing the n output data to a first storage device and read addresses for reading the n output data from the first storage device. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a block diagram of a communication device according to a first embodiment. [Figure 2] FIG. 2 is a block diagram of an interleave circuit according to the first embodiment. [Figure 3] FIG. 10 is a diagram showing an example of block interleaving processing. [Figure 4] 4 is a flowchart of an interleave circuit according to the first embodiment. [Figure 5] FIG. 10 is a diagram showing an example of the configuration of a rearrangement circuit. [Figure 6] FIG. 10 is a diagram showing an example of input data. [Figure 7] FIG. 10 is a diagram showing the state after four cycles have passed since the start of processing. [Figure 8] FIG. 10 is a diagram showing the state after five cycles have elapsed since the start of processing. [Figure 9] FIG. 10 is a diagram showing the state after six cycles have passed since the start of processing. [Figure 10] FIG. 10 is a diagram showing the state after seven cycles have passed since the start of processing. [Figure 11] 10A and 10B are diagrams showing examples of input data and output data after rearrangement. [Figure 12] FIG. 10 is a diagram showing the relationship between output order, addresses, and data. [Figure 13] FIG. 1 is a block diagram of a deinterleave circuit. [Figure 14] 10 is a flowchart of a deinterleave circuit. [Figure 15] FIG. 2 is a diagram showing an example of input data input to a deinterleave circuit. [Figure 16] FIG. 10 is a diagram showing an example of data written to a memory. [Figure 17] FIG. 10 is a block diagram of an interleave circuit according to a second embodiment. [Figure 18] 10 is a flowchart of an interleave circuit according to a second embodiment. [Figure 19] FIG. 10 is a diagram showing an example of rearrangement of n-bit data. [Figure 20] FIG. 10 is a diagram showing the relationship between output order, addresses, memory types, and data. [Figure 21] FIG. 2 is a hardware configuration diagram of a communication device according to the first or second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of an interleave circuit and a communication device according to the present invention will be described in detail below with reference to the accompanying drawings.

[0010] As described above, conventional interleaving techniques can result in reduced throughput or make circuit implementation difficult. For example, some conventional interleaving circuits cannot simultaneously input a large number of bits and rearrange data at a low throughput of 1 bit per cycle. Furthermore, when the block size is large, conventional techniques require a huge number of flip-flops or the memory word size becomes large to operate at high throughput, making circuit implementation difficult.

[0011] Therefore, in the following embodiment, an interleave circuit and a communication device are realized that can suppress a decrease in throughput even when the block size is large, and that can be implemented with a practical circuit configuration.

[0012] (First embodiment) 1 is a block diagram showing an example of the configuration of a communication device 10 according to the first embodiment. As shown in FIG. 1, the communication device 10 includes an interleave circuit 100, an error correction unit 211, a communication control unit 212, and a storage unit 220.

[0013] The interleave circuit 100 receives data to be used for communication and outputs output data obtained by rearranging the received data (input data). For example, the interleave circuit 100 performs block interleave processing to rearrange data within each block of a predetermined block size.

[0014] The error correction unit 211 performs error correction on the output data rearranged by the interleave circuit 100. In this embodiment, the interleave circuit 100 performs block interleaving before error correction, which prevents the error rate from becoming uneven and reduces the possibility of error correction failure.

[0015] The communication control unit 212 controls communication using the output data. For example, the communication control unit 212 transmits the output data to an external communication device that is the communication partner. Note that the external communication device may need to perform a process of rearranging the output data to its original order (deinterleaving). An example of the configuration of a deinterleaving circuit that performs deinterleaving will be described later.

[0016] The storage unit 220 stores various data used by the communication device 10. For example, the storage unit 220 stores input data and output data. The storage unit 220 can be configured using any commonly used storage medium, such as a flash memory, a memory card, a RAM (Random Access Memory), an HDD (Hard Disk Drive), or an optical disk.

[0017] Each of the above units (error correction unit 211, communication control unit 212) is realized, for example, by one or more processors. For example, each of the above units may be realized by having a processor such as a CPU (Central Processing Unit) execute a program, i.e., by software. Each of the above units may be realized by a processor such as a dedicated IC (Integrated Circuit), i.e., by hardware. Each of the above units may be realized by a combination of software and hardware. When multiple processors are used, each processor may realize one of the units, or may realize two or more of the units.

[0018] Next, a description will be given of an example configuration of the interleave circuit 100. Fig. 2 is a block diagram showing an example configuration of the interleave circuit 100. The interleave circuit 100 includes a rearrangement circuit 110, an address calculation circuit 120, and memories 130a and 130b.

[0019] For each n×n-bit input data, the rearrangement circuit 110 outputs output data obtained by rearranging the input data in a bit order different from the input bit order. For example, the rearrangement circuit 110 receives input data each containing n bits (n is an integer of 2 or more) in parallel for each cycle, rearranges the n input data input in n cycles into n output data each containing n bits input in mutually different cycles, and outputs the n output data.

[0020] The memories 130a and 130b are storage devices (examples of first storage devices) that store the output data rearranged by the rearrangement circuit 110. The interleave circuit 100 of this embodiment is configured to include two memories 130a and 130b each large enough to store one block of data. The memories 130a and 130b store data in units of n bits (one word), for example. In other words, the word size of the memories 130a and 130b is n bits.

[0021] The interleave circuit 100 performs double buffer operation, switching between the memory used for writing (write memory) and the memory used for reading (read memory) for each block, of the two memories 130a and 130b. Hereinafter, when there is no need to distinguish between the memories 130a and 130b, they will simply be referred to as memory 130.

[0022] The address calculation circuit 120 calculates write addresses for writing the n pieces of output data to the memory 130 and read addresses for reading the n pieces of output data from the memory 130 .

[0023] Next, an example of block interleaving will be described. Figure 3 is a diagram showing an example of block interleaving. Each of the data D0 to D63 represents 1-bit data. These data are rearranged as one block. That is, in this example, the block size is 64 bits. However, the block size is not limited to this, and may be larger or smaller than 64 bits.

[0024] The interval at which rearrangement is performed is called the interleaving interval, and is represented by the number of bits n. Figure 3 shows an example where the interleaving interval n is 4. If the number of n-bit (4-bit when n=4) input data in a block is d, the block size can also be expressed as n x d. Note that the interleaving interval n is not limited to 4 and may be any value. For example, in order to achieve a practical equalization of the error rate, the interleaving interval n may be set to about 512.

[0025] The input data is input in the order D0, D1, D2, D3, D4, etc. The output data after rearrangement is output in the order D0, D4, D8, D12, D16, etc., D60, D1, D5, etc. In this way, in this embodiment, the data is rearranged so that it is output in an order different from the input order within the block.

[0026] In this embodiment, input data is rearranged in n×n-bit units. In Fig. 3, for example, when 16-bit (4×4-bit) input data D0 to D15 is input, this 16-bit input data is rearranged. In the following, the number of n×n-bit data in a block is assumed to be N. In the example of Fig. 3, N=4 (=64 / 16).

[0027] Next, the operation of the interleave circuit 100 according to the first embodiment will be described. Fig. 4 is a flowchart showing an example of the operation of the interleave circuit 100 according to the first embodiment. Fig. 4 shows an example of the operation when processing one block.

[0028] At the start of operation, the interleave circuit 100 initializes internal signals, write addresses, and read addresses (step S101), and then rearranges the data while sequentially inputting n-bit input data (steps S102 to S106).

[0029] In this embodiment, input data is input at a throughput of n bits / cycle. After initialization (step S101), n ​​cycles of input data are not available from cycle 1 to cycle (n-1), so rearranged output data is not output. After at least n cycles of input data are input, rearranged n-bit output data is output. An example of processing after n cycles of input data are input (after cycle n) will be described below.

[0030] First, the rearrangement circuit 110 receives n-bit input data (step S102). The rearrangement circuit 110 rearranges the n×n-bit input data using the input data received in step S102 and previously received input data, and outputs n-bit output data that is a part of the rearrangement result (step S103).

[0031] The rearrangement circuit 110 writes the n-bit output data into the write memory in accordance with the write address calculated by the address calculation circuit 120 (step S104).

[0032] The interleave circuit 100 reads and outputs n-bit data from the read memory in which the rearranged output data is stored, in accordance with the read address calculated by the address calculation circuit 120 (step S105).

[0033] The order of the output data output from the rearrangement circuit 110 is different from the order of the data in the entire block. Therefore, the address calculation circuit 120 calculates and updates the write address of the output data using the following address calculation formula (step S106). Write address = j × N + k j: Bit position of n bits in the output data (0≦j≦n-1) N: Number of n×n-bit data k: Position of n × n bits of data within the block (0≦k≦N-1)

[0034] Furthermore, the address calculation circuit 120 calculates the read address of the output data by, for example, incrementing the address by 1 starting from an initial value of 0. Note that the calculation methods for the write address and the read address may be interchanged. For example, the address calculation circuit 120 may calculate the read address using the address calculation formula described above, and calculate the write address by incrementing from the initial value. In this way, the address calculation circuit 120 may calculate each address by any method as long as it is a method for calculating the write address and the read address so that one of the n pieces of output data is output from the memory 130 in each of n consecutive cycles.

[0035] The interleave circuit 100 may perform this series of steps (steps S102 to S106) as a pipeline process, thereby processing each step for each n-bit data in one cycle.

[0036] The interleave circuit 100 determines whether all the data in the block has been processed (step S107). If all the data in the block has not been processed (step S107: No), the interleave circuit 100 returns to step S102 and repeats the process for the next n bits of input data.

[0037] When all the data in the block has been processed (step S107: Yes), the interleave circuit 100 switches between the two memories 130a, 130b, one to be used for writing (write memory) and the other to be used for reading (read memory) (step S108), and terminates the operation.

[0038] In this manner, in this embodiment, by rearranging one block of data and outputting the rearranged data, rearrangement processing can be performed at a rate of n bits / cycle.

[0039] Next, we will explain a configuration example of the rearrangement circuit 110. Fig. 5 is a diagram showing a configuration example of the rearrangement circuit 110. Fig. 5 shows an example of a circuit configuration for performing block interleaving processing when the interleaving interval n is 4 bits, as explained in Fig. 3.

[0040] As shown in Fig. 5, rearrangement circuit 110 receives n-bit (4-bit in the example of Fig. 5) input data (e.g., D0 to D3) and outputs n-bit output data (e.g., D'0 to D'3). In the example of Fig. 5, the least significant bit (LSB: Least Significant Byte) of the input data is D0, and the most significant bit (MSB: Most Significant Bit) of the input data is D3. Furthermore, the least significant bit of the output data is D'0, and the most significant bit of the output data is D'3.

[0041] The rearrangement circuit 110 includes flip-flops 501 to 522 (an example of a register) and n (four in the example of FIG. 5) n-bit MUXes (multiplexers) 530-0 to 530-3 (an example of a selection circuit).

[0042] The n-bit MUXes 530-0 to 530-3 are n-bit data selection circuits that select and output any one of the n-bit data. Data including the outputs of the n-bit MUXes 530-0 to 530-3 becomes n-bit output data.

[0043] When the output data is 4 bits (n=4), each of n-bit MUXes 530-0 to 530-3 selects the bit at the j-th bit position of the output data. Hereinafter, the n-bit MUX that selects the bit at the j-th bit position may be referred to as n-bit MUX 530-j.

[0044] Flip-flops 501 to 522 are configured to function as a shift register with (n+i) or more stages for each ith (0≦i≦n−1) bit position of input data.

[0045] Below, we will explain an example in which a shift register is configured with (n+i) stages for each ith bit position of the input data. Note that while it is preferable to have a small number of registers (flip-flops), it may be configured with a shift register with more than (n+i) stages, taking into account the efficiency of circuit layout, etc. The minimum number of flip-flops, Nff, can be calculated using the following formula (1).

number

[0046] 5, for the 0th bit position of the input data, a four-stage shift register is configured with four flip-flops 501 to 504. In the first cycle, D0 is input and stored in flip-flop 501. Thereafter, in the second to fourth cycles, D0 is sequentially shifted and stored in flip-flops 502 to 504, respectively.

[0047] The input of n-bit MUX 530-j is connected to the output of the (n-j+i)th flip-flop for the ith bit of the input data. For example, in response to a selection signal that is instructed, n-bit MUX 530-j selects and outputs a bit stored in one of the n flip-flops connected thereto, but different from each other, in each of n consecutive cycles.

[0048] For example, the rearrangement circuit 110 switches the selection signal that indicates the bit to be selected by each n-bit MUX 530-j every time n-bit input data is input, thereby realizing rearrangement of n×n-bit input data.

[0049] For example, the n-bit MUX 530-2 is connected to the outputs of the second-stage flip-flop 502 for input D0 (i=0), the third-stage flip-flop 507 for input D1 (i=1), the fourth-stage flip-flop 513 for input D2 (i=2), and the fifth-stage flip-flop 520 for input D3 (i=3). The rearrangement circuit 110 designates signals instructing the selection of bits input from the flip-flops 502, 507, 513, and 520 as selection signals 0, 1, 2, and 3, respectively. The n-bit MUX 530-2 selects and outputs the bits stored in the flip-flops 502, 507, 513, and 520 in accordance with the selection signals 0, 1, 2, and 3 instructed in four consecutive cycles.

[0050] An example of the rearrangement operation by rearrangement circuit 110 will be described with reference to FIGS. Fig. 6 is a diagram showing an example of input data. Figs. 7 to 10 are diagrams showing states after 4 cycles, 5 cycles, 6 cycles, and 7 cycles have elapsed since the start of processing, respectively. Fig. 11 is a diagram showing examples of input data and output data after rearrangement.

[0051] 6 is input sequentially, after four cycles have elapsed, n×n-bit data 50 (D0 to D15) is stored in the shift registers as shown in Fig. 7. The rearrangement circuit 110 sets the selection signal of the n-bit MUX 530-j to 0, and outputs data D0, D4, D8, and D12.

[0052] In the same cycle, rearrangement circuit 110 can input n-bit data (D16 to D19) starting from the next n×n-bit data 51. In this way, rearrangement processing of n×n-bit data can be performed continuously without any gaps.

[0053] Similarly, rearrangement circuit 110 can rearrange data within n×n-bit data units by switching the selection signal while shifting the data (FIGS. 8 to 10). For example, in FIG. 8, data D1, D5, D9, and D13 selected according to selection signal 1 are output. In FIG. 9, data D2, D6, D10, and D14 selected according to selection signal 2 are output. In FIG. 10, data D3, D7, D11, and D15 selected according to selection signal 3 are output.

[0054] Figure 11 includes an example of output data 60 after rearranging the input data shown in Figure 6. The output data 60 corresponds to rearranged data of the data 50 of Figure 6.

[0055] Thereafter, rearrangement circuit 110 sets the selection signal to 0 again and repeats the same process on the next n×n-bit data (data 51 in FIG. 6), thereby continuously rearranging n×n-bit data.

[0056] The output data output from the rearrangement circuit 110 is output in an order different from the data order (input order) of the entire block. Fig. 12 is a diagram showing the relationship between the output order of the output data, the addresses of the memory 130, and the data after interleaving.

[0057] The rearranged output data is output from the rearrangement circuit 110 in n-bit increments. For example, the n-bit output data obtained by rearranging the input data shown in FIG. 11 is output in the order shown in the rearrangement circuit output order column in FIG. 12. The address calculation circuit 120 calculates the write address of the output data so that it becomes the value shown in the address column in FIG. 12. For example, the address calculation circuit 120 calculates the write address using the above address calculation formula.

[0058] This allows the output data to be stored in the memory 130 in the output order shown in Fig. 3. Note that the addresses shown in Fig. 12 are based on the assumption that the word size of the memory 130 is n bits.

[0059] For example, data whose output order of the rearrangement circuit is 4 is data obtained by rearranging data in n×n bit units, which corresponds to k=0 in FIG. 11. In the rearranged output data 60 (FIG. 11), the bit position j of the data corresponding to the data whose output order of the rearrangement circuit is 4 is 3. Also, as shown in FIG. 11, the number N of data in n×n bit units is 4. Therefore, the address calculation circuit 120 can calculate the write address as j×N+k=3×4+0=12 using the above address calculation formula.

[0060] If the number of n×n-bit data is a power of 2, the address calculation circuit 120 may calculate the address by bit concatenation, instead of multiplication, with the higher-order bits representing the position within the n×n-bit data and the lower-order bits representing the position of the n×n-bit data. This reduces the circuit size.

[0061] Next, a configuration example of a deinterleave circuit will be described. The deinterleave circuit may be provided in an external communication device that communicates with the communication device 10, or may be provided within the communication device 10. Fig. 13 is a block diagram showing a configuration example of a deinterleave circuit 400. The deinterleave circuit 400 includes a rearrangement circuit 110, an address calculation circuit 420, and memories 130a and 130b. Compared to the interleave circuit 100, the deinterleave circuit 400 has a configuration in which the arrangements of the rearrangement circuit 110, the address calculation circuit 420, and the memories 130a and 130b are swapped.

[0062] The configurations of the rearrangement circuit 110 and memories 130a and 130b are similar to those of the interleave circuit 100, so they are given the same reference numerals and their description will be omitted.

[0063] The address calculation circuit 420 calculates a write address for writing data (input data) rearranged by the interleave circuit 100 to the memory 130, and a read address for reading the input data from the memory 130. The address calculation circuit 420 calculates the write address of the data using the following address calculation formula: Write address = k × N + j j: Bit position of n bits in the data (0≦j≦n-1) N: Number of n×n-bit data k: Position of n × n bits of data within the block (0≦k≦N-1)

[0064] Compared with the address calculation formula by the address calculation circuit 120 of the interleave circuit 100, this address calculation formula is a formula in which k and j are swapped.

[0065] Next, a description will be given of the operation of the deinterleave circuit 400. Fig. 14 is a flowchart showing an example of the operation of the deinterleave circuit 400. Fig. 14 shows an example of the operation when processing one block.

[0066] At the start of operation, the deinterleave circuit 400 initializes internal signals, write addresses, and read addresses (step S201), and then rearranges the data while sequentially inputting n-bit input data (steps S202 to S207).

[0067] The deinterleave circuit 400 receives n-bit input data (step S202).

[0068] The address calculation circuit 420 calculates and updates the write address of the input data using the above address calculation formula (step S203). The address calculation circuit 420 also calculates the read address of the input data by incrementing the initial value by 1, for example, from 0. The deinterleave circuit 400 writes the input data to the memory 130 according to the calculated write address (step S204).

[0069] 15 is a diagram showing an example of input data input to the deinterleave circuit 400. The input data is data rearranged by the interleave circuit 100, and therefore, for example, the data is arranged in the same order as the interleaved data in FIG.

[0070] FIG. 16 is a diagram showing an example of write addresses calculated for the input data shown in FIG. 15, and data (memory write data) written to the memory 130 in accordance with the write addresses.

[0071] 14, the rearrangement circuit 110 reads n-bit input data from the memory 130 in accordance with the read address calculated by the address calculation circuit 420 (step S205). The rearrangement circuit 110 rearranges the n×n-bit input data sequentially read from the memory, and outputs n-bit output data that is a part of the rearrangement result (steps S206 and S207).

[0072] The deinterleave circuit 400 determines whether all the data in the block has been processed (step S208). If all the data in the block has not been processed (step S208: No), the deinterleave circuit 400 returns to step S202 and repeats the process for the next n bits of input data.

[0073] When all the data in the block has been processed (step S208: Yes), the deinterleave circuit 400 switches between the two memories 130a, 130b, one to be used for writing (write memory) and the other to be used for reading (read memory) (step S209), and terminates the operation.

[0074] When the rearrangement circuit 110 of the deinterleave circuit 400 performs rearrangement on the data in FIG. 16, data before rearrangement by the interleave circuit 100, such as that shown in FIG. 6, is obtained.

[0075] According to this embodiment, by using a permutation circuit and memory having n-bit parallel input and parallel output, permutation processing can be performed at a rate of n bits / cycle. By adjusting n, even when the block size is large, high-throughput block interleaving processing can be achieved with a relatively small number of flip-flops and a practical word size (n bits).

[0076] For example, a technology is known in which the word size is n×m bits (n and m are multiple bits). For high-speed operation, when n=m=512, this technology results in a word size of 512×512=262,144 bits, making the configuration difficult. In contrast, in this embodiment, the word size is n bits=512 bits, making it possible to configure a circuit within a practical range.

[0077] (Second embodiment) In the second embodiment, an example will be described in which a relatively small-capacity storage device (second storage device) and a relatively large-capacity storage device (first storage device) are used. Note that the overall configuration of the communication device 10 is the same as that shown in FIG. 1 except that the interleave circuit 100 is replaced with an interleave circuit 100-2, and therefore detailed description thereof will be omitted.

[0078] Fig. 17 is a block diagram showing an example of the configuration of an interleave circuit 100-2 according to the second embodiment. As shown in Fig. 17, the interleave circuit 100-2 includes a rearrangement circuit 110, an address calculation circuit 120-2, memories 130-2a and 130-2b, a storage control circuit 140-2, and a large-capacity memory 150-2.

[0079] The second embodiment differs from the first embodiment in that the address calculation circuit 120-2, the functions of the memories 130-2a and 130-2b, and the storage control circuit 140-2 and the large-capacity memory 150-2 are added. The other configurations and functions are the same as those in the block diagram of the interleave circuit 100 according to the first embodiment shown in FIG. 2, and therefore the same reference numerals are used and the description thereof will be omitted here.

[0080] The memories 130-2a and 130-2b are storage devices that store the output data rearranged by the rearrangement circuit 110. For example, the memories 130-2a and 130-2b are configured to store half of one block of data. The storage capacity of the memories 130-2a and 130-2b is not limited to half of one block, and may be, for example, 1 / m of one block (m is an integer greater than or equal to 3).

[0081] The interleave circuit 100-2 performs a double buffer operation in which, of the two memories 130-2a and 130-2b, one memory to be used for writing (write memory) and the other memory to be used for reading (read memory) are switched for each block.

[0082] The large-capacity memory 150-2 is a storage device (first storage device) having a storage capacity relatively larger than that of the memories 130-2a and 130-2b. The large-capacity memory 150-2 is a storage device having a size capable of storing, for example, one block of data.

[0083] The memories 130-2a and 130-2b correspond to storage devices (second storage devices) having a storage capacity relatively smaller than that of the large-capacity memory 150-2. Hereinafter, the memories 130-2a and 130-2b may be referred to as small-capacity memories.

[0084] The small-capacity memory is realized by, for example, SRAM (Static Random Access Memory). The large-capacity memory 150-2 is realized by, for example, DRAM (Dynamic Random Access Memory). SRAM generally allows for faster data read and write than DRAM, but is more expensive than DRAM.

[0085] The address calculation circuit 120-2 calculates a write address for writing output data to the memory 130-2 and a read address for reading the output data from the memory 130-2. The address calculation circuit 120-2 also calculates a write address for writing data read from the memory 130-2 to the large-capacity memory 150-2 and a read address for reading data from the large-capacity memory 150-2. The method of calculating the write address and read address of the large-capacity memory 150-2 is the same as that of the address calculation circuit 120 in the first embodiment.

[0086] The storage control circuit 140-2 reads the output data stored in the small-capacity memory and controls the process of storing the read output data in the large-capacity memory 150-2. For example, the storage control circuit 140-2 writes the data read from the small-capacity memory to the large-capacity memory 150-2 by burst transfer via the bus.

[0087] In this way, interleave circuit 100-2 of this embodiment rearranges data by a certain size (for example, half the size of one block) and stores the data in the small-capacity memory, and writes the data read from the small-capacity memory to large-capacity memory 150-2. Because the data rearranged so as to be contiguous is stored in the small-capacity memory, the data can be written to large-capacity memory 150-2 at high speed by burst transfer.

[0088] Next, the operation of the interleave circuit 100-2 according to the second embodiment will be described. Fig. 18 is a flowchart showing an example of the operation of the interleave circuit 100-2 according to the second embodiment. Fig. 18 shows an example of the operation when processing one block.

[0089] Steps S301 to S303 are the same as steps S101 to S103 in the interleave circuit 100 according to the first embodiment, and therefore a description thereof will be omitted.

[0090] The rearrangement circuit 110 writes the n-bit output data into a write memory in the small-capacity memory in accordance with the write address calculated by the address calculation circuit 120-2 (step S304).

[0091] The storage control circuit 140-2 reads n bits of data from a read memory in the small-capacity memory, which stores output data in which half the data of one block (partial data) has been rearranged, in accordance with the read address calculated by the address calculation circuit 120-2, and writes the read data to the large-capacity memory 150-2 (step S305). At this time, the storage control circuit 140-2 may write the data to the large-capacity memory 150-2 by burst transfer.

[0092] The address calculation circuit 120-2 calculates and updates the write address and read address of the next data in the small-capacity memory, as well as the write address in the large-capacity memory 150-2 (step S306).

[0093] The interleave circuit 100-2 may perform this series of steps (steps S302 to S306) as a pipeline process, thereby processing each step for each n-bit data in one cycle.

[0094] The interleave circuit 100-2 determines whether there is free space in the small-capacity memory, in other words, whether data has been stored to the storage capacity of the small-capacity memory (step S307). If there is free space in the small-capacity memory (step S307: No), the interleave circuit 100-2 returns to step S102 and repeats the process for the next n bits of input data.

[0095] If there is no free space in the small-capacity memory (step S307: Yes), the interleave circuit 100-2 switches between the two memories 130-2a and 130-2b as the memory used for writing (write memory) and the memory used for reading (read memory) (step S308).

[0096] The interleave circuit 100-2 determines whether all the data in the block has been processed (step S309). If all the data in the block has not been processed (step S309: No), the interleave circuit 100-2 returns to step S102 and repeats the process for the next n bits of input data.

[0097] If all the data in the block has been processed (step S309: Yes), interleave circuit 100-2 ends its operation.

[0098] 19 is a diagram showing an example of rearrangement of n-bit data using a small-capacity memory and large-capacity memory 150-2. In this embodiment, a portion of data (partial data) of one block is rearranged using the small-capacity memory, and the partial data is written to a corresponding area in large-capacity memory 150-2. This operation is repeated, and finally, one block of rearranged data is stored in large-capacity memory 150-2.

[0099] Next, an example of a method for calculating a write address for a small-capacity memory will be described with reference to Fig. 20. Fig. 20 is a diagram showing the relationship between the output order of output data from rearrangement circuit 110, addresses in large-capacity memory 150-2, addresses in small-capacity memory, memory types, and data after interleaving.

[0100] The memory type is information indicating which of the two memories 130-2a and 130-2b is the small-capacity memory used as the write memory. In the following, the memory type "MA" refers to the memory 130-2a, and the memory type "MB" refers to the memory 130-2b.

[0101] In this example, half of the data in one block is sorted in the small-capacity memory and then written to the large-capacity memory 150-2. The addresses in the large-capacity memory 150-2 for each sorting circuit output order can be calculated using the address calculation formula above.

[0102] The write addresses when writing data whose output order of the rearrangement circuit is 1 to 8 into memory 130-2a and data whose output order of the rearrangement circuit is 9 to 16 into memory 130-2b are the values ​​shown in the small capacity memory address column in FIG.

[0103] The address calculation circuit 120-2 calculates the value of the small-capacity memory address, for example, using the following equation (2): tempAddr is the write address of the large-capacity memory 150-2. The correction value b is 0 when the memory type is MA, and 1 when the memory type is MB.

number

[0104] For example, for data whose output order from the rearrangement circuit in FIG. 20 is 15, the address is calculated as in the following equation (3): This value matches the corresponding value 5 in the small capacity memory address column in FIG.

number

[0105] Furthermore, the address calculation circuit 120-2 calculates the read address of the small-capacity memories for each of the two small-capacity memories by incrementing the initial value by 1, for example, from 0.

[0106] In this manner, in this embodiment, by treating the memories 130-2a and 130-2b (small-capacity memories) like caches, high-speed operation is possible while reducing the storage capacity of the memories 130-2a and 130-2b. For example, while the two memories 130 in the first embodiment have a combined storage capacity of two blocks, the small-capacity memories in this embodiment have half that storage capacity. In this case, as long as writing to the large-capacity memory 150-2 is not rate-determining, high-throughput block interleaving processing at a rate of n bits / cycle can be realized.

[0107] As described above, according to the first and second embodiments, it is possible to suppress a decrease in throughput and to implement interleaving processing with a practical circuit configuration.

[0108] Next, a hardware configuration of a communication device according to the first or second embodiment will be described with reference to Fig. 21. Fig. 21 is an explanatory diagram showing an example of the hardware configuration of a communication device according to the first or second embodiment.

[0109] The communication device according to the first or second embodiment includes a control device such as a CPU 351, a storage device such as a ROM (Read Only Memory) 352 or a RAM 353, a communication I / F 354 that connects to a network and communicates, and a bus 361 that connects each part.

[0110] The program executed by the communication device according to the first or second embodiment is provided in advance in the ROM 352 or the like.

[0111] The program executed by the communication device according to the first or second embodiment may be configured to be provided as a computer program product by being recorded in an installable or executable file format on a computer-readable recording medium such as a CD-ROM (Compact Disk Read Only Memory), a flexible disk (FD), a CD-R (Compact Disk Recordable), or a DVD (Digital Versatile Disk).

[0112] Furthermore, the program executed by the communication device according to the first or second embodiment may be stored on a computer connected to a network such as the Internet and provided by being downloaded via the network. Also, the program executed by the communication device according to the first or second embodiment may be provided or distributed via a network such as the Internet.

[0113] The program executed by the communication device according to the first or second embodiment can cause a computer to function as each unit of the communication device. In this computer, the CPU 351 can read the program from a computer-readable storage medium onto a main storage device and execute the program.

[0114] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0115] 10. Communications equipment 100, 100-2 interleave circuit 110 Sorting Circuit 120 Address Calculation Circuit 130a, 130b, 130-2a, 130-2b memory 140-2 Memory control circuit 150-2 Large capacity memory 211 Error Correction Unit 212 Communication control section 220 Storage section 400 Deinterleave circuit 501~522 Flip-flops 530-0~530-3 n-bit MUX

Claims

1. a permutation circuit that receives input data in parallel, each of which includes n bits (n is an integer of 2 or more) per cycle, and permutes the n pieces of input data input in the n cycles into n pieces of output data, each of which includes n bits input in mutually different cycles; an address calculation circuit that calculates write addresses for writing the n pieces of output data to a first storage device and read addresses for reading the n pieces of output data from the first storage device; The sorting circuit a register having (n+i) or more stages functioning as a shift register for each ith (0≦i≦n−1) bit position of the input data; outputting the output data including n bits stored in n registers among the registers at (n+i) stages or more; Interleave circuit.

2. The sorting circuit selecting, in each cycle, the output data including n bits stored in the register corresponding to any of the n bit positions of the input data, and outputting the selected output data; 2. The interleave circuit of claim 1.

3. For each ith (0≦i≦n−1) bit position of the input data, (n+i) stages of the register are provided; the sorting circuit includes n selection circuits; The jth (0≦j≦n−1) selection circuit is Among the registers in the (n+i)th stage corresponding to the i-th (0≦i≦n−1) bit position of the input data, the register is connected to the register in the (n−j+i)th stage, selecting bits stored in different registers from among the connected registers in each of n consecutive cycles; 3. The interleave circuit of claim 2.

4. further comprising a second storage device having a storage capacity smaller than that of the first storage device; the sorting circuit stores the output data in the second storage device; further comprising a storage control circuit that reads the output data stored in the second storage device and stores the read output data in the first storage device; 2. The interleave circuit of claim 1.

5. the address calculation circuit calculates the write address and the read address so as to output any one of the n output data from the first storage device in each of n consecutive cycles; 2. The interleave circuit of claim 1.

6. an interleave circuit that outputs output data obtained by rearranging input data; an error correction unit that performs error correction on the output data, The interleave circuit includes: a permutation circuit that receives input data in parallel, each of which includes n bits (n is an integer of 2 or more) per cycle, and permutes the n pieces of input data input in the n cycles into n pieces of output data, each of which includes n bits input in mutually different cycles; an address calculation circuit that calculates write addresses for writing the n pieces of output data to a first storage device and read addresses for reading the n pieces of output data from the first storage device; The sorting circuit a register having (n+i) or more stages functioning as a shift register for each ith (0≦i≦n−1) bit position of the input data; outputting the output data including n bits stored in n registers among the registers at (n+i) stages or more; Communication equipment.

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