Method, apparatus and system for encoding and decoding tensors

Abstract

A system and method of decoding a bitstream to produce tensors for use by a neural network second portion. The method comprises decoding a network abstraction layer (NAL) unit from the bitstream having a predetermined length, wherein the NAL unit of the predetermined length indicates a network abstraction layer (NAL) unit format of one inner codec of a plurality of inner codecs, each other inner codec having NAL unit lengths different to the predetermined length; selecting an inner codec from the plurality of inner codecs based on the decoded NAL unit of the predetermined length; and decoding the bitstream using the selected inner codec to produce the tensors.

Description

METHOD, APPARATUS AND SYSTEM FOR ENCODING AND DECODINGTENSORSREFERENCE TO RELATED APPLICATION(S)

[0001] This application claims the benefit under 35 U.S.C. §119 of the filing date of Australian Patent Application No. 2024203901, filed 07 June 2024, hereby incorporated by reference in its entirety as if fully set forth herein.TECHNICAL FIELD

[0002] The present invention relates generally to digital video signal processing and, in particular, to a method, apparatus and system for encoding and decoding tensors for a convolutional neural network. The present invention also relates to a computer program product including a computer readable medium having recorded thereon a computer program for encoding and decoding tensors for a convolutional neural network using video compression technology.BACKGROUND

[0003] Convolutional neural networks (CNNs) are an emerging technology addressing, among other things, use cases involving machine vision such as object detection, instance segmentation, object tracking, human pose estimation, and action recognition. Applications for CNNs can involve use of ‘edge devices’, with sensors and some processing capability, coupled to application servers as part of a ‘cloud’. CNNs can require relatively high computational complexity, more than can typically be afforded either in computing capacity or power consumption by an edge device. Executing a CNN in a distributed manner has emerged as one solution to running leading-edge networks using limited capability edge devices without requiring all computational complexity to be incurred within cloud servers whilst edge devices have potentially under-utilised inferencing resources. In other words, distributed processing allows legacy edge devices to still provide the capability of leading-edge CNNs by distributing processing between the edge device and other processing means, such as cloud servers. Such a distributed network architecture may be referred to as ‘collaborative intelligence’ (CI) and offers benefits such as re-using a partial result from a first portion of the network with several different second portions, perhaps with each portion being optimised for a different task. CIarchitectures introduce a need for efficient compression of tensor data, for transmission over a network such as a WAN.

[0004] CNNs typically include many layers, such as convolution layers and fully connected layers, with data passing from one layer to the next in the form of ‘tensors’. Splitting a network across different devices introduces a need to compress the intermediate multi-dimensional tensor data that passes from one layer to the next within a CNN in order to facilitate transmission over a network having bandwidth limitations or costs. Compression of such tensors may be referred to as ‘feature compression’ and the intermediate tensor data is often referred to as ‘features’ or ‘feature maps’. Features or feature maps are generally a collection of two-dimensional (2D) arrays of values which, when combined into a 3D (or 4D) data structure form a tensor, with each feature map corresponding to one ‘channel’ of the tensor. Intermediate tensor data represents a partially processed form of input such as an image frame or video frame, encountered within a neural network. Although a unit of data to be processed in a neural network is typically a tensor, operations performed may be described in relation to a feature map, in which case it is understood that the operation is to be performed to each feature map in the tensor. International Organisation for Standardisation / International Electrotechnical Commission Joint Technical Committee 1 / Subcommittee 29 / Working Groups 4 (ISO / IEC JTC 1 / SC 29 / WG 4), also known as the “Moving Picture Experts Group” (MPEG) Video coding are tasked with developing a standard for feature compression, known as the ‘feature coding for machines’ (FCM) standard. Previously WG 2 ‘MPEG Technical Requirements’ had completed a ‘Call for Proposals’ which received responses that demonstrated significant outperformance over feature compression results achieved using state-of-the-art standardised video compression technology directly applied to the tensors.

[0005] CNNs typically require weights for each of the layers to be predetermined in a training stage, where a very large amount of training data is passed through the CNN and a result determined by the network undergoing training being compared to ground truth associated with the training data. Discrepancy between the obtained and desired result is expressed as a Toss’ and measured with a Toss function’. Using the determined loss, a process for updating network weights, such as stochastic gradient descent (SGD), is performed. Network weight update typically involves a process of back-propagation of ‘gradients’ that begins at the output layer of the network and proceeds backward to terminate when the input layer to the network is updated, propagating through intermediate, or ‘hidden’, layers of the network. Gradients are indicative of deltas to be applied to network weights and are themselves updated as part of the backpropagation process. The rate of weight update is set by a ‘learning rate’ hyperparameter, typically set to facilitate the training process in finding a global minima in terms of loss (i.e., highest possible task performance for the network architecture and training data) while avoiding the training process becoming ‘stuck’ in a local minima. Becoming stuck in a local minima corresponds to obtaining sub-optimal task performance for the network architecture and being incapable of finding new weight values that could lead to higher task performance. Network weights are repeatedly updated by supplying input data and ground truth data organised into ‘batches’ to iteratively refine the network performance until further improvement in accuracy is no longer achievable. An iteration through the entire training dataset forms one ‘epoch’ of training and training typically requires performing multiple epochs to achieve a high level of performance for the task. Weights for a trained network are then available for deployment, and the network operates in a mode where weights are fixed and gradients for weight update are omitted. The process of executing a pretrained CNN with an input and progressively transforming the input into an output according to a topology of the CNN is commonly referred to as ‘inferencing’.

[0006] Generally, a tensor is an array of elements having four dimensions, namely: batch, channels, height and width. The first dimension, ‘batch’, is typically of size one when inferencing on video data and indicates that one frame is passed through a CNN as one batch. When training a network, the value of the batch dimension may be increased so that multiple frames are passed through the network in each batch before the network weights are updated, according to a predetermined ‘batch size’. A multi -frame video may be passed through as a single tensor with the batch dimension increased in size according to the number of frames of a given video. However, for practical considerations relating to memory consumption and access, inferencing on video data is typically performed on a frame-wise basis. The ‘channels’ dimension indicates the number of concurrent ‘feature maps’ for a given tensor and the height and width dimensions indicate the size of the feature maps at the particular stage of the CNN. Channel count varies through the layers of a CNN according to the network architecture. Feature map size also varies, depending on subsampling or upsampling occurring in specific network layers.

[0007] The overall complexity of the CNN tends to be relatively high, with relatively large numbers of multiply-accumulate (MAC) operations being performed and numerous intermediate tensors being written to and read from memory, along with reading weights for performance of each layer of the CNN. As such, dividing a neural network into portions allowsimplementation of more complex networks even in systems containing less capable edge devices, without requiring cloud servers to bear the full burden of performing the network.

[0008] Feature compression may benefit from existing video compression standards, such as ISO / IEC 23090-2 “Versatile Video Coding” (VVC) / H.266, developed by the Joint Video Experts Team (JVET), a joint activity by ISO / IEC and ITU-T. VVC is anticipated to address ongoing demand for ever-higher compression performance, especially as video formats increase in capability (for example, with higher resolution and higher frame rate) and to address increasing market demand for service delivery over WANs, where bandwidth costs are relatively high. VVC is implementable in contemporary silicon processes and offers an acceptable trade-off between achieved performance versus implementation cost. The implementation cost may be considered for example, in terms of one or more of silicon area, CPU processor load, memory utilisation and bandwidth. Other video compression standards, such as ISO / IEC 23008-2 “High Efficiency Video Coding” (HEVC) / H.265 or ISO / IEC 14496- 15, “Advanced Video Coding” may also be used for feature compression applications. Other standards such as AV-1, developed by the Alliance for Open Media (AOMedia) may also be used.

[0009] Video data includes a sequence of frames of image data, each frame including one or more colour channels. Where feature map data is to be represented in a packed frame, generally a monochrome frame having luminance only and no chroma channels is adequate. When only luma samples are present, the resulting monochrome frames are said to use a “4:0:0 chroma format”.

[0010] The VVC standard specifies a ‘block based’ architecture, in which frames are firstly divided into an array of square regions known as ‘coding tree units’ (CTUs). In VVC, CTUs generally occupy 128x 128 luma samples. Other possible CTU sizes when using the VVC standard are 32x32 and 64x64. However, CTUs at the right and bottom edge of each frame may be smaller in area, with implicit splitting occurring to ensure coding blocks remain in the frame. Associated with each CTU is a ‘coding tree’ defining a decomposition of the area of the CTU into a set of blocks, also referred to as ‘coding units’ (CUs). Blocks applicable to only the luma channel or only the chroma channels are referred to as ‘coding blocks’ (CBs). A prediction of the contents of a coding block is held in a ‘prediction block’ (PB) or ‘prediction unit’ (PU) and a residual block defining an array of sample values to be additively combined with the PB or PU is referred to as a ‘transform block’ (TB) or ‘transform unit’ (TU), owing tothe typical use of a transformation process in the generation of the TB or TU. In the case of HEVC, the CTU size may be 64^64, 32x32, or 16x 16 luma samples. In the case of advanced video coding (AVC), a “Macroblock” is the analogue of a CTU and has a size of 16x 16 luma samples.

[0011] Notwithstanding the above distinction between ‘units’ and ‘blocks’, the term ‘block’ may be used as a general term to refer to areas or regions of a frame for which operations are applied to all colour channels.

[0012] For each CU, a prediction unit (PU) of the contents (sample values) of the corresponding area of frame data is generated (a ‘prediction unit’). Further, a representation of the difference (or ‘spatial domain’ residual) between the prediction and the contents of the area as seen at input to the encoder is formed. The difference in each colour channel may be transformed and coded as a sequence of residual coefficients, forming one or more TUs for a given CU. The applied transform may be a Discrete Cosine Transform (DCT) or other transform, applied to each block of residual values. The transform is applied separably, (i.e., the two-dimensional transform is performed in two passes, one horizontally and one vertically). The block is firstly transformed by applying a one-dimensional transform to each row of samples in the block. Then, the partial result is transformed by applying a one-dimensional transform to each column of the partial result to produce a final block of transform coefficients that substantially decorrelates the residual samples. Transforms of various sizes are supported by the VVC standard, including transforms of rectangular-shaped blocks, with each side dimension being a power of two. Transform coefficients are quantised for entropy encoding into a bitstream.

[0013] PBs or PUs in VVC may be generated using either an intra-frame prediction or an inter-frame prediction process. Intra-frame prediction involves the use of previously processed samples in a frame being used to generate a prediction of a current block of data samples in the frame. Inter-frame prediction involves generating a prediction of a current block of samples in a frame using a block of samples obtained from one or two previously decoded frames. The block of samples obtained from a previously decoded frame is offset from the spatial location of the current block according to a motion vector, which often has filtering applied. Intra-frame prediction blocks can be (i) a uniform sample value (“DC intra prediction”), (ii) a plane having an offset and horizontal and vertical gradient (“planar intra prediction”), (iii) a population of the block with neighbouring samples applied in a particular direction (“angular intra prediction”) or(iv) the result of a matrix multiplication using neighbouring samples and selected matrix coefficients.

[0014] Encoders and decoders conforming to different video encoding standards may be used to compress intermediate feature maps from a first portion (a ‘backbone’) of a neural network separated into two portions. In compression, the feature maps from the backbone are arranged into a frame and quantised from a floating-point domain to a sample domain suitable for compression as video data. Neural network layers, such as convolutions, batch normalisations, and activation functions, may be applied to reduce the dimensionality of the tensors prior to compression using a video compression standard such as VVC. Dimensionality reduction of tensors reduces the volume of data to be compressed, improving compression efficiency and reducing the runtime of the VVC encoding and decoding stages. Dimensionality reduction introduces complexity offsetting the reduction in runtime seen in the VVC encoding. A need exists to support the use of encoders and decoders conforming to various video encoding standards to improve flexibility and multi -encoder compatibility of FCM implementations.SUMMARY

[0015] It is an object of the present invention to substantially overcome, or at least ameliorate, one or more disadvantages of existing arrangements.

[0016] One aspect of the present disclosure provides a method of decoding a bitstream to produce tensors for use by a neural network second portion, the method comprising: decoding a network abstraction layer (NAL) unit from the bitstream having a predetermined length, wherein the NAL unit of the predetermined length indicates a NAL unit format of one inner codec of a plurality of inner codecs, each other inner codec of the plurality of inner codecs having a NAL unit length different to the predetermined length; selecting an inner codec from the plurality of inner codecs based on the decoded NAL unit of the predetermined length; and decoding the bitstream using the selected inner codec to produce the tensors.

[0017] Another aspect of the present disclosure provides a method of encoding tensors to a bitstream for use by a neural network second portion, the method comprising: selecting an inner codec from a plurality of inner codecs for use in encoding tensors to the bitstream; encoding a network abstraction layer (NAL) unit to the bitstream having a predetermined length, wherein the NAL unit of the predetermined length indicates a NAL unit format of the selected inner codec of the plurality of inner codecs, each other inner codec of the plurality of inner codecshaving a NAL unit length different to the predetermined length; and encoding the tenors to the bitstream using the selected inner codec.

[0018] Another aspect of the present disclosure provides a decoder for decoding a bitstream to produce tensors for use by a neural network second portion, the decoder configured to: decode a network abstraction layer (NAL) unit from the bitstream having a predetermined length, wherein the NAL unit of the predetermined length indicates a NAL unit format of one inner codec of a plurality of inner codecs, each other inner codec of the plurality of inner codecs having a NAL unit length different to the predetermined length; select an inner codec from the plurality of inner codecs based on the decoded NAL unit of the predetermined length; and decode the bitstream using the selected inner codec to produce the tensors.

[0019] Another aspect of the present disclosure provides a non-transitory computer-readable storage medium which stores a program for executing a method of decoding a bitstream to produce tensors for use by a neural network second portion, the method comprising: decoding a network abstraction layer (NAL) unit from the bitstream having a predetermined length, wherein the NAL unit of the predetermined length indicates a NAL unit format of one inner codec of a plurality of inner codecs, each other inner codec of the plurality of inner codecs having a NAL unit length different to the predetermined length; selecting an inner codec from the plurality of inner codecs based on the decoded NAL unit of the predetermined length; and decoding the bitstream using the selected inner codec to produce the tensors.

[0020] Another aspect of the present disclosure provides an encoder for encoding tensors to a bitstream for use by a neural network second portion, the encoder configured to: select an inner codec from a plurality of inner codecs for use in encoding tensors to the bitstream; encode a network abstraction layer (NAL) unit to the bitstream having a predetermined length, wherein the NAL unit of the predetermined length indicates a NAL unit format of the selected inner codec of the plurality of inner codecs, each other inner codec of the plurality of inner codecs having a NAL unit length different to the predetermined length; and encode the tenors to the bitstream using the selected inner codec.

[0021] Another aspect of the present disclosure provides a non-transitory computer-readable storage medium which stores a program for executing a method of encoding tensors to a bitstream for use by a neural network second portion, the method comprising: selecting an inner codec from a plurality of inner codecs for use in encoding tensors to the bitstream; encoding anetwork abstraction layer (NAL) unit to the bitstream having a predetermined length, wherein the NAL unit of the predetermined length indicates a NAL unit format of the selected inner codec of the plurality of inner codecs, each other inner codec of the plurality of inner codecs having a NAL unit length different to the predetermined length; and encoding the tenors to the bitstream using the selected inner codec.

[0022] Other aspects are also disclosed.BRIEF DESCRIPTION OF THE DRAWINGS

[0023] At least one embodiment of the present invention will now be described with reference to the following drawings and appendices, in which:

[0024] Fig. l is a schematic block diagram showing a distributed machine task system;

[0025] Figs. 2A and 2B form a schematic block diagram of a general-purpose computer system upon which the distributed machine task system of Fig. 1 may be practiced;

[0026] Fig. 3 A is a schematic block diagram showing functional modules of a backbone portion of a CNN;

[0027] Fig. 3B is a schematic block diagram showing a residual block of Fig. 3 A;

[0028] Fig. 3C is a schematic block diagram showing a residual unit of Fig. 3A;

[0029] Fig. 3D is a schematic block diagram showing a CBL module of Fig. 3 A;

[0030] Fig. 4 is a schematic block diagram showing functional modules of an alternative backbone portion of a CNN;

[0031] Fig. 5 is a schematic block diagram of a tensor encoder using a configurable tensor compressor stage;

[0032] Fig. 6 is a schematic block diagram showing a multi-scale feature fusion stage for a tensor compressor;

[0033] Fig. 7 shows a picture structure with low delay and one level of temporal interpolation;

[0034] Fig. 8 is a schematic block diagram showing functional modules of a video encoder;

[0035] Figs. 9A & 9B are schematic block diagrams showing an arrangement of regions or subpictures for holding compressed feature map data from compressed tensor data;

[0036] Fig. 10 is a schematic block diagram showing the structure of a network abstraction layer (NAL) unit;

[0037] Fig. 11 is a schematic block diagram showing a bitstream holding NAL units for various compression standards;

[0038] Fig. 12 is a schematic block diagram showing a tensor decoder with a configurable tensor decompressor;

[0039] Fig. 13 is a schematic block diagram showing functional modules of a video decoder;

[0040] Fig. 14 is a schematic block diagram showing an implementation of a configurable feature reconstruction module performing a decoder network topology;

[0041] Fig. 15 is a schematic block diagram showing an embodiment of a multi-scale feature reconstruction stage;

[0042] Fig. 16A is a schematic block diagrams showing a head portion of a CNN;

[0043] Fig. 16B is a schematic block diagram showing an upscaler module of Fig. 16A;

[0044] Fig. 16C is a schematic block diagram showing a detection module of Fig. 16A;

[0045] Fig. 17 is a schematic block diagram showing an alternative head portion of a CNN;

[0046] Fig. 18 shows a method for performing a first portion of a CNN, selecting a feature map compression standard, compressing tensors using the selected feature map compressor, and encoding resulting compressed tensors into a bitstream;

[0047] Fig. 19 shows a method for decoding a bitstream, determining a selected feature map compression standard, reconstructing tensors according to an selected feature map compression standard, and performing a second portion of the CNN; and

[0048] Appendix A shows a syntax table for NAL units conforming to the AVC standard,

[0049] Appendix B shows a syntax table for NAL units conforming to the HEVC standard;

[0050] Appendix C shows a syntax table for NAL units conforming to the VVC standard;

[0051] Appendix D shows a syntax structure for identifying one manner of feature map compression, such as a video compression standard, out of a plurality of manners of feature map compression; and

[0052] Appendix E shows syntax structures for signalling a feature coding for machines vision model parameter set (FCM VMPS), sequence parameter set (FCM SPS), and picture parameter set (FCM PPS).DETAILED DESCRIPTION INCLUDING BEST MODE

[0053] Where reference is made in any one or more of the accompanying drawings to steps and / or features, which have the same reference numerals, those steps and / or features have for the purposes of this description the same function(s) or operation(s), unless the contrary intention appears.

[0054] A distributed machine task system may include an edge device, such as a network camera or smartphone producing intermediate compressed data. The distributed machine task system may also include a final device, such as a server farm based (‘cloud’) application, operating on the intermediate compressed data to produce a task result. Additionally, the edge device functionality may be embodied in the cloud and the intermediate compressed data may be stored for later processing, potentially for multiple different tasks depending on need.

[0055] A convenient form of intermediate compressed data is a compressed video bitstream, owing to the availability of high-performing compression standards and implementations thereof. Video compression standards typically operate on integer samples of some given bit depth, such as 10 bits, arranged in planar arrays. Colour video has three planar arrays, corresponding, for example, to colour components Y, Cb, Cr, or R, G, B, depending on application. CNNs typically operate on floating point data in the form of tensors but may also operate on integer data, also forming tensors. Tensors generally have a relatively smaller spatial dimensionality compared to incoming video data upon which the CNN operates while having more channels than the three channels typical of colour video data, for example 128, 256, or 512 channels.

[0056] Tensors typically have the following dimensions: frames, channels, height, and width. For example, a tensor of dimensions [1, 256, 76, 136] would be said to contain floating-point or integer values for one frame comprising an array of two-hundred and fifty-six (256) feature maps (channels), each of size 136x76. For video data, inferencing is typically performed one frame at a time (frame or 'batch’ value of 1), rather than using tensors containing multiple frames. VVC, HEVC, and AVC support a division of a picture into ’slices’, or contiguous sequences of coded CTUs or Macroblocks in the case of AVC. In VVC and HEVC, a ‘tile’ mechanism is also available to divide a picture into a number of independently decodeable regions.

[0057] Fig. l is a schematic block diagram showing functional modules of a distributed machine task system 100, capable of performing a machine task network in a distributed manner. The division of a particular neural network into two portions requires specifying a ‘split point’ in the network. Layers in the network from the input layer up to the split point are performed in a first device and the resulting intermediate tensor(s) are compressed. Layers from the split point up to the last layer in the network are performed using decompressed tensor(s) from the first device as input to the layer(s) immediately following the split point. At the split point there may be one or more tensors that need to be compressed for conveyance over a communication channel with limited bandwidth compared to the bandwidth requirement for transmission of uncompressed tensors. Where a ‘feature pyramid network’ (FPN) is in use, it is common for layers in the FPN to be related in width and height such that a given layer is half the width and half the height of an adjacent layer among the layers. FPN architectures may also involve the width and height halving alternatively from one layer to the next layer. In some architectures, multiple tensors of the same width and height are produced within the FPN. An FPN may occur relatively early in the neural network topology, resulting in a necessity for a split point to occur within the FPN in order for a useful division of the network workload across the edge device and the cloud to be achieved. When a split occurs within the FPN of the machine task network, performance of a variety of machine task networks where layers up to the split point are common among the machine task networks (‘shared backbone’ architecture) may be achieved. Where a split point occurs within the FPN, tensor compression methods may exploit redundancies across the FPN layers to improve compression performance. Compression methods applicable to the various network topologies used in contemporary CNNs are therefore beneficial for application in a wide range of scenarios.

[0058] The system 100 may be used for implementing methods for decorrelating, packing and quantising feature maps into planar frames for encoding and decoding feature maps from encoded data for various neural networks. Various neural networks may be split at different points and may result in intermediate tensors of various number and dimensionality. A feature compression scheme capable of adapting to different types of intermediate data and capable of providing different quality reconstruction results in advantageous flexibility. Moreover, the system 100 provides flexibility to interface neural networks of various architectures and for various applications subjected to splitting into portions (e.g., for distributed execution).

[0059] The system 100 includes a source device 110 for generating frame data 113. The frame data 113 is passed to a CNN backbone 114 to produce tensors 115. The tensors 115 are passed to a tensor encoder 116, which produces an encoded bitstream 121. The system 100 also includes a destination device 140 for decoding tensor data in the form of a received bitstream 143. The destination device 140 may be used for decoding the tensor data (or tensors) for content (e.g., of audio data, video data, image data, and textual data) of the bitstream 143.

[0060] A communication channel 130 is used to communicate the encoded bitstream 121 from the source device 110 to the destination device 140. In some arrangements, the source device 110 and destination device 140 may either or both comprise respective mobile telephone handsets (e.g., “smartphones”) or network cameras and cloud applications. The communication channel 130 may be a wired connection, such as Ethernet, or a wireless connection, such as WiFi or 5G, including connections across a Wide Area Network (WAN). The communication channel 130 may also be implemented across ad-hoc connections. Moreover, the source device 110 and the destination device 140 may comprise applications where encoded video data is captured on some computer-readable storage medium, such as a hard disk drive in a file server or memory. Although the system 100 is described as including the video source 112, which would provide the frame data 113 for a neural network targeting a computer vision application, other types of source data, such as audio or text, may be input to a suitable neural network implemented in the CNN backbone 114 and a CNN head 150. The CNN backbone 114 may also be referred to as a neural network first portion or NN part 1. The CNN head 150 may also be referred to as a neural network second portion or NN part 2.

[0061] As shown in Fig. 1, the source device 110 includes a video source 112, the CNN backbone 114, the tensor encoder 116, and a transmitter 122. The video source 112 typicallycomprises a source of captured video frame data (shown as 113), such as an image capture sensor, a previously captured video sequence stored on a non-transitory recording medium, or a video feed from a remote image capture sensor. The video source 112 may also be an output of a computer graphics card, for example, displaying the video output of an operating system and various applications executing upon a computing device (e.g., a tablet computer). Examples of source devices 110 that may include an image capture sensor as the video source 112 include smart-phones, video camcorders, professional video cameras, and network video cameras. The video source 112 may produce independent images or may produce temporally sequential images, i.e., a video.

[0062] The neural network implemented in the CNN backbone 114 and the CNN head 150 may depend on the application. For example, a ‘YOLOv3’ network may be used as one part of an object tracking system and a ‘FasterRCNN’ network may be used as an object detection system. The number and dimensionality of tensors 115 depends on a particular network performed in the system 100 and the split point of the particular network.

[0063] The CNN backbone 114 receives the video frame data 113 and performs specific layers of an overall CNN, such as layers corresponding to the ‘backbone’ of the CNN, outputting tensors 115. The backbone layers of the CNN may produce multiple tensors as output, for example, corresponding to different spatial scales of an input image represented by the video frame data 113 when splitting the network within the FPN. An FPN may result in three tensors, corresponding to three layers, output from the backbone 114 as the tensors 115 (e.g., if a ‘YOLOv3’ network is performed by the system 100), with varying spatial resolution and channel count. When the system 100 is performing networks such as ‘Faster RCNN X101- FPN’ or ’Mask RCNN XI 01 -FPN’ the tensors 115 may include tensors for four layers (P2-P5). Use of a FPN results in a plurality of tensors forming a hierarchical representation for a single frame to be encoded to (and decoded from) the bitstream when the split point of the network occurs within the FPN, as described hereafter. The tensor encoder 116 produces the encoded bitstream 121 from the tensors 115.

[0064] The bitstream 121 is supplied to the transmitter 122 for transmission over the communications channel 130 or the bitstream 121 is written to storage 132 for later use.

[0065] The source device 110 supports a particular network for the CNN backbone 114.However, the destination device 140 may use one of several networks for the head CNN 150.In using one of several networks for the head CNN 150, partially processed data in the form of packed feature maps may be stored for later use in performing various tasks without needing to again perform the operation of the CNN backbone 114.

[0066] The bitstream 121 is transmitted by the transmitter 122 over the communication channel 130 as encoded data. The bitstream 121 can in some implementations be stored in a storage memory 132, where the storage 132 is a non-transitory storage device such as a “Flash” memory or a hard disk drive, until later being transmitted over the communication channel 130 (or in-lieu of transmission over the communication channel 130). For example, encoded video data may be served upon demand to customers over a wide area network (WAN) for a video analytics application.

[0067] The destination device 140 includes a receiver 142, a tensor decoder 146, the CNN head 150, and a CNN task result buffer 152. The receiver 142 receives encoded video data from the communication channel 130 and passes the bitstream 143 to the tensor decoder 146. The tensor decoder 146 outputs decoded tensors 149, which are supplied to the CNN head 150. The CNN head 150 receives the tensors 149 and performs the later layers of the neural network that began with the CNN backbone 114 to produce a task result 151. The task result 151 is stored in the task result buffer 152. The contents of the task result buffer 152 may be presented to the user (e.g., via a graphical user interface), or provided to an analytics application where some action is decided based on the task result, which may include summary level presentation of aggregated task results to a user. It is also possible for the functionality of each of the source device 110 and the destination device 140 to be embodied in a single device, examples of which include mobile telephone handsets and tablet computers and cloud applications.

[0068] As seen in Fig. 1, the system 100 also comprises a tensor codec repository 180. The codec repository 180 may include network topologies covering a variety of neural networks and associated split points, and reconstruction fidelity levels. The network topologies may be stored in in the tensor codec repository 180 for future reference (or use). The tensor codec repository 180 may be accessed ‘out of band’ or separately stored in each of the source device 110 and the destination device 140. In other words, the tensor codec repository 180 may be accessed over a network by the source device 110 and the destination device 140 rather than via the bitstream 143. A network topology identifier 174 and 176 may be sent by the tensor encoder 116 and the tensor decoder 146, respectively, to the tensor codec repository 180. Thenetwork topology identifiers 174 and 176 may be used for determining a given network topology from the bitstream 143.

[0069] As a result of a request for a given network topology, a network topology 172 and 178 may be returned by the tensor codec repository 180 to the tensor encoder 116 and the tensor decoder 146, respectively. As described in detail below, the information including the network topology identifier 178 may be decoded and used by the tensor decoder 146 for producing decoded tensors using the determined network topology. The tensor codec repository 180 may be accessible via public file repository or within a private network accessible to the source device 110 and the destination device 140. A given network topology defines the composition and interconnection of a set of machine learning primitive operations, including convolutions, batch normalisations, activation functions, concatenations. A network topology may be available for a split point. However, with mismatch in the supported dimensionality, in particular the spatial dimensions of the feature maps may differ from those provided by CNN backbone 114. Moreover, the data type provided from the CNN backbone 114 and supplied to the CNN head 150 may differ from that used internally by the network topology. For example, integer inferencing is commonly used due to its reduced complexity compared to floating-point inferencing. Where a network topology is available but configured to use floating-point inferencing, an adaptation between integer and floating-point domains is needed to couple the network topology implemented in the tensor encoder 116 and the tensor decoder 146 with the CNN backbone 114 and the CNN head 150.

[0070] The video source 112 can provide vision model parameters 113a to the tensor encoder 116, as described hereafter. The vision model parameters 113a include the spatial resolution of the frame data 113, used for bounding boxes (an example of the task result 151) to be scaled to correspond to the resolution of the frame data 113.

[0071] The arrangements described allow a different ‘inner codec’ to be selected and used based on implementation requirements. In the context of the arrangements described, the ‘inner codec’ relates to the functionality for encoding tensors reduced in dimensionality compared to the tensors 115 from the CNN backbone 114 (or a feature pyramid) for transmission between the source device 110 and the destination device 140, and correspondingly decoding a bitstream to produce compressed tensors after reception at the destination device 140, where the compressed tensors will be further processed to produce tensors 149, restored in dimensionality to correspond to the tensors 115. The ‘inner codec’ generates and decodes a bitstream in theexamples described. In other implementations, a different encoded output, for example a packed frame may be used.

[0072] Notwithstanding the example devices mentioned above, each of the source device 110 and destination device 140 may be configured within a general -purpose computing system, typically through a combination of hardware and software components. Fig. 2A illustrates such a computer system 200, which includes: a computer module 201; input devices such as a keyboard 202, a mouse pointer device 203, a scanner 226, a camera 227, which may be configured as the video source 112, and a microphone 280; and output devices including a printer 215, a display device 214 and loudspeakers 217. An external Modulator-Demodulator (Modem) transceiver device 216 may be used by the computer module 201 for communicating to and from a communications network 220 via a connection 221. The communications network 220, which may represent the communication channel 130, may be a (WAN), such as the Internet, a cellular telecommunications network, or a private WAN. Where the connection 221 is a telephone line, the modem 216 may be a traditional “dial-up” modem. Alternatively, where the connection 221 is a high capacity (e.g., cable or optical) connection, the modem 216 may be a broadband modem. A wireless modem may also be used for wireless connection to the communications network 220. The transceiver device 216 may provide the functionality of the transmitter 122 and the receiver 142 and the communication channel 130 may be embodied in the connection 221.

[0073] The computer module 201 typically includes at least one processor unit 205, and a memory unit 206. For example, the memory unit 206 may have semiconductor random access memory (RAM) and semiconductor read only memory (ROM). The computer module 201 also includes a number of input / output (VO) interfaces including: an audio-video interface 207 that couples to the video display 214, loudspeakers 217 and microphone 280; an I / O interface 213 that couples to the keyboard 202, mouse 203, scanner 226, camera 227 and optionally a joystick or other human interface device (not illustrated); and an interface 208 for the external modem 216 and printer 215. The signal from the audio-video interface 207 to the computer monitor 214 is generally the output of a computer graphics card. In some implementations, the modem 216 may be incorporated within the computer module 201, for example within the interface 208. The computer module 201 also has a local network interface 211, which permits coupling of the computer system 200 via a connection 223 to a local-area communications network 222, known as a Local Area Network (LAN). As illustrated in Fig. 2A, the local communications network 222 may also couple to the wide network 220 via a connection 224,which would typically include a so-called “firewall” device or device of similar functionality. The local network interface 211 may comprise an Ethernet™ circuit card, a Bluetooth™ wireless arrangement or an IEEE 802.11 wireless arrangement; however, numerous other types of interfaces may be practiced for the interface 211. The local network interface 211 may also provide the functionality of the transmitter 122 and the receiver 142 and communication channel 130 may also be embodied in the local communications network 222.

[0074] The VO interfaces 208 and 213 may afford either or both of serial and parallel connectivity, the former typically being implemented according to the Universal Serial Bus (USB) standards and having corresponding USB connectors (not illustrated). Storage devices 209 are provided and typically include a hard disk drive (HDD) 210. Other storage devices such as a floppy disk drive and a magnetic tape drive (not illustrated) may also be used. An optical disk drive 212 is typically provided to act as a non-volatile source of data. Portable memory devices, such optical disks (e.g. CD-ROM, DVD, Blu ray Disc™), USB-RAM, portable, external hard drives, and floppy disks, for example, may be used as appropriate sources of data to the computer system 200. Typically, any of the HDD 210, optical drive 212, networks 220 and 222 may also be configured to operate as the video source 112, or as a destination for decoded video data to be stored for reproduction via the display 214. The source device 110 and the destination device 140 of the system 100 may be embodied in the computer system 200.

[0075] The components 205 to 213 of the computer module 201 typically communicate via an interconnected bus 204 and in a manner that results in a conventional mode of operation of the computer system 200 known to those in the relevant art. For example, the processor 205 is coupled to the system bus 204 using a connection 218. Likewise, the memory 206 and optical disk drive 212 are coupled to the system bus 204 by connections 219. Examples of computers on which the described arrangements can be practised include IBM-PC’s and compatibles, Sun SPARCstations, Apple Mac™ or alike computer systems.

[0076] The tensor encoder 116, the tensor decoder 146 and methods to be described, may be implemented as one or more software application programs 233 executable within the computer system 200. In particular, the tensor encoder 116, the tensor decoder 146 and the steps of the described methods are effected by instructions 231 (see Fig. 2B) in the software 233 that are carried out within the computer system 200. The software instructions 231 may be formed as one or more code modules, each for performing one or more particular tasks. The software mayalso be divided into two separate parts, in which a first part and the corresponding code modules performs the described methods and a second part and the corresponding code modules manage a user interface between the first part and the user.

[0077] The software may be stored in a computer readable medium, including the storage devices described below, for example. The software is loaded into the computer system 200 from the computer readable medium, and then executed by the computer system 200. A computer readable medium having such software or computer program recorded on the computer readable medium is a computer program product. The use of the computer program product in the computer system 200 preferably effects an advantageous apparatus for implementing the source device 110 and the destination device 140 and the described methods.

[0078] The software 233 is typically stored in the HDD 210 or the memory 206. The software is loaded into the computer system 200 from a computer readable medium, and executed by the computer system 200. Thus, for example, the software 233 may be stored on an optically readable disk storage medium (e.g., CD-ROM) 225 that is read by the optical disk drive 212.

[0079] In some instances, the application programs 233 may be supplied to the user encoded on one or more CD-ROMs 225 and read via the corresponding drive 212, or alternatively may be read by the user from the networks 220 or 222. Still further, the software can also be loaded into the computer system 200 from other computer readable media. Computer readable storage media refers to any non-transitory tangible storage medium that provides recorded instructions and / or data to the computer system 200 for execution and / or processing. Examples of such storage media include floppy disks, magnetic tape, CD-ROM, DVD, Blu-ray Disc™, a hard disk drive, a ROM or integrated circuit, USB memory, a magneto-optical disk, or a computer readable card such as a PCMCIA card and the like, whether or not such devices are internal or external of the computer module 201. Examples of transitory or non-tangible computer readable transmission media that may also participate in the provision of the software, application programs, instructions and / or video data or encoded video data to the computer module 201 include radio or infra-red transmission channels, as well as a network connection to another computer or networked device, and the Internet or Intranets including e-mail transmissions and information recorded on Websites and the like.

[0080] The second part of the application program 233 and the corresponding code modules mentioned above may be executed to implement one or more graphical user interfaces (GUIs)to be rendered or otherwise represented upon the display 214. Through manipulation of typically the keyboard 202 and the mouse 203, a user of the computer system 200 and the application may manipulate the interface in a functionally adaptable manner to provide controlling commands and / or input to the applications associated with the GUI(s). Other forms of functionally adaptable user interfaces may also be implemented, such as an audio interface utilizing speech prompts output via the loudspeakers 217 and user voice commands input via the microphone 280.

[0081] Fig. 2B is a detailed schematic block diagram of the processor 205 and a “memory” 234. The memory 234 represents a logical aggregation of all the memory modules (including the storage devices 209 and semiconductor memory 206) that can be accessed by the computer module 201 in Fig. 2A.

[0082] When the computer module 201 is initially powered up, a power-on self-test (POST) program 250 executes. The POST program 250 is typically stored in a ROM 249 of the semiconductor memory 206 of Fig. 2 A. A hardware device such as the ROM 249 storing software is sometimes referred to as firmware. The POST program 250 examines hardware within the computer module 201 to ensure proper functioning and typically checks the processor 205, the memory 234 (209, 206), and a basic input-output systems software (BIOS) module 251, also typically stored in the ROM 249, for correct operation. Once the POST program 250 has run successfully, the BIOS 251 activates the hard disk drive 210 of Fig. 2A. Activation of the hard disk drive 210 causes a bootstrap loader program 252 that is resident on the hard disk drive 210 to execute via the processor 205. This loads an operating system 253 into the RAM memory 206, upon which the operating system 253 commences operation. The operating system 253 is a system level application, executable by the processor 205, to fulfil various high level functions, including processor management, memory management, device management, storage management, software application interface, and generic user interface.

[0083] The operating system 253 manages the memory 234 (209, 206) to ensure that each process or application running on the computer module 201 has sufficient memory in which to execute without colliding with memory allocated to another process. Furthermore, the different types of memory available in the computer system 200 of Fig. 2A need to be used properly so that each process can run effectively. Accordingly, the aggregated memory 234 is not intended to illustrate how particular segments of memory are allocated (unless otherwise stated), butrather to provide a general view of the memory accessible by the computer system 200 and how such memory is used.

[0084] As shown in Fig. 2B, the processor 205 includes a number of functional modules including a control unit 239, an arithmetic logic unit (ALU) 240, and a local or internal memory 248, sometimes called a cache memory. The cache memory 248 typically includes a number of storage registers 244-246 in a register section. One or more internal busses 241 functionally interconnect these functional modules. The processor 205 typically also has one or more interfaces 242 for communicating with external devices via the system bus 204, using the connection 218. The memory 234 is coupled to the bus 204 using the connection 219.

[0085] The application program 233 includes a sequence of instructions 231 that may include conditional branch and loop instructions. The program 233 may also include data 232 which is used in execution of the program 233. The instructions 231 and the data 232 are stored in memory locations 228, 229, 230 and 235, 236, 237, respectively. Depending upon the relative size of the instructions 231 and the memory locations 228-230, a particular instruction may be stored in a single memory location as depicted by the instruction shown in the memory location 230. Alternately, an instruction may be segmented into a number of parts each of which is stored in a separate memory location, as depicted by the instruction segments shown in the memory locations 228 and 229.

[0086] In general, the processor 205 is given a set of instructions which are executed therein. The processor 205 waits for a subsequent input, to which the processor 205 reacts to by executing another set of instructions. Each input may be provided from one or more of a number of sources, including data generated by one or more of the input devices 202, 203, data received from an external source across one of the networks 220, 202, data retrieved from one of the storage devices 206, 209 or data retrieved from a storage medium 225 inserted into the corresponding reader 212, all depicted in Fig. 2 A. The execution of a set of the instructions may in some cases result in output of data. Execution may also involve storing data or variables to the memory 234.

[0087] The tensor encoder 116, the tensor decoder 146 and the described methods may use input variables 254, which are stored in the memory 234 in corresponding memory locations 255, 256, 257. The tensor encoder 116, the tensor decoder 146 and the described methods produce output variables 261, which are stored in the memory 234 in correspondingmemory locations 262, 263, 264. Intermediate variables 258 may be stored in memory locations 259, 260, 266 and 267.

[0088] Referring to the processor 205 of Fig. 2B, the registers 244, 245, 246, the arithmetic logic unit (ALU) 240, and the control unit 239 work together to perform sequences of microoperations needed to perform “fetch, decode, and execute” cycles for every instruction in the instruction set making up the program 233. Each fetch, decode, and execute cycle comprises: a fetch operation, which fetches or reads an instruction 231 from a memory location 228, 229, 230; a decode operation in which the control unit 239 determines which instruction has been fetched; and an execute operation in which the control unit 239 and / or the ALU 240 execute the instruction.

[0089] Thereafter, a further fetch, decode, and execute cycle for the next instruction may be executed. Similarly, a store cycle may be performed by which the control unit 239 stores or writes a value to a memory location 232.

[0090] Each step or sub-process in the methods of Figs. 18 and 19, to be described, is associated with one or more segments of the program 233 and is typically performed by the register section 244, 245, 246, the ALU 240, and the control unit 239 in the processor 205 working together to perform the fetch, decode, and execute cycles for every instruction in the instruction set for the noted segments of the program 233.

[0091] Fig. 3A is a schematic block diagram 300 showing functional modules of a backbone portion 310 of a CNN. The diagram 300 which may serve as an implementation of the CNN backbone 114 when the system 100 is configured to perform a ‘YOLOv3’ network. The backbone portion 114 is sometimes referred to as ‘DarkNet-53’, although different backbones are also possible, resulting in a different number of and dimensionality of layers of the tensors 115 for each frame. In one implementation, the backbone portion 310 may be used as a person detector for the purpose of object tracking.

[0092] As shown in Fig. 3A, the video data 113 is passed to a resizer module 304. The resizer module 304 resizes each frame of the video data 113 to a resolution suitable for processing by the CNN backbone 310, producing resized frame data 312. If the resolution of the video data 113 is already suitable for the CNN backbone 310, operation of the resizer module 304 is not needed. The resized frame data 312 is passed to a convolutional batch normalisation leaky rectified linear (CBL) module 314 to produce tensors 316. The CBL module 314 contains modules as described with reference to a CBL module 360 as shown in Fig 3D.

[0093] The CBL module 360 takes as input a tensor 361 of the resized frame data 312. The tensor 361 is passed to a convolutional layer 362 to produce tensor 363. If the convolutional layer 362 has a stride of one, the tensor 363 has the same spatial dimensions as the tensor 361. If the convolution layer 362 has a larger stride, such as two, the tensor 363 has smaller spatial dimensions compared to the tensor 361, for example, halved in width and height for the stride of two. Regardless of the stride, the size of channel dimension of the tensor 363 may vary compared to the channel dimension of the tensor 361 for a particular CBL block. The tensor 363 is passed to a batch normalisation module 364, which outputs a tensor 365. The batch normalisation module 364 normalises the input tensor 363 and applies a scaling factor and an offset value to produce the output tensor 365. The scaling factor and offset value are derived from a training process. The tensor 365 is passed to a leaky rectified linear activation (“LeakyReLU”) module 366 to produce a tensor 367. The module 366 provides a ‘leaky’ activation function whereby positive values in the tensor are passed through and negative values are severely reduced in magnitude, for example, to 0. IX their former value.

[0094] Returning to Fig. 3 A, the tensor 316 is passed from the CBL block 314 to a residual block module 320, such as a ‘resl+2+8’ module (also referred to as a resl 1 module) containing a concatenation of three residual blocks, each residual block containing one (1) residual unit, two (2) residual units, and eight (8) residual units, respectively. The spatial resolution of the tensors is halved horizontally and halved vertically in each of the residual blocks (see Fig. 3B) by a convolution with stride equal to two in a CBL block 344.

[0095] A residual block is described with reference to a ResBlock 340 as shown in Fig. 3B. The ResBlock 340 receives a tensor 341. The tensor 341 is zero-padded by a zero-padding module 342 to produce a tensor 343. The tensor 343 is passed to the CBL module 344 to produce a tensor 345. The CBL module 344 contains a convolution (for example 362) with a stride parameter set to two, resulting in the tensor 345 having half the width and half the height of the tensor 343. The tensor 345 is passed to a residual unit 346. The residual unit 346contains a series of concatenated residual units, based on the number of residual block (for example, eleven (11) units for the block 320). The last residual unit of the residual units 346 outputs a tensor 347.

[0096] A residual unit is described with reference to a ResUnit 350 as shown in Fig. 3C. The ResUnit 350 takes a tensor 351 as input. The tensor 351 is passed to a CBL module 352 to produce a tensor 353. The tensor 353 is passed to a second CBL unit 354 to produce a tensor 355. An add module 356 sums the tensor 355 with the tensor 351 to produce a tensor 357. The add module 356 may also be referred to as a ‘shortcut’ as the input tensor 351 substantially influences the output tensor 357. For an untrained network, ResUnit 350 acts to pass-through tensors. As training is performed, the CBL modules 352 and 354 act to deviate the tensor 357 away from the tensor 351 in accordance with training data and ground truth data.

[0097] Returning to Fig. 3 A, the Resl 1 module 320 outputs a tensor 322. The tensor 322 is output from the backbone module 310 as one of the layers and also provided to a Res8 module 324. The Res8 module 324 is a residual block (i.e., 340), which includes eight residual units (i.e. 350). The Res8 module 324 produces a tensor 326. The tensor 326 is passed to a Res4 module 328 and output from the backbone module 310 as one of the layers. The Res4 module is a residual block (i.e., 340), which includes four residual units (i.e., 350). The Res4 module 328 produces a tensor 329. The tensor 329 is output from the backbone module 310 as one of the layers. Collectively, the layer tensors 322, 326, and 329 are output as the tensors 115 and may be referred to as layers 0-2 or L0, LI, and L2, respectively. The backbone CNN 310 may take as input a video frame of resolution 1088x608 and produce three tensors, corresponding to three layers, with the following dimensions: [1, 256, 76, 136], [1, 512, 38, 68], [1, 1024, 19, 34], Another example of the three tensors 115 corresponding to three layers may be [1, 512, 34, 19], [1, 256, 68, 38], [1, 128, 136, 76] which are respectively separated at layer index 75, 90, and 105 when the layers are enumerated according to the YOLOv3 software implementation of the backbone 300 and a head 1200.

[0098] Each of the Resl 1 320, Res8 324 and Res4 328 operates in a similar manner to ResBlock 340. Each of the CBL 314, the CBL 344 and the CBL 354 operate in a similar manner to the CBL 360.

[0099] Fig. 4 is a schematic block diagram showing functional modules of an alternative backbone portion 400 of a CNN, which may serve as an implementation of the CNN backbone 114 when the system 100 is configured to perform a “FasterRCNN” or“MaskRCNN” ResNet 101 network. Frame data 113 is input and passes through a stem network 408, a res2 module 412, a res3 module 416, a res4 module 420, and a res5 module 424 via tensors 409, 413, 417, 421, 425 respectively. The backbone portion 400 may be used as part of a general object detector or for instance segmentation, with various classes of object supported.[000100] The stem network 408 includes a convolution with a kernel size of 7x7 and a stride of two (2) and a max pooling operation. The res2 module 412, the res3 module 416, the res4 module 420 and the res5 module 424 perform convolution operations, such as LeakyReLU activations. Each module 412, 416, 420 and 424 also performs one halving of the width and height of the processed tensors via a stride setting of two. Each of the tensors 413, 417, 421 and 425 are passed to one of 1x1 lateral convolution modules 446, 444, 442 and 440 respectively. The modules 446, 444, 442, and 440 produce tensors 447, 445, 443 and 441 respectively. The tensor 441 is passed to a 3x3 output convolution module 470, which produces an output tensor P5 471.[000101] The tensor 441 is also passed to upsampler module 450 to produce an upsampled tensor 451. A summation module 460 sums the tensors 443 and 451 to produce a tensor 461. The tensor 461 is passed to an upsampler module 452 and a 3x3 lateral convolution module 472. The module 472 outputs a P4 tensor 473. The upsampler module 452 produces an upsampled tensor 453. A summation module 462 sums tensors 445 and 453 to produce a tensor 463. The tensor 463 is passed to a 3x3 lateral convolution module 474 and an upsampler module 454. The module 474 outputs a P3 tensor 475. The upsampler module 454 outputs an upsampled tensor 455. A summation module 464 sums the tensors 447 and 455 to produce tensor 465, which is passed to a 3x3 lateral convolution module 476. The module 476 outputs a P2 tensor 477. The upsampler modules 450, 452, and 454 use nearest neighbour interpolation for low computational complexity. The tensors 471, 473, 475, and 477 form the output tensors 115 of the CNN backbone 400. Although Fig. 4 shows a particular backbone portion of the Faster RCNN network architecture (a ‘P-layer split point), different divisions into backbone and head are possible. Splitting the network at tensor 409 is termed a ‘stem’ split point. Splitting the network at tensors 447, 445, 443, and 441 is termed a ‘C-layer’ split point.[000102] The bitstream includes a plurality of network abstraction layer (NAL) units. Fig. 10 is a schematic block diagram showing the structure of a NAL unit 1000. Each NAL unit is prefixed with a start code 1010, consisting of three contiguous bytes having values of 0x00, 0x00, and 0x01. The start code 1010 is followed by a NAL unit header 1012. The NAL unitheader 1012 is of a format as described with reference to Appendices A, B, and C, for AVC, HEVC, and VVC, respectively. For HEVC and VVC the NAL unit header 1012 is a predetermined length that is always two bytes. For AVC, the NAL unit header 1012 is a predetermined length of either one, three or four bytes, i.e., different to the predetermined length for the other codecs. The NAL unit header 1012 includes a nal unit type, used to identify the parsing process to be applied to parse a raw bitstream sequence payload (RBSP) 1020. The NAL unit type is either a five- or six -bit fixed length code and includes ‘reserved’ values, which may be defined as part of a future revision of the respective specification (AVC, HEVC, or VVC) and ‘unspecified’ values, which will not be used in future versions of the AVC, HEVC, or VVC standards and are instead available for use by other bodies wishing to extend to encoding methods other than AVC, HEVC, or VVC. To avoid detection of false start codes that may be present in the RBSP by chance, the RBSP 1020 is encapsulated into a NAL unit payload 1014 with a process of insertion of ‘emulation prevention bytes’. In forming the NAL unit payload 1014, whenever a two-byte sequence 0x00 0x00 is encountered in the RBSP 1020, such as zero bytes 1016, an ‘emulation_prevention_three_byte’, such as byte 1018, having value 0x03, is inserted immediately following the zero bytes 1016. The process of emulation_prevention_three_byte insertion to form the NAL unit payload 1014 from the RBSP 1020 ensures an absence of any false start codes that would trigger erroneous parsing of the bitstream 121. The start of the RBSP 1020 is the earliest position at which detection of two zero bytes for the purpose of emulation_prevention_three_byte insertion is possible, which would take place between the second and third byte of the RBSP 1020. To prevent false start code detection in the early bytes (first or second) of the RBSP 1020, the last byte of the NAL unit header 1012 needs to be nonzero.[000103] For HEVC and VVC, the last syntax element of the NAL unit header 1012 is ‘nuh_temporal_id_plusl’, coded with a three-bit fixed-length codeword and prohibited from using the bit string “000”. For HEVC and VVC the NAL unit header 1012 is always a predetermined length of two bytes in length. For AVC, when using a one-byte NAL unit header (that is the predetermined length of the NAL unit header is one byte rather than three bytes or four bytes), the nal unit type needs to be avoided. For AVC, nal unit type equal to 0 may be marked as ‘reserved’ or ‘prohibited’ indicating that nal unit type is not available for use by other bodies outside of one responsible for issuing new versions of the AVC specification. In the implementation described, the nal unit type of 0 shall not be used, preventing the possibility of a NAL unit header for AVC consisting of a zero byte.[000104] A bit ‘forbidden zero bit’, a single bit always set to value zero, is coded as the first bit to be parsed (in bit position 7, as bit consumption in each byte progresses from bit 7 down to bit 0), in the NAL unit header 1012, regardless of the usage of AVC, HEVC, or VVC as “inner codec”. The forbidden zero bit may be used to signal an alternative NAL unit header format, containing a different space for NAL unit types, such as the FCM VMPS, FCM_SPS, and FCM PPS NAL units. Standards such as RFC6184 include functionality to set the forbidden zero bit in a NAL unit header when transmission errors are detected in received data that forms a NAL unit payload associated with the NAL unit header.[000105] A decoder conforming to AVC, HEVC, or VVC, is not required to decode NAL units with the forbidden zero bit set. In some implementations, the decoder may attempt to decode NAL units with the forbidden zero bit set anyway to provide output frame data that is likely corrupted but may be more desirable than discarding the NAL unit and not provide any associated output frame data. In the context of FCM, tensor compression involves a reduction into a smaller dimensionality space, quantisation, and generally packing into a video frame and coding the video frame with a conventional video codec. Coding of the video frame is known as an ‘inner codec’ as this is performed as a stage in the FCM ‘outer’ codec. Reuse of a conventional video codec (such as VVC, HEVC or AVC) permits deployment of the FCM standard onto existing system-on-chips by reusing codec implementations already provided by ASIC vendors.[000106] Fig. 5 is a schematic block diagram 500 of an example implementation of the tensor encoder 116 using a configurable tensor compressor stage, a tensor data type adaptation stage, and a tensor dimensionality adaptation stage, and a selectable video encoder 542, also referred to as the "inner codec". The video encoder 542 implements one of several video standards, such as AVC, HEVC, or VVC. The video encoder 542 may also implement a customised compression method, such as lossless CABAC encoding of each quantised value in the input tensors 115, using an algorithm such as ISO / IEC 15938-17, also known as “deepCABAC”.[000107] Fig. 11 is a schematic block diagram showing the bitstream 121 or 143 holding encoded packed feature maps, parameter sets for the FCM codec and parameter sets for the inner codec.[000108] Fig. 18 shows a method 1800 for performing a first portion of a CNN, selecting a tensor compressor, compressing tensors using the selected tensor compressor, and encoding resulting compressed tensors using a video encoder conforming to a selected video compressionstandard. The tensor encoder 116 (and the example implementation 500) and the method 1800 may be implemented as one or more software application programs 233 executable within the computer system 200. The tensor encoder 116 and the method 1800 may be effected by instructions 231 (see Fig. 2B) in the software 233 that are carried out within the computer system 200. The software instructions 231 may be formed as one or more code modules, each for performing one or more particular tasks. The method 1800 commences at a select inner codec step 1801.[000109] At the step 1801, the processor 205 selects one video compression standard out of a plurality of video compression standards. AVC, HEVC, and VVC may be options for selection at step 1801 and the video compression standard selected may be dependent on considerations such as the capabilities of the source device 110 and the destination device 140. A capabilities negotiation may take place between the source device 110 and the destination device 140 whereby a selection is made such that the same compression standard is used in each device, prioritising VVC over HEVC and HEVC over AVC. Selection at step 1801 may be constrained based on a profile of the FCM standard, such that a smaller set of compression standards is available, such as HEVC and AVC, from which one is selected based on the aforementioned capabilities negotiation step. Rather than selecting a repurposed video codec for compressing features, specific FCM profiles may select a customised approach such as compressing quantized values of features using deepCAB AC, with or without prediction of values within a feature map or from one feature map to another. Such customised approaches may be targeted applications where achieving low bitrate is a secondary consideration compared to achieving very low complexity, for example. In typical use, the selection of the step 1801 is performed one time and thus does not change during the course of encoding one bitstream. Arrangements may select a different inner codec during coding of the bitstream 121 provided that the switch from one inner codec to a different inner codec is made prior to encoding a new group-of- pictures (GOP), i.e., prior to a new “intra random access picture” (HEAP) or “instantaneous decoder refresh” (IDR) picture. Control in the processor 205 progresses from the step 1801 to an encode inner codec identifier step 1802.[000110] At the step 1802, a metadata encoder 544, under execution of the processor 205, encodes an identifier for the selection of which inner codec to use from step 1801 to FCM metadata 548. The identifier is encoded using a NAL unit, in particular as an “inner codec identifier NAL (ICI) unit” 1110 (see Fig. 11). A NAL unit multiplexor 550 multiplexes the NAL unit 1110 from the FCM NAL units bitstream 548 into the bitstream 121. The syntax described with reference to Appendix D is used to encode the selected inner codec. Asdescribed in Appendix D, an inner codex identifier NAL unit 1110 has a fixed length of one- byte, i.e., having a one-byte header and no RBSP, distinguishing such NAL units from all HEVC and VVC NAL units. A five-bit code of “11111” (decimal 31), which occupies bit positions corresponding to “nal unit type” in the AVC standard, distinguishes the NAL unit from an extension to the AVC standard. Notably, the “forbidden zero bif ’, common to AVC, HEVC, and VVC, is retained as a bit always set to the value of zero. The “forbidden zero bif ’ remains free to be used for other purposes, such as indication of errors at the transport layer, which is outside of the scope of the AVC, HEVC, and VVC standards. A two-bit codeword “inner codec identifier”, occupying the same bit positions as the “nal ref idc” syntax element of the AVC standard, signals which one of AVC, HEVC, or WC, or a custom codec are to be used. An instance of the inner codec identifier NAL unit is required at each random-access entry point into the bitstream, that is, required at the start of the bitstream and prior to each IRAP or IDR picture 1122 and associated parameter sets, such as an SPS (sequence parameter set) 1118 and a PPS (picture parameter set) 1120, as shown in Fig. 11. Each of the SPS 1118 and the PPS 1120 contain NAL unit headers of the format indicated by the inner codec identifier 1110. As a result of the inner codec identifier NAL unit 1110, the format of NAL unit headers of subsequent NAL units is known. Thus, the NAL unit headers are parseable, when any one of the AVC, HEVC, or WC may be used as inner codecs in the bitstream 121. The step 1802 can operate to encode the inner codec identifier NAL unit 1110 and associated codewords forbidden zero bit, inner codec identifier and constant_value_31 (as per the example of Appendix D) for the selected inner encoder to the bitstream 121. The step 1802 operates to encode a NAL unit to the bitstream having a predetermined length, wherein the NAL unit of the predetermined length corresponds to possible NAL units of one of the selectable inner codecs (AVC) but the bit field (at bit positions four down to zero) that would indicate nal unit type in the case of AVC indicates a reserved or prohibited codeword (such as Oxlf or 31 or Obi 1111). Instead, the presence of binary value Obi 1111 at bit positions four down to zero indicate this NAL unit selects one inner codec out of a of a plurality of inner codecs (AVC, VVC, HEVC, custom for example). The other potential inner codecs (HEVC, VVC, custom) have NAL unit lengths different to the predetermined length possible for AVC (i.e., one byte), as described above. Since a NAL unit with one byte length (excluding the start code) only appears for AVC and for the inner codec identifier, any such NAL unit can be unambiguously parsed, based on bits four down to bit zero, to determine whether the NAL unit is intended for parsing by an AVC inner codec for an inner codec identification purpose. A bitstream must an inner codec identifier NAL unit, to select an inner codec, prior to any NAL units intended to be parsed by the selected inner codec.[000111] Additional NAL units conveying parameters for modules aside from the inner codec, such as an FCM VMPS (vision model parameter set) 1112, an FCM SPS 1114, and an FCM PPS 1116 use the same NAL unit header format as the inner codec and thus must also follow the inner codec identifier NAL unit 1110. As indicated in Appendix D, a custom inner codec may also be selected at step 1801 and encoded at step 1802. When a custom inner codec is selected, a custom NAL unit header format is used (and encoded at step 1802), which may duplicate the bit fields of an existing standard such as VVC. A custom codec typically requires a custom enumeration of NAL unit types and support the selection of one out of a plurality of inner codecs, to provide an extensiblity mechanism. Selections can include direct deepCABAC coding of tensor values, intra-predictive deepCABAC coding of tensor values, tensor encoding using an end-to-end learned codec such as the approach described in paper “Learned Image Compression with Discretized Gaussian Mixture Likelihoods and Attention Modules” by Cheng et al. NAL units (such as the FCM VMPS 1112, the FCM SPS 1114, and the FCM PPS 1116) defining parameters within the FCM standard scope but outside of the inner codec scope are referred to as ‘FCM NAL units’, and the enumerated nal_unit_type of FCM NAL units is dependent on the selected inner codec, since each standard of AVC, HEVC, and VVC has different enumerations of nal unit type and different ‘unspecified’ values, available for use such as by the FCM standard. In one example, nal unit type of the FCM VMPS 1112 is described with reference to Appendices A-C for AVC, HEVC and VVC inner codecs respectively (nal_unit_type of FCM VMPS is 24 for AVC, 48 for HEVC, and 28 for VVC). Also, nal unit type of the FCM SPS and nal unit type of the FCM PPS are described with reference to Appendices A-C for AVC, HEVC and VVC inner codecs respectively. As with the HLS (high level syntax) design of the inner codec, the syntax of the FCM PPS and the FCM SPS are intended to avoid parsing dependencies, i.e., an FCM PPS can be parsed regardless of the loss of the FCM SPS for the bitstream. It should be noted that due to the differing NAL unit header format among the inner codecs, loss of the ICI NAL unit prevents parsing of any other NAL units in the bitstream. Also, as with the inner codec NAL format, emulation prevention bytes are inserted as needed into the FCM NAL units to avoid possible false start code detection. The inner codec identifier NAL unit 1110 needs to precede the FCM NAL units in order for the tensor decoder 146 to parse the bitstream 121. The NAL unit 1110 is therefore usually encoded at the start of the bitstream by the step 1802. However, multiple instances of the NAL unit 1110 including the NAL unit header can be present in the bitstream 121, as encoded by step 1802. The multiple instances can, for example be present at the start of the bitstream before other NAL units and one or more instances may be prior to any ‘random access’ (entry) point into the bitstream, such as prior to periodic intra random access pictures(IRAPs) that may be coded in the bitstream 121. If a different inner codec is selected at step 1801 during coding of the bitstream 121 as describe above, i.e., a switch from one inner codec to a different inner codec, a plurality of inner codecs are used in the bitstream and NAL units 1110 are encoded to the bitstream correspondingly at step 1802. Also, regardless of the inner codec in use and the assigned nal unit type, the syntax structure for each parameter set (FCM VMPS1 12, the FCM SPS1114, and the FCM PPS 1116) is unchanged. Control in the processor progresses from the step 1802 to an encode FCM Vision model parameter set (VMPS) step 1803.[000112] At the step 1803, the metadata encoder 544, under execution of the processor 205, encodes vision model parameters 113a, used for the operation of the CNN head 150, as the FCM VMPS 1112 as FCM metadata 548. In one implementation, the FCM VMPS 1112 may include output_picture_width and output_picture_height (width and height of output pictures) for the vision model parameters 113a, as shown in the example of Appendix E. The NAL unit type (nal unit type) of the FCM VMPS 1112 is dependent on the inner codec selected at step 1801. NAL unit types of the FCM VMPS are described with reference to Appendices A-C for AVC, HEVC and VVC inner codecs respectively. The vision model parameters 113a include the spatial resolution of the frame data 113, needed for bounding boxes (an example of the task result 151) to be scaled to correspond to the resolution of the frame data 113, which is not otherwise known by the destination device 140. Control in the processor 205 progresses from the step 1803 to a select set of tensor compressors / decompressors step 1805.[000113] At the step 1805, a tensor compressor selector 510, under execution of the processor 205, selects a set of mechanisms that may be used for compressing and decompressing intermediate tensors. Each mechanism of the set forms a ‘bottleneck’ and corresponds to an encoder network topology coupled to a decoder network topology. The interface between the encoder network topology and the decoder network topology is the narrowest and hence the layer with most reduced dimensionality. The interface between the encoder network topology and the decoder network topology also includes one or more tensors that may be referred to as ‘compressed tensors’ . The one or more tensors may be produced from operations such as convolutions, batch normalisations, activation functions, or matrix multiplications, tensor additions and / or subtractions. The dimensionality of tensors at the interface between the encoder network topology and the decoder network topology may vary from one invocation of the method 1800 to a next invocation of the method 1800 (e.g., the channel count may vary). Support for a plurality of mechanisms in one bitstream enablesadapting to changing network conditions and application requirements by switching from one mechanism to another dynamically. For example, an object segmentation network may operate using a mechanism providing low bitrate at the expense of lower quality output (resulting in lower mAP) of the task result 151 from the CNN head 150.[000114] Each mechanism selected at the step 1805 needs to match the dimensionality of the tensors 115 at the input to the encoder network topology and output of the decoder network topology in order to be compatible with the neural network formed by the backbone 114 and the head 150. Tensors in compressed form, (i.e., at the ‘bottleneck’ point or output from the encoder network topology and input to the decoder network topology), may have varying number and dimensionality. Where a mechanism involves the use of trainable elements, such as convolutions, the tensor compressor selector 510 also determines selected weights 516 to be used by the encoder network topology and the decoder network topology. Multiple weights may be available for a given encoder network topology and decoder network topology, such as different weights targeting different quality operating points. Control in the processor 205 progresses from the step 1805 to a select tensor compressor / decompressor step 1810.[000115] At the step 1810, the tensor compressor selector 510, under execution of the processor 205, selects a mechanism to be used for compression and decompression of the tensors 115. The tensor compressor selector 510 outputs a selected tensor decompressor 512 and associated metadata 520. The selection made at the step 1810 is from the set determined at the step 1805. The selection may be the result of a request by the destination device via an out- of-band signalling mechanism to increase or decrease the decoded quality (and hence the bit- rate) of the bitstream 121. Where a mechanism is parameterizable (e.g., the channel count of one or more of the compressed tensors may be varied dynamically), a suitable value is selected at the step 1810.[000116] The system 100 performs a given neural network which is divided into a first portion, performed by the CNN backbone 114, and a second portion, performed by the CNN head 150. The first portion of the neural network may be a Darknet-53 backbone as described with reference to Figs. 3 A-3D, a backbone of a FasterRCNN or MaskRCNN network, as described with reference to Fig. 4, or a first portion of some other neural network. The number and dimensionality of the tensors 115 depends on the network being implemented in the system 100 and the division of the network into a first portion, executed in the CNN backbone 114, and a second portion, executed in the CNN head 150. Compression and decompression mechanismsinvolve an encoder network topology, to be performed in the source device 110, and a decoder network topology, to be performed in the destination device 140.[000117] The encoder network topology and decoder network topology may involve the use of trained layers, such as convolutions, in which case weights are also needed. The encoder network topology and the decoder network topology form a ‘bottleneck’ between the first network portion (i.e., the CNN backbone 114) and the second network portion (i.e., the CNN head 150), with the interface between the encoder network topology and the decoder network topology forming the ‘narrowest’ part of the bottleneck and thus the lowest bitrate when compressed in the form of packed video frames. Different mechanisms (encoder network topologies and corresponding decoder network topologies) may be selected, signalled, and activated dynamically to adapt the bitrate of the bitstream 121 to network conditions or to adjust to meet application requirements for quality. Mechanisms or topologies providing higher quality generally have larger dimensions of the compressed tensors and hence require a larger packed frame area, resulting in a higher bitrate for the bitstream 121. Control in the processor 205 progresses from the step 1810 to an instantiate tensor compressor step 1815.[000118] At the step 1815, the source device 110, under execution of the processor 205, obtains a tensor structural description 522 from a tensor codec repository 514 based on the selected tensor decompressor 512. The source device 110 instantiates the tensor structural description 522 into a form suitable for execution by the tensor compressor 530. The instantiating step 1815 may involve declaring required memory and initialising data structures in the memory 205 associated with the tensor structural description 522, or allocating resources in a reconfigurable hardware device such as a field programmable gate array (FPGA). Operations defined in the tensor structural description 522 may be converted to a form more amenable for execution by the processor 205 as part of the instantiation step 1815. ‘Just-in- time compilation’ is one approach for obtaining a representation such as a ‘byte code’ that may be executed more rapidly by the processor 205 than interpreting the tensor structural description 522 directly to perform each tensor compression operation. Where the instantiated tensor compressor 530 contains trainable elements, such as convolutions, a tensor weight repository 518 is accessed to obtain necessary weights 524 for use by the trainable elements, with the weights selected based on the weight selection 516. The tensor codec repository 514 and the tensor weight repository 518 may be populated from the tensor codec repository 180. Control in the processor 205 progresses from the step 1815 to a determine complexity indication step 1830.[000119] At the step 1830, the source device 110, under execution of the processor 205, determines an indication representative of a worst-case complexity for any decoder network topology that could be signalled for the bitstream 121. Where the source device 110 may select one topology from multiple possible decoder network topologies at the step 1810 it is desirable for the destination device 140 to know, at the beginning of decoding the bitstream 121, whether the destination device 140 will be able to decode the entirety of the bitstream. The first signalled decoder network topology in the bitstream 121 may not be the most complex topology used for decoding that bitstream 121. For example, the system 100 may commence operation in a low bitrate mode, later increasing bitrate (and required decoder network topology) based on some criteria. Aspects of decoder network complexity include the number of multiply-and- accumulate (MAC) operations and the number of weights required to execute the decoder network topology. The decoder network complexity indication is configured to indicate the highest complexity of all possible decoder network topologies that the source device 110 may instruct the destination device 140 to perform. The decoder network complexity indication may be based on a decoded capability indication. In one arrangement, the decoder network complexity indication may be a scalar value mapped onto each aspect of the network complexity. For example, the network complexity indication may be a scalar value that relates to aspects such as MAC count and weight count by reference to look-up tables, with the network complexity indication set to accommodate the worst-case aspect of each aspect of the set of decompressors determined at the step 1805. Control in the processor 205 progresses from the step 1830 to a perform neural network first portion step 1840.[000120] At the step 1840, the CNN backbone 114, under execution of the processor 205, performs the first portion of a neural network using frame data 113 from the video source 112 as input. The step 1840 outputs the tensors 115. Control in the processor 205 progresses from the step 1840 to a perform tensor downsampling step 1850.[000121] At the step 1850, a tensor downsampler 520 performs a temporal decimation operation on the tensors 115 to produced temporal downsampled tensors 524. When a downsampling ratio of two is selected, tensors of every alternate (e.g., frames with an odd picture order count) are dropped, resulting in a halving of the frame rate for the tensors 524 compared to the frame rate of the frame data 113. Other downsampling ratios, such as three to one, four to one are possible with signalling to support any integer ratio. However, a maximum limit, such as an example maximum ratio of four, is needed to prevent the need for excessive tensor buffering. The downsampling ratio is signalled in the FCM PPS 1116 when fcm_pps_temporal_upsampling_enabled_flag is equal to one, allowing the ratio to alteredduring the course of one bitstream. The tensor downsampler 520 may be configured into an active state, where tensor downsampling is performed, or into a bypass state, where the tensors 115 are propagated to the tensors 524 with no alteration. Configuration of the tensor downsampler 520 into active or bypassed state may be predetermined, e.g., by user configuration, or may be altered during operation of the source device 110, such as in response to available bandwidth of the communications channel 130 or the level of detected activity such as the number of bounding boxes in the task result 151. The fcm_pps_temporal_upsampling_enabled_flag in the FCM PPS 1116 is encoded (see 18110 below) regardless of the value of the fcm sps temporal upsampling enabled flag in the FCM SPS 1114 to avoid a parsing dependency of the FCM PPS 1116 on the FCM SPS 1114. However, the fcm_pps_temporal_upsampling_enabled_flag is not permitted to be enabled (1) when the fcm sps temporal upsampling enabled flag is set to disabled (0). Control in the processor 205 progresses from the step 1850 to a perform tensor compression step 1860.[000122] At the step 1860, a tensor compressor 530, under execution of the processor 205, compresses the tensors 524 to produce compressed tensors 532. The compressed tensors 532 are fewer in number than the tensors 524 and reduced in dimensionality (i.e., reduced in either or both of channel count and feature map width and height). The compressed tensors 532 form a representation of the tensors 524 that may be referred to as the ‘reduced domain’ or ‘feature reduced domain’ and the operation of the tensor compressor 530 may be referred to as ‘feature reduction’ . The tensor compressor 530 may implement the instantiated tensor compressor 512 in the form of precompiled ‘byte code’ or machine code or other form more amenable to direct execution by the processor 205, including by an inferencing engine as part of or associated with the processor 205, such as a graphics processing unit (GPU). The step 1860 operates to produce the tensors 532 from the tensors produced at step 1840. The tensor downsampler 520 may be configured into an ‘active’ state where the instantiated tensor compressor 512 is used to produce the tensors 532 or into a ‘bypass’ state where the tensors 524 are passed along as the tensors 532 without modification. When in the active state, the tensors 532 have at least a smaller tensor count, a smaller channel count, or a smaller spatial size compared to the tensors 524. Control in the processor 205 progresses from the step 1860 to a quantise tensors step 1870.[000123] At the step 1870, a quantiser module 534, under execution of the processor 205, when configured into an ‘active’ state quantises floating-point values in each tensor of the compressed tensors 532 to produce quantised compressed tensors 536. The quantised compressed tensors 536 have integer values and occupy a range within a sample range asdefined by the operational bit depth of the video encoder 542. For example, when encoding video using 8-bit, or 10-bit samples, integer values in the interval [0, 255] or [0, 1023], respectively, are permitted. Quantisation firstly normalises elements from the tensor 532 into a [0.0, 1.0] floating-point range, resulting in one minimum and one maximum floating-point value for the tensor 532. A tensor normalised into the [0.0, 1.0] range is then converted and rescaled into an integer sample range, such as [0, 1023] or [0, 255], For each tensor, the minimum and maximum floating-point values form a quantisation range 526 for the first normalisation and the range for the second normalisation (to integer sample range) is dependent on the bit-depth of the video encoder 542. The normalisation to integer range may operate on a minimum and a maximum value that is updated from one frame to the next such that the minimum value is either decreased based on the current tensors 532 or retains the same value as derived for the previous tensors 532 (i.e., the tensors from the previous performance of the step 1860). The maximum value of the integer range is either increased based on the current tensors 532 or retains the same value as computed for the previous tensors 532. The quantiser module 534 can be configured into a ‘bypass’ state where the tensors 532 are passed along as the tensors 536. Configuration into the ‘bypass’ state may be applied when the tensors 532 already contain integer values or when the selected video encoder 542 is capable of encoding tensor values in floating-point format. Control in the processor 205 progresses from the step 1870 to a pack tensors step 1880.[000124] At the step 1880, a packer module 538, under execution of the processor 205, packs the feature maps of the tensor 536 into a frame, forming a packed feature frame 540. Operation of the packer module 540 generally results in placement of the two-dimensional feature maps into an arrangement as described with reference to Fig. 9B. When multiple tensors are present in the tensors 536, a frame 900b is of sufficient size to hold feature maps for all the tensors of the tensors 536. Control in the processor 205 progresses from the step 1880 to an encode frame step 1890.[000125] At the step 1890, the video encoder 542 (selected at operation of the step 1801 and having a corresponding identifier encoded at step 1802), under execution of the processor 205, compresses the video frame 540 to produce a compressed video bitstream 546. The encoder 542 is selected to embody one compression approach out of multiple compression approaches in accordance with the selection of step 1801. In the case of the use of H.266 / VVC, operation of the video encoder 542 is described with reference to Fig. 8. In the case of H.265 / HEVC or H.264 / AVC, operation involves generally subsets of the functional modules as described with reference to Fig. 8. The first packed frame 540 to be coded results in theSPS 1118 and the PPS 1120, followed by the IRAP picture 1122 (referred to as an ‘instantaneous decoder refresh’ picture I H.264 / AVC) as shown in Fig. 11. When using a low- delay coding configuration a subsequent picture would be coded as inter-picture 1124. In the case of a customised compression approach, a method such as directly compressing each value in the tensors 536 using an arithmetic coder such as deepCABAC or variable-length coding such as exponential Golomb coding may be applied, with the frame packing step 1880 omitted. Control in the processor 205 progresses from the step 1890 to an encode FCM SPS step 18100.[000126] At the step 18100, the metadata encoder 544 encodes sequence-level parameters needed for the FCM decoder into the FCM sequence parameter set 1114 as part of the FCM metadata 548. The FCM SPS 1114 includes tensor information specifying the dimensionality of the compressed tensors 532 and the placement of feature maps as packing information for each tensor among the compressed tensors 532 into a video frame 540. The tensor information includes, for each tensor, a maximum channel count and a used channel count. The frame area for a region must be sufficient for the tensors within the region to be packed up to the maximum channel count, i.e., the maximum number of feature maps. Flags signalling the application or bypass of the inner decoding, corresponding to the encoding at 1890, inverse quantisation corresponding to quantisation performed at step 1870, and feature restoration corresponding to feature compression performed at step 1860, and temporal upsampling step, corresponding to downsampling performed at step 1850, are also included in the FCM SPS 1114.[000127] The metadata encoder 544, under execution of the processor 205, at step 18100 encodes the selected tensor decompressor 520 into the bitstream 121 as a decoder network topology in the FCM SPS 1114, as described with reference to Fig. 11. The selected tensor decompressor 520 may be signalled as an explicit network topology, using a textual representation (or syntax) such as Open Neural Network Exchange (‘ONNX’) format or Neural Network Exchange Format (‘NNEX’), from the Khronos Group, or using other formats including a short code fragment such as a Pytorch function. Compression of textual representations of the tensor decompressor using techniques such as a ‘DEFLATE’ or ‘LZMA’ algorithm may be applied to reduce the overhead of the metadata when stored in the bitstream 121. As such, information (such as the textual representation or the syntax described above) representing the network topology is signalled in compressed form.[000128] The decoder network topology information representing the decoder network topology is to be decoded from the bitstream 143 on the destination device 140 to determine thenetwork topology to be used on the destination device 140. The decoder network topology specifies operations to be performed in the destination device 140 to convert tensors from a compressed representation to their original number and dimensionality, such that the uncompressed tensors may be supplied to the CNN head 149. When the network topology is selected by reference to a collection of network topologies, such as available in the tensor codec repository 514, and associated weights as available in the tensor weight repository 518, a registered decoder idc syntax element is used. The registered decoder idc syntax element may provide a direct index into a look-up table, a string or universally unique identifier (UUTD) to perform an associative look-up to obtain the selected decoder network topology and weights. The network weights may also be signalled in the FCM SPS 1114 using a format such as ISO / IEC 15938-17 “Compression of Neural Networks for Multimedia Description and Analysis”. When signalling information representing a given network topology, the given network topology may be registered with the destination device 140 for reference and activation in subsequent bitstreams, avoiding the need to signal information representing the network topology with every bitstream. In one arrangement, the system 100 may provide predetermined network topologies that do not need to be explicitly signalled in the bitstream. Predetermined network topologies may be activated in the destination device 140 via a reference to an identifier. Predetermined network topologies may be made available to the destination device 140 via external means, such as downloaded from a repository or registry of network topologies. Repositories or registries of network topologies may be accessible publicly or may be accessible within some private scope, for example, obtained via a private network or a secure network (e.g., VPN) available to instances of the destination device 140 but not the general public. Where the destination device 140 is known to have access (either already registered or available for download from an external server) to the desired network topology, the source device 110 may encode the reference to identify and activate the specific network topology required to be used when decoding the bitstream 121. Appendix E shows an example syntax structure for information encoded at operation of the step 18100. Control in the processor 205 progresses from the step 18100 to an encode FCM PPS step 18110.[000129] At the step 18110, the metadata encoder 544, under execution of the processor 205, encodes the quantisation range 526 for each tensor of the compressed tensors 532 into an FCM PPS 1116, as additional FCM metadata 548. Appendix E shows an example syntax structure for information encoded at operation of the step 18110. Quantisation ranges are used in the bitstream 121 to enable inverse quantisation to the correct range by the destination device 140. The quantisation range signalled in the FCM PPS 1116 is effective from the picture at whichthe FCM PPS 1116 precedes onwards, in output order from a picture decoder 1204, i.e., the IRAP 1122, which has a picture order count (POC) of 0. An FCM PPS 1123 precedes inter picture 1124, which has a POC of 1 and thus a quantization range coded in FCM PPS 1123 applies from POC 1 onwards (until a subsequent FCM PPS is encountered preceding another picture with higher POC, and the subsequent FCM PPS signals another quantization range update). Accordingly, when there is no change in the quantisation range for a given frame, the FCM PPS 1116 need not be encoded for that frame. The FCM PPS 1116 may explicitly encode the picture order count from which the FCM PPS 1116 parameters apply, i.e., a POC of 0, (from that POC until another FCM PPS with a higher POC is decoded, such as the FCM PPS 1123. A fixed number of least significant bits of the POC, such as 8 or 12 bits, may be coded to avoid coding the entire 32-bit POC with each FCM PPS. The MSBs of the POC may inferred based on the pattern that POC is increasing over time (with localised exception when a random-access configuration is used, due to localised difference in coding order vs output order). In one arrangement FCM PPSs (e.g., 1116 and 1122) include a picture parameter set ID syntax element, which corresponds to the picture parameter set ID of any PPSs present in the bitstream, such as the PPS 1120. The slice header or picture header of each picture includes a picture parameter set ID (“ph_pic_parameter_set_id” in VVC) which activates one of the previously signalled PPSs and FCM PPSs, i.e., parameters in the FCM PPS identified by a particular picture parameter set ID are selected by the ph_pic_parameter_set_id decoded from the slice header or picture header of a picture or slice. The NAL unit multiplexor 550 operates to combine the NAL units of the FCM metadata 548 and the compressed video bitstream 546 to produce the bitstream 121, such that the inner coded identifier 1110 is coded firstly, followed by the FCM VMPS 1112, the FCM SPS 1114, and the FCM PPS 1116. Following the FCM PPS 1116 the NAL units produced by the video encoder 542 are present, such as the SPS 1118, the PPS 1120, and an IRAP picture 1122, and an inter picture such as the inter picture 1124. The FCM SPS 1114 needs to be coded with the IRAP picture 1122 as the decoder needs to know tensor dimensionality information and decoder network topology information to proceed. One instance of the FCM PPS 1116 is needed with the IRAP picture 1122 in order for inverse quantisation to operate, subsequent instances are needed only when there is a change in the quantisation range 526 to be used with a given picture. An instance of the PPS 1116 is effective from the next coded picture. The method 1800 terminates and processing progresses to the next instance of the source data 113 (e.g., the next frame from the video source 112).[000130] Fig. 6 is a schematic block diagram 600 showing one type of multi-scale feature fusion (MSFF) module 600, which may serve as the tensor compressor 530. The MSFFmodule 600 takes the tensors 115 and produces a compressed tensor 532, having reduced dimensionality compared to the tensors 115 and thus resulting in a reduction in bitrate when encoded as part of a packed frame. The MSFF module 600 uses trained network layers and requires a corresponding module in the tensor decoder 146 to restore tensor dimensionality so the tensors 149 may be supplied to the CNN head 150. The MSFF module 600 takes four tensors as input and requires each one the tensors to have two-hundred and fixty-six (256) channels, so that the MSFF module 600 is compatible with the P-layers of the FasterRCNN or MaskRCNN networks. However, variants of the MSFF module 600 compatible with different numbers of layers and different channel counts are possible.[000131] The MSFF module 600 produces one tensor as output with sixty-four (64) channels and a feature map size corresponding to the P5 layer seen at the input, however variants with different channel count are also possible. Each variant of the MSFF module 600 requires different weights to be used for proper operation. Where several variants of the MSFF module 600 are able to be used in the system 100 for a given network, the packing format may be set to a worst-case feature map count of the compressed tensors of the currently used decoder network topology, and the actual used channel count may be updated at runtime as part of the tensor information.[000132] The MSFC module 600 includes an MSFF block 610 shown in Fig. 6, which produces a single tensor from the plurality of tensors 115 using one or more downsampling filters. The MSFF block 610, under execution of the processor 205, combines each tensor of a first set of tensors (i.e., 602, 603, 604, 605), to produce a combined tensor 629. The combined tensor 629 forms a representation of the FPN layer tensors. Downsample modules 622a, 622b, and 622c operate on the tensors having larger spatial scale, i.e., P4 604 at (2h, 2w, 256), and P3 603 at (4h, 4w, 256), and P2 602 at (8h, 8w, 256), respectively. Modules 622a, 622b, and 622c perform downsampling to match the spatial scale of the smallest tensor, i.e., P5 605 at (h, w, 256), producing downscaled P5 tensors 623a, 623b, 623c, respectively. A concatenation module 624 performs a channel-wise concatenation of the tensors 605, 623a, 623b, and 623c to produce concatenated tensor 625, of dimensions (h, w, 1024). The concatenated tensor 625 is passed to a squeeze and excitation (SE) module 626 to produce a tensor 627. The SE module 626 sequentially performs a global pooling, a fully-connected layer with reduction in channel count, a rectified linear unit activation unit, a second fully-connected layer restoring the channel count, and a sigmoid activation function to produce a scaling tensor. The tensor 625 is scaled according to the scaling tensor to produce the output as the tensor 627. The SEblock 626 is capable of being trained to adaptively alter the weighting of different channels in the tensor passed through, based on the first fully-connected layer output.[000133] The first fully-connected layer output reduces each feature map for each channel to a single value. Each single value is passed through a non-linear activation unit (ReLU) to create a conditional representation of the single value, suitable for weighting of other channels, with restoration to the full channel count performed by the second fully-connected layer. The SE block 626 is thus capable of extracting non-linear inter-channel correlation in producing the tensor 627 from the tensor 625, to a greater extent than is possible purely with convolutional (linear) layers. The tensor 627 is passed to a convolutional layer 628. The convolutional layer 628 implements one or more convolutional layers to produce the combined tensor 629, with channel count reduced to F channels, typically 256 channels (i.e., F = 256). Further reduction in the channel count is achieved by a single-scale feature compression (SSFC) module 650.[000134] The SSFC module 650 receives the tensor 629 and applies a convolution 652 to reduce the channel count from F (256) down to C’ (nominally set to 64 channels) to produce tensor 653. The tensor 653 is then passed to a batch normalisation module 654 to produce batch normalised tensor 655, which is passed to a hyperbolic tangent activation layer 656 to produce the compressed tensor 532. The output of the MSFC module 600 is a one tensor per frame with a fixed feature map size and fixed channel count.[000135] Fig. 7 is a schematic block diagram showing an example picture structure 700 with one level of temporal interpolation added to a low-delay bi-predicted coding structure. The video encoder 542 may be configured to implement the picture structure 700, providing an alternative to the use of the temporal downsampler 520 and a temporal upsampler 1260, described with reference to Fig. 12. The picture structure 700 operates such that odd-numbered pictures, by picture order count (POC) refer to the immediately preceding and following pictures for inter prediction, via list 0 (L0) and list 1 (LI), respectively. For example, POC #1 refers to POC #0 and POC #2. This requires POC #2 to be decoded prior to POC #1, resulting in one frame of structural delay implicit in the picture structure 700. Then, each even- numbered POC includes a reference to the previous picture with an even-numbered POC, for example POC #2 refers to POC #0. To assist with coding of relatively stable scenes, past reference to pictures of POC # modulus 8 equal to 0 are also kept, up to a limit, such as the last two or three such pictures. For example, POC # 6 also refers to POC #0 and POC #14 (i.e., belonging to the subsequent GOP) refers to POC #8 (first picture of the second GOP) and POC #0 (first picture of the first GOP). Each picture with an even-numbered POC references theprevious even-numbered POC and pictures with POC modulus 8 of the current and as many previous GOPs as possible up to a limit, such as the decoded picture buffer size limitation of six pictures (in HEVC) or eight pictures (in VVC), with one picture slot reserved for the current picture, resulting in a maximum of five or seven reference pictures, respectively. The GOP structure shown in Fig. 7 repeats every eight frames, so where prior references with negative numbers are shown (e.g., -8 or -16), these are to be interpreted as references to preceding GOPs. In the case of pictures with even-numbered POCs, both reference lists include the same set of preceding pictures with the same ordering.[000136] Fig. 8 is a schematic block diagram showing functional modules of a video encoder 800 which may be implemented as the video encoder 542. The video encoder 542 may be implemented using a general -purpose computer system 200, as shown in Figs. 2A and 2B, where the various functional modules may be implemented by dedicated hardware within the computer system 200, by software executable within the computer system 200 such as one or more software code modules of the software application program 233 resident on the hard disk drive 205 and being controlled in its execution by the processor 205. Alternatively, the video encoder 542 may be implemented by a combination of dedicated hardware and software executable within the computer system 200. The video encoder 542 and the described methods may alternatively be implemented in dedicated hardware, such as one or more integrated circuits performing the functions or sub functions of the described methods. Such dedicated hardware may include graphic processing units (GPUs), digital signal processors (DSPs), application-specific standard products (ASSPs), application-specific integrated circuits (ASICs), FPGAs or one or more microprocessors and associated memories. In particular, the video encoder 542 comprises modules 810-890 which may each be implemented as one or more software code modules of the software application program 233.[000137] Although the video encoder 542 of Fig. 8 is an example of a versatile video coding (WC) video encoder, other video codecs may also be used to perform the processing stages described herein. For example, HEVC or AVC or other types of encoders may be used. The examples described generate a bitstream of encoded data. If other codecs were used, some implementations may pack data into a different format such as a frame format or the like. The video encoder 800 receives frame data 712, each frame including one or more colour channels. The frame data 712 corresponds to the tensors 540 in packed form, as implemented at the step 1890. The frame data 712 may be in any chroma format and bit depth supported by the profile in use, for example 4:0:0, 4:2:0 for the “Main 10” profile of the VVC standard, at eight (8) to ten (10) bits in sample precision.[000138] As seen in Fig. 8, a block partitioner 810 firstly divides the frame data 712 into CTUs, generally square in shape and configured such that a particular size for the CTUs is used. The maximum enabled size of the CTUs may be 32x32, 64x64, or 128x 128 luma samples for example, configured by a ‘sps_log2_ctu_size_minus5’ syntax element present in the ‘sequence parameter set’ (i.e., the SPS 1118). The ‘sps_log2_ctu_size_minus5’ syntax element uses values 0, 1, and 2 to correspond to CTU sizes of 32x32, 64x64, and 128x 128, respectively The CTU size also provides a maximum CU size, as a CTU with no further splitting will contain one CU. Ternary splitting is prohibited when a CU has one or more dimensions of length 128 luma samples. As a consequence, processing may fully handle each 64x64 quadrant of the 128x 128 before progressing from one quadrant to the next quadrant. Large CUs such as 64x 128 are processed as a pair of 64x64 regions. As a result of quadrant-based processing (sometimes referred to as “virtual pipeline data units” or “VPDUs”), internal storage in the video encoder 800, and a corresponding video decoder 1204 (also referred to as a picture decoder), is only needed for 64x64 samples even when the CTU size is configured as 128x128. Feature maps are typically smaller than video frame size, due to use of intervening pooling operations or convolution operations with stride parameter greater than one. Feature maps do not require the large CU sizes provided by VVC. Use of a 32x32 CTU size provides sufficient flexibility in block structure to efficiently encode structural detail found in feature maps with a smaller amount of memory required for intermediate storage in the memory 206, i.e., storage for partially decoded data from a bitstream 1206 but prior to a frame buffer 1396, to be described. Use of a smaller CTU size reduces the variety of CU sizes that are able to be tested in the block partitioner 810, reducing runtime. Constraining the CTU size to 32x32 indicates a reduced memory consumption in the video decoder 1204 required for decoding the bitstream 1206 however the worst-case of 128x 128 would need to be supported should such a bitstream be encountered. A collection of syntax elements forming a ‘general constraints info’ syntax structure may be present in the SPS 1118 that constrains allowed values of other syntax elements in the SPS 1118 and indicate a compatibility point other than a profile defined in the H.266 / VVC specification, such compatibility points are known as ‘subprofiles’ and enable application-specific definition of a subset of the tools of a given H.266 / VVC profile. A gci_three_minus_max_log2_ctu_size_constraint_idc syntax element with values 0, 1, 2 constrains the maximum allowed CTU size in the SPS 1118 to 128x 128, 64x64, or 32x32, respectively. A general constraint restricting the maximum CTU size to 32x32 may form a subprofile (or part of a subprofile), enabling the worst-case complexity requirement of the video decoder 1204 to be reduced compared to the case where the full H.266 / VVC profile were required to be supported. One instance of the SPS 1118 is needed prior to the first picture in thebitstream 121 and also at any subsequent entry points (or ‘random access points’) into the bitstream 121 from which decoding can commence. The block partitioner 810 further divides each CTU into one or more CBs according to a luma coding tree and a chroma coding tree. The luma channel may also be referred to as a primary colour channel. Each chroma channel may also be referred to as a secondary colour channel. The CBs have a variety of sizes, and may include both square and non-square aspect ratios. However, in the VVC standard, CBs, CUs, PUs, and TUs always have side lengths that are powers of two. Thus, a current CB, represented as 812, is output from the block partitioner 810, progressing in accordance with an iteration over the one or more blocks of the CTU, in accordance with the luma coding tree and the chroma coding tree of the CTU.[000139] The CTUs resulting from the first division of the frame data 712 may be scanned in raster scan order and may be grouped into one or more ‘slices’. A slice may be an ‘intra’ (or ‘I’) slice. An intra slice (I slice) indicates that every CU in the slice is intra predicted.Generally, the first picture in a coded layer video sequence (CLVS) contains only I slices, and is referred to as an ‘intra picture’. The CLVS may contain periodic intra pictures, forming ‘random access points’ (i.e., intermediate frames in a video sequence upon which decoding can commence). Alternatively, a slice may be uni- or bi-predicted (‘P’ or ‘B’ slice, respectively), indicating additional availability of uni- and bi-prediction in the slice, respectively.[000140] The video encoder 542 encodes sequences of pictures according to a picture structure. One picture structure is Tow delay’, in which case pictures using inter-prediction may only reference pictures occurring previously in the sequence. Low delay enables each picture to be output as soon as the picture is decoded, in addition to being stored for possible reference by a subsequent picture. Another picture structure is ‘random access’, whereby the coding order of pictures differs from the display order. Random access allows inter-predicted pictures to reference other pictures that, although decoded, have not yet been output. A degree of picture buffering is needed so the reference pictures in the future in terms of display order are present in the decoded picture buffer, resulting in a latency of multiple frames.[000141] When a chroma format other than 4:0:0 is in use, in an I slice, the coding tree of each CTU may diverge below the 64^64 level into two separate coding trees, one for luma and another for chroma. Use of separate trees allows different block structure to exist between luma and chroma within a luma 64x64 area of a CTU. For example, a large chroma CB may be collocated with numerous smaller luma CBs and vice versa. In a P or B slice, a single codingtree of a CTU defines a block structure common to luma and chroma. The resulting blocks of the single tree may be intra predicted or inter predicted.[000142] In addition to a division of pictures into slices, pictures may also be divided into ‘tiles’. A tile is a sequence of CTUs covering a rectangular region of a picture. CTU scanning occurs in a raster-scan manner within each tile and progresses from one tile to the next. A slice can be either an integer number of tiles, or an integer number of consecutive rows of CTUs within a given tile.[000143] For each CTU, the video encoder 542 as shown in Fig. 8 operates in two stages. In the first stage (referred to as a ‘search’ stage), the block partitioner 810 tests various potential configurations of a coding tree. Each potential configuration of a coding tree has associated ‘candidate’ CBs. The first stage involves testing various candidate CBs to select CBs providing relatively high compression efficiency with relatively low distortion. The testing generally involves a Lagrangian optimisation whereby a candidate CB is evaluated based on a weighted combination of rate (i.e., coding cost) and distortion (i.e., error with respect to the input frame data 712). ‘Best’ candidate CBs (i.e., the CBs with the lowest evaluated rate / distortion) are selected for subsequent encoding into the bitstream portion 121. Included in evaluation of candidate CBs is an option to use a CB for a given area or to further split the area according to various splitting options and code each of the smaller resulting areas with further CBs, or split the areas even further. As a consequence, both the coding tree and the CBs themselves are selected in the search stage.[000144] The video encoder 542 produces a prediction block (PB), indicated by an arrow 820, for each CB, for example, CB 812. The PB 820 is a prediction of the contents of the associated CB 812. A subtracter module 822 produces a difference, indicated as 824 (or ‘residual’, referring to the difference being in the spatial domain), between the PB 820 and the CB 812. The difference 824 is a block-size difference between corresponding samples in the PB 820 and the CB 812. The difference 824 is transformed, quantised and represented as a transform block (TB), indicated by an arrow 836. The PB 820 and associated TB 836 are typically chosen from one of many possible candidate CBs, for example, based on evaluated cost or distortion.[000145] A candidate coding block (CB) is a CB resulting from one of the prediction modes available to the video encoder 542 for the associated PB and the resulting residual. When combined with the predicted PB in the video encoder 542, the TB 836 reduces the differencebetween a decoded CB and the original CB 812 at the expense of additional signalling in a bitstream.[000146] Each candidate coding block (CB) (i.e., prediction block (PB) in combination with a transform block (TB)), has an associated coding cost (or ‘rate’) and an associated difference (or ‘distortion’). The distortion of the CB is typically estimated as a difference in sample values, such as a sum of absolute differences (SAD), a sum of squared differences (SSD) or a Hadamard transform applied to the differences. The estimate resulting from each candidate PB may be determined by a mode selector 886 using the difference 824 to determine a prediction mode 887. The prediction mode 887 indicates the decision to use a particular prediction mode for the current CB, for example, intra-frame prediction or inter-frame prediction. Estimation of the coding costs associated with each candidate prediction mode and corresponding residual coding may be performed at significantly lower cost than entropy coding of the residual.Accordingly, a number of candidate modes may be evaluated to determine an optimum mode in a rate-distortion sense even in a real-time video encoder.[000147] Determining a preferred mode in terms of rate-distortion is typically achieved using a variation of Lagrangian optimisation. Lagrangian or similar optimisation processing can be employed to both select a preferred partitioning of a CTU into CBs (by the block partitioner 810) as well as the selection of a prediction mode from a plurality of possibilities. Through application of a Lagrangian optimisation process of the candidate modes in the mode selector module 886, the intra prediction mode with the lowest cost measurement is selected as a ‘best’ mode. The lowest cost mode includes a selected secondary transform index 888, which is encoded in the bitstream 121 by an entropy encoder 838.[000148] In the second stage of operation of the video encoder 542 (referred to as a ‘coding’ stage), an iteration over the determined coding tree(s) of each CTU is performed in the video encoder 542. For a CTU using separate trees, for each 64^64 luma region of the CTU, a luma coding tree is firstly encoded followed by a chroma coding tree. Within the luma coding tree, only luma CBs are encoded and within the chroma coding tree only chroma CBs are encoded. For a CTU using a shared tree, a single tree describes the CUs (i.e., the luma CBs and the chroma CBs) according to the common block structure of the shared tree.[000149] The entropy encoder 838 supports bitwise coding of syntax elements using variablelength and fixed-length codewords, and an arithmetic coding mode for syntax elements.Portions of the bitstream such as ‘parameter sets’, for example, the SPS, the picture parameter set (PPS), and the picture header (PH) use a combination of fixed-length codewords and variable-length codewords. Slices, also referred to as contiguous portions, have a slice header that uses variable length coding followed by slice data, which uses arithmetic coding. The slice header defines parameters specific to the current slice, such as slice-level quantisation parameter offsets, and may include an instance of the PH. The slice data includes the syntax elements of each CTU in the slice. Use of variable length coding and arithmetic coding requires sequential parsing within each portion of the bitstream. The portions may be delineated with a start code to form ‘network abstraction layer units’ or ‘NAL units’. Arithmetic coding is supported using a context-adaptive binary arithmetic coding process.[000150] Arithmetically coded syntax elements consist of sequences of one or more ‘bins’. Bins, like bits, have a value of ‘0’ or ‘ 1’ . However, bins are not encoded in a bitstream portion 716 (corresponding to the bitstream 546) as discrete bits. Bins have an associated predicted (or ‘likely’ or ‘most probable’) value and an associated probability, known as a ‘context’. When the actual bin to be coded matches the predicted value, a ‘most probable symbol’ (MPS) is coded. Coding a most probable symbol is relatively inexpensive in terms of consumed bits in the bitstream portion 121, including costs that amount to less than one discrete bit. When the actual bin to be coded mismatches the likely value, a ‘least probable symbol’ (LPS) is coded. Coding a least probable symbol has a relatively high cost in terms of consumed bits. The bin coding techniques enable efficient coding of bins where the probability of a ‘0’ versus a ‘ 1’ is skewed. For a syntax element with two possible values (i.e., a ‘flag’), a single bin is adequate. For syntax elements with many possible values, a sequence of bins is needed. The convention for converting values of a syntax element into a sequence of bins is termed ‘binarisation’ . Where the values ‘0’ and ‘ 1 ’ for a bin are equally (or near equally) likely, it is possible to omit use of a context and assume an equiprobable distribution. Bins with a context are termed ‘context-coded bins’ and bins omitting a context are termed ‘bypass-coded bins’. The binarization of a syntax element into one or more bins may result in a combination of context-coded and bypass-coded bins. Unlike directly coding one bit into the bitstream, a bypass-coded bin uses the arithmetic coding engine, which facilitates mixing context-coded and bypass-coded bins into syntax element binarisations.[000151] For a given binarization, the presence of later bins in the sequence may be determined based on the value of earlier bins in the sequence, resulting in variable-length binarisations. Additionally, each bin may be associated with more than one context, with one context selectedfor use in coding a specific instances of the bin. The selection of a particular context may be dependent on earlier bins in the syntax element, the decoded values of neighbouring syntax elements (i.e., those from neighbouring blocks) and the like. Each time a context-coded bin is encoded, the context that was selected for that bin (if any) is updated in a manner reflective of the new bin value. As such, the binary arithmetic coding scheme is said to be adaptive.[000152] The absence of a context for bypass-coded bins saves memory and reduces complexity, and thus bypass bins are used where the distribution of values for the particular bin is not skewed. One example of an entropy coder employing context and adaption is known in the art as CABAC (context adaptive binary arithmetic coder) and many variants of this coder have been employed in video coding.[000153] A QP controller 890 determines a quantisation parameter 892, used to establish a quantisation step size for use by a quantiser 834 and a dequantiser 840. A larger quantisation step size results in primary transform coefficients 828 being quantised into smaller values, reducing bitrate of the bitstream portion 716 at the expense of a reduction in the fidelity of inverse transform coefficients 846.[000154] The entropy encoder 838 encodes the quantisation parameter 892 and, if in use for the current CB, the LFNST index 888, using a combination of context-coded and bypass-coded bins. The quantisation parameter 892 is encoded at the beginning of each slice and changes in the quantisation parameter 892 within a slice are coded using a ‘delta QP’ syntax element. The delta QP syntax element is signalled at most once in each area known as a ‘quantisation group’. The quantisation parameter 892 is applied to residual coefficients of the luma CB. An adjusted quantisation parameter is applied to the residual coefficients of collocated chroma CBs. The adjusted quantisation parameter may include mapping from the luma quantisation parameter 892 according to a mapping table and a CU-level offset, selected from a list of offsets. The secondary transform index 888 is signalled when the residual associated with the transform block includes significant residual coefficients only in those coefficient positions subject to transforming into primary coefficients by application of a secondary transform.[000155] Residual coefficients of each TB associated with a CB are coded using a residual syntax. The residual syntax is designed to efficiently encode coefficients with low magnitudes, using mainly arithmetically coded bins to indicate significance of coefficients, along with lower-valued magnitudes and reserving bypass bins for higher magnitude residual coefficients.Accordingly, residual blocks comprising very low magnitude values and sparse placement of significant coefficients are efficiently compressed. Moreover, two residual coding schemes are present. A regular residual coding scheme is optimised for TBs with significant coefficients predominantly located in the upper-left corner of the TB, as is seen when a transform is applied. A transform-skip residual coding scheme is available for TBs where a transform is not performed and is able to efficiently encode residual coefficients regardless of their distribution throughout the TB.[000156] A multiplexer module 884 outputs the PB 820 from an intra-frame prediction module 864 according to the determined best intra prediction mode, selected from the tested prediction mode of each candidate CB. The candidate prediction modes need not include every conceivable prediction mode supported by the video encoder 542. Intra prediction falls into three types, first, “DC intra prediction”, which involves populating a PB with a single value representing the average of nearby reconstructed samples; second, “planar intra prediction”, which involves populating a PB with samples according to a plane, with a DC offset and a vertical and horizontal gradient being derived from nearby reconstructed neighbouring samples. The nearby reconstructed samples typically include a row of reconstructed samples above the current PB, extending to the right of the PB to an extent and a column of reconstructed samples to the left of the current PB, extending downwards beyond the PB to an extent; and, third, “angular intra prediction”, which involves populating a PB with reconstructed neighbouring samples filtered and propagated across the PB in a particular direction (or ‘angle’). In VVC, sixty-five (65) angles are supported, with rectangular blocks able to utilise additional angles, not available to square blocks, to produce a total of eighty-seven (87) angles.[000157] A fourth type of intra prediction is available to chroma PBs, whereby the PB is generated from collocated luma reconstructed samples according to a ‘cross-component linear model’ (CCLM) mode. Three different CCLM modes are available, each mode using a different model derived from the neighbouring luma and chroma samples. The derived model is used to generate a block of samples for the chroma PB from the collocated luma samples. Luma blocks may be intra predicted using a matrix multiplication of the reference samples using one matrix selected from a predefined set of matrices. This matrix intra prediction (MIP) achieves gain by using matrices trained on a large set of video data, with the matrices representing relationships between reference samples and a predicted block that are not easily captured in angular, planar, or DC intra prediction modes.[000158] The module 864 may also produce a prediction unit by copying a block from nearby the current frame using an ‘intra block copy’ (IBC) method. The location of the reference block is constrained to an area equivalent to one CTU, divided into 64x64 regions known as VPDUs, with the area covering the processed VPDUs of the current CTU and VPDUs of the previous CTU(s) within each row or CTUs and within each slice or tile up to the area limit corresponding to one 128x 128 luma samples, regardless of the configured CTU size for the bitstream. This area is known as an ‘IBC virtual buffer’ and limits the IBC reference area, thus limiting the required storage. The IBC buffer is populated with reconstructed samples 854 (i.e., prior to loop filtering), and so a separate buffer to a frame buffer 872 is needed. When the CTU size is 128x 128 the virtual buffer includes samples only from the CTU adjacent and to the left of the current CTU. When the CTU size is 32x32 or 64x64 the virtual buffer includes CTUs from up to the four or sixteen CTUs to the left of the current CTU. Regardless of the CTU size, access to neighbouring CTUs for obtaining samples for IBC reference blocks is constrained by boundaries such as edges of pictures, slices, or tiles. Particularly for feature maps of FPN layers having smaller dimensions, use of a CTU size such as 32x32 or 64x64 results in a reference area more aligned to cover a set of previous feature maps. Where feature map placement is ordered based on SAD, SSE or other difference metric, access to similar feature maps for IBC prediction offers coding efficient advantage.[000159] The residual for a predicted block when encoding feature map data is different to the residual seen for natural video. Natural video is typically captured by an image sensor, or screen content, as generally seen in operating system user interfaces and the like. Feature map residuals tend to contain much detail. The level of detail in feature map residuals is amenable to transform skip coding more than predominantly low-frequency coefficients of various transforms. An intra-predicted luma coding block may be partitioned into a set of equal-sized prediction blocks, either vertically or horizontally, which each block having a minimum area of sixteen (16) luma samples.[000160] Where previously reconstructed neighbouring samples are unavailable, for example at the edge of the frame, a default half-tone value of one half the range of the samples is used. For example, for 10-bit video a value of five-hundred and twelve (512) is used. As no previous samples are available for a CB located at the top-left position of a frame, angular and planar intra-prediction modes produce the same output as the DC prediction mode (i.e. a flat plane of samples having the half-tone value as magnitude).[000161] For inter-frame prediction a prediction block 882 is produced using samples from one or two frames preceding the current frame in the coding order frames in the bitstream by a motion compensation module 880 and output as the PB 820 by the multiplexer module 884. Moreover, for inter-frame prediction, a single coding tree is typically used for both the luma channel and the chroma channels. The order of coding frames in the bitstream may differ from the order of the frames when captured or displayed. When one frame is used for prediction, the block is said to be ‘uni-predicted’ and has one associated motion vector. When two frames are used for prediction, the block is said to be ‘bi-predicted’ and has two associated motion vectors. For a P slice, each CU may be intra predicted or uni -predicted. For a B slice, each CU may be intra predicted, uni -predicted, or bi-predicted.[000162] Frames are typically coded using a ‘group of pictures’ structure, enabling a temporal hierarchy of frames. Frames may be divided into multiple slices, each of which encodes a portion of the frame. A temporal hierarchy of frames allows a frame to reference a preceding and a subsequent picture in the order of displaying the frames. The images are coded in the order necessary to ensure the dependencies for decoding each frame are met. An affine inter prediction mode is available where instead of using one or two motion vectors to select and filter reference sample blocks for a prediction unit, the prediction unit is divided into multiple smaller blocks and a motion field is produced so each smaller block has a distinct motion vector. The motion field uses the motion vectors of nearby points to the prediction unit as ‘control points’. Affine prediction allows coding of motion different to translation with less need to use deeply split coding trees. A bi-prediction mode available to VVC performs a geometric blend of the two reference blocks along a selected axis, with angle and offset from the centre of the block signalled. This geometric partitioning mode (“GPM”) allows larger coding units to be used along the boundary between two objects, with the geometry of the boundary coded for the coding unit as an angle and centre offset. Motion vector differences, instead of using cartesian (x, y) offset, may be coded as a direction (up / down / left / right) and a distance, with a set of power-of-two distances supported. The motion vector predictor is obtained from a neighbouring block (‘merge mode’) as if no offset is applied. The current block will share the same motion vector as the selected neighbouring block.[000163] The samples are selected according to a motion vector 878 and reference picture index. The motion vector 878 and reference picture index applies to all colour channels and thus inter prediction is described primarily in terms of operation upon Pus rather than PBs. The decomposition of each CTU into one or more inter-predicted blocks is described with a singlecoding tree. Inter prediction methods may vary in the number of motion parameters and their precision. Motion parameters typically comprise a reference frame index, indicating which reference frame(s) from lists of reference frames are to be used plus a spatial translation for each of the reference frames, but may include more frames, special frames, or complex affine parameters such as scaling and rotation. In addition, a pre-determined motion refinement process may be applied to generate dense motion estimates based on referenced sample blocks.[000164] Having determined and selected the PB 820 and subtracted the PB 820 from the original sample block at the subtractor 822, a residual with lowest coding cost, represented as 824, is obtained and subjected to lossy compression. The lossy compression process comprises the steps of transformation, quantisation and entropy coding. A forward primary transform module 826 applies a forward transform to the difference 824, converting the difference 824 from the spatial domain to the frequency domain, and producing primary transform coefficients represented by an arrow 828. The largest primary transform size in one dimension is either a 32-point DCT-2 or a 64-point DCT-2 transform, configured by a ‘sps_max_luma_transform_size_64_flag’ in the sequence parameter set. If the CB being encoded is larger than the largest supported primary transform size expressed as a block size (e.g., 64x64 or 32x32), the primary transform 826 is applied in a tiled manner to transform all samples of the difference 824. Where a non-square CB is used, tiling is also performed using the largest available transform size in each dimension of the CB. For example, when a maximum transform size of thirty -two (32) is used, a 64 x 16 CB uses two 32x 16 primary transforms arranged in a tiled manner. When a CB is larger in size than the maximum supported transform size, the CB is filled with TBs in a tiled manner. For example, a 128x 128 CB with 64-pt transform maximum size is filled with four 64x64 TBs in a 2x2 arrangement. A 64x 128 CB with a 32-pt transform maximum size is filled with eight 32x32 TBs in a 2x4 arrangement.[000165] Application of the transform 826 results in multiple TBs for the CB. Where each application of the transform operates on a TB of the difference 824 larger than 32x32, e.g., 64x64, all resulting primary transform coefficients 828 outside of the upper-left 32x32 area of the TB are set to zero (i.e., discarded). The remaining primary transform coefficients 828 are passed to the quantiser module 834. The primary transform coefficients 828 are quantised according to the quantisation parameter 892 associated with the CB to produce primary transform coefficients 832. In addition to the quantisation parameter 892, the quantiser module 834 may also apply a ‘scaling list’ to allow non-uniform quantisation within the TB by furtherscaling residual coefficients according to their spatial position within the TB. The quantisation parameter 892 may differ for a luma CB versus each chroma CB. The primary transform coefficients 832 are passed to a forward secondary transform module 830 to produce transform coefficients represented by the arrow 836 by performing either a non-separable secondary transform (NSST) operation or bypassing the secondary transform. The forward primary transform 826 is typically separable, transforming a set of rows and then a set of columns of each TB. The forward primary transform module 826 uses either a type-II discrete cosine transform (DCT-2) in the horizontal and vertical directions, or bypass of the transform horizontally and vertically, or combinations of a type- VII discrete sine transform (DST-7) and a type- VIII discrete cosine transform (DCT-8) in either horizontal or vertical directions for luma TBs not exceeding 16 samples in width and height. Use of combinations of a DST-7 and DCT- 8 is referred to as ‘multi transform selection set’ (MTS) in the VVC standard.[000166] The forward secondary transform of the module 830 is generally a non-separable transform, which is only applied for the residual of intra-predicted CUs and may nonetheless also be bypassed. The forward secondary transform operates either on sixteen (16) samples (arranged as the upper-left 4x4 sub-block of the primary transform coefficients 828) or fortyeight (48) samples (arranged as three 4x4 sub-blocks in the upper-left 8x8 coefficients of the primary transform coefficients 828) to produce a set of secondary transform coefficients. The set of secondary transform coefficients may be fewer in number than the set of primary transform coefficients from which they are derived. Due to application of the secondary transform to only a set of coefficients adjacent to each other and including the DC coefficient, the secondary transform is referred to as a Tow frequency non-separable secondary transform’ (LFNST). Such secondary transforms may be obtained through a training process and due to their non-separable nature and trained origin, exploit additional redundancy in the residual signal not able to be captured by separable transforms such as variants of DCT and DST. Moreover, when the LFNST is applied, all remaining coefficients in the TB are zero, both in the primary transform domain and the secondary transform domain.[000167] The quantisation parameter 892 is constant for a given TB and thus results in a uniform scaling for producing residual coefficients in the primary transform domain for a TB. The quantisation parameter 892 may vary periodically with a signalled ‘delta quantisation parameter’. The delta quantisation parameter (delta QP) is signalled once for CUs contained within a given area, referred to as a ‘quantisation group’. If a CU is larger than the quantisation group size, delta QP is signalled once with one of the TBs of the CU. That is, the delta QP issignalled by the entropy encoder 838 once for the first quantisation group of the CU and not signalled for any subsequent quantisation groups of the CU. A non-uniform scaling is also possible by application of a ‘quantisation matrix’, whereby the scaling factor applied for each residual coefficient is derived from a combination of the quantisation parameter 892 and the corresponding entry in a scaling matrix. The scaling matrix may have a size that is smaller than the size of the TB, and when applied to the TB a nearest neighbour approach is used to provide scaling values for each residual coefficient from a scaling matrix smaller in size than the TB size. The residual coefficients 836 are supplied to the entropy encoder 838 for encoding in the bitstream portion 716. Typically, the residual coefficients of each TB with at least one significant residual coefficient of the TU are scanned to produce an ordered list of values, according to a scan pattern. The scan pattern generally scans the TB as a sequence of 4^4 ‘subblocks’, providing a regular scanning operation at the granularity of 4x4 sets of residual coefficients, with the arrangement of sub-blocks dependent on the size of the TB. The scan within each sub-block and the progression from one sub-block to the next typically follow a backward diagonal scan pattern. Additionally, the quantisation parameter 892 is encoded into the bitstream portion 716 using a delta QP syntax element, and a slice QP for the initial value in a given slice or subpicture and the secondary transform index 888 is encoded in the bitstream portion 716.[000168] As described above, the video encoder 542 needs access to a frame representation corresponding to the decoded frame representation seen in the video decoder. Thus, the residual coefficients 836 are passed through an inverse secondary transform module 844, operating in accordance with the secondary transform index 888 to produce intermediate inverse transform coefficients, represented by an arrow 842. The intermediate inverse transform coefficients 842 are inverse quantised by the dequantiser module 840 according to the quantisation parameter 892 to produce the inverse transform coefficients, represented by an arrow 846. The dequantiser module 840 may also perform an inverse non-uniform scaling of residual coefficients using a scaling list, corresponding to the forward scaling performed in the quantiser module 834. The inverse transform coefficients 846 are passed to an inverse primary transform module 848 to produce residual samples, represented by an arrow 850, of the TU. The inverse primary transform module 848 applies DCT-2 transforms horizontally and vertically, constrained by the maximum available transform size as described with reference to the forward primary transform module 826. The types of inverse transform performed by the inverse secondary transform module 844 correspond with the types of forward transform performed by the forward secondary transform module 830. The types of inverse transformperformed by the inverse primary transform module 848 correspond with the types of primary transform performed by the primary transform module 826. A summation module 852 adds the residual samples 850 and the PB 820 to produce reconstructed samples (indicated by an arrow 854) of the CU.[000169] The reconstructed samples 854 are passed to a reference sample cache 856 and an inloop filters module 868. The reference sample cache 856, typically implemented using static RAM on an ASIC to avoid costly off-chip memory access, provides minimal sample storage needed to satisfy the dependencies for generating intra-frame PBs for subsequent CUs in the frame. The minimal dependencies typically include a Tine buffer’ of samples along the bottom of a row of CTUs, for use by the next row of CTUs and column buffering the extent of which is set by the height of the CTU. The reference sample cache 856 supplies reference samples (represented by an arrow 858) to a reference sample filter 860. The sample filter 860 applies a smoothing operation to produce filtered reference samples (indicated by an arrow 862). The filtered reference samples 862 are used by the intra-frame prediction module 864 to produce an intra-predicted block of samples, represented by an arrow 866. For each candidate intra prediction mode the intra-frame prediction module 864 produces a block of samples, that is 866. The block of samples 866 is generated by the module 864 using techniques such as DC, planar or angular intra prediction. The block of samples 866 may also be produced using a matrix-multiplication approach with neighbouring reference sample as input and a matrix selected from a set of matrices by the video encoder 800, with the selected matrix signalled in the bitstream 121 using an index to identify which matrix of the set of matrices is to be used by the video decoder.[000170] The in-loop filters module 868 applies several filtering stages to the reconstructed samples 854. The filtering stages include a ‘deblocking filter’ (DBF) which applies smoothing aligned to the CU boundaries to reduce artefacts resulting from discontinuities. Another filtering stage present in the in-loop filters module 868 is an ‘adaptive loop filter’ (ALF), which applies a Wiener-based adaptive filter to further reduce distortion. A further available filtering stage in the in-loop filters module 868 is a ‘sample adaptive offset’ (SAO) filter. The SAO filter operates by firstly classifying reconstructed samples into one or multiple categories and, according to the allocated category, applying an offset at the sample level.[000171] Filtered samples, represented by an arrow 870, are output from the in-loop filters module 868. The filtered samples 870 are stored in a frame buffer 872. The frame buffer 872typically has the capacity to store several (e.g., up to sixteen (16)) pictures and thus is stored in the memory 206. The frame buffer 872 is not typically stored using on-chip memory due to the large memory consumption required. As such, access to the frame buffer 872 is costly in terms of memory bandwidth. The frame buffer 872 provides reference frames (represented by an arrow 874) to a motion estimation module 876 and the motion compensation module 880. The reference frames 874 are output as a reconstructed frame 718 of the encoder module 542. In the example of Fig. 8, the reconstructed frame is a result of operation of lossy VVC encoding, that is due to operation of the modules 810 to 890.[000172] The motion estimation module 876 estimates a number of ‘motion vectors’ (indicated as 878), each being a Cartesian spatial offset from the location of the present CB, referencing a block in one of the reference frames in the frame buffer 872. A filtered block of reference samples (represented as 882) is produced for each motion vector. The filtered reference samples 882 form further candidate modes available for potential selection by the mode selector 886. Moreover, for a given CU, the PU 820 may be formed using one reference block (‘uni -predicted’) or may be formed using two reference blocks (‘bi-predicted’). For the selected motion vector, the motion compensation module 880 produces the PB 820 in accordance with a filtering process supportive of sub-pixel accuracy in the motion vectors. As such, the motion estimation module 876 (which operates on many candidate motion vectors) may perform a simplified filtering process compared to that of the motion compensation module 880 (which operates on the selected candidate only) to achieve reduced computational complexity. When the video encoder 542 selects inter prediction for a CU the motion vector 878 is encoded into the bitstream portion 121.[000173] Although the video encoder 542 of Fig. 8 is described with reference to versatile video coding (VVC), other video coding standards or implementations may also employ the processing stages of modules 810-890. The frame data 712 (and bitstream 716) may also be read from (or written to) memory 206, the hard disk drive 210, a CD-ROM, a Blu-ray disk™ or other computer readable storage medium. Additionally, the frame data 712 (and bitstream 716) may be received from (or transmitted to) an external source, such as a server connected to the communications network 220 or a radio-frequency receiver. The communications network 220 may provide limited bandwidth, necessitating the use of rate control in the video encoder 120 to avoid saturating the network at times when the frame data 712 is difficult to compress.[000174] The bitstream 716 may be constructed from one or more slices, representing spatial sections (collections of CTUs) of the frame data 712, produced by one or more instances of the video encoder 542, each producing the bitstream portion 716 and operating in a co-ordinated manner under control of the processor 205. The bitstream portion 716 may also contain one slice that corresponds to one region to be output as a collection of subpictures forming one picture, each being independently encodable and independently decodable with respect to any of the other slices or subpictures in the picture.[000175] Figs. 9A & 9B are schematic block diagrams showing an arrangement for holding or packing compressed feature map data from compressed tensor data. A feature map, corresponding to one channel of a tensor, is packed or stored in rectangular area of the frame. The feature maps of each channel are packed typically in a left-to-right manner firstly and top- to-bottom manner secondly filling the frame width in the order of incrementing channel count. Fig. 9A shows a frame 900 that contains a region 910 in which feature maps of a tensor are to be packed. Frames containing feature maps packed onto the area of the frame may be referred to as “feature frames”. The size of the frame 900 may be specified in terms of width and height in units of samples, smallest CU width / height, or CTU width / height. Fig. 9B shows the frame 900b which corresponds to the frame 900 once feature maps, i.e., feature maps obtained from the tensor 532, are packed. Where the tensor compressor 530 was configured to perform the feature reduction network topology described with reference to Fig. 6, the tensor 532 contains feature maps corresponding to the P5 layer, such as a feature map 930.[000176] Fig. 12 is a schematic block diagram 1200 showing an example implementation of the tensor decoder 146. In the example of Fig. 12, the tensor decoder 146 includes a configurable tensor decompressor 1250 and a selectable picture decoder 1204. Fig. 19 shows a method 1900 for decoding a bitstream, including reconstructing tensors according to an indicated tensor decompressor, and performing a second portion of the CNN. In the example described, the method 1900 is configured for decoding an FCM bitstream where the inner coding is performed using one of several compression standards, each of which has a different NAL unit format, affecting signalling of metadata outside the scope of the inner coding stage.[000177] The tensor decoder 1200 (146) and the method 1900 may be implemented as one or more software application programs 233 executable within the computer system 200. The tensor decoder 146 and the method 1900 may be effected by instructions 231 (see Fig. 2B) in the software 233 that are carried out within the computer system 200. The softwareinstructions 231 may be formed as one or more code modules, each for performing one or more particular tasks. The method 1900 begins at a decode codec identifier NAL unit step 1902.[000178] At the step 1902, a NAL unit demultiplexor 1202 passes NAL units 1207 received in the bitstream 143 to a metadata parser 1208, under execution of the processor 205, to decode received NAL units. At this stage, the specific inner codec is not known and so the only NAL unit format that can be unambiguously decoded is the inner codec identifier NAL unit as described with reference to Appendix D. In particular, an inner codec identifier syntax element is decoded from inner codec identifier (ICI) 1110 at step 1902. For example, if AVC was selected as the inner codec at step 1802, step 1902 operates to decode a NAL unit from the bitstream having a predetermined length. As described in relation to Appendix D, the NAL unit of the predetermined length indicates a NAL unit format of one inner codec of a plurality of inner codecs. Each other inner codec (such as HEVC, VVC or ‘custom’) has a NAL unit length different to the predetermined length. The bitstream includes a plurality of NAL units and the decoded NAL unit of predetermined length for identifying a particular inner codec is the NAL unit header 1012.[000179] Control in the processor 205 progresses from the step 1902 to a select inner codec step 1904.[000180] At the step 1904, the tensor decoder 146, under execution of the processor 205, selects one inner codec from a plurality of inner codecs based on the decoded NAL unit of the predetermined length decoded at step 1902. The inner codec, i.e., the compression standard to be performed by the picture decoder 1204, is determined from the inner codec identifier syntax element decoded at the step 1902. Control in the processor 205 progresses from the step 1902 to a decode FCM VMPS step 1906.[000181] At the step 1906, the NAL unit demultiplexor 1202, configured to parse NAL unit headers in accordance with the selected inner codec, passes the FCM VMPS 1112 to the metadata parser 1208. The demultiplexor 1202 is able to distinguish NAL units for the metadata parser (FCM VMPS, FCM SPS, and FCM PPS) from NAL units for the picture decoder 1204 based on the nal unit type enumerations described with reference to Appendices A-C. The metadata parser 1208 decodes the FCM VMPS 1112 in accordance with the syntax structure shown in Appendix E to produce vision model parameters (output_picture_width and output_picture_height in the example of Appendix E), which are passed to the CNN head 150.The vision model parameters produced at step 1906 correspond to the parameters 113a of Fig. 1. Vision model parameters may include items such as the dimensions of the frame data 113, needed for bounding boxes to be scaled correctly. Control in the processor 205 progresses from the step 1906 to a decode FCM SPS step 1907.[000182] At the step 1907, the metadata parser 1208 parses the FCM SPS 1114 received from the bitstream 143 via the demultiplexor 1202 to obtain tensor information relating to dimensionality of compressed tensors and placement of feature maps as packing information for each tensor in the bitstream 143. The FCM SPS 1114 is parsed to obtain the information encoded at step 18100. The FCM SPS 1114 is parsed at step 1907 in accordance with the syntax structure and semantics described with reference to Appendix E, for example. Control in the processor 205 progresses from the step 1907 to a decode FCM PPS step 1908.[000183] At the step 1908, the metadata parser 1208 parses the FCM PPS 1116 if received from the bitstream 143 via the demultiplexor 1202. The FCM PPS 1116 is parsed to obtain information encoded at step 18110. The step 1908 operated to decode and parse information in accordance with the syntax structure and semantics described with reference to Appendix E, for example. For example, the FCM PPS 1116 includes information relating to quantisation ranges in elements qr min exp, qr min exp sign, qr min mantissa, qr min mantissa sign, qr max exp, qr max exp sign, qr max mantissa, qr max mantissa sign) in the example of Appendix E. Control in the processor 205 progresses from the step 1908 to a determine tensor decompressor step 1910.[000184] At the step 1910, the tensor decoder 146 determines a decoder network topology to be used for restoring dimensionality of compressed tensors to a dimensionality compatible for use as input to the CNN head 150. The metadata parser 1208, under execution of the processor 205, decodes information representing the decoder topology from the FCM SPS 1114 as a full decoder network topology. Alternatively, the metadata parser 1208 decodes a reference to a description of the decoder network topology, which may have been previously included in the bitstream 143 or may have been obtained via external means (e.g., downloaded from an internet connection). The decoder network topology may be encoded using formats such as ONNX, NNEX, or Pytorch code. The decoded network topology may include a format indication, signalling which format is in use. For a given format, multiple versions may be defined (or new versions may be created in future) and so a format version indicator may also be included in the decoded network topology. Formats may be textual in nature and thus use ofan optional compression stage, using a technique such as ZIP or LZMA, may be signalled to minimise the storage overhead of the decoder network topology in the bitstream 143.[000185] As seen in Fig. 12, a tensor decompressor information 1230 is output by the parser 1208. The tensor decompressor information 1230 specifies a decoder network topology either by reference or by structure. If the tensor decompressor information 1230 specifies the decoder network topology by reference, the structure of the decoder network topology is obtained from a tensor decompressor repository 1232 (if available) or the repository 1232 obtains the topology from the tensor codec repository 180. The decoder network topology may be retained in the repository 1232 for future use even after a different decoder network topology is used. The repository 1232 outputs information 1238 corresponding to the decoder topology to the tensor decompressor 1250. The decoder network topology may be retained in the repository 1232 for future use even after a subsequent ICI (e.g., 1110) is received, indicating the commencement of a new bitstream. If the decoder network topology requires weights, weight information 1234 is provided from the metadata parser 1208 to a tensor weights repository 1236 to specify weights either by reference or by value. The repository 1236 output information 1240 corresponding to the weights information. A given feature restoration network topology may allow specific dimensions of the input and output tensors to be changed at runtime, sometimes referred to as ‘dynamic axes’. Such dynamic axes may correspond to the width and height of feature maps of the tensors being compressed or restored. Control in the processor 205 progresses from the step 1910 to a decode complexity indication step 1920.[000186] At the step 1920, the metadata parser 1208, under execution of the processor 205, decodes one or more syntax elements indicating the worst-case complexity of any decoder network topology that will be implemented in the tensor decompressor 1250 as the complexity indication from the FCM SPS 1114. Worst-case complexity includes one or more of the worst case in terms of storage of intermediate tensors within the tensor decompressor 1250, worstcase number of MAC operations to be performed by the tensor decompressor 1250 and worst case floating-point operations of any kind to be performed in the tensor decompressor 1250. Control in the processor 205 progresses from the step 1920 to a determine tensor decompressor complexity step 1930.[000187] At the step 1930, the tensor decoder 146, under execution of the processor 205, determines the required complexity to perform the determined decoder network topology. An operation count is produced by performing a traversal of the stages defined in the determineddecoder network topology and counting operations implied by each stage without performing the stage. Dimensionality of any persistent tensor data (i.e., tensors retained from one invocation of the tensor decompressor 1250 to the next invocation), is recorded. The volume of intermediate tensor data is retained, such that the maximum amount of intermediate tensor data concurrently retained in the memory 206 is determined. Control in the processor 205 progresses from the step 1930 to a complexity test step 1950.[000188] At the step 1950, the tensor decoder 146, under execution of the processor 205, compares the decoder network topology complexity determined at the step 1930 with the complexity indication decoded at the step 1920. If the determined complexity is less than or equal to the complexity indication (“OK” at step 1950) control in the processor 205 progresses from the step 1950 to an instantiate tensor decompressor step 1970. If the determined complexity is greater than the complexity indication (“NOT OK” at step 1950) control in the processor 205 progresses from the step 1950 to an error condition step 1960.[000189] At the step 1960, the tensor decoder 146 enters an error state and decoding cannot continue due to the possibility of a signalled decoder network topology exceeding the capabilities of the tensor decompressor 1250. The method 1900 terminates.[000190] At the step 1970, the tensor decompressor 1250 is initialized in accordance with the decoder network topology as determined at the step 1910. The step 1970 is performed only when a new decoder network topology was determined at the step 1910, i.e. subsequent invocations of the method 1900 for which no new decoder network topology is determined may reuse resources allocated at the step 1970. Sufficient storage memory is allocated to hold any persistent tensors, (i.e., tensors retained from one invocation of the method 1900 to the next invocation of the method 1900), along with memory to hold the maximum concurrently used intermediate tensors in performing the decoder network topology. In the case where hardware acceleration is applied for the decoder network topology, reservation of sufficient execution units, such as MACs, DSP blocks, e.g., in an FPGA, may also take place. In the case where the decoder network topology is to be performed in software, sufficient execution time on available resources such as CPU or GPU is reserved to enable real-time operation of the method 1900 (i.e., sufficient to allow repeated invocations of the method 1900 as incoming packed frames are decoded without accumulated stalling, jitter, buffering delay). Control in the processor 205 progresses from the step 1970 to a decode packed frame step 1980.[000191] At the step 1980, the picture decoder 1204, under execution of the processor 205, decodes one packed frame from the bitstream 1206 to produce a decoded frame 1210, provided fcm sps inner decoding bypass flag was set to disabled (i.e., zero, or do not bypass the inner decoding step). The bitstream 1206 includes NAL units from the bitstream 143 having NAL unit types that are not allocated as FCM VMPS, FCM SPS, or FCM PPS. Due to operation of step 1890 at the encoding stage, the step 1980 executes to produce one or more integer tensors from the bitstream. The step 1980 operates to decode the bitstream using the selected inner codec of step 1904 to produce the tensors to be provided to the neural network head (second portion) 150. Operation of the picture decoder 1204 is described with reference to Fig. 13. Control in the processor 205 progresses from the step 1980 to an unpack tensors step 1990.[000192] At the step 1990, an unpacker 1214, under execution of the processor 205, reads feature maps from the decoded frame 1210 in accordance with the packing format as determined at the step 1906 in decoding the FCM VMPS 1112 and described with reference to Figs. 9A & 9B. For each tensor, a number of feature maps are decoded, the number corresponding to the number of used channels in the tensor as signalled in the tensor information. Aspects of the tensor information used for packing and unpacking are reduced- domain tensor dimensionality and placement of each reduced-domain tensor in the decoded frame 1210. The channels for each tensor are unpacked as two-dimensional feature maps. The number of feature maps or channels to decode for a given tensor is decoded from the bitstream 143 as a ‘channel count’. The unpacker 1214 outputs integer tensors 1216, where the tensors 1216 have been decoded using the decoder topology for the tensor decoder 146. Due to use of the video decoder 1204, the tensors 1216 contain integer elements in the range afforded by the bit depth in use in the video decoder 1204. Control in the processor 205 progresses from the step 1990 to an inverse quantise tensors step 19100.[000193] At the step 19100, an inverse quantiser 1218, under execution of the processor 205, performs inverse quantisation on the integer tensors 1216 to produce inverse quantised tensors 1220, provided fcm sps quantisation bypass flag is set to zero (i.e., do not bypass inverse quantisation). The inverse quantiser 1218 applies quantisation ranges decoded from the bitstream 143, to the determined channel count of each tensor, also converting the resultant tensor to a floating-point data format. The quantisation ranges indicate a maximum and minimum value (or lower and upper bound) used in the floating-point domain at the output from the feature reduction network or tensor compressor 530, i.e., 532. To perform inverse quantisation, the quantisation range is decoded from the FCM PPS 1116 by the metadataparser 1208 as 1270 at the step 1908. The step 19100 therefore operates to decode the quantisation range and produce one or more floating-point tensors (1220) from the integer tensor(s) produced at the step 1990 using the range information. The quantisation range indicates a range of values, and the tensors 1220 are produced so that each element of each feature map of each tensor has a value within the indicated range. The quantisation range may be obtained by decoding syntax elements qr min exp, qr min exp sign, qr min mantissa, qr min mantissa sign, qr max exp, qr max exp sign, qr max mantissa, qr max mantissa sign, as described with reference to Appendix E. Control in the processor 205 progresses from the step 19100 to one of a buffer quantised tensors step 19110.[000194] At the step 19110, a tensor storage module 1222, under execution of the processor 205, provides inter-frame storage of the inverse quantised tensors 1220. Of the tensors for each region of the packing format, each tensor with at least one channel or feature map decoded is stored in the tensor storage module 1222. The tensor storage module 1222 produces output tensors 1224, including the most recent tensor for each tensor where at least one feature map was decoded. In other words, where a tensor was not decoded for a current frame (i.e., a channel count of zero was determined), the most recent value for the tensor where a nonzero channel count was decoded, is used. Control in the processor 205 progresses from the step 19110 to a perform tensor decompression step 19120.[000195] At the step 19120, the tensor decompressor 1250, under execution of the processor 205, performs the steps specified by the decoder network topology using the tensors 1224 as input to produce decoded tensors 1254 when fcm sps feature restoration bypass flag is set to zero, i.e., do not bypass the tensor decompreesion or feature restoration step. Operation of the step 19120 is described further with reference to Fig. 14. By virtue of the check performed at the step 1950, performance of the decoder network topology will not consume resources beyond those already allocated by the destination device 140 for the purpose of tensor decompression and hence will succeed in producing an output. Control in the processor 205 progresses from the step 19120 to a perform upsampling step 19130.[000196] At the step 19130, a temporal upsampler 1260, under execution of the processor 205, performs a temporal upsampling (interpolation) to produce the tensors 149 from the tensors 1254. The temporal upsampler is active when fcm_pps_temporal_upsampling_enabled_flag is set to indicate application of temporalupsampling, in accordance with the ratio indicated by temporal_upsampling_ratio_minus2. Each temporal upsampling operation takes two consecutive sets of tensors from the tensors 1254 and produces one or more intermediate tensors, output along with the tensors 1254 to produce tensors 149. Due to use of the second set of tensors from 1254 to produce intermediate tensors, structural delay is introduced when temporal upsampling is enabled, hence temporal upsampling is suited to applications that can tolerate a degree of latency. Control in the processor 205 progresses from the step 1930 to a perform neural network second portion step 19140.[000197] At the step 19140, the CNN head 150, under execution of the processor 205, performs the remaining layers of the neural network implemented by the system 100, using the tensors 149 as input. The method 1900 terminates and the processor 205 may reinvoke the method 1900 upon receiving the next packed frame in the bitstream 143.[000198] Fig. 13 is a schematic block diagram 1300 showing functional modules of an example implementation of the video decoder 1204. The video decoder 1204 may be implemented as one or more software application programs 233 executable within the computer system 200. The video decoder 1204 may be effected by instructions 231 (see Fig. 2B) in the software 233 that are carried out within the computer system 200. The software instructions 231 may be formed as one or more code modules, each for performing one or more particular tasks.[000199] The bitstream 1206 is input to an entropy decoder module 1320. The entropy decoder module 1320 extracts syntax elements from the bitstream 143 by decoding sequences of ‘bins’ and passes the values of the syntax elements to other modules in the video decoder 1204. The entropy decoder module 1320 uses variable-length and fixed length decoding to decode SPS, PPS or slice header using an arithmetic decoding engine to decode syntax elements of the slice data as a sequence of one or more bins. Each bin may use one or more ‘contexts’, with a context describing probability levels to be used for coding a ‘one’ and a ‘zero’ value for the bin. Where multiple contexts are available for a given bin, a ‘context modelling’ or ‘context selection’ step is performed to choose one of the available contexts for decoding the bin. The process of decoding bins forms a sequential feedback loop, where each slice may be decoded in entirety by a given entropy decoder 1020 instance.[000200] The entropy decoder module 1320 applies an arithmetic coding algorithm, for example ‘context adaptive binary arithmetic coding’ (CAB AC), to decode syntax elementsfrom the bitstream 143. The decoded syntax elements are used to reconstruct parameters within the video decoder 1204. Parameters include residual coefficients (represented by an arrow 1324), a quantisation parameter 1374, a secondary transform index 1370, and mode selection information such as an intra prediction mode (represented by an arrow 1358). The mode selection information also includes information such as motion vectors, and the partitioning of each CTU into one or more CBs. Parameters are used to generate PBs, typically in combination with sample data from previously decoded CBs.[000201] The residual coefficients 1324 are passed to an inverse secondary transform module 1336 where either a secondary transform is applied or no operation is performed (bypass) according to a secondary transform index. The inverse secondary transform module 1336 produces reconstructed transform coefficients 1332. That is, the module 1336 produces primary transform domain coefficients from secondary transform domain coefficients. The reconstructed transform coefficients 1332 are input to a dequantiser module 1328. The dequantiser module 1328 performs inverse quantisation (or ‘scaling’) on the residual coefficients 1332, that is, in the primary transform coefficient domain, to create reconstructed intermediate transform coefficients, represented by an arrow 1340, according to the quantisation parameter 1374. The dequantiser module 1328 may also apply a scaling matrix to provide non-uniform dequantization within the TB, corresponding to operation of the dequantiser module 840. Should use of a non-uniform inverse quantisation matrix be indicated in the bitstream 1206, the video decoder 1204 reads a quantisation matrix from the bitstream 143 as a sequence of scaling factors and arranges the scaling factors into a matrix. The inverse scaling uses the quantisation matrix in combination with the quantisation parameter to create the reconstructed intermediate transform coefficients 1340.[000202] The reconstructed transform coefficients 1340 are passed to an inverse primary transform module 1344. The module 1344 transforms the coefficients 1340 from the frequency domain back to the spatial domain. The inverse primary transform module 1344 applies inverse DCT-2 transforms horizontally and vertically, constrained by the maximum available transform size as described with reference to the forward primary transform module 826. The result of operation of the module 1344 is a block of residual samples, represented by an arrow 1348. The block of residual samples 1348 is equal in size to the corresponding CB. The residual samples 1348 are supplied to a summation module 1350.[000203] At the summation module 1350, the residual samples 1348 are added to a decoded PB (represented as 1352) to produce a block of reconstructed samples, represented by an arrow 1356. The reconstructed samples 1356 are supplied to a reconstructed sample cache 1360 and an in-loop filtering module 1388. The in-loop filtering module 1388 produces reconstructed blocks of frame samples, represented as 1392. The frame samples 1392 are written to a frame buffer 1396. The frame buffer 1396 outputs image or video frames 1210.[000204] The reconstructed sample cache 1360 operates similarly to the reference sample cache 856 of the video encoder 542. The reconstructed sample cache 1360 provides storage for reconstructed samples needed to intra predict subsequent CBs without the memory 206 (e.g., by using the data 232 instead, which is typically on-chip memory). Reference samples, represented by an arrow 1364, are obtained from the reconstructed sample cache 1360 and supplied to a reference sample filter 1368 to produce filtered reference samples indicated by arrow 1372. The filtered reference samples 1372 are supplied to an intra-frame prediction module 1376. The module 1376 produces a block of intra-predicted samples, represented by an arrow 1380, in accordance with the intra prediction mode parameter 1358 signalled in the bitstream 1206 and decoded by the entropy decoder 1320. The intra prediction module 1376 supports the modes of the encoder-side module 864, including IBC and MIP. The block of samples 1380 is generated using modes such as DC, planar or angular intra prediction.[000205] When the prediction mode of a CB is indicated to use intra prediction in the bitstream 143, the intra-predicted samples 1380 form the decoded PB 1352 via a multiplexor module 1384. Intra prediction produces a prediction block (PB) of samples, which is a block in one colour component, derived using ‘neighbouring samples’ in the same colour component. The neighbouring samples are samples adjacent to the current block and by virtue of being preceding in the block decoding order have already been reconstructed. Where luma and chroma blocks are collocated, the luma and chroma blocks may use different intra prediction modes. However, the two chroma CBs share the same intra prediction mode.[000206] When the prediction mode of the CB is indicated to be inter prediction in the bitstream 1206, a motion compensation module 1334 produces a block of inter-predicted samples, represented as 1338. The block of inter-predicted samples 1338 are produced using a motion vector, decoded from the bitstream 143 by the entropy decoder 1320, and reference frame index to select and filter a block of samples 1398 from the frame buffer 1396. The block of samples 1398 is obtained from a previously decoded frame stored in the frame buffer 1396.For bi-prediction, two blocks of samples are produced and blended together to produce samples for the decoded PB 1352. The frame buffer 1396 is populated with filtered block data 1392 from the in-loop filtering module 1388. As with the in-loop filtering module 868 of the video encoder 542, the in-loop filtering module 1388 applies any of the DBF, the ALF and SAO filtering operations. Generally, the motion vector is applied to both the luma and chroma channels, although the filtering processes for sub-sample interpolation in the luma and chroma channel are different.[000207] Fig. 14 is a schematic block diagram showing an implementation 1400 of a configurable feature reconstruction module performing a decoder network topology, which may serve as the tensor decompressor 1250. A model 1405, in the example of Fig. 14 an ONNX model 1405 of the decoder network topology to be performed as the decompressor 1250 receives the tensor decompressor network topology information 1238 and the tensor weight information 1240. The structure of the tensor decompressor 1250 is selected by the ONNX model 1405 based on the information 1238. The weights for the tensor decompressor 1250 are selected by the ONNX model 1405 based on the information 1240. Based on the selections at the model 1405, a decompression model 1410 executes. In the example of Fig. 14, an ONNX runtime model 1410 executes to receive the compressed tensors 1224 and output the decompressed tensors 1254. As indicated in Fig. 14, resources required to run the ONNX model 1410 may be allocated from one or more resources, such as one or more of a CPU 1420, an FPGA 1424, a vector processing unit (VPU) 1428, a GPU 1432 and an interface model DirectML1436. Each of the resources 1420, 1424, 1428, 1432 and 1436 can be implemented on the module 201 or can be executed across one or more similar devices.[000208] Fig. 15 is a schematic block diagram showing a tensor decompressor 1500 using a multi-scale feature reconstruction stage, which may be selected at the step 1910 for use in the tensor decompressor 1250. In particular, the decompressor 1500 can be implemented as the runtime model 1410 of Fig. 14. The tensor decompressor 1500 includes a single-scale feature compression (SSFC) decompressor 1510. The SSFC decompressor 1510 receives the tensor 1224 having a reduced channel count, such as 64 channels, and passes the tensor 1224 to a convolution layer 1512, which outputs a tensor 1513 having a restored channel count, such as 256 channels. The tensor 1513 is passed to a batch normalisation module 1514 to produce a tensor 1515. The tensor 1515 is passed to a PreLU module 1516 to produce a tensor 1520. The tensor decompressor 1500 includes a MSFR module 1530. The MSFR module 1530 operates to produce a plurality of tensors from the tensor 1520 produced by execution of step 19120, described with reference to Fig. 19, using one or more trained convolutional layers. Upsamplemodules 1532, 1534, and 1536 upsample the tensor 1520 horizontally and vertically by factors of two, four, and eight, respectively, to produce tensors 1533, 1535, and 1537. The tensor 1537 forms one (P’2, 1557) output from the MSFR module 1530 and is passed to a downsample module 1542.[000209] The downsample module 1542 downsamples the tensor 1537 by a factor of two horizontally and vertically to produce a tensor 1543 having the same dimensionality as the tensor 1535. The tensor 1543 is provided to a convolution layer 1548 which outputs a tensor 1549. A summation module 1554 adds the tensors 1535 and 1549 to produce a tensor 1555 as an output (P’3) of the MSFR module 1530.[000210] A downsample module 1540 downsamples the tensor 1535 by a factor of two horizontally and vertically to produce a tensor 1541 having the same dimensionality as the tensor 1533. The tensor 1541 is provided to a convolution layer 1546 which outputs a tensor 1547. A summation module 1552 adds the tensors 1533 and 1547 to produce a tensor 1553 as an output (P’4) of the MSFR module 1530.[000211] A downsample module 1538 downsamples the tensor 1533 by a factor of two horizontally and vertically to produce a tensor 1539 having the same dimensionality as the tensor 1520. The tensor 1539 is provided to a convolution layer 1544 which outputs a tensor 1545. A summation module 1550 adds the tensors 1520 and 1545 to produce a tensor 1551 as an output (P’5) of the MSFR module 1530. The tenors P’2 1557, P’3 1555, P’4 1553 and P’5 1551 form the tensors 1254 of Fig. 12.[000212] Fig. 16A is a schematic block diagram showing an example implementation 1600 of the head portion 150 of a CNN for object detection, corresponding to a portion of a “YOLOv3” network excluding the “DarkNet-53” backbone portion. The CNN head portion 150 of Fig. 16A can be used when the CNN backbone is implemented as in Fig. 3 A for example.Depending on the task to be performed in the destination device 140, different networks may be substituted for the CNN head portion 150. Incoming tensors 149 are separated into the tensor of each layer (i.e., tensors 1610, 1620, and 1634). The tensor 1610 is passed to a CBL module 1612 to produce tensor 1614. The tensor 1614 is passed to a detection module 1616 and an upscaler module 1622. The detection module outputs bounding boxes 1618, in the form of a detection tensor. The bounding boxes 1618 are passed to a non-maximum suppression (NMS) module 1648.[000213] To produce bounding boxes addressing co-ordinates in the original video data 113, prior to resizing for the backbone portion of the network 114, scaling by the original video width and height is performed at the upscaler module 1622. The upscaler module 1622 receives the tensor 1614 and the tensor 1620 and produces an upscaled tensor 1624, which is passed to a CBL module 1626. The CBL module 1626 produces a tensor 1628 as output. The tensor 1628 is passed to a detection module 1630 and an upscaler module 1636. The detection module 1630 produces a detection tensor 1632, which is supplied to the NMS module 1648.[000214] The upscaler module 1636 is another instance of the module 1622. The upscaler module 1636 receives the tensor 1628 and the tensor 1634 and outputs an upscaled tensor 1638. The upscaled tensor 1638 is passed to a CBL module 1640, which outputs a tensor 1642 to a detection module 1644. The detection module 1644 produces a detection tensor 1646, which is supplied to the NMS module 1648.[000215] The CBL modules 1612, 1626, and 1640 each contain a concatenation of five CBL modules (e.g., CBL model 360 shown in Fig. 3D). The upscaler modules 1622 and 1636 are each instances of an upscaler module 1660 as shown in Fig. 16B. The module 1648 receives the tensors 1618, 1632 and 1646 and outputs the task result 151.[000216] As shown in Fig. 16B, the upscaler module 1660 accepts a tensor 1662 (for example the tensor 1614 of Fig. 16A) as an input. The tensor 1662 is passed to a CBL module 1666 (having structure of the module 360) to produce a tensor 1668. The tensor 1668 is passed to an upsampler 1670 to produce an upsampled tensor 1672. A concatenation module 1674 produces a tensor 1676 by concatenating the upsampled tensor 1672 with a second input tensor 1664 (for example the tensor 1620 input to the upscaler 1622 in Fig. 16A).[000217] The detection modules 1616, 1630, and 1644 are instances of a detection module 1680 as shown in Fig. 16C. The detection module 1680 receives a tensor 1682. The tensor 1682 is input to a CBL module 1684 having structure of the module 360. The CBL module 1684 generates a tensor 1686. The tensor 1686 is passed to a convolution module 1688, which implements a detection kernel to output a tensor 1690. In some arrangements, the detection kernel applies a 1 x 1 kernel to produce the output on feature maps at each of the three layers of the tensor. The detection kernel is 1 x 1 x (B x (5 + C) ), where B is the number of bounding boxes a particular cell can predict, typically three (3), and C is the number of classes, which may be eighty (80), resulting in a kernel size of two-hundred and fifty five (255) detection attributes (i.e. tensor 1290). The constant “5” represents four boundary box attributes(box centre x, y and size scale x, y) and one object confidence level (“objectness”). The result of a detection kernel has the same spatial dimensions as the input feature map, but the depth of the output corresponds to the detection attributes. The detection kernel is applied at each layer, typically three layers, resulting in a large number of candidate bounding boxes. A process of non-maximum suppression is applied by the NMS module 1648 to the resulting bounding boxes to discard redundant boxes, such as overlapping predictions at similar scale, resulting in a final set of bounding boxes as output for object detection.[000218] Fig. 17 is a schematic block diagram showing a head portion 1700 of a CNN. The head portion 1700 can be implemented as the CNN head portion 150 where the CNN backbone 114 is implemented as the backbone 400 for example. The head portion 1700 forms part of an overall network known as ‘Faster RCNN’ and includes a feature network (i.e., backbone portion 400), a region proposal network, and a detection network. Input to the head portion 1700 are the tensors 149, which include P2-P6 layer tensors 1710, 1712, 1714, 1716, and 1718. The P2-P5 layer tensors 1710, 1712, 1714, and 1716, correspond to the P2 to P 5 outputs 477, 475, 473, and 471 of Fig. 4. The P2-P6 tensors 1710, 1712, 1714, 1716, and 1718 are input to a region proposal network (RPN) head module 1720. The P6 tensor 1718 is produced by a max pool module 1742, operating on P5 tensor 1716 to perform a 2x2 max pooling operation. The RPN head module 1720 performs a convolution on the input tensors, generating an intermediate tensor. The intermediate tensor is fed into two subsequent sibling layers, (i) one for classifications and (ii) one for bounding box, or ‘region of interest’ (RO I), regression. A resultant output is classification and bounding boxes 1722. The classification and bounding boxes 1722 are passed to an NMS module 1724. The NMS module 1724 prunes out redundant bounding boxes by removing overlapping boxes with a lower score to produce pruned bounding boxes 1726. The bounding boxes 1726 are input to a region of interest (RO I) pooler 1728. The ROI pooler 1728 uses some of the layer tensors of the tensor 149 (described further hereafter) and the bounding boxes 1726 to produce fixed-size feature maps from various input size maps using max pooling operations. In the max pooling operation a subsampling takes the maximum value in each group of input values to produce one output value in the output tensor.[000219] Input to the ROI pooler 1728 are the P2-P5 feature maps 1710, 1712, 1714, and 1716, and region of interest proposals 1726. Each proposal (ROI) from 1726 is associated with a portion of the feature maps (1710-1716) to produce a fixed-size map. The fixed-size map is of a size independent of the underlying portion of the feature map 1710-1716. One of the feature maps 1710-1716 is selected such that the resulting cropped map has sufficient detail, forexample, according to the following rule: floor(4 + log2(sqrt(box_area) / 224)), where 224 is the canonical box size. The ROI pooler 1728 operates to crop incoming feature maps according to the proposals 1726 producing a tensor 1730.[000220] The tensor 1730 is fed into a fully connected (FC) neural network head 1732. The FC head 1732 performs two fully connected layers to produce class score and bounding box predictor delta tensor 1734. The class score is generally an 80-element tensor, each element corresponding to a prediction score for the corresponding object category. The bounding box prediction deltas tensor is an 80x4 = 320 element tensor, containing bounding boxes for the corresponding object categories. Final processing is performed by an output layers module 1736, receiving the tensor 1734 and performing a filtering operation to produce a filtered tensor 1738. Low-scoring (low classification) objects are removed from further consideration. A non-maximum suppression module 1740 receives the filtered tensor 1738 and removes overlapping bounding boxes by removing the overlapped box with a lower classification score, resulting in an inference output tensor 1742, corresponding to the tensor 151.[000221] Referring to Appendix E, the weights information may include a ‘no weights flag’, indicating that the decoder network topology to be used does not require any weights in order to operate.[000222] In an arrangement of the source device 110 and the destination device 140, network weights are signalled in the bitstream 121 as a delta relative to another set of network weights (the ‘base weights’) that are known to the system 100 or may be obtained via external means, such as from the tensor codec repository 180. The base weights may be indicated via reference using an identifier number stored in the bitstream 121. Signalling of network weights as a delta relative to other network weights may be accomplished using a syntax such as ‘MPEG Incremental Neural Network Representation’, under development as part of ISO / IEC 15938-17.[000223] Methods presented herein enable efficient representation of tensors in a format being amenable to compression using contemporary block-based compression standards such as VVC, HEVC, AVC or other standards. Block-based compression, although not intuitively applicable to data such as compressed feature maps or coefficients for projecting basis vectors to reconstruct feature maps, uncover additional unexpected redundancy in blocks such as by use of various transforms including trained secondary transforms. Although methods presented herein are described with reference to the ‘Faster RCNN’ and ‘YOLOv3’ network architecturesand specific divisions of these networks into ‘backbone’ and ‘head’ portions, the methods are applicable to any neural network operating on multi-dimensional tensor data and are applicable to different divisions of such networks into ‘backbone’ and ‘head’ portions.[000224] It should be noted that although the source device 110 and the destination device 140 are described with reference to the video source 112 comprising video and image data, other types of content such as audio data or textual data may also be supplied as input to neural networks applicable to such types of input and the resulting intermediate feature maps may be compressed and decompressed by the modules 116 and 146 with suitable encoder and decoder network topologies.INDUSTRIAL APPLICABILITY[000225] The arrangements described are applicable to the computer and data processing industries and particularly for the digital signal processing for the encoding and decoding of signals such as video and image signals, achieving high compression efficiency.[000226] Some implementations described use of an inserted NAL unit that identifies the compression approach used for coding feature maps and consequently also the NAL unit header format used for NAL units in the bitstream, including those related to tensor quantisation, reduction and restoration operations, i.e., operations outside the scope of packed feature frame coding. Accordingly, such implementations allow several different compression standards to be indicated in an FCM bitstream for ‘inner coding’ of packed feature frames, while supporting signalling of higher-level metadata needed to decode the FCM bitstream. Allowing compression standard used to be indicated in an FCM bitstream provides improved flexibility in implementation, including ability to be back-compatible with longer-existing standards such as AVC, compatibility with more recent standards such as HEVC or VVC and further flexibility to allow use of custom or other compression standards, unspecified’ values, which will not be used in future[000227] The foregoing describes only some embodiments of the present invention, and modifications and / or changes can be made thereto without departing from the scope and spirit of the invention, the embodiments being illustrative and not restrictive.APPENDIX AAVC / H.264 NAL unit formatBytes 0 to nalUnitHeaderBytes-1 in the NAL unit form the NAL unit header.A modified version of Table 7-1 from the AVC / H.264 spec, with codes reserved from FCM parameter sets and reservation NAL unit type necessary to distinguish from an ICI NAL unit is shown, as follows:* nal unit type = 0 is marked as ‘reserved (prohibited)’ rather than ‘unspecified’ to indicate this value is not available for allocation by groups, as such NAL units using this type would otherwise need to ensure the first byte of the RBSP could not contain a zero byte (0x00) due to the inability to insert an emulation_prevention_three_byte between the first and second bytes of the RBSP.APPENDIX BHEVC / H.265 NAL unit header and payloadNAL unit type codesAPPENDIX CVVC / H.266 NAL unit format is as follows:VVC / H.266 NAL unit header format is as follows (always 16 bits or two bytes):VVC / H.266 NAL unit types:APPENDIX DInner codec identifier NAL unitNumBytesInNALunit shall be equal to 1.Inner codec identifier specifies the inner codec as follows:In the case of value 3 (“custom”), an alternative NAL unit encapsulation with FCM-specific NAL unit headers is supported, supporting custom inner codecs.The following custom inner codecs are supported:• End-to-end learned inner codec o Entropy coded payloads are encoded as RBSPs.• Bypassed inner codec o Quantized tensors values are encoded as RBSPs.■ Optionally with basic encoding like DeepCABAC, and optionally using delta coding mechanism to compress runs of zeros as zero-delta values.APPENDIX EAn example FCM VMPS, FCM SPS, and FCM PPS message format and associated semantics for representing metadata associated with tensor decompressor structure, tensor packing, and complexity indication in a bitstream are as follows:FCM vision model parameter setFCM Sequence parameter setFCM picture parameter setWhere u(n) refers to a fixed-length codeword n bits in length and ue(v) refers to an unsigned exponential Golomb variable-length codeword.FCM SPS and FCM PPS semantics: fcm sps inner decoding bypass flag set equal to one indicates that the inner decoding (module 1204) is not performed and when equal to zero indicates that the inner decoding is performed. fcm_sps_quantisation_bypass_flag set equal to one indicates that the inverse quantisation (module 1218) is not performed and when equal to zero indicates that the inverse quantisation is performed. fcm_sps_feature_restoration_bypass_flag set equal to one indicates that the feature restoration (module 1250) is not performed and when equal to zero indicates that the feature restoration is performed. fcm sps temporal upsampling enabled flag set equal to one indicates that temporal interpolation or upsampling (module 1260) may be performed according to the most recently signalled temporal upsampling ratio, when set to zero indicates that the temporal upsampling is not performed. fcm pps temporal upsampling enabled flag set equal to one indicates that temporal interpolation or upsampling (module 1260) is performed according to the most recently signalled temporal upsampling ratio, when set to zero indicates that the temporal upsampling is not performed. It is a requirement of bitstream conformance that when fcm sps temporal upsampling enabled flag is equal to zero, fcm_pps_temporal_upsampling_enabled_flag is also equal to zero.temporal_upsampling_ratio_minus2 signals the integer upsampling ratio minus 2, i.e., a value of zero signals an upsampling ratio of two, a value of one signals an upsampling ratio of three, and so on. terminate sequence flag is set to one when temporal upsampling is enabled and the source device 110 is terminating encoding of the bitstream and wishes to signal zero or more ‘trailing pictures’, i.e., pictures to be output from the temporal upsampler 1260 produced using only one previous picture and no forward reference to the next picture output from the picture decoder 1204. Each trailing picture is a duplicate of the most recently decoded picture. trailing_picture_cnt signals how many trailing pictures to output before termination of the bitstream 121. The values of trailing_picture_cnt must be between zero and temporal upsampling ratio minus one. For example, when the temporal upsampling ratio is set to two (temporal_upsampling_ratio_minus2 equal to zero), trailing_picture_cnt is permitted to be zero or one. set_level_flag equal to one indicates that the tensor decompression complexity indication is to be signalled in this instance of the FCM decoder info SEI message. fcm_level signals the complexity indication for any tensor decompressors to be performed in the decoder. The complexity indication provides a worst-case limit on the complexity of any instantiated tensor decompressor. It is a requirement of bitstream conformance that the tensor decompression complexity indication is signalled prior to use of the FCM decoder, e.g., signalled with the first frame of packed tensor data in the bitstream. The following table shows permitted maximum values for complexity aspects for given fcvcm level values:update decoder flag equal to one indicates that the FCM decoder is to be updated, effective from this instance of the FCMM decoder info SEI message onwards. no weights flag equal to one indicates that the FCM decoder does not include any trained elements (e.g., convolutions) and therefore does not require any weights. explicit_signal_decoder_flag equal to one indicates that the FCM decoder architecture is signalled explicitly in this instance of the FCM decoder info SEI message. When equal to zero, this instance of the FCM decoder info SEI message instead references a previously signalled FCM decoder architecture or references an FCM decoder architecture obtained by external means, e.g., a predetermined architecture or an architecture available from a publicly accessible registry. explicit_decoder_compression_idc specifies the compression technique (if any) applied to the payload containing the representation of the FCM decoder architecture, in accordance with the following table:explicit_decoder_format_idc specifies the format in which the FCM decoder architecture is encoded, with the following formats supported:explicit_decoder_format_version_idc specifies the version of the format in which the FCVCM decoder architecture is encoded. For each supported format, a separate enumeration of explicit_decoder_format_version_idc values to versions Of the format is specified. explicit_decoder_payload_len specifies the length of the payload containing the FCM decoder representation in bytes, after application of Compression (if applicable). decoder_payload[ i ] specifies the ith byte of the FCM decoder representation. register decoder idc flag equal to one indicates that the FCM decoder representation signalled in this instance of the FCM decoder info SEI message is to be registered (retained) in the decoder for potential future reference. decoder_idc specifies an index value for addressing the FCM decoder representation in a registry of retained FCM decoder architectures. explicit_signal_weights_flag equal to one indicates that weights associated with the signalled FCM decoder representation are included in this instance of the FCM decoder info SEI message. explicit_weights_idc specifies an index for the weights signalled in this instance of the FCM decoder info SEI message. explicit_weights_payload_len specifies the length of the weights payload in the FCM decoder info SEI message. weights_payload[ i ] specifies the ith byte of the weights payload in the FcM decoder info SEI Message. register_weights_idc_flag equal to one specifies that the weights signalled in this instance of the FCVCM decoder info SEI message are stored in the FCM decoder for potential future reference. registered_decoder_idc specifies an index coded as a null-terminated UTF-8 string or with a signalled length to address an FCM decoder representation that is either known to the decoder by external means or was registered with the FCM decoder in an earlier instance of the FCM decoder info SEI Message. The registered decoder idc may be signalled as an index, as a variable-length string, or a universally unique identifier (UUID), or other mechanism that enables the decoder network topology to be uniquely identified. Signalling of the registered decoder idc may also select associated weights to be used with the selected decoder network topology.set region ent flag equal to one indicates that this instance of the FCM decoder info SEI message signals a count of regions into which the current and subsequent pictures are to be divided. region_cnt indicates a count of regions into which the current and subsequent pictures are to be divided. Each region is rectangular in shape and aligned to CTU boundaries. Each region is populated with feature Maps from one or more Tensors. set_region_packing_flag equal to one indicates that this instance of the FCM decoder info SEI message specifies a division of the current picture into one or more rectangular regions. This division remains in effect until the next instance of an FCM decoder info SEI message with set_region_packing_flag equal to one. top_left_rsctuaddr[ i ] specifies the address in raster-scan order of the CTU in the top-left position in the ith region. top_right_rsctuaddr[ i ] specifies the address in raster-scan order of the CTU in the top-right position in the ith region. bottom_left_rsctuaddr[ i ] specifies the address in raster-scan order of the CTU in the bottomleft position in the ith region. bottom_right_rsctuaddr[ i ] specifies the address in raster-scan order of the CTU in the bottom-right position in the ith region. horizontal_packing_flag[ i ] equal to one specifies when the packing or unpacking progresses from one feature maps of one tensor to feature maps of the next tensor within the ith region, packing will continue long in a left-to-right manner. When equal to zero, upon progressing from feature maps of one tensor to feature maps of the next tensor, packing of feature maps advances to the leftmost position in the current region and below the previously packed feature maps within the current region. The value one may be used where multiple tensors, each containing few (e.g., one) feature maps are to be packed, requiring a region generally larger in width than in height and generally smaller frame area for the regions. explicit cropping enabled flag equal to one specifies that the FCM decoder may crop the decoded tensors from the feature restoration module 1250 to match the required dimensions of the restored-domain tensors according to the crop * syntax elements (the ‘cropping parameters’). When cropping enabled flag is equal to zero, it is a requirement of bitstream conformance that the tensors resulting from the feature restoration module 1250 match the required dimensions of the restored-domain tensors.set reduced tensor info flag equal to one specifies that the number of tensors in the defined regions and dimensions of the reduced-domain tensors is signalled in this instance of the FCM decoder info SEI message. region_tensor_cnt[ i ] specifies the number of reduced-domain tensors to be packed in the ith region. reduced_tensor_batch_size[ i ][ j ] specifies the batch size of the jth tensor in the reduced domain being packed into the ith region. reduced_tensor_max_channels[ i ] [ j ] specifies the maximum number of feature maps (i.e., channels) of the jth tensor in the reduced domain being packed in the ith region. reduced_tensor_width[ i ] [ j ] specifies the width of feature maps of the jth tensor in the reduced domain being packed in the ith region. reduced_tensor_height[ i ][ j ] specifies the height of feature maps of the jth tensor in the reduced domain being packed in the ith region. set_restored_tensor_info_flag equal to one specifies that the number of and dimensionality of tensors output from the FCM decoder, i.e., tensors in the restored domain, is specified in this instance of the FCM decoder info SEI message. restored_tensor_cnt specifies the number of restored-domain tensors output from the FCM decoder. restored_tensor_batch_size[ i ] specifies the batch size in the ith restored-domain tensor output from the FCM decoder. restored_tensor_channels[ i ] specifies the number of channels in the ith restored-domain tensor output from the FCM decoder. restored_tensor_width[ i ] specifies the width of the ith restored-domain tensor output from the FCM decoder. restored_tensor_height[ i ] specifies the height of the ith restored-domain tensor output from the FCM decoder. update_tensor_channels_flag equal to one indicates that the flags to update packed number of feature maps for each tensor in each region are to be signalled in this instance of the FCM decoder info SEI message.update_tensor_channel_flag[ i ][ j ] equal to one indicates that the packed number of feature maps for the jth tensor in the ith region is to be signalled in this instance of the FCM decoder info SEI message. tensor_channel_cnt[ i ][ j ] specifies the packed number of feature maps (i.e., channels) for the jth tensor of the ith region. When tensor channel cntf i ][ j] is not signalled and tensor max channelsf i ][ j] is signalled, the value is inferred to be equal to the corresponding tensor max channelsf i ][ j ]. When tensor channel cntf i ][ j ] is not signalled or inferred in the current instance of the FCM decoder info SEI message, the value remains in effect from the previous instance of the FCM decoder SEI message (if available), otherwise the value is inferred as 0. qr_mantissa_len specifies the number of bits to be used to encode the mantissa portion of the reduced-domain quantisation range. qr_min_exp[ i ][ j ] specifies the exponent portion of the lower bound of the reduced-domain quantisation range for the jth tensor in the reduced domain being packed in the ith region, qr min exp signf i ][ j ] specifies the sign of the exponent portion of the lower bound of the reduced-domain quantisation range for jth tensor in the reduced domain being packed in the ith region. qr_min_mantissa[ i ][ j ] specifies the fraction portion of the lower bound of the reduced- domain quantisation range for the jth tensor in the reduced domain being packed in the ith region, with a bit width as specified by qr mantissa len. qr_min_mantissa_sign[ i ][ j ] specifies the sign of the fraction portion of the lower bound of the reduced-domain quantisation range for the jth tensor in the reduced domain being packed in the ith region. qr_max_exp[ i ][ j ] specifies the exponent portion of the upper bound of the reduced-domain quantisation range for the jth tensor in the reduced domain being packed in the ith region. qr_max_exp_sign[ i ][ j ] specifies the sign of the exponent portion of the upper bound of the reduced-domain quantisation range for jth tensor in the reduced domain being packed in the ith region. qr_max_mantissa[ i ][ j ] specifies the fraction portion of the upper bound of the reduced- domain quantisation range for the jth tensor in the reduced domain being packed in the ith region, with a bit width as specified by qr mantissa len. qr_max_mantissa_sign[ i ][ j ] specifies the sign of the fraction portion of the upper bound of the reduced-domain quantisation range for the jth tensor in the reduced domain being packed in the ith region, output datatype update flag equal to one specifies that this instance of the FCM decoder SEI message updates the datatype of the FCM decoder output tensors and / or their range. output_datatype_idc equal to zero specifies a custom data format for the FCM decoder output and other values indicating floating-point or integer data formats.output_datatype_exponent_len specifies the length of the exponent for a custom output data format, with a value of zero indicating an integer rather than floating-point output format. output_datatype_mantissa_len specifies the length of the mantissa for a custom output data format when the exponent length is nonzero or the number of bits for a custom output data format when the exponent length is equal to zero. output datatype implicit mantissa flag equal to one specifies that tensors output from the FCM decoder all use a mantissa value rather than using a mantissa signalled on a per-element basis for each output tensor. output_data_implicit_mantissa_value when present signals the implicit mantissa used for all elements of all output tensors from the FCM decoder. output scaling enable flag equal to one indicates that this instance of the FCM decoder SEI message updates the quantisation min and max (or lower and upper bound) for the quantisation stage performed after the feature restoration stage. qr_second_mantissa_len specifies the number of bits to be used to encode the mantissa portion of the quantisation range. qr_second_min_exp[ i ] specifies the exponent portion of the lower bound of the output quantisation range for the ith tensor in the restored domain. qr_second_min_exp_sign[ i ] specifies the sign of the exponent portion of the lower bound of the output quantisation range for ith tensor in the restored domain. qr_second_min_mantissa_sign[ i ] specifies the sign of the fraction portion of the lower bound of the output quantisation range for the ith tensor in the restored domain. qr_second_max_exp[ i ] specifies the exponent portion of the upper bound of the output quantisation range for the ith tensor in the restored domain. qr_second_max_exp_sign[ i ] specifies the sign of the exponent portion of the upper bound of the output quantisation range for ith tensor in the restored domain. qr_second_max_mantissa[ i ] specifies the fraction portion of the upper bound of the output quantisation range for the ith tensor in the restored domain, with a bit width as specified by qr second mantissa len. qr_second_max_mantissa_sign[ i ] specifies the sign of the fraction portion of the upper bound of the output quantisation range for the ith tensor in the restored domain.

Claims

CLAIMS1. A method of decoding a bitstream to produce tensors for use by a neural network second portion, the method comprising: decoding a network abstraction layer (NAL) unit from the bitstream having a predetermined length, wherein the NAL unit of the predetermined length indicates a NAL unit format of one inner codec of a plurality of inner codecs, each other inner codec of the plurality of inner codecs having a NAL unit length different to the predetermined length; selecting an inner codec from the plurality of inner codecs based on the decoded NAL unit of the predetermined length; and decoding the bitstream using the selected inner codec to produce the tensors.

2. The method according to claim 1, wherein the bitstream includes a plurality of NAL units and the decoded NAL unit is a NAL unit header.

3. The method according to claim 2, wherein the header is present in the bitstream prior to any units of data to be provided to the inner codec.

4. The method according to claim 2, wherein multiple instances of the NAL unit header are present in the bitstream.

5. The method according to claim 4, wherein one or more instances of the NAL unit header are present prior to random access entry points in the bitstream.

6. The method according to claim 5, wherein a plurality of inner codecs are used in the bitstream.

7. The method according to claim 1, wherein the predetermined length is one byte.

8. The method according to claim 1, wherein the plurality of inner codecs includes at least one of advanced video coding (AVC), high efficiency video coding (HEVC) and versatile video coding (VVC).

9. The method according to claim 1, wherein the plurality of inner codecs includes AVC, HEVC, VVC and a custom codec.

10. The method according to claim 1, wherein the NAL unit follows a start code in the bitstream.

11. A method of encoding tensors to a bitstream for use by a neural network second portion, the method comprising: selecting an inner codec from a plurality of inner codecs for use in encoding tensors to the bitstream; encoding a network abstraction layer (NAL) unit to the bitstream having a predetermined length, wherein the NAL unit of the predetermined length indicates a NAL unit format of the selected inner codec of the plurality of inner codecs, each other inner codec of the plurality of inner codecs having a NAL unit length different to the predetermined length; and encoding the tenors to the bitstream using the selected inner codec.

12. The method according to claim 11, wherein the bitstream includes a plurality of NAL units and the decoded NAL unit is a NAL unit header.

13. The method according to claim 12, wherein the header is present in the bitstream prior to any units of data to be provided to the inner codec.

14. The method according to claim 12, wherein multiple instances of the NAL unit header are present in the bitstream.

15. The method according to claim 14, wherein one or more instances of the NAL unit header are present prior to random access entry points in the bitstream.

16. The method according to claim 1, wherein the plurality of inner codecs includes at least one of advanced video coding (AVC), high efficiency video coding (HEVC) and versatile video coding (VVC).

17. A decoder for decoding a bitstream to produce tensors for use by a neural network second portion, the decoder configured to: decode a network abstraction layer (NAL) unit from the bitstream having a predetermined length, wherein the NAL unit of the predetermined length indicates a NAL unit format of one inner codec of a plurality of inner codecs, each other inner codec of the plurality of inner codecs having a NAL unit length different to the predetermined length; select an inner codec from the plurality of inner codecs based on the decoded NAL unit of the predetermined length; and decode the bitstream using the selected inner codec to produce the tensors.

18. A non-transitory computer-readable storage medium which stores a program for executing a method of decoding a bitstream to produce tensors for use by a neural network second portion, the method comprising: decoding a network abstraction layer (NAL) unit from the bitstream having a predetermined length, wherein the NAL unit of the predetermined length indicates a NAL unit format of one inner codec of a plurality of inner codecs, each other inner codec of the plurality of inner codecs having a NAL unit length different to the predetermined length; selecting an inner codec from the plurality of inner codecs based on the decoded NAL unit of the predetermined length; and decoding the bitstream using the selected inner codec to produce the tensors.

19. An encoder for encoding tensors to a bitstream for use by a neural network second portion, the encoder configured to: select an inner codec from the plurality of inner codecs for use in encoding tensors to the bitstream;encode a network abstraction layer (NAL) unit to the bitstream having a predetermined length, wherein the NAL unit of the predetermined length indicates a NAL unit format of the selected inner codec of the plurality of inner codecs, each other inner codec of the plurality of inner codecs having a NAL unit length different to the predetermined length; and encode the tenors to the bitstream using the selected inner codec.

20. A non-transitory computer-readable storage medium which stores a program for executing a method of encoding tensors to a bitstream for use by a neural network second portion, the method comprising: selecting an inner codec from a plurality of inner codecs for use in encoding tensors to the bitstream; encoding a network abstraction layer (NAL) unit to the bitstream having a predetermined length, wherein the NAL unit of the predetermined length indicates a NAL unit format of the selected inner codec of the plurality of inner codecs, each other inner codec of the plurality of inner codecs having a NAL unit length different to the predetermined length; and encoding the tenors to the bitstream using the selected inner codec.

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