Microprocessor register tag allocation at issue time

Abstract

A method is provided for assigning register tags to instructions at issue time. The method includes receiving an instruction for execution by a microprocessor. The method further includes dispatching the instruction to an issue queue without assigning a register tag to the instruction. The method further includes determining that the instruction is ready to be issued. The method includes assigning an available register tag to the instruction in response to determining that the instruction is ready to be issued. The method further includes issuing the instruction.

Description

[Technical Field]

[0001] The present disclosure relates generally to the field of computing, and more particularly to assigning register tags to instructions executed by a microprocessor at issue time. [Background technology]

[0002] A microprocessor is a computer processor that incorporates the functions of a central processing unit into one or more integrated circuits (ICs). The processor executes instructions (e.g., store instructions) based on clock cycles. A clock cycle, or simply "cycle," is a single electronic pulse of the processor. Summary of the Invention

[0003] Embodiments of the present disclosure include methods, computer program products, and systems for assigning register tags to instructions at issue time.

[0004] According to one aspect, a method includes receiving an instruction for execution by a microprocessor. The method further includes dispatching the instruction to an issue queue without assigning a register tag to the instruction. The method further includes determining that the instruction is ready to be issued. The method includes assigning an available register tag to the instruction in response to determining that the instruction is ready to be issued. The method further includes issuing the instruction.

[0005] According to another aspect, a system is provided comprising a processor configured to perform a method including receiving an instruction for execution by a microprocessor; dispatching the instruction to an issue queue without assigning a register tag to the instruction; determining that the instruction is ready to be issued; and, in response to determining that the instruction is ready to be issued, assigning an available register tag to the instruction; and issuing the instruction.

[0006] According to another aspect, a computer program product is provided comprising one or more computer-readable storage media having program instructions embodied thereon, the program instructions being executable by the processor to perform a method including receiving an instruction for execution by the processor; dispatching the instruction to an issue queue without assigning a register tag to the instruction; determining that the instruction is ready to be issued; and, in response to determining that the instruction is ready to be issued, assigning an available register tag to the instruction; and issuing the instruction.

[0007] The above summary is not intended to describe each illustrated embodiment or every implementation of the present disclosure.

[0008] The drawings included in this disclosure are incorporated into and form a part of this specification. These drawings illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure. The drawings are merely illustrative of typical embodiments and are not intended to limit the disclosure. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a block diagram of a processor core in which illustrative embodiments of the present disclosure may be implemented. [Figure 2] FIG. 2 is a high-level block diagram of various components of an exemplary processor microarchitecture, in accordance with an embodiment of the present disclosure. [Figure 3] FIG. 1 is a block diagram of an example micro-architecture of a processor configured to assign register tags at issue time, in accordance with an embodiment of the present disclosure. [Figure 4] 1 is a flow diagram of an exemplary method for assigning register tags to instructions at issue time, according to an embodiment of the present disclosure. [Figure 5]FIG. 1 is a high-level block diagram of an exemplary computer system that may be used in implementing one or more of the methods, tools, and modules described herein and any associated functionality, in accordance with embodiments of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0010] The embodiments described herein are susceptible to various modifications and alternative forms, details of which have been shown by way of example in the drawings and will be described in detail. It is to be understood, however, that the particular embodiments described are not to be construed in a limiting sense. On the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention.

[0011] The present disclosure relates generally to the field of computing, and more particularly to assigning register tags to instructions executed by a microprocessor at issue time. While the present disclosure is not necessarily limited to such applications, various aspects of the present disclosure may be understood through a discussion of various examples using this context.

[0012] Microprocessor architectures utilize various registers to store data for execution / manipulation by instructions. To keep track of which register (or location within a register) stores data for a particular instruction, the microprocessor utilizes a register file (or two or more register files). The register file holds the register locations required for the various instructions executed by the hardware threads within a superslice. In some processors, the register file may be divided into blocks. For example, in some POWER® processors, the register file is called the slice target register file (STF) and consists of four smaller STF blocks that work together to provide a larger register file for the core. (POWER is a registered trademark owned by International Business Machines Corporation.)

[0013] To ensure that multiple instructions do not attempt to store different data in the same location, a microprocessor assigns register tags (e.g., STF tags) to instructions. Unused register tags may be kept in a free list (e.g., STF free list). When an instruction is received at dispatch time, the processor checks for available registers. If a register is available, the processor assigns the instruction a register tag from the free list, and the instruction is allowed to proceed with the associated tag. Once a register tag is assigned, it is removed from the free list, and its corresponding entry in the register file (and therefore the register location) cannot be assigned to a new instruction. The use of register tags and register files allows the processor to ensure that instructions do not collide (e.g., do not overwrite data needed by yet another instruction).

[0014] In traditional processor architectures, register tags (and, accordingly, entries in the register file) are assigned to instructions relatively early in the pipeline, often during instruction dispatch, in any case before the instruction is sent to the Issue Queue (ISQ). As a result, register tags are assigned to instructions and therefore unavailable to other instructions for a relatively long time. This can lead to high register file utilization, and some instructions may have to wait an unnecessarily long time for register tags to be freed up.

[0015] Embodiments of the present disclosure address these and other problems with traditional microprocessor architectures by allocating register files at issue time, thus reducing the window in which registers must be allocated, allowing instructions to be dispatched to the issue queue and waiting for register tags.

[0016] In some embodiments, dispatch logic within the processor may write the instruction tag (ITAG) of the received instruction to the mapper. Additionally, older ITAGs may be pushed to a save and restore buffer (SRB). The SRB tracks previous mappings of a given register. For example, if the processor writes to a particular general purpose register (GPR), such as GPR3, five times, the mapper will have only the youngest register, and the SRB will store the five previous ITAGs. The purpose of the SRB is to back up the processor state in case the processor needs to perform a flush. The dispatch logic also dispatches the instruction to the ISQ. In some embodiments, these operations are performed without assigning register tags to the instructions.

[0017] An instruction waits in the ISQ without a register tag until issue time approaches. At issue time, register tag allocation logic in the processor assigns a free register tag to the instruction. The processor also broadcasts the instruction's ITAG and register tag to the ISQ and mapper. The mapper uses the received ITAG to identify a matching location and writes it to the assigned register tag. The mapper also sets the instruction's ready bit (W, for example, by setting W=1). The ready bit indicates whether the data is in the register and the instruction is ready to execute. Similarly, in the ISQ, a matching location is identified, the assigned register tag is written to the source location, and the ready bit is set. The register tag is also written to the matching location in the SRB, and the ready bit is set in the SRB. The instruction is then executed.

[0018] If an instruction reaches its issue time and no register tags are available, the instruction is not issued until register tags become available. In some embodiments, an entry in the register file is kept free to prevent a situation in which a next-to-complete (NTC) instruction does not have an available register entry. This reserved entry can be allocated to the NTC instruction to allow it to issue if it does not have a register tag. If a hang occurs (e.g., if register tags are not freed by issuing an instruction), a flush is performed to clear and reclaim the in-flight register tags. In some embodiments, a mini-hang-buster may be implemented by clearing only some register tags instead of performing a full flush.

[0019] Performing register tag allocation at issue time has many advantages over existing architectures. For example, it reduces dispatch complexity because register file availability does not need to be considered during dispatch. Furthermore, allocating register tags late results in more efficient use of register file entries because the processor knows that issuing an instruction will return a result. Furthermore, it can reduce the number of required register file entries, and therefore the physical size of the register file, or enable deeper speculation if the register file size is not reduced. In other words, embodiments of the present disclosure can enable a system with the same register file size to have a deeper out-of-order window or to go deeper into a predicted branch path before resolving the path. The release list can also be physically located closer to the ISQ and / or vector / scalar unit (VSU), which should help dispatch complete the entire pipeline because the ITAG release list no longer needs to pay attention to the register file hole count. Finally, embodiments of the present disclosure can reuse logic that already sets the valid bit in the ISQ.

[0020] Embodiments of the present disclosure will now be described with reference to the drawings. While embodiments of the present disclosure are generally described with reference to a POWER® processor, it should be understood that this is done for illustrative purposes. The present disclosure may be implemented with other processor architectures, and the present disclosure should not be limited to POWER® processors.

[0021] As used herein, a "producer" is an operation / instruction on which a dispatched instruction depends. For example, if a first operation writes to GPR3 ​​and then a second operation reads from GPR3, the first operation is considered the producer of the second operation. Therefore, the producer ITAG is the ITAG of the producer instruction.

[0022] As used herein, a "source STF tag" is an STF tag that identifies which physical register an instruction will read to perform its operation. The source STF tag resides in ISQ 330 before the instruction begins issuing. A "destination STF tag" is an STF tag associated with the register that the instruction actually writes to. For instructions that have not issued and depend on the destination STF tag, the destination STF tag is fed back to ISQ 330, mapper 320, and SRB 340. For example, assume there are back-to-back instructions that use a particular register (REG1). The first instruction writes to REG1, and the second instruction reads from REG1 and performs some operation on the data read from REG1. The destination STF tag of the first instruction is fed back to ISQ 330, mapper 320, and SRB 340 so that the second instruction can identify the appropriate register from which to read the data. In other words, the destination STF tag of the first instruction acts as the source STF tag of the second instruction.

[0023] Similarly, the "source ITAG" of a particular instruction is the ITAG of the instruction on which the particular instruction depends. In other words, the source ITAG is the producer's ITAG. Similarly, the "destination ITAG" is the instruction's own ITAG. Thus, the destination ITAG of a first instruction serves as the source ITAG for any instruction that depends on the first instruction (e.g., whose stored data is read by the first instruction).

[0024] Referring now to the figures, FIG. 1 illustrates a block diagram of a processor core 100 according to an embodiment of the present disclosure. In some embodiments, processor core 100 may be part of a multi-core central processing unit (CPU). In other embodiments, processor core 100 may be part of a single-core CPU. Processor core 100 may support simultaneous multithreading (SMT). Thus, each processor core 100 may be capable of executing multiple hardware threads. For example, processor core 100 illustrated in FIG. 1 supports SMT-4 mode (e.g., using four hardware threads per core).

[0025] Within a core, hardware threads may be divided into superslices, which are groups of slices that share some hardware. For example, an SMT-4 processor may contain four hardware threads divided into two different superslices, with each superslice having the hardware and architected resources necessary for the two hardware threads to operate independently from the hardware threads in the other superslice. In other words, each superslice may operate independently from the other superslices. Therefore, each superslice may maintain its own register file.

[0026] Processor core 100 includes two superslices 100A and 100B. The first superslice 100A (also referred to as superslice 0) may include internal hardware 121A (also referred to as microarchitectural resources) and two hardware threads 101A and 111A. Similarly, the second superslice 100B (also referred to as superslice 1) may include internal hardware 121B and two hardware threads 101B and 111B. The internal hardware 121A and 121B (collectively or individually referred to herein as internal hardware 121) may be substantially similar or identical for each superslice. Similarly, the first hardware threads 101A, 101B (collectively or individually referred to herein as first hardware threads 101) and second hardware threads 111A, 111B (collectively or individually referred to herein as second hardware threads 111) in each superslice 100A, 100B may be substantially similar or identical for each superslice. Additionally, although not shown in FIG. 1 , processor core 100 may include some components that are external to (i.e., common to) superslices 100A, 100B. For example, processor core 100 may include an instruction fetch unit (IFU) that supplies both superslices 100A, 100B.

[0027] Internal hardware 121 may include execution units 125. Execution units 125 may include one or more fixed-point units (FXU) 125A, load-store units (LSU) 125B, vector / scalar units (VSU) 125C, floating point units (FPU) 125D, and decimal floating point units (DFU) 125E. In some embodiments, processor core 100 may include other execution units, such as a cryptographic unit, a condition register unit, and / or a branch register unit, among others.

[0028] Internal hardware 121 may also include, for example, one or more caches 122, issue queues 123, buffers 124, and / or branch prediction units (not shown). Cache 122 may be a multi-level hierarchical cache. For example, each core within a processor (e.g., processor core 100) may have its own L1 cache. The L1 cache may be shared by all hardware threads within a processor core (e.g., first hardware thread 101 and second hardware thread 111). A core may access an L2 cache and an L3 cache, which may be shared with other processor cores, between superslices within the same core, or both.

[0029] The internal hardware 121 also includes a mapper 130 that is responsible for managing the STF tags for the hardware threads 101, 111.

[0030] Hardware threads 101 and 111 may each have their own set of architected resources 102 and 112. Architected resources 102 and 112 may include one or more registers dedicated to a particular hardware thread. For example, architected resources 102 and 112 may include one or more sets of general-purpose registers (GPRs) 103 and 113, floating-point registers (FPRs) 104 and 114, and special-purpose registers (SPRs) 105 and 115. In some embodiments, FPRs 104 and 114 may support storage of floating-point vectors. In these embodiments, FPRs 104 and 114 may be vector / scalar registers (VSRs).

[0031] Processor core 100 supports SMT using four hardware threads and may therefore be referred to as supporting SMT-4 or being an SMT-4 processor core. While processor core 100 shown in FIG. 1 is an SMT-4 processor core, other types of processor cores otherwise consistent with this disclosure are contemplated. For example, in some embodiments, an SMT-2 (two hardware threads per core) or SMT-8 (eight hardware threads per core) processor may be used when implementing one or more of the methods disclosed herein.

[0032] 2, there is shown a high-level block diagram of various components of an exemplary microprocessor 200 according to an embodiment of the present disclosure. Microprocessor 200 includes an instruction fetch unit (IFU) 202, an instruction sequencing unit (ISU) 204, a load store unit (LSU) 208, a vector / scalar unit (VSU) 206, and completion and exception handling logic 210.

[0033] IFU 202 is a processing unit responsible for organizing program instructions to be fetched from memory and executed in the proper order. IFU 202 is often considered to be part of the control unit (e.g., the unit responsible for directing the operation of the processor) of a central processing unit (CPU).

[0034] ISU 204 is a compute unit responsible for dispatching instructions to issue queues, renaming registers to support out-of-order execution, issuing instructions from the issue queue to the execution pipeline, completing instructions in progress, and handling exceptions. ISU 204 includes an issue queue, from which all instructions are issued once dependencies are resolved. ISU 204 may also include logic for assigning STF tags to instructions in the issue queue at issue time.

[0035] The VSU 206 is a computing unit that maintains ownership of the slice target file (STF). The STF holds all register data supplied by the instruction. For example, for a store instruction without a target, the STF holds the registers required for the store address operand and store data sent to the LSU 208 for execution. The VSU 206 includes an FXU (e.g., FXU 125A), a VSU (e.g., VSU 125C), an FPU (e.g., FPU 125D), and a DFU (e.g., DFU 125E).

[0036] LSU 208 is an execution unit responsible for executing all load and store instructions, managing the processor's core's interface with the rest of the system using a unified cache, and performing address translation. For example, LSU 208 generates virtual addresses for load and store operations and loads data from memory (for load operations) or stores data from registers to memory (for store operations). LSU 208 may include a queue for memory instructions, and LSU 208 may operate independently from other units.

[0037] Completion and exception handling logic 210 (hereinafter "completion logic" 210) is responsible for completing instructions. If an instruction causes an exception, completion logic 210 flushes the instruction and signals the IFU to refetch the instruction.

[0038] It should be understood that the components 202-210 shown in Figure 2 are provided for illustrative purposes and to explain the principles of embodiments of the present disclosure. Some processor architectures may include more, fewer, or different components, and in some embodiments, various functions of components 202-210 may be performed by different components. For example, exception and completion handling may be performed by ISU 204.

[0039] Additionally, a processor may include two or more of components 202-210. For example, a multi-core processor may include one or more instruction fetch units (IFUs) 202 per core. Additionally, while embodiments of the present disclosure are generally described with reference to POWER® processors, this is done for illustrative purposes. The present disclosure may be implemented with other processor architectures, and the present disclosure should not be limited to POWER® processors.

[0040] Referring now to FIG. 3 , a block diagram of an exemplary microprocessor 300 configured to assign STF tags to instructions at issue time is shown, in accordance with an embodiment of the present disclosure. Microprocessor 300 includes dispatch 310, mapper 320, issue queue (ISQ) 330, save and restore buffer (SRB) 340, STF tag assignment logic 350, execution logic 360, and comparison logic 370, 380. While various components in FIG. 3 are shown as stand-alone components, it should be understood that various components may actually be subcomponents of larger components. For example, dispatch 310 and mapper 320 may be part of ISU 204.

[0041] In the current design, STF tags are allocated at dispatch time, and this dispatch time allocation can put significant pressure on the STF hole count timing of dispatch 310. This dispatch time allocation also requires a deeper pool of STF tags because STF tags are allocated earlier in the pipeline and therefore can remain in use for a much longer period of time.

[0042] However, in embodiments of the present disclosure, STF tags are assigned at issue time, which reduces the time that STF tags must reside in the pipeline. This design reduces the timing pressures associated with the dispatch STF tag hole count and potentially leads to a smaller STF register file (RF) design, as it reduces the amount of STF tags required in the execution pipe.

[0043] Dispatch 310 includes two dispatch lanes 310A and 310B for dispatching instructions (e.g., FXU / VSU). Dispatch 310 dispatches instructions to ISQ 330. Dispatch 310 also sends logical registers to be mapped to STF tags to mapper 320. Logical registers written by an instruction along with its ITAG are written to mapper 320 at dispatch time. In addition, the previous writer of a logical register (e.g., GPR) is moved to SRB 340. This involves moving the old ITAG along with its W (written) bit and its STF tag (if written). When an instruction is dispatched, a new ITAG is written, and the old ITAG is pushed to the SRB, the destination STF tag is not yet assigned to the instruction.

[0044] Dispatch 310 reads mapper 320 to identify the producer ITAG and source STF tag. If the ready bit (W) is set (e.g., =1), the producer has already executed and the producer's source STF tag has been assigned. In this case, the producer's source STF tag is read from mapper 320, and then the producer's source STF tag is written to ISQ 330 as the instruction's source STF tag. If the ready bit (W) is not set (e.g., =0), the producer has not yet executed, and the data in the source STF tag is not ready for use with the current instruction (e.g., because the producer instruction has not yet completed execution). In this case, the source STF tag is not valid in ISQ 330. Therefore, the instruction will wait in ISQ 330 until its producer has executed and an STF tag for it has been assigned. It should be understood that this is a simplified example for illustrative purposes, and that there will typically be more than one source register, and each source register may have a different producer instruction.

[0045] Dispatch 310 writes the instruction to ISQ 330 as usual. At issue time, if an STF tag is available, the instruction is sent to execution logic 360 for execution. Additionally, STF tag assignment logic 350 assigns an STF tag to the instruction. STF tag assignment logic 350 may include an STF release list that is used to determine whether and which STF tags are available. Execution logic 360 then issues the instruction.

[0046] After the instruction is executed, at writeback execution time, the producer ITAG and assigned STF tag (i.e., the destination STF tag of the issuing instruction) are broadcast to mapper 320, ISQ 330, and SRB 340. Mapper 320 and SRB 340 must include the assigned STF tag so that dependent instructions can obtain a valid source STF at dispatch time. Following receipt of the producer ITAG and assigned STF tag, the following actions are performed in mapper 320, ISQ 330, and SRB 340:

[0047] In mapper 320, the GPR / VSR producer ITAG is compared with the ITAG in mapper 320. This is done using comparison logic (e.g., comparison logic 370 or comparison logic 380). At matching locations (i.e., locations where the producer ITAG matches the ITAG of an instruction in mapper 320), the STF tag is written to the mapper 320 entry and the ready bit is set (e.g., set to W=1) to indicate that the data required by the instruction is stored in the register.

[0048] In ISQ 330, the GPR / VSR producer ITAG is compared with the source ITAG in ISQ 330. This is done using comparison logic 370. At matching locations (i.e., locations where the producer ITAG matches the source ITAG of an instruction in ISQ 330), the STF tag is written into the source STF tag field and the ready bit is set (e.g., set W=1).

[0049] In SRB 340, the GPR / VSR producer ITAG is compared with the ITAG in SRB 340. This is done using comparison logic 380. At matching locations (i.e., locations where the producer ITAG matches the ITAG of an instruction in SRB 340), the STF tag is written to SRB 340 and the ready bit is set (e.g., set to W=1).

[0050] If an STF tag is not available at issue time, ISQ 330 stops issuing instructions and waits until an STF tag is available. If an issue hangs because the oldest instruction in the issue queue cannot be issued due to a lack of available STF tags, a flush can be performed to flush younger (i.e., newer) instructions and reclaim some STF tags. Once the STF tags are reclaimed and available for ISQ 330 to use, ISQ 330 can resume issuing instructions.

[0051] In some embodiments, the completion logic (which may be the same logic as the STF tag allocation logic 350, for example) does not perform an NTC flush because an NTC flush would clear all instructions in the pipe, which could result in wasted work. For this type of flush (also referred to herein as a mini-hang buster), the completion logic only needs to flush a few youngest instructions from the head pointer-N (where N is the number of instructions to flush) to clear enough STF tags for the ISQ 330 to continue creating issued instructions.

[0052] In some embodiments, a flush request may be issued when an instruction ready to issue does not have an available STF tag. The flush request may cause several younger instructions to be flushed. In some embodiments, the microprocessor 300 may have multiple flush modes. For example, the microprocessor 300 may be configured to perform a flush after an NTC instruction has not received a tag for a given number of cycles. Additionally or alternatively, the microprocessor 300 may be configured to perform a flush if the microprocessor 300 determines that instructions are not executing at an expected rate (e.g., instructions are being streamed out of the ISQ 330, which may indicate that no STF tags are available). In some embodiments, the microprocessor 300 may be configured to perform a flush in response to the number of available STF tags in the release list being below a threshold. In some embodiments, the microprocessor 300 may consider a combination of the above (with or without other considerations) when determining whether to perform a flush. The type of flush (e.g., a full flush vs. a mini-hang buster) may be determined based on which flush criteria are met, the extent of the identified problem, or both.

[0053] After the flush, data may be read from the SRB 340 to the mapper 320 to restore the previous state of the microprocessor 300.

[0054] Referring now to FIG. 4, a flow diagram of an exemplary method 400 for assigning STF tags at issue time is shown, according to an embodiment of the present disclosure. Method 400 may be implemented by hardware, firmware, software, or any combination thereof running on a processor. For example, one or more operations of method 400 may be performed by a processor (e.g., microprocessor 300 shown in FIG. 3). Method 400 may begin at operation 402, in which dispatch logic writes a particular instruction to an ISQ. The particular instruction may be written to the ISQ after it is received from an instruction fetch unit.

[0055] In operation 404, the processor reads the mapper to identify the producer ITAG and its destination STF tag. A producer is an older instruction that is creating one or more sources on which a particular instruction depends. For example, a producer may write data to a register, and then the received instruction may read that data to perform its operation.

[0056] In decision block 406, the processor determines whether the ready bit of the particular instruction is set. If the ready bit is not set (no in decision block 406), the producer is not executing. Therefore, in operation 408, the particular instruction waits until the producer is executed. The particular instruction waits in the ISQ. Once the producer is executed, the producer destination STF tag is written as the source STF tag of the particular instruction. This is shown in operation 410. If the ready bit is set (yes in decision block 406), in operation 412, the producer STF tag is written as the source STF tag of the particular instruction.

[0057] At issue time of a particular instruction, the processor determines whether there are any free STF tags available. This is shown in decision block 414. The processor may check the STF free list to determine whether there are any available STF tags. If there are any available STF tags (yes in decision block 414), this means there is an available entry in the STF, and one of the available STF tags is assigned to the particular instruction, and the particular instruction is executed. This is shown in operation 416.

[0058] After executing the particular instruction in operation 416, the processor performs a write-back operation in operation 418. This write-back operation is performed so that any instructions that depend on the particular instruction receive their source STF tag and can also be executed. The write-back operation may include comparing the destination ITAG of the particular instruction with the source ITAG stored in the ISQ, mapper, and SRB. For each matching entry identified in the ISQ, mapper, and SRB, the destination STF tag of the particular instruction is written as the source STF tag and the ready bit is set. After performing the write-back in operation 418, method 400 may end.

[0059] If there are no STF tags available for the particular instruction at issue time (No at decision block 414), then in decision block 420, the processor determines whether flush criteria are met. The flush criteria may include one or more criteria that determine whether to flush the mapper and ISQ. The flush criteria may also determine the type of flush to perform. If the flush criteria are not met (No at decision block 420), method 400 returns to decision block 414. If the flush criteria are met (Yes at decision block 420), then in operation 422, the processor flushes at least some instructions from the ISQ. This frees up the STF tag for the particular instruction, making it executable at this point.

[0060] In some embodiments, after flushing the instructions in operation 422, the previous state of the processor may be restored using the data stored in the SRB. This is shown in operation 424. After restoring the state of the processor, method 400 may return to decision block 414. If the flush was successful in freeing the STF tag (this time, yes at decision block 414), the method may then proceed to operation 416 and operation 418. However, if the flush failed to free the STF tag (again, no at decision block 414), method 400 may again proceed to decision block 420 and operations 422 and 424.

[0061] 5, there is shown a high-level block diagram of an exemplary computer system 501 that may be used in implementing one or more of the methods, tools, and modules described herein and any associated functionality (e.g., using one or more processor circuits, or a computer processor of a computer), in accordance with embodiments of the present disclosure. In some embodiments, major components of computer system 501 may include one or more CPUs 502, a memory subsystem 504, a terminal interface 512, a storage interface 516, an I / O (input / output) device interface 514, and a network interface 518, all of which may be communicatively coupled, directly or indirectly, for inter-component communication via a memory bus 503, an I / O bus 508, and an I / O bus interface unit 510.

[0062] Computer system 501 may include one or more general-purpose programmable central processing units (CPUs) 502A, 502B, 502C, and 502D, collectively referred to herein as CPUs 502. In some embodiments, computer system 501 may include multiple processors, as is typical of relatively large systems. However, in other embodiments, computer system 501 may alternatively be a single CPU system. Each CPU 502 may execute instructions stored in memory subsystem 504 and may include one or more levels of on-board cache.

[0063] The system memory 504 may include computer system-readable media in the form of volatile memory, such as random access memory (RAM) 522 or cache memory 524. The computer system 501 may further include other removable / non-removable, volatile / non-volatile computer system storage media. By way of example only, a storage system 526 may be provided for reading from and writing to a non-removable, non-volatile magnetic medium, such as a hard drive. Although not shown, a magnetic disk drive may be provided for reading from and writing to a removable, non-volatile magnetic disk (e.g., a floppy disk) or an optical disk drive may be provided for reading from and writing to a removable, non-volatile optical disk, such as a CD-ROM, DVD-ROM, or other optical medium. Additionally, the memory 504 may include flash memory, such as a flash memory stick drive or flash drive. Memory devices may be connected to the memory bus 503 by one or more data media interfaces. The memory 504 may include at least one program product having a set (e.g., at least one set) of program modules configured to implement the functions of various embodiments.

[0064] The memory 504 may store one or more programs / utilities 528, each having at least one set of program modules 530. The programs / utilities 528 may include a hypervisor (also called a virtual machine monitor), one or more operating systems, one or more application programs, other program modules, and program data. Each of the operating system, one or more application programs, other program modules, and program data, or any combination thereof, may include an implementation of a networking environment. The program modules 530 generally perform the functions or methodologies of the various embodiments.

[0065] 5 depicts memory bus 503 as a single bus structure providing a direct communication path between CPU 502, memory subsystem 504, and I / O bus interface 510, in some embodiments memory bus 503 may include multiple distinct buses or communication paths that may be arranged in any of a variety of forms, such as point-to-point links in a hierarchical, star, or web configuration, multiple hierarchical buses, parallel and redundant paths, or any other suitable type of configuration. Additionally, while I / O bus interface 510 and I / O bus 508 are depicted as single respective units, in some embodiments computer system 501 may include multiple I / O bus interface units 510, multiple I / O buses 508, or both. Additionally, while multiple I / O interface units are depicted isolating I / O bus 508 from the various communication paths running to the various I / O devices, in other embodiments some or all of the I / O devices may be directly connected to one or more system I / O buses.

[0066] In some embodiments, computer system 501 may be a multi-user mainframe computer system, a single-user system, or a server computer or similar device that has little or no direct user interface but receives requests from other computer systems (clients). Further, in some embodiments, computer system 501 may be implemented as a desktop computer, a portable computer, a laptop or notebook computer, a tablet computer, a pocket computer, a telephone, a smart phone, a network switch or router, or any other suitable type of electronic device.

[0067] It should be noted that Figure 5 is intended to illustrate representative major components of an exemplary computer system 501. However, in some embodiments, individual components may be more or less complex than those depicted in Figure 5, and components other than or in addition to those depicted in Figure 5 may be present, and the number, type, and configuration of such components may vary. Furthermore, the modules are listed and described illustratively according to one embodiment and are not meant to indicate the necessity of any particular module or the exclusivity of other potential modules (or the functionality / purpose applied to any particular module).

[0068] The present invention may be a system, method, and / or computer program product at any possible level of integration of technical details, and may include a computer-readable storage medium (or multiple computer-readable storage media) having computer-readable program instructions for causing a processor to implement aspects of the present invention.

[0069] A computer-readable storage medium may be a tangible device capable of retaining and storing instructions for use by an instruction-execution device. A computer-readable storage medium may be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the above. A non-exhaustive list of more specific examples of computer-readable storage media includes the following: portable computer diskettes, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disk read-only memory (CD-ROM), digital versatile disk (DVD), memory sticks, floppy disks, mechanically encoded devices such as punch cards or raised structures in grooves with instructions recorded on them, and any suitable combination of the above. As used herein, computer-readable storage media should not be construed as being ephemeral signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission medium (e.g., light pulses through fiber optic cable), or electrical signals transmitted over electrical wires.

[0070] The computer-readable program instructions described herein may be downloaded from a computer-readable storage medium to each computing / processing device or to an external computer or storage device via a network, such as the Internet, a local area network, a wide area network, or a wireless network, or a combination thereof. The network may include copper transmission cables, optical fiber transmissions, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in a computer-readable storage medium within the respective computing / processing device.

[0071] The computer-readable program instructions for carrying out the operations of the present invention may be either assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, configuration data for integrated circuits, or source or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk®, C++, and procedural programming languages ​​such as the “C” programming language or similar programming languages. The computer-readable program instructions may execute entirely on the user's computer as a standalone software package, partially on the user's computer, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, to carry out aspects of the present invention, electronic circuitry including, for example, a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA), may execute computer-readable program instructions by utilizing state information of the computer-readable program instructions to personalize the electronic circuitry.

[0072] Aspects of the present disclosure are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the disclosure. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0073] These computer-readable program instructions may be provided to a processor of a computer or other programmable data processing apparatus to produce a machine, such that the instructions, when executed by the processor of the computer or other programmable data processing apparatus, produce means for performing the functions / acts specified in one or more blocks of the flowcharts and / or block diagrams. These computer-readable program instructions may also be stored on a computer-readable medium, such that the computer-readable storage medium on which the instructions are stored comprises an article of manufacture containing instructions implementing aspects of the functions / acts specified in one or more blocks of the flowcharts and / or block diagrams, and can direct a computer, programmable data processing apparatus, or other device, or combination thereof, to function in a particular manner.

[0074] The computer-readable program instructions may also be loaded into a computer, other programmable data processing apparatus, or other device to create a computer-implemented process that causes the computer, other programmable apparatus, or other device to perform a series of operational steps, such that the instructions, which execute on the computer, other programmable apparatus, or other device, perform the functions / acts specified in one or more blocks of the flowcharts and / or block diagrams.

[0075] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of instructions, including one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions noted in the blocks may occur out of the order noted in the figures. For example, two blocks shown in succession may in fact be accomplished as a single step, or may be executed concurrently, substantially concurrently, partially, or fully in a time-overlapping manner, or the blocks may even be executed in the reverse order, depending on the functionality involved. It should also be noted that each block of the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented by a dedicated hardware-based system that performs the specified functions or actions or executes a combination of dedicated hardware and computer instructions.

[0076] It should be understood that the foregoing advantages are exemplary advantages and should not be construed as limiting. Embodiments of the present disclosure may include all, some, or none of the foregoing advantages while remaining within the spirit and scope of the present disclosure.

[0077] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of various embodiments. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms unless the context clearly dictates otherwise. It will be further understood that the terms "includes" and / or "including," when used herein, indicate the presence of stated features, integers, steps, operations, elements, or components, or combinations thereof, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof, or combinations thereof. In the foregoing detailed description of exemplary embodiments of various embodiments, reference has been made to the accompanying drawings (like numbers represent like elements), which form a part of this specification, and in which are shown by way of illustration specific exemplary embodiments in which the various embodiments may be practiced. These embodiments have been described in sufficient detail to enable those skilled in the art to practice the embodiments, but other embodiments may be used, and logical, mechanical, electrical, and other changes may be made without departing from the scope of the various embodiments. In the foregoing description, numerous specific details have been set forth in order to provide a thorough understanding of various embodiments. However, various embodiments may be practiced without these specific details. In other instances, well-known circuits, structures, and techniques have not been shown in detail so as not to obscure the embodiments.

[0078] As used herein, "a number of," when used with respect to an item, means one or more of the item. For example, "several different types of networks" is one or more different types of networks.

[0079] Where different reference numbers include a common number followed by different letters (e.g., 100a, 100b, 100c) or punctuation followed by different numbers (e.g., 100-1, 100-2 or 100.1, 100.2), use of the reference number alone (e.g., 100) without a letter or subsequent number may refer to the entire group of elements, any subset of the group, or illustrative exemplars of the group.

[0080] Furthermore, the phrase "at least one of," when used in reference to a list of items, means that different combinations of one or more of the listed items can be used, and that only one of each item in the list may be required. In other words, "at least one of" means that any combination and number of items from the list may be used, but not all items in the list are required. An item can be a specific object, thing, or category.

[0081] For example, without limitation, "at least one of item A, item B, or item C" may include A, item A and item B, or item B. This example may also include item A, item B, and item C, or item B and item C. Of course, any combination of these items may be present. In some illustrative examples, "at least one of" may be, for example, without limitation, two of item A, one of item B, and ten of item C, four of item B, and seven of item C, or other suitable combinations.

[0082] Various embodiments have been mentioned above. However, it should be understood that the present disclosure is not limited to the specifically described embodiments. Instead, any combination of the described features and elements, whether related to different embodiments, is contemplated to implement and practice the present disclosure. Numerous modifications, changes, and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. Moreover, while embodiments of the present disclosure may achieve advantages over other possible solutions or prior art, whether or not a particular advantage is achieved by a given embodiment does not limit the present disclosure. Accordingly, the described aspects, features, embodiments, and advantages are merely illustrative and should not be considered elements or limitations of the appended claims unless expressly recited in the claims. Furthermore, it is intended that the following claims be construed to encompass all such changes and modifications that are within the true spirit and scope of the present invention.

Claims

1. receiving instructions for execution by a microprocessor; dispatching said instruction to an issue queue without assigning a register tag to said instruction; determining that the instruction is ready to be issued; responsive to determining that the instruction is ready to be issued, assigning an available register tag to the instruction; issuing said instruction; determining whether a flush criterion is met in response to determining that a register tag is not available for a next to complete (NTC) instruction; flushing one or more instructions from the issue queue in response to the flush criteria being met, the one or more instructions being newer than the NTC instruction, and flushing the one or more instructions causes register tags for the one or more instructions to be reclaimed; assigning one of the retrieved register tags to the NTC instruction; issuing the NTC command; A method comprising:

2. receiving instructions for execution by a microprocessor; dispatching said instruction to an issue queue without assigning a register tag to said instruction; determining that the instruction is ready to be issued; responsive to determining that the instruction is ready to be issued, assigning an available register tag to the instruction; issuing said instruction; after issuing the instruction, comparing the ITAG of the instruction with the source ITAGs of other instructions in the issue queue; identifying a second instruction that depends on the instruction based on the comparison; and writing the register tag assigned to the instruction to a source register tag field for the second instruction's entry in the issue queue, the second instruction's entry in a mapper, and the second instruction's entry in a save and restore buffer; A method comprising:

3. determining that the instruction depends on a producer instruction and that the instruction is ready to be issued; determining that the ready bit of said instruction is set; 3. The method of claim 1 or 2, comprising:

4. 4. The method of claim 3, wherein a source register tag of the instruction identifies an entry in a register file containing a register location that the instruction must execute.

5. The method of claim 3 , wherein the ready bit identifies whether the producer instruction has already executed.

6. The method comprises: after issuing the instruction, comparing the ITAG of the instruction with the source ITAGs of other instructions in the issue queue; identifying a second instruction that depends on the instruction based on the comparison; and writing the register tag assigned to the instruction to a source register tag field for the second instruction's entry in the issue queue, the second instruction's entry in a mapper, and the second instruction's entry in a save and restore buffer; The method of claim 1 further comprising:

7. determining that the instruction is ready to be issued; determining that all instructions on which said instruction depends have been issued; 3. The method of claim 1 or 2, comprising:

8. receiving instructions for execution by a microprocessor; dispatching said instruction to an issue queue without assigning a register tag to said instruction; determining that the instruction is ready to be issued; responsive to determining that the instruction is ready to be issued, assigning an available register tag to the instruction; issuing said instruction; determining whether a flush criterion is met in response to determining that a register tag is not available for a next to complete (NTC) instruction; flushing one or more instructions from the issue queue in response to the flush criteria being met, the one or more instructions being newer than the NTC instruction, and flushing the one or more instructions causes register tags for the one or more instructions to be reclaimed; assigning one of the retrieved register tags to the NTC instruction; issuing the NTC command; 1. A system comprising: a processor configured to perform a method comprising:

9. receiving instructions for execution by a microprocessor; dispatching said instruction to an issue queue without assigning a register tag to said instruction; determining that the instruction is ready to be issued; responsive to determining that the instruction is ready to be issued, assigning an available register tag to the instruction; issuing said instruction; after issuing the instruction, comparing the ITAG of the instruction with the source ITAGs of other instructions in the issue queue; identifying a second instruction that depends on the instruction based on the comparison; and writing the register tag assigned to the instruction to a source register tag field for the second instruction's entry in the issue queue, the second instruction's entry in a mapper, and the second instruction's entry in a save and restore buffer; 1. A system comprising: a processor configured to perform a method comprising:

10. determining that the instruction depends on a producer instruction and that the instruction is ready to be issued; determining that the ready bit of said instruction is set; 10. The system of claim 8 or 9, comprising:

11. 11. The system of claim 10, wherein a source register tag of the instruction identifies an entry in a register file containing a register location that the instruction must execute.

12. The system of claim 10 , wherein the ready bit identifies whether the producer instruction has already executed.

13. The method comprises: after issuing the instruction, comparing the ITAG of the instruction with the source ITAGs of other instructions in the issue queue; identifying a second instruction that depends on the instruction based on the comparison; and writing the register tag assigned to the instruction to a source register tag field for the second instruction's entry in the issue queue, the second instruction's entry in a mapper, and the second instruction's entry in a save and restore buffer; The system of claim 8 further comprising:

14. Determining that the instruction is ready to be issued 、 determining that all instructions on which said instruction depends have been issued; 10. The system of claim 8 or 9, comprising:

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