Gate drive circuit and display device

Abstract

The present invention discloses a gate driver circuit and a display device. In the gate driver circuit, the output control terminal of the first shift register of every five adjacent shift registers is electrically connected to the input signal terminal of the fifth shift register, and the output control terminal of the sixth shift register of every six adjacent shift registers is electrically connected to the reset signal terminal of the first shift register. The cascaded gate driver circuit of the present invention requires fewer cascaded signal lines, saving space and further realizing a narrower bezel for the display device. Furthermore, the cascaded gate driver circuit of the present invention provides more flexibility in the signal provided by the external circuit board, allowing the pulse width of the clock signal to be adjusted via the external circuit board, thereby enabling the high-level width of the gate signal output from the gate signal output terminal to be adjusted, providing greater flexibility in the manufacturing process.

Description

[Technical Field]

[0001] [CROSS-REFERENCE TO RELATED APPLICATIONS] This application claims priority from a Chinese patent application filed with the China Patent Office on February 28, 2020, bearing application number 202010129236.0, and entitled "Gate driving circuit and display device," the entire disclosure of which is incorporated herein by reference.

[0002] The present invention relates to the field of display technology, and in particular to gate drive circuits and display devices. [Background technology]

[0003] With the rapid development of display technology, displays are showing a trend toward high integration and low cost. Among them, Gate Driver on Array (GOA) technology integrates TFT (Thin Film Transistor) gate switch circuits into the display panel's array substrate to form the display panel's scan driver. The need for wiring space in the bonding area and fan-out area of ​​the gate integrated circuit (IC) not only reduces product costs in terms of material costs and manufacturing processes, but also allows for the creation of beautifully designed displays with symmetry and narrow bezels. Furthermore, this integration process eliminates the bonding process in the gate scan line direction, thereby improving productivity and yield. Summary of the Invention

[0004] A gate driving circuit provided by an embodiment of the present invention includes a plurality of cascaded shift registers, each of which includes an input signal terminal, a reset signal terminal, an output control terminal, and a gate signal output terminal, and each of the gate signal output terminals is electrically connected to a gate line of a display panel in a one-to-one correspondence, wherein: For every five adjacent shift registers, the output control terminal of the first said shift register is electrically connected to the input signal terminal of the fifth said shift register; For every six adjacent shift registers, the output control terminal of the sixth shift register is electrically connected to the reset signal terminal of the first shift register.

[0005] In a possible embodiment, the gate driving circuit provided in the embodiment of the present invention includes 10 clock signal lines, and each of the shift registers further includes a clock signal terminal, wherein: The clock signal end of the 10k-9th level shift register is electrically connected to the first clock signal line, the clock signal end of the 10k-8th level shift register is electrically connected to the second clock signal line, the clock signal end of the 10k-7th level shift register is electrically connected to the third clock signal line, the clock signal end of the 10k-6th level shift register is electrically connected to the fourth clock signal line, the clock signal end of the 10k-5th level shift register is electrically connected to the fifth clock signal line, and the 10k- The clock signal terminal of the 4-level shift register is electrically connected to the 6th clock signal line, the clock signal terminal of the 10k-3-th level shift register is electrically connected to the 7th clock signal line, the clock signal terminal of the 10k-2-th level shift register is electrically connected to the 8th clock signal line, the clock signal terminal of the 10k-1-th level shift register is electrically connected to the 9th clock signal line, and the clock signal terminal of the 10k-th level shift register is electrically connected to the 10th clock signal line, where k is a positive integer.

[0006] In a possible embodiment, in the above gate driving circuit provided by the embodiment of the present invention, the duty ratio of the clock signal of each of the clock signal lines is about 40%.

[0007] In a possible embodiment, in the above gate drive circuit provided by the embodiment of the present invention, each of the shift registers includes an input circuit, a reset circuit, a control circuit, a first output circuit, a second output circuit, and a reconfiguration circuit, wherein: the input circuit is configured to control a potential of a first node in response to a signal input from the input signal terminal; the reset circuit is configured to provide a signal input from a first reference signal terminal to the first node in response to a signal input from the reset signal terminal; the control circuit is configured to respond to a signal input from the input signal terminal and provide a signal at the first reference signal terminal to a second node, to control potentials of the first node and the second node in response to a signal input from a control signal terminal, to provide a signal at the second reference signal terminal to the gate signal output terminal in response to the potential of the second node, and to provide a signal at the first reference signal terminal to the output control terminal in response to the potential of the second node; the first output circuit is configured to respond to a potential at the first node and provide a signal at the clock signal terminal to the gate signal output terminal; the second output circuit is configured to provide a signal at the clock signal end to the output control end in response to a potential at the first node; The reset circuit is connected to a reset signal terminal Signal potential and configured to provide a signal at the first reference signal end to the first node.

[0008] In a possible embodiment, in the above gate drive circuit provided by the embodiment of the present invention, the input circuit includes a first switch transistor, wherein: The gate and a first electrode of the first switch transistor are electrically connected to the input signal terminal, and the second electrode of the first switch transistor is electrically connected to the first node.

[0009] In a possible embodiment, in the above gate drive circuit provided by the embodiment of the present invention, the reset circuit includes a second switch transistor, wherein: The second switch transistor has a gate electrically connected to the reset signal terminal, a first electrode electrically connected to the first node, and a second electrode electrically connected to the first reference signal terminal.

[0010] In a possible embodiment, in the above gate drive circuit provided by the embodiment of the present invention, the control circuit includes a third switch transistor, a fourth switch transistor, a fifth switch transistor, a sixth switch transistor, a seventh switch transistor, an eighth switch transistor, a ninth switch transistor and a tenth switch transistor, wherein: a gate of the third switch transistor is electrically connected to the input signal end, a first electrode of the third switch transistor is electrically connected to the second node, and a second electrode of the third switch transistor is electrically connected to the first reference signal end; a gate of the fourth switch transistor is electrically connected to the second node, a first electrode of the fourth switch transistor is electrically connected to the first node, and a second electrode of the fourth switch transistor is electrically connected to the first reference signal end; a gate of the fifth switch transistor is electrically connected to the second node, a first electrode of the fifth switch transistor is electrically connected to a gate signal output terminal of the gate drive circuit, and a second electrode of the fifth switch transistor is electrically connected to the second reference signal terminal; the gate of the sixth switch transistor and the first electrode Yes, both Before a second electrode electrically connected to the control signal terminal, and a first electrode electrically connected to a first electrode of the eighth switch transistor and a gate of the seventh switch transistor; a first electrode of the seventh switch transistor is electrically connected to the control signal terminal and a second electrode of the seventh switch transistor is electrically connected to the second node; a gate of the eighth switch transistor is electrically connected to the first node, and a second electrode of the eighth switch transistor is electrically connected to the first reference signal end; a gate of the ninth switch transistor is electrically connected to the first node, a first electrode of the ninth switch transistor is electrically connected to the second node, and a second electrode of the ninth switch transistor is electrically connected to the first reference signal end; The gate of the tenth switch transistor is electrically connected to the second node, the first electrode is electrically connected to the output control terminal of the gate drive circuit, and the second electrode is electrically connected to the first reference signal terminal.

[0011] In a possible embodiment, in the above gate driving circuit provided by the embodiment of the present invention, there are two control circuits, each electrically connected to a different control signal terminal, and the two control signal terminals alternately input effective control signals.

[0012] In a possible embodiment, in the above gate drive circuit provided by the embodiment of the present invention, the first output circuit includes an eleventh switch transistor and a capacitor, wherein: a gate of the eleventh switch transistor is electrically connected to the first node, a first electrode of the eleventh switch transistor is electrically connected to the clock signal terminal, and a second electrode of the eleventh switch transistor is electrically connected to the gate signal output terminal; The capacitor is connected between the gate and the second electrode of the eleventh switch transistor.

[0013] In a possible embodiment, in the above gate drive circuit provided by the embodiment of the present invention, the second output circuit includes a twelfth switch transistor, wherein: The gate of the twelfth switch transistor is electrically connected to the first node, the first electrode is electrically connected to the clock signal terminal, and the second electrode is electrically connected to the output control terminal.

[0014] In a possible embodiment, in the above gate drive circuit provided by the embodiment of the present invention, the reset circuit includes a thirteenth switch transistor, wherein: The gate of the thirteenth switch transistor is electrically connected to the reset signal terminal, the first electrode is electrically connected to the first node, and the second electrode is electrically connected to the first reference signal terminal.

[0015] Similarly, an embodiment of the present invention further provides a display device including the above gate drive circuit provided by an embodiment of the present invention. [Brief explanation of the drawings]

[0016] [Figure 1] FIG. 1 is a schematic structural diagram of a gate driving circuit provided in the related art; [Figure 2] FIG. 2 is a schematic diagram of the timing structure of the gate drive circuit shown in FIG. 1. [Figure 3] FIG. 2 is a schematic diagram of the structure of a gate driving circuit provided by an embodiment of the present invention. [Figure 4] FIG. 4 is a schematic diagram of the timing structure of the gate drive circuit shown in FIG. 3. [Figure 5] 1 is a schematic diagram of a particular structure of a shift register in which all transistors are N-type transistors provided by an embodiment of the present invention; DETAILED DESCRIPTION OF THE INVENTION

[0017] Particular implementations of gate drive circuits and display devices provided by embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0018] As shown in FIG. 1, FIG. 1 is a schematic structural diagram of a gate driver circuit provided in the related art that adopts a 10CLK design, and the gate driver circuit includes a plurality of cascaded shift registers (...GOA(n-4), GOA(n-3)...GOA(n+4), GOA(n+5)...). Each shift register includes an input signal terminal IN, a reset signal terminal RS, an output control terminal OC, and a gate signal output terminal GO. Each gate signal output terminal GO is electrically connected to a gate line of the display panel in a one-to-one correspondence. Here, for every six adjacent shift registers, for example, in the case of six adjacent shift registers GOAn to GOA(n+5), the output control terminal OC of the first shift register GOAn is electrically connected to the input signal terminal IN of the sixth shift register GOA(n+5); for example, in the case of six adjacent shift registers GOA(n-1) to GOA(n+4), the output control terminal OC of the first shift register GOA(n-1) is electrically connected to the input signal terminal IN of the sixth shift register GOA(n+4), and so on.

[0019] For every seven adjacent shift registers, for example, in the case of seven adjacent shift registers GOAn to GOA(n+6), the output control terminal OC of the seventh shift register GOA(n+6) is electrically connected to the reset signal terminal RS of the first shift register GOAn; for example, in the case of seven adjacent shift registers GOA(n-1) to GOA(n+5), the output control terminal OC of the seventh shift register GOA(n+5) is electrically connected to the reset signal terminal RS of the first shift register GOA(n-1), and so on.

[0020] The above cascade structure shown in Figure 1 resets the first node PU of the GOA circuit by a time lag of one row, resulting in the gate line being reverse-discharged to the CLK signal through the switch transistor electrically connected to the CLK. As shown in Figure 2, Figure 2 is the input and output timing diagram of each shift register of the gate driver circuit shown in Figure 1. In the cascade structure design of Figure 1, the CLK high pulse signal and low pulse signal are half the time, respectively, and the clock signal duty cycle is only 50%. The flexibility of the external circuit board that inputs the clock signal to the clock signal line is low, and the cascade structure shown in Figure 1 requires many cascade signal lines, which does not save space for further narrowing the bezel.

[0021] In consideration of this, the gate driving circuit provided by the embodiment of the present invention includes a plurality of cascaded shift registers (...GOA(n-4), GOA(n-3)...GOA(n+4), GOA(n+5)...) as shown in Figure 3. Each shift register includes an input signal end IN, a reset signal end RS, an output control end OC and a gate signal output end GO. Each gate signal output end GO is electrically connected to a gate line of the display panel in a one-to-one correspondence.

[0022] For every five adjacent shift registers, for example, in the case of five adjacent shift registers from GOAn to GOA(n+4), the output control terminal OC of the first shift register GOAn is electrically connected to the input signal terminal IN of the fifth shift register GOA(n+4); for example, in the case of five adjacent shift registers from GOA(n-1) to GOA(n+3), the output control terminal OC of the first shift register GOA(n-1) is electrically connected to the input signal terminal IN of the fifth shift register GOA(n+3), and so on.

[0023] For every six adjacent shift registers, for example, GOAn to GOA(n+5), the output control terminal OC of the sixth shift register GOA(n+5) is electrically connected to the reset signal terminal RS of the first shift register GOAn; for example, for six adjacent shift registers, for example, GOA(n-1) to GOA(n+4), the output control terminal OC of the sixth shift register GOA(n+4) is electrically connected to the reset signal terminal RS of the first shift register GOA(n-1), and so on.

[0024] In the gate driver circuit provided by one embodiment of the present invention, for every five adjacent shift registers, the output control terminal of the first shift register is electrically connected to the input signal terminal of the fifth shift register, and for every six adjacent shift registers, the output control terminal of the sixth shift register is electrically connected to the reset signal terminal of the first shift register, thereby reducing the number of cascaded signal lines in the cascaded gate driver circuit, saving space and further realizing a narrower bezel for the display device. Furthermore, for the cascaded gate driver circuit provided by the present invention, the signals provided by the external circuit board are more flexible, and the pulse width of the clock signal can be adjusted via the external circuit board, so that the high-level width of the gate signal output from the gate signal output terminal can be adjusted, providing greater flexibility in the manufacturing process of the display device.

[0025] In a specific implementation, the above gate driving circuit provided by an embodiment of the present invention includes, for example, ten clock signal lines (CLK1, CLK2, CLK3...CLK10), as shown in Figure 3. Each shift register further includes a clock signal terminal CLK.

[0026] The clock signal terminal of the 10k-9th level shift register is electrically connected to the first clock signal line, for example, the clock signal terminals of the 1st level, 2nd level, 21st level, etc. shift registers are all electrically connected to the first clock signal line CLK1.

[0027] The clock signal terminal of the 10k-8th level shift register is electrically connected to the second clock signal line, for example, the clock signal terminals of the 2nd level, 12th level, 22nd level, etc. shift registers are all electrically connected to the second clock signal line CLK2.

[0028] The clock signal terminal of the 10k-7th level shift register is electrically connected to the third clock signal line, for example, the clock signal terminals of the 3rd level, 13th level, 23rd level, etc. shift registers are all electrically connected to the third clock signal line CLK3.

[0029] The clock signal terminal of the 10k-6th level shift register is electrically connected to the fourth clock signal line, for example, the clock signal terminals of the 4th level, 14th level, 24th level, etc. shift registers are all electrically connected to the fourth clock signal line CLK4.

[0030] The clock signal end of the 10k-5th level shift register is electrically connected to the fifth clock signal line, for example, the clock signal ends of the 5th level, 15th level, 25th level, etc. shift registers are all electrically connected to the fifth clock signal line CLK5.

[0031] The clock signal end of the 10k-4th level shift register is electrically connected to the sixth clock signal line, for example, the clock signal ends of the 6th level, 16th level, 26th level, etc. shift registers are all electrically connected to the sixth clock signal line CLK6.

[0032] The clock signal end of the 10k-3th level shift register is electrically connected to the seventh clock signal line, for example, the clock signal ends of the 7th level, 17th level, 27th level, etc. shift registers are all electrically connected to the seventh clock signal line CLK7.

[0033] The clock signal terminal of the 10k-2th level shift register is electrically connected to the 8th clock signal line, for example, the clock signal terminals of the 8th level, 18th level, 28th level, etc. shift registers are all electrically connected to the 8th clock signal line CLK8.

[0034] The clock signal terminal of the (10k-1)th level shift register is electrically connected to the ninth clock signal line, for example, the clock signal terminals of the ninth level, 19th level, 29th level, etc. shift registers are all electrically connected to the ninth clock signal line CLK9.

[0035] The clock signal terminal of the 10k-th level shift register is electrically connected to the 10th clock signal line, for example, the clock signal terminals of the 10th level, 20th level, 30th level... shift registers are all electrically connected to the 10th clock signal line CLK10, where k is a positive integer.

[0036] In a specific implementation, the above gate driving circuit provided by the embodiment of the present invention may be implemented as shown in FIG. 4, which illustrates the input / output timing of each shift register in the gate driving circuit shown in FIG. 3. The duty ratio of the clock signal on each clock signal line is approximately 40%. Thus, by using the cascade structure provided by the embodiment of the present invention, the duty ratio of the clock signal on each clock signal line can be approximately 40%, which allows the signal provided by the external circuit board to be more flexible. Even when manufacturing a display product, the pulse width of the clock signal can be adjusted via the external circuit board, thereby allowing the high-level width of the gate signal output from the gate signal output terminal to be adjusted with high flexibility.

[0037] It should be noted that the duty ratio of the clock signal on each clock signal line may also be slightly higher or lower than 40% as designed according to actual needs.

[0038] In a specific implementation, in the above-described gate drive circuit provided by an embodiment of the present invention, for example, as shown in FIG. 5, each shift register includes an input circuit 1, a reset circuit 2, a control circuit, a first output circuit 4, a second output circuit, and a reset circuit 6. To avoid the problem of characteristic shift or damage to the switch transistors of the control circuits caused by long-term DC bias of the switch transistors, one embodiment of the present invention can provide two control circuits, a first control circuit 3 and a second control circuit 3', respectively. The control signal terminal VDD includes a first control signal terminal VDD1 and a second control signal terminal VDD2 electrically connected to the first control circuit 3 and the second control circuit 3'. The first control signal terminal VDD1 and the second control signal terminal VDD2 alternately input effective control signals.

[0039] The input circuit 1 is configured to control the potential of the first node PU in response to a signal input via an input signal terminal IN.

[0040] The reset circuit 2 is configured to provide a signal input by one reference signal terminal VSS1 to the first node PU in response to a signal input by a reset signal terminal RS.

[0041] The first control circuit 3 is configured to provide a signal from the first reference signal terminal VSS1 to the second node PD1 in response to a signal input through the input signal terminal IN, control the potentials of the first node PU and the second node PD1 in response to a signal input through the first control signal terminal VDD1, provide a signal from the second reference signal terminal VSS2 to the gate signal output terminal GO in accordance with the potential of the second node PD1, and provide the signal from the first reference signal terminal VSS1 to the output control terminal OC in accordance with the potential of the second node PD1.

[0042] The second control circuit 3' is configured to provide the signal of the first reference signal terminal VSS1 to the third node PD2 in response to a signal input through the input signal terminal IN, to control the potentials of the first node PU and the third node PD2 in response to a signal input through the second control signal terminal VDD2, to provide the signal of the second reference signal terminal VSS2 to the gate signal output terminal GO in response to the potential of the third node PD2, and to provide the signal of the first reference signal terminal VSS1 to the output control terminal OC in response to the potential of the third node PD2.

[0043] The first output circuit 4 is configured to provide a signal at the clock signal terminal CLK to the gate signal output terminal GO in response to the potential at the first node PU.

[0044] The second output circuit 5 is configured to provide the signal at the clock signal terminal CLK to the output control terminal OC in response to the potential at the first node PU.

[0045] The reset circuit 6 is configured to provide the signal at the first reference signal terminal VSS1 to the first node PU in response to the potential of the reset signal terminal STV0 signal.

[0046] Specifically, after the output of each frame of an image is completed, i.e., after the output signal to the cascaded multiple shift registers provided by the embodiment of the present invention, the potentials of all first nodes PU in the cascaded multiple shift registers are reset via the reset circuit 6 before the next frame of an image is output.

[0047] In a specific implementation, in the above gate drive circuit provided by the embodiment of the present invention, for example, as shown in FIG. 5, the input circuit 1 may specifically include a first switch transistor M1.

[0048] The gate and the first electrode of the first switch transistor M1 are both electrically connected to the input signal terminal, and the second electrode is electrically connected to the first node.

[0049] The above is merely an example to describe the specific structure of the input circuit in the shift register. In a specific implementation, the specific structure of the input circuit is not limited to the above structure provided by the embodiment of the present invention. It may also be other structures known to those skilled in the art. There is no limitation here.

[0050] In a specific implementation, in the above gate drive circuit provided by the embodiment of the present invention, for example, as shown in FIG. 5, the reset circuit 2 may specifically include a second switch transistor M2.

[0051] The gate of the second switch transistor M2 is electrically connected to the reset signal terminal RS, the first electrode is electrically connected to the first node PU, and the second electrode is electrically connected to the first reference signal terminal VSS1.

[0052] The above is merely an example to describe the specific structure of the reset circuit in the shift register. In a specific implementation, the specific structure of the reset circuit is not limited to the above structure provided by the embodiment of the present invention. It may also be other structures known to those skilled in the art. There is no limitation here.

[0053] In a specific implementation, in the above gate drive circuit provided by the embodiment of the present invention, for example, as shown in FIG. 5, the first control circuit 3 may specifically include a third switch transistor M3, a fourth switch transistor M4, a fifth switch transistor M4, a sixth switch transistor M6, a seventh switch transistor M7, an eighth switch transistor M8, a ninth switch transistor M9, and a tenth switch transistor M10.

[0054] The gate of the third switch transistor M3 is electrically connected to the input signal terminal IN, the first electrode is electrically connected to the second node PD1, and the second electrode is electrically connected to the first reference signal terminal VSS1.

[0055] The gate of the fourth switch transistor M4 is electrically connected to the second node PD1, the first electrode is electrically connected to the first node PU, and the second electrode is electrically connected to the first reference signal terminal VSS1.

[0056] The gate of the fifth switch transistor M5 is electrically connected to the second node PD1, the first electrode is electrically connected to the gate signal output terminal GO of the gate driving circuit, and the second electrode is electrically connected to the second reference signal terminal VSS2.

[0057] The gate and the first electrode of the sixth switch transistor M6 are both electrically connected to the first control signal terminal VDD1, and the second electrode is electrically connected to the first electrode of the eighth switch transistor M8 and the gate of the seventh switch transistor M7.

[0058] A first electrode of the seventh switch transistor M7 is electrically connected to the first control signal terminal VDD1, and a second electrode of the seventh switch transistor M7 is electrically connected to the second node PD1.

[0059] The gate of the eighth switch transistor M8 is electrically connected to the first node PU, and the second electrode thereof is electrically connected to the first reference signal terminal VSS1.

[0060] The gate of the ninth switch transistor M9 is electrically connected to the first node PU, the first electrode is electrically connected to the second node PD1, and the second electrode is electrically connected to the first reference signal terminal VSS1.

[0061] The gate of the tenth switch transistor M10 is electrically connected to the second node PD1, the first electrode is electrically connected to the output control terminal OC of the gate drive circuit, and the second electrode is electrically connected to the first reference signal terminal VSS1.

[0062] The second control circuit 3' includes a fourteenth switch transistor M3', a fifteenth switch transistor M4', a sixteenth switch transistor M5', a seventeenth switch transistor M6', an eighteenth switch transistor M7', a nineteenth switch transistor M8', a twentieth switch transistor M9', and a 21 The switch transistor M10' may include a

[0063] The gate of the fourteenth switch transistor M3' is electrically connected to the input signal terminal IN, and the first electrode of the fourteenth switch transistor M3' is electrically connected to the input signal terminal IN. 3 Node PD 2 and the second electrode is electrically connected to the first reference signal terminal VSS1.

[0064] The gate of the 15th switch transistor M4′ is electrically connected to the third node PD2, the first electrode is electrically connected to the first node PU, and the second electrode is electrically connected to the first reference signal terminal VSS1.

[0065] The gate of the sixteenth switch transistor M5′ is electrically connected to the third node PD2, the first electrode is electrically connected to the gate signal output terminal GO of the gate driving circuit, and the second electrode is electrically connected to the second reference signal terminal VSS2.

[0066] The gate and the first electrode of the 17th switch transistor M6' are both electrically connected to the second control signal terminal VDD2, and the second electrode is electrically connected to the first electrode of the 19th switch transistor M8' and the gate of the 18th switch transistor M7'.

[0067] A first electrode of the eighteenth switch transistor M7' is electrically connected to the second control signal terminal VDD2, and a second electrode of the eighteenth switch transistor M7' is electrically connected to the third node PD2.

[0068] The gate of the nineteenth switch transistor M8' is electrically connected to the first node PU, and the second electrode thereof is electrically connected to the first reference signal terminal VSS1.

[0069] The gate of the twentieth switch transistor M9′ is electrically connected to the first node PU, the first electrode is electrically connected to the third node PD2, and the second electrode is electrically connected to the first reference signal terminal VSS1.

[0070] No. 21 The gate of the switch transistor M10′ is electrically connected to the third node PD2, the first electrode is electrically connected to the output control terminal OC of the gate drive circuit, and the second electrode is electrically connected to the first reference signal terminal VSS1.

[0071] The above is merely an example to describe the specific structure of the first control circuit and the second control circuit in the shift register, and in a specific implementation, the specific structure of the first control circuit and the second control circuit is not limited to the structure provided by the above embodiment of the present invention, and may be other structures known to those skilled in the art, which are not limited to the present invention.

[0072] In a specific implementation, in the above gate drive circuit provided by the embodiment of the present invention, for example, as shown in FIG. 5, the first output circuit 4 may specifically include an eleventh switch transistor M11 and a capacitor C.

[0073] The gate of the eleventh switch transistor M11 is electrically connected to the first node PU, the first electrode is electrically connected to the clock signal terminal CLK, and the second electrode is electrically connected to the gate signal output terminal GO of the gate driving circuit.

[0074] The capacitor C is connected between the gate and the second electrode of the eleventh switch transistor M11.

[0075] The above is merely an example to describe the specific structure of the first output circuit in the shift register. In specific implementation, the specific structure of the first output circuit is not limited to the above structure provided by the embodiment of the present invention, and may be other structures known to those skilled in the art, but is not limited thereto.

[0076] In a specific implementation, in the above gate drive circuit provided by the embodiment of the present invention, for example, as shown in FIG. 5, the second output circuit 5 may specifically include a twelfth switch transistor M12.

[0077] The gate of the twelfth switch transistor M12 is electrically connected to the first node PU, the first electrode is electrically connected to the clock signal terminal CLK, and the second electrode is electrically connected to the output control terminal OC of the gate drive circuit.

[0078] The above is merely an example to describe the specific structure of the second output circuit in the shift register. In specific implementation, the specific structure of the second output circuit is not limited to the above structure provided by the embodiment of the present invention, and may be other structures known to those skilled in the art, but is not limited thereto.

[0079] In a specific implementation, in the above gate drive circuit provided by the embodiment of the present invention, for example, as shown in FIG. 5, the reset circuit 6 can specifically include a thirteenth switch transistor M1.

[0080] The gate of the thirteenth switch transistor M13 is electrically connected to the reset signal terminal STV0, the first electrode is electrically connected to the first node PU, and the second electrode is electrically connected to the first reference signal terminal VSS1.

[0081] The above is merely an example to describe the specific structure of the reset circuit in the shift register. In a specific implementation, the specific structure of the reset circuit is not limited to the above structure provided by the embodiment of the present invention, and may also be other structures known to those skilled in the art, but is not limited thereto.

[0082] In addition, in a normal shift register, the signal output from the gate signal output terminal GO of the same level is used as the signal of the input signal terminal IN of the gate driving circuit of the next level, but during operation, the output of the gate signal output terminal GO fluctuates due to the influence of the gate line, etc., making the output unstable. In the present invention, the signal output from the second output circuit of the Nth level shift register is output from the output control terminal OC and used as the signal of the input signal terminal IN of the N+4th level shift register, thereby improving the stability of the signal output and ensuring the normal output of the gate.

[0083] It should be noted that the embodiment of the present invention mainly solves the problem that in existing 75-inch 8K 120Hz display products, there are many cascade signal lines for cascading shift registers, and the flexibility of external circuit boards to provide clock signals to existing gate drive circuits is low. The input and output operating principles of the gate drive circuit under normal operating conditions are the same as those of gate drive circuits in the related art, and will not be described in detail here.

[0084] In a specific implementation, in the above gate driving circuit provided by an embodiment of the present invention, for example, as shown in Figure 5, all switch transistors can be N-type transistors. The potentials of the first reference signal terminal VSS1 and the second reference signal terminal VSS2 are both low potentials, and the first control signal terminal VDD1 and the second control signal terminal VDD2 alternately output high potentials and low potentials. That is, when the first control signal terminal VDD1 is high potential, the second control signal terminal VDD2 is low potential, and when the first control signal terminal VDD1 is low potential, the second control signal terminal VDD2 is high potential.

[0085] Of course, in certain implementations, in the above gate drive circuits provided by the embodiments of the present invention, all switch transistors can also be P-type transistors.

[0086] Furthermore, in certain implementations, N-type transistors are turned on under the action of a high potential and turned off under the action of a low potential, and P-type transistors are turned off under the action of a high potential and turned on under the action of a low potential.

[0087] It should be noted that the switch transistors referred to in the above embodiments of the present invention may be thin film transistors (TFTs) or metal oxide semiconductor field effect transistors (MOSs). This is not limited thereto. In a specific implementation, the functions of the first and second electrodes of these switch transistors may be interchanged according to the type of transistor and the input signal, and no specific distinction is made here. Specifically, the first electrode of the switch transistors referred to in the above embodiments of the present invention may be a source electrode, and the second electrode may be a drain electrode, or the first electrode may be a drain electrode, and the second electrode may be a source electrode. No specific distinction is made here.

[0088] Based on the same inventive idea, one embodiment of the present invention also provides a display device including the above gate driving circuit, which may be a display panel of any product with a display function, such as a mobile phone, tablet computer, television, monitor, notebook computer, digital photo frame, navigation system, etc. For implementation of the display device, please refer to the above embodiment of the gate driving circuit, and a repeated description will not be provided here.

[0089] In an embodiment of the present invention, a gate driving circuit and a display device are provided, in which, for every five adjacent shift registers, the output control terminal of the first shift register is electrically connected to the input signal terminal of the fifth shift register, and for every six adjacent shift registers, the output control terminal of the sixth shift register is electrically connected to the reset signal terminal of the first shift register. The cascaded gate driving circuit provided by the present invention requires fewer cascaded signal lines, saving space and further realizing a narrower bezel for the display device. Furthermore, the cascaded gate driving circuit provided by the present invention allows for more flexible signal provision via an external circuit board, allowing the pulse width of the clock signal to be adjusted via the external circuit board, thereby enabling the high-level width of the gate signal output from the gate signal output terminal to be adjusted, providing greater flexibility in the manufacturing process.

[0090] It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit and scope of the present invention. Therefore, the present invention is also intended to cover these modifications and variations, provided that they fall within the scope of the claims of the present invention and their equivalents.

Claims

1. A gate drive circuit, the gate drive circuit includes a plurality of cascaded shift registers; Each of the shift registers includes an input signal end, a reset signal end, an output control end, and a gate signal output end, and each of the gate signal output ends is electrically connected to a gate line of a display panel in a one-to-one correspondence; For every five adjacent shift registers, the output control terminal of a first shift register is electrically connected to the input signal terminal of a fifth shift register; For every six adjacent shift registers, the output control terminal of the sixth shift register is electrically connected to the reset signal terminal of the first shift register; each said shift register includes an input circuit, a reset circuit, a first control circuit, a second control circuit, a first output circuit, a second output circuit and a reset circuit; the input circuit is configured to control a potential of a first node in response to a signal input by the input signal terminal; the reset circuit is configured to provide a signal input by a first reference signal terminal to the first node in response to a signal input by the reset signal terminal; the first control circuit is configured to provide a signal at the first reference signal terminal to a second node in response to a signal inputted by the input signal terminal, to control potentials of the first node and the second node in response to a signal inputted by a first control signal terminal, to provide a signal at the second reference signal terminal to the gate signal output terminal in response to the potential of the second node, and to provide a signal at the first reference signal terminal to the output control terminal in response to the potential of the second node; the second control circuit is configured to provide a signal at the first reference signal terminal to a third node in response to a signal inputted by the input signal terminal, to control potentials of the first node and the third node in response to a signal inputted by a second control signal terminal, to provide a signal at the second reference signal terminal to the gate signal output terminal in response to the potential of the third node, and to provide a signal at the first reference signal terminal to the output control terminal in response to the potential of the third node; the first output circuit is configured to provide a signal at a clock signal terminal to the gate signal output terminal in response to a potential at the first node; the second output circuit is configured to provide a signal at the clock signal end to the output control end in response to a potential at the first node; the reset circuit is configured to provide the signal on the first reference signal end to the first node in response to a potential of a signal on a reset signal end; the first control circuit includes a third switch transistor, a fourth switch transistor, a fifth switch transistor, a sixth switch transistor, a seventh switch transistor, an eighth switch transistor, a ninth switch transistor, and a tenth switch transistor; a gate of the third switch transistor is electrically connected to the input signal end, a first electrode of the third switch transistor is electrically connected to the second node, and a second electrode of the third switch transistor is electrically connected to the first reference signal end; a gate of the fourth switch transistor is electrically connected to the second node, a first electrode of the fourth switch transistor is electrically connected to the first node, and a second electrode of the fourth switch transistor is electrically connected to the first reference signal end; a gate of the fifth switch transistor is electrically connected to the second node, a first electrode of the fifth switch transistor is electrically connected to the gate signal output terminal, and a second electrode of the fifth switch transistor is electrically connected to the second reference signal terminal; a gate and a first electrode of the sixth switch transistor are electrically connected to the first control signal terminal, and a second electrode of the sixth switch transistor is electrically connected to a first electrode of an eighth switch transistor and a gate of a seventh switch transistor; a first electrode of the seventh switch transistor electrically connected to the first control signal terminal, and a second electrode of the seventh switch transistor electrically connected to the second node; a gate of the eighth switch transistor is electrically connected to the first node, and a second electrode of the eighth switch transistor is electrically connected to the first reference signal end; a gate of the ninth switch transistor is electrically connected to the first node, a first electrode of the ninth switch transistor is electrically connected to the second node, and a second electrode of the ninth switch transistor is electrically connected to the first reference signal end; a gate of the tenth switch transistor is electrically connected to the second node, a first electrode of the tenth switch transistor is electrically connected to the output control end, and a second electrode of the tenth switch transistor is electrically connected to the first reference signal end; the second control circuit includes a fourteenth switch transistor, a fifteenth switch transistor, a sixteenth switch transistor, a seventeenth switch transistor, an eighteenth switch transistor, a nineteenth switch transistor, a twentieth switch transistor, and a twenty-first switch transistor; a gate of the fourteenth switch transistor is electrically connected to the input signal end, a first electrode of the fourteenth switch transistor is electrically connected to the third node, and a second electrode of the fourteenth switch transistor is electrically connected to the first reference signal end; a gate of the fifteenth switch transistor is electrically connected to the third node, a first electrode of the fifteenth switch transistor is electrically connected to the first node, and a second electrode of the fifteenth switch transistor is electrically connected to the first reference signal end; a gate of the sixteenth switch transistor is electrically connected to the third node, a first electrode of the sixteenth switch transistor is electrically connected to the gate signal output terminal, and a second electrode of the sixteenth switch transistor is electrically connected to the second reference signal terminal; a gate and a first electrode of the seventeenth switch transistor are electrically connected to the second control signal terminal, and a second electrode of the seventeenth switch transistor is electrically connected to a first electrode of a nineteenth switch transistor and a gate of an eighteenth switch transistor; a first electrode of the eighteenth switch transistor is electrically connected to the second control signal terminal, and a second electrode of the eighteenth switch transistor is electrically connected to the third node; a gate of the nineteenth switch transistor is electrically connected to the first node, and a second electrode of the nineteenth switch transistor is electrically connected to the first reference signal end; a gate of the twentieth switch transistor is electrically connected to the first node, a first electrode of the twentieth switch transistor is electrically connected to the third node, and a second electrode of the twentieth switch transistor is electrically connected to the first reference signal end; a gate of the second switch transistor electrically connected to the third node, a first electrode of the second switch transistor electrically connected to the output control terminal, and a second electrode of the second switch transistor electrically connected to the first reference signal terminal.

2. Ten clock signal lines are included, and each of the shift registers further includes a clock signal terminal; The clock signal terminal of the shift register of the 10k-9th level is electrically connected to a first clock signal line, the clock signal terminal of the shift register of the 10k-8th level is electrically connected to a second clock signal line, the clock signal terminal of the shift register of the 10k-7th level is electrically connected to a third clock signal line, the clock signal terminal of the shift register of the 10k-6th level is electrically connected to a fourth clock signal line, the clock signal terminal of the shift register of the 10k-5th level is electrically connected to a fifth clock signal line, and the clock signal terminal of the shift register of the 10k-4th level is electrically connected to a fourth clock signal line.

2. The gate driving circuit of claim 1, wherein the clock signal terminal of the register is electrically connected to a sixth clock signal line, the clock signal terminal of the shift register at a (10k-3)th level is electrically connected to a seventh clock signal line, the clock signal terminal of the shift register at a (10k-2)th level is electrically connected to an eighth clock signal line, the clock signal terminal of the shift register at a (10k-1)th level is electrically connected to a ninth clock signal line, and the clock signal terminal of the shift register at a (10k-1)th level is electrically connected to a tenth clock signal line, where k is a positive integer.

3. 3. The gate drive circuit according to claim 2, wherein the duty ratio of the clock signal on each of said clock signal lines is about 40%.

4. the input circuit includes a first switch transistor; 2. The gate drive circuit according to claim 1, wherein a gate and a first electrode of the first switch transistor are electrically connected to the input signal terminal, and a second electrode of the first switch transistor is electrically connected to the first node.

5. the reset circuit includes a second switch transistor; 2. The gate drive circuit according to claim 1, wherein a gate of the second switch transistor is electrically connected to the reset signal terminal, a first electrode of the second switch transistor is electrically connected to the first node, and a second electrode of the second switch transistor is electrically connected to the first reference signal terminal.

6. 2. The gate drive circuit according to claim 1, wherein the first control signal terminal and the second control signal terminal alternately input effective control signals.

7. the first output circuit includes an eleventh switch transistor and a capacitor; a gate of the eleventh switch transistor is electrically connected to the first node, a first electrode of the eleventh switch transistor is electrically connected to the clock signal terminal, and a second electrode of the eleventh switch transistor is electrically connected to the gate signal output terminal; 2. The gate drive circuit according to claim 1, wherein the capacitor is connected between the gate and the second electrode of the eleventh switch transistor.

8. the second output circuit includes a twelfth switch transistor; 2. The gate drive circuit according to claim 1, wherein a gate of the twelfth switch transistor is electrically connected to the first node, a first electrode of the twelfth switch transistor is electrically connected to the clock signal terminal, and a second electrode of the twelfth switch transistor is electrically connected to the output control terminal.

9. the reset circuit includes a thirteenth switch transistor; 2. The gate drive circuit of claim 1, wherein a gate of the thirteenth switch transistor is electrically connected to the reset signal terminal, a first electrode of the thirteenth switch transistor is electrically connected to the first node, and a second electrode of the thirteenth switch transistor is electrically connected to the first reference signal terminal.

10. A display device comprising the gate drive circuit according to any one of claims 1 to 9.

Images