Bounding Volume Hierarchy Generation

Abstract

Techniques are provided for performing ray tracing operations that include identifying bounding box surface area weighted centroids of a group of primitives associated with a bounding box in a bounding volume hierarchy ("BVH"), generating candidate partitions at the centroids that define geometric subgroups, identifying the candidate partitions with the smallest surface area bounding boxes, and generating nodes in the BVH that contain the geometry of the geometric subgroups of the identified candidate partitions.

Description

[Technical Field]

[0001] (CROSS-REFERENCE TO RELATED APPLICATIONS) This application claims the benefit of U.S. Provisional Patent Application No. 63 / 107,166, entitled "BOUNDING VOLUME HIERARCHY GENERATION," filed October 29, 2020, which is incorporated herein by reference in its entirety. This application claims the benefit of U.S. Provisional Patent Application No. 17 / 114,485, entitled "BOUNDING VOLUME HIERARCHY GENERATION," filed December 7, 2020, which is incorporated herein by reference in its entirety. [Background technology]

[0002] Ray tracing is a type of graphics rendering technique in which simulated rays are cast to test object intersections, and pixels are colored based on the results of the ray cast. Ray tracing is more computationally expensive than rasterization-based techniques, but produces more physically accurate results. Improvements to ray tracing behavior are constantly being made.

[0003] A more detailed understanding may be had from the following description, given by way of example in conjunction with the accompanying drawings, in which: [Brief explanation of the drawings]

[0004] [Figure 1] 1 is a block diagram of an example device in which one or more features of the present disclosure may be implemented. [Figure 2] FIG. 2 illustrates details of the device of FIG. 1, according to an example. [Figure 3] FIG. 1 illustrates a ray tracing pipeline for rendering graphics using ray tracing techniques, according to an example. [Figure 4] FIG. 1 illustrates a bounding volume hierarchy, according to an example. [Figure 5A] FIG. 1 illustrates exemplary operations for subdividing a scene and constructing a BVH, according to one example. [Figure 5B] FIG. 1 illustrates exemplary operations for subdividing a scene and constructing a BVH, according to one example. [Figure 6] FIG. 1 illustrates exemplary operations for constructing a BVH. [Figure 7] FIG. 1 illustrates an intermediate BVH, according to an example. [Figure 8] FIG. 1 illustrates an integrated BVH, according to an example. [Figure 9] 1 is a flow diagram of a method for generating a bounding volume hierarchy, according to an example. DETAILED DESCRIPTION OF THE INVENTION

[0005] Techniques are provided for performing ray tracing operations that include identifying a bounding-box-surface-area-weighted centroid of a group of primitives associated with a bounding box in a bounding volume hierarchy ("BVH"), generating candidate partitions at the centroid that define geometric subgroups, identifying the candidate partitions with the smallest surface area bounding boxes, and generating nodes of the BVH that contain the geometry of the geometric subgroups of the identified candidate partitions.

[0006] 1 is a block diagram of an example device 100 capable of implementing one or more features of the present disclosure. Device 100 may be, for example, but not limited to, a computer, a gaming device, a handheld device, a set-top box, a television, a mobile phone, a tablet computer, or any other computing device. Device 100 includes a processor 102, a memory 104, a storage device 106, one or more input devices 108, and one or more output devices 110. Device 100 also includes one or more input drivers 112 and one or more output drivers 114. Any of the input drivers 112 may be embodied as hardware, a combination of hardware and software, or software, and are responsible for controlling (e.g., controlling the operation of, receiving input from, and providing data to) input driver 112. Similarly, any of the output drivers 114 may be embodied as hardware, a combination of hardware and software, or software and serve to control (e.g., control the operation of, receive input from, and provide data to) the output device 110. It should be understood that device 100 may include additional components not shown in FIG.

[0007] In various alternatives, processor 102 includes a central processing unit (CPU), a graphics processing unit (GPU), a CPU and a GPU located on the same die, or one or more processor cores, and in different embodiments, each processor core is a CPU or a GPU. In various alternatives, memory 104 is located on the same die as processor 102 or is located separately from processor 102. Memory 104 includes volatile or non-volatile memory (e.g., random access memory (RAM), dynamic RAM, cache).

[0008] Storage devices 106 include fixed or removable storage devices (e.g., but not limited to, hard disk drives, solid state drives, optical disks, flash drives). Input devices 108 include, but are not limited to, keyboards, keypads, touchscreens, touchpads, detectors, microphones, accelerometers, gyroscopes, biometric scanners, or network connections (e.g., wireless local area network cards for transmitting and / or receiving wireless IEEE 802 signals). Output devices 110 include, but are not limited to, displays, speakers, printers, haptic feedback devices, one or more optics, antennas, or network connections (e.g., wireless local area network cards for transmitting and / or receiving wireless IEEE 802 signals).

[0009] The input driver 112 and the output driver 114 include one or more hardware, software, and / or firmware components configured to interface with and drive the input device 108 and the output device 110, respectively. The input driver 112 communicates with the processor 102 and the input device 108, enabling the processor 102 to receive input from the input device 108. The output driver 114 communicates with the processor 102 and the output device 110, enabling the processor 102 to send output to the output device 110. The output driver 114 includes an accelerated processing device ("APD") 116 coupled to a display device 118, which in some examples is a physical display device or a simulated device that presents output using a remote display protocol. The APD 116 is configured to accept computational and graphics rendering commands from the processor 102, process the computational and graphics rendering commands, and provide pixel output to the display device 118 for display. As described in further detail below, APD 116 includes one or more parallel processing units configured to perform calculations according to the single-instruction-multiple-data (SIMD) paradigm. Thus, although various functions are described herein as being performed by or in conjunction with APD 116, in various alternatives, functions described as being performed by APD 116 are not driven by a host processor (e.g., processor 102) but are additionally or alternatively performed by other computing devices having similar capabilities that are configured to provide graphical output to display device 118. For example, it is contemplated that any processing system that performs processing tasks according to the SIMD paradigm may be configured to perform the functions described herein. Alternatively, it is contemplated that computing systems that do not perform processing tasks according to the SIMD paradigm may perform the functions described herein.

[0010] 2 illustrates details of device 100 and APD 116, according to one example. Processor 102 (FIG. 1) executes operating system 120, drivers 122, and applications 126, and, in some circumstances, alternatively or additionally, executes other software. Operating system 120 controls various aspects of device 100, such as managing hardware resources, handling service requests, scheduling and controlling process execution, and performing other operations. APD driver 122 controls the operation of APD 116 and sends tasks, such as graphics rendering tasks or other work, to APD 116 for processing. APD driver 122 also includes a just-in-time compiler that compiles programs for execution by processing components of APD 116 (such as SIMD unit 138, discussed in more detail below).

[0011] APD 116 executes commands and programs for selected functions, such as graphics and non-graphics operations that are suitable for parallel processing. In various examples, APD 116 is used to perform graphics pipeline operations, such as pixel operations, geometry calculations, and rendering of images to display device 118, based on commands received from processor 102. APD 116 also performs computational operations not directly related to graphics operations, such as operations related to video, physics simulation, computational fluid dynamics, or other tasks, based on commands received from processor 102. In some examples, these computational operations are performed by executing computational shaders on SIMD unit 138.

[0012] The APD 116 includes a computation unit 132 that includes one or more SIMD units 138 configured to perform operations in a parallel manner according to the SIMD paradigm at the request of the processor 102 (or another unit). The SIMD paradigm allows multiple processing elements to share a single program control flow unit and program counter, thus executing the same program but with different data. In one example, each SIMD unit 138 includes 16 lanes, each of which executes the same instruction simultaneously with other lanes in the SIMD unit 138, but is capable of executing the instruction with different data. In some situations, lanes are switched off with prediction when not all lanes need to execute a given instruction. In some situations, prediction is also used in the execution of programs in which control flow diverges. More specifically, for programs with conditional branches or other instructions whose control flow is based on calculations performed by individual lanes, prediction of lanes corresponding to currently unexecuted control flow paths and serial execution of different control flow paths allows for arbitrary control flow.

[0013] The basic unit of execution within compute unit 132 is the work item. Each work item represents a single instantiation of a program executing in parallel on a particular lane. In various examples, work items execute simultaneously (or partially concurrently and partially sequentially) as a “wavefront” on a single SIMD unit 138. One or more wavefronts are included in a “workgroup,” which includes a collection of work items designated to execute the same program. In some embodiments, a workgroup is executed by executing each of the wavefronts that make up the workgroup. In alternative examples, a wavefront executes on a single SIMD unit 138 or on different SIMD units 138. In some embodiments, a wavefront is the maximal collection of work items that execute simultaneously (or pseudo-simultaneously) on a single SIMD unit 138. “Pseudo-simultaneous” execution occurs in the case of wavefronts that are larger than the number of lanes in SIMD unit 138. In such a situation, a wavefront executes over multiple cycles, with different collections of work items executing in different cycles. APD scheduler 136 is configured to perform operations related to scheduling various workgroups and wavefronts on compute units 132 and SIMD units 138 .

[0014] The parallel processing provided by the computation units 132 is well suited to graphics-related operations such as pixel value calculations, vertex transformations, and other graphics operations. Thus, in some cases, the graphics pipeline 134, which accepts graphics processing commands from the processor 102, provides computational tasks to the computation units 132 for execution in parallel.

[0015] Computation unit 132 is also used to perform computational tasks that are not related to graphics or that are not performed as part of the "normal" operation of graphics pipeline 134 (e.g., custom operations performed to supplement the processing performed on the operation of graphics pipeline 134). Applications 126 or other software executing on processor 102 send programs defining such computational tasks to APD 116 for execution.

[0016] APD 116, which includes compute units 132, implements ray tracing, a technique for rendering a 3D scene by testing the intersection of simulated rays with objects in the scene. In some embodiments, much of the work involved in ray tracing is performed by programmable shader programs executing on SIMD units 138 within compute units 132, as described in more detail below.

[0017] Figure 3 illustrates a ray tracing pipeline 300 for rendering graphics using ray tracing techniques, according to an example. The ray tracing pipeline 300 provides an overview of the operations and entities involved in rendering a scene using ray tracing. In some embodiments, the ray generation shader 302, any hit shader 306, intersection shader 307, nearest hit shader 310, and miss shader 312 are shader implementation stages that represent ray tracing pipeline stages whose functions are performed by shader programs executing within the SIMD unit 138. The specific shader programs at each specific shader implementation stage are defined by application-provided code (i.e., by code provided by the application developer that is pre-compiled by the application compiler and / or compiled by the driver 122). The acceleration structure traversal stage 304 performs ray intersection tests to determine whether a ray hits a triangle. The other programmable shader stages (ray generation shader 302, any hit shader 306, nearest hit shader 310, miss shader 312) are implemented as shader programs executing on SIMD units 138. The acceleration structure traversal stage is implemented in software (e.g., as a shader program executing on SIMD units 138), in hardware, or as a combination of hardware and software. Ray tracing pipeline 300, in various embodiments, is organized partially or fully in software, or partially or fully in hardware, and in various embodiments, by processor 102, scheduler 136, by a combination thereof, or partially or fully by any other hardware and / or software unit.

[0018] In examples, traversal through the ray tracing pipeline 300 is performed partially or completely by the scheduler 136, either autonomously or under the control of the processor 102, or partially or completely by a shader program (such as a bounding volume hierarchy traversal shader program) executing on one or more of the SIMD units 138. In some examples, testing rays against boxes and triangles (inside the acceleration structure traversal stage 304) is hardware accelerated (meaning that a fixed-function hardware unit performs those testing steps). In other examples, such testing is performed by software, such as a shader program, executing on one or more of the SIMD units 138. As used herein, when the phrase "the ray tracing pipeline does something" is used, it means that the hardware and / or software implementing the ray tracing pipeline 300 does that thing. Although illustrated as executing on SIMD unit 138 in FIG. 3, it should be understood that in other embodiments, other hardware (such as one or more processors), whether or not having SIMD capabilities (e.g., processor 102), may alternatively execute the shader programs of the illustrated ray tracing pipeline 300.

[0019] In some modes of operation, the ray tracing pipeline 300 operates in the following manner: A ray generation shader 302 is executed, which sets up data for rays to test against triangles and calls upon an acceleration structure traversal stage 304 to test rays for intersection with triangles.

[0020] The acceleration structure traversal stage 304 traverses the acceleration structure, which is a data structure that describes the scene and objects within the scene, and tests the ray against triangles in the scene. In some examples, during this traversal, for triangles intersected by the ray, the ray tracing pipeline 300 triggers the execution of any hit shader 306 and / or intersection shader 307 if those shaders are specified by the intersected triangle's material. Note that multiple triangles can be intersected by a single ray. The acceleration structure traversal stage is not guaranteed to traverse the acceleration structure in order from closest to the ray origin to farthest from the ray origin. In some examples, the acceleration structure traversal stage 304 triggers the execution of the closest hit shader 310 for the triangle closest to the ray's origin that the ray hits, or triggers a miss shader if the triangle was not hit.

[0021] Note that any hit shader 306 or intersection shader 307 can “reject” an intersection from the accelerated structure traversal stage 304; thus, the accelerated structure traversal stage 304 triggers execution of the miss shader 312 if no intersections with the ray are found, or if one or more intersections are found but are all rejected by any hit shader 306 and / or intersection shader 307. An exemplary situation in which any hit shader 306 “rejects” a hit is when at least a portion of the triangle that the accelerated structure traversal stage 304 reports as a hit is completely transparent (invisible). In one example, the accelerated structure traversal stage 304 tests geometry rather than transparency. Thus, in these examples, any hit shader 306 that is invoked due to an intersection with a triangle that has at least some transparency may determine that the reported intersection should not be counted as a hit because it “intersects” with a transparent portion of the triangle. A typical use of the closest hit shader 310 is to color rays based on material texture. A typical use of miss shader 312 is to color rays with a color set by the skybox. It should be understood that in various embodiments, the shader programs defined for closest hit shader 310 and miss shader 312 implement a wide variety of techniques for coloring rays and / or performing other operations.

[0022] A typical way that the ray generation shader 302 generates rays is using a technique called backward ray tracing. In backward ray tracing, the ray generation shader 302 generates rays that have their origin at a point on the camera. The point at which the ray intersects a plane defined to correspond to the screen defines a pixel on the screen that is used to determine the ray's color. If the ray hits an object, the pixel is colored based on the closest hit shader 310. If the ray does not hit an object, the pixel is colored based on the miss shader 312. Multiple rays can be cast for each pixel, and the pixel's final color is determined by some combination of the colors determined for each of the pixel's rays.

[0023] Any of the hit shader 306, intersection shader 307, closest hit shader 310, and miss shader 312 can spawn unique rays that enter the ray tracing pipeline 300 at a ray test point. These rays can be used for any purpose. One common use is to implement ambient lighting or reflection. In one example, when the nearest hit shader 310 is invoked, it spawns rays in various directions. For each object or light hit by the spawned ray, the nearest hit shader 310 adds lighting intensity and color to the pixel corresponding to the nearest hit shader 310. While several examples of how various components of the ray tracing pipeline 300 can be used to render a scene are described, it should be understood that any of a wide variety of techniques may alternatively be used.

[0024] As mentioned above, determining whether a ray intersects an object is referred to herein as a "ray intersection test." Ray intersection testing involves firing a ray from an origin and determining whether the ray intersects a geometric primitive (e.g., a triangle), and if so, how far from the origin of the triangle intersection it is. To increase efficiency, ray tracing testing uses a representation of space called an acceleration structure, such as a bounding volume hierarchy. In a bounding volume hierarchy, each non-leaf node represents an axis-aligned bounding box that bounds the geometries of all of the node's children. In one example, a base node represents the maximum extent of the entire region over which ray intersection testing is being performed. In this example, the base node has two children, each of which typically represents a different axis-aligned bounding box that subdivides the entire region. Each of those two children has two child nodes that represent axis-aligned bounding boxes that subdivide their parent's space, and so on. Leaf nodes represent triangles or other geometric primitives over which ray intersection testing is being performed. Non-leaf nodes are sometimes referred to herein as "box nodes" and leaf nodes are sometimes referred to herein as "triangle nodes."

[0025] The bounding volume hierarchical data structure allows the number of ray-triangle intersections (which are complex and therefore expensive in terms of processing resources) to be reduced compared to a scenario in which such a data structure is not used and therefore every triangle in the scene needs to be tested for the ray. Specifically, if a ray does not intersect with a particular bounding box and that bounding box bounds many triangles, all triangles within that box are eliminated from testing. Thus, ray intersection testing is performed as a series of tests of the ray against axis-aligned bounding boxes, followed by tests against the triangles.

[0026] 4 is a diagram illustrating a bounding volume hierarchy, according to an example. For simplicity, the hierarchy is shown in 2D. However, it should be understood that extension to 3D is straightforward and the tests described herein are generally performed in three dimensions.

[0027] A spatial representation 402 of the bounding volume hierarchy is shown on the left side of FIG. 4, and a tree representation 404 of the bounding volume hierarchy is shown on the right side of FIG. 4. In both the spatial representation 402 and the tree representation 404, non-leaf nodes are represented by the letter "N" and leaf nodes are represented by the letter "O." A ray intersection test is performed by traversing through the tree 404, and for each non-leaf node tested, if the test for that non-leaf node fails, the branch below that node is eliminated. In one example, a ray intersects with O5 but not with any other triangles. The test tests for N1 and determines that the test is successful. The test tests for N2 and determines that the test is unsuccessful (because O5 is not within N1). Note that the test eliminates all subnodes of N2 and tests for N3, which also passes. Note that the test tests N6 and N7, and N6 passes but N7 fails. Note that this test tests O5 and O6, O5 passes but O6 fails. Instead of testing eight triangle tests, two triangle tests (O5 and O6) and five box tests (N1, N2, N3, N6, N7) are performed.

[0028] FIG. 4 illustrates a bounding volume hierarchy (BVH) builder 450, according to one example. The BVH builder 450 accepts scene geometry 452 and generates a bounding volume hierarchy 404. The scene geometry 452 includes primitives describing a scene provided by an application or other entity. The BVH builder 450 is implemented as software executing on a processor configured to perform the functions described herein, as hardwired circuitry configured to perform the functions described herein, or as a combination of software executing on a processor and hardwired circuitry configured to both perform the functions described herein. In various examples, the BVH builder 450 resides within a computer system (e.g., computer system 100) such as executing on the processor 102 or APD 116, or is a hardware unit within the processor 102 or APD 116. In various examples, the BVH builder 450 builds the BVH at compile time on a computer system different from the computer system that performs ray tracing using the constructed BVH to render the scene. In other examples, the BVH builder 450 builds the BVH at runtime on the same computer that renders the scene using ray tracing techniques. In various examples, a driver, application, or hardware unit of the APD 116 performs this runtime rendering. Exemplary techniques for building a BVH are now described.

[0029] 5A and 5B are diagrams illustrating exemplary operations for subdividing a scene and constructing a BVH, according to one example. In both of these figures, a scene 501 is shown. The scene 501 includes a number of triangles 502. The scene 501 is the scene geometry 452 in FIG. 4. The BVH builder 450 generates a BVH based on the scene 501.

[0030] According to a technique for constructing the BVH, the BVH builder 450 determines a centroid 506 for each of the triangles 502. In one example, the centroid is the intersection of lines from each vertex to the midpoint of the opposite side. The BVH builder 450 also determines an axis-aligned bounding box 504 for each of the triangles 502. Each bounding box 504 is a box defined by the minimum and maximum extents of the triangle in each dimension.

[0031] The BVH builder 450 determines the scene centroid 507 as the weighted average of the bounding box surface areas of all of the triangle centroids. The weighted average of the bounding box surface areas of all of the triangle centroids is the average of the weighted centroids of the triangles 502. The weighted centroid of each triangle is the coordinate of the triangle centroid multiplied by the bounding box 504 of that triangle 502. The average is the sum of each such weighted centroid divided by the total surface area of ​​the triangles 502. In formula form, this average is expressed as:

number

[0032] In this equation, W centroid is the scene centroid 507. tri is the centroid of the triangle. SurfaceArea aabbOfTri is the surface area of ​​the axis-aligned bounding box 504 of the triangle 502. The scene centroid 507 is therefore the sum of the centroid multiplied by the bounding box surface area of ​​each triangle 502 divided by the sum of all the bounding box surface areas.

[0033] Based on the scene centroid 507, the BVH builder 450 generates several candidate slices 508 of the scene 501. The candidate slices 508 of the scene are proposed subdivisions of the triangles 502 in the scene 501 into different bounding boxes corresponding to different box nodes. The BVH builder 450 generates different candidate slices by slicing the scene 501 with a plane that is parallel to one of the axes and intersects the scene centroid 507. Thus, for a 3-coordinate system, the BVH builder 450 generates three candidate slices 508, one for each axis.

[0034] Each candidate slice 508 defines two different triangle groupings. Each triangle grouping is associated with a particular side of the candidate slice 508. The BVH builder 450 assigns to each triangle grouping the triangles in the scene 501 whose centroids lie on the side of the candidate slice 508 associated with the triangle grouping. In FIG. 5A , the BVH builder 450 assigns triangles 502(1)-(4) to the left triangle grouping and triangles 502(5)-(10) to the right triangle grouping, reflecting the side of the candidate slice 508 to which the centroids of these triangles 502 belong.

[0035] The BVH builder 450 determines a triangle grouping bounding box 510 for each triangle grouping. A triangle grouping bounding box is an axis-aligned bounding box that bounds all triangles in the triangle grouping. Note that triangle grouping bounding boxes 510 may overlap, for example, if the centroid of triangle 502 is close to a candidate slice 508, such that part of the triangle "spills" onto the other side of the candidate slice 508. For each candidate slice 508, the BVH builder 450 calculates the total surface area of ​​each triangle grouping bounding box 510 and sums the surface areas of the triangle grouping bounding boxes 510 for a particular candidate slice 508. The BVH builder 450 then selects the candidate slice 508 with the smallest total surface area of ​​its triangle grouping bounding boxes 510 as the candidate slice 508 to use to generate the BVH branches.

[0036] The BVH builder 450 iteratively performs the operations described above with respect to FIGS. 5A-5B to generate a tree structure for the BVH 404. In each iteration, the BVH builder 450 determines how to subdivide the triangles of a given box node to generate child nodes for that box node. In each iteration, the BVH builder 450 sets the triangles that fall within the bounding box of the box node being examined in that iteration as the "scene" 501 in FIGS. 5A-5B, and performs the operations described with respect to FIGS. 5A-5B. The BVH builder 450 generates children of the box node to reflect the selected candidate slices 508 and the corresponding triangle groups. More specifically, the BVH builder 450 sets a box node or leaf node corresponding to each generated triangle grouping as the box node's child. If the triangle grouping contains two or more triangles, the generated child is another box node; if the triangle grouping contains one triangle, the generated child is a leaf node.

[0037] Figure 5A reflects candidate slices 508 aligned along the y-axis, and Figure 5B reflects candidate slices 508 aligned along the x-axis, with the corresponding triangular subdivisions shown in each figure. Because candidate slice 508(1) in Figure 5A is associated with the smallest total surface area (due to substantial overlap in Figure 5B), BVH builder 450 selects that candidate slice 508(1) to generate a box node child that bounds all of the triangles shown.

[0038] Note that although the candidate slices are described as being parallel to the axes of the coordinate system, the planes slicing the primitives can be of any orientation, as long as they pass through the centroid 507.

[0039] Figure 6 illustrates example operations for constructing BVH 404. Specifically, Figure 6 shows two BVH states 600 in which BVH builder 450 has constructed different portions of BVH 404. In BVH state 1 600(1), BVH builder 450 has already examined the geometry associated with box node 602(1). This geometry includes geometry 604(1) (for box node 602(2)) and geometry 604(2) (for box node 602(3)). BVH builder 450 has generated box nodes 602(2) and 602(3) by splitting the geometry according to techniques described elsewhere herein (e.g., Figures 5A and 5B).

[0040] BVH builder 450 examines box node 602(2) and box node 602(3) to generate additional nodes that are children of these box nodes 602. For box node 602(2), BVH builder 450 determines a division for the triangles in geometry 604(1) for that box node 602(2) and generates new child nodes based on that division. These child nodes are shown in state 600(2). Specifically, box node 602(4) contains geometry 604(3), and box node 602(5) contains geometry 604(4). Similarly, BVH builder 450 examines box node 602(3) to generate box node 602(6) and box node 602(7). Although not shown, additional states 600 are performed to generate the BVH. It should also be understood that if the division results in a single triangle, BVH builder 450 generates a leaf node rather than a box node.

[0041] 7 illustrates an example intermediate BVH 700, which is the result of the BVH builder 450 iteratively dividing the geometry and generating nodes until every individual triangle has been assigned a leaf node.

[0042] The BVH 700 includes multiple nodes 702, each of which is either a box node or a triangle node. A box node (e.g., node 702(1)) includes a node identifier 704 and a node reference 706 that references another node 702. A triangle node (e.g., node 702(5)) includes a node identifier 704 and triangle data 708 that describes the triangle geometry (and potentially other information) for that triangle node.

[0043] In the example of Figure 7, box node 702(1) includes box node identifier 704(1) that points to node reference 706(1) and node reference 706(2). Node reference 706(1) points to box node 702(2) and node reference 706(2). Box node 702(2) includes box node identifier 704(2) that points to node reference 706(3) and node reference 706(4). Node reference 706(3) points to box node 702(4), and node reference 706(4) points to triangle node 702(5). Triangle node 702(5) includes node identifier 704(5) that points to triangle data 708(1).

[0044] The BVH builder 450 converts the intermediate BVH 700 into an integrated BVH in the following manner: The BVH builder 450 identifies levels 701 of the BVH 700. A level is a portion of the BVH 700 that is the same number of references below the top-level box node 702. In the BVH 700 of FIG. 7, level 1 701(1) includes node 702(1). Level 2 701(2) includes nodes 702(2) and 702(3). Level 3 701(3) includes nodes 702(4), 702(5), 702(6), and 702(7). Level 4 701(4) includes nodes 702(8) through 702(15).

[0045] The BVH builder 450 merges box nodes at multiple levels 701 to generate a merged box node. In one example, the BVH builder 450 merges an odd level 701 with the next even level. In one example, the BVH builder 450 merges level 1 701(1) and level 2 701(2). Specifically, the BVH builder generates a merged node by combining a node 702 from such a higher level 701 (odd level 701) with its box node children 702 in a lower level 701 (even level 701) to generate a new box node. The BVH builder 450 does not combine triangle nodes with box nodes in this manner. The merged box node includes all node references 706 from the top level 701. The result is a new box node that contains more node references 706 than the box nodes in the BVH 700, and also reduces the number of levels 701.

[0046] 8 is a diagram illustrating an example of a unified BVH 800. The BVH 800 includes a box node 802 and a triangle node 808. The box node 802 includes a box node identifier 804 and a node reference 806. The triangle node 808 includes a triangle node identifier 810 and triangle data 812.

[0047] Triangle node 808 is similar to a triangle node (e.g., node 702(5) in Figure 7). Box node 802 is similar to a box node (e.g., 702(1) in Figure 7), except that box node 802 includes more node references 806 than the box node in Figure 7.

[0048] BVH builder 450 generates integrated BVH 800 from intermediate BVH 700, as described above with respect to Figure 7. The example integrated BVH 800 of Figure 8 is generated from intermediate BVH 700 of Figure 7. Specifically, box node 802(1) is generated from level 1 701(1) and level 2 702(2). More specifically, BVH builder 450 generates box node 801(1) starting from box node 702(1). BVH builder 450 determines that box node 702(1) includes node reference 706(1) and node reference 706(2). Therefore, BVH builder 450 identifies the nodes 702 pointed to by those node references. 7, the node 702 pointed to by node reference 706(1) is node 702(2), and the node 702 pointed to by node reference 706(2) is node 702(3). BVH builder 450 identifies the node references 706 within these nodes 702 and includes these node references within the box node 802 being generated, thus combining two levels 701 into one level 701 and converting a box node 702 with two node references 706 into a box node 802 with four references 806 (although it should be understood that a box node 702 may have fewer than two node references 706, and therefore a box node 802 may have fewer than four node references 806).

[0049] For node references 706 that point to triangle nodes, BVH builder 450 also includes those node references 706 in combined box node 802. For example, box node 702(4) has two node references 706 that point to triangle nodes (nodes 702(8) through 702(11)). Therefore, BVH builder 450 includes these node references 706 in combined box node 802. In the manner described, BVH builder 450 generates box node 802(1), box node 802(2) (from box node 702(4) and triangle nodes 702(8) through 702(11)), and box node 802(3) (from box node 702(7) and triangle nodes 702(12) through 702(15)).

[0050] The triangle nodes in the unified BVH 800 are unchanged compared to the BVH 700. However, in some embodiments, the BVH builder 450 compresses these triangle nodes 808 to generate compressed triangle nodes (not shown). In one example, a compressed triangle node contains data for multiple triangles, with shared vertices represented fewer times than the number of instances those vertices appear in all triangles in the compressed triangle node. For example, if a compressed triangle node contains two triangles that share a vertex, the BVH builder 450 includes those triangles in a compressed triangle node that contains only one instance of the data (e.g., position) for that shared vertex. In another example, three or four triangles all share a vertex, and the compressed triangle node contains only one instance of that vertex (rather than three or four instances). In addition, the BVH builder 450 converts references to triangle nodes 808 into references to compressed triangle nodes. Thus, it is possible for multiple node references 806 to point to the same compressed triangle node (but to different triangles within that compressed triangle node).

[0051] The BVH builder 450 gives the box nodes 802 in FIG. 8 a bounding box that encloses all triangles that are descendants of those box nodes 802.

[0052] While the BVH builder 450 has been described as generating merged box nodes 802 from two levels 701 of the intermediate BVH 700, in some embodiments, the BVH builder 450 generates merged box nodes from three or more levels 701 of the intermediate BVH 700. In such cases, the merged box node includes all node references 706 from box nodes 702 in the lowest layer 701 being merged that are not triangle nodes descending from a particular box node 702 in the top layer 701. In one example, a box node 702 in a particular layer has six box nodes descending from it in level 3 layer 701. The BVH builder 450 generates a merged box node that includes all of the node references 706 in those six box nodes.

[0053] Although triangles are sometimes described as the geometry contained within a leaf node, leaf nodes can contain any type of geometry, or even specify intersection tests using code rather than shape information.

[0054] 9 is a flow diagram of a method 900 for generating a bounding volume hierarchy, according to an example. Although described with respect to the systems of FIGS. 1-8, one skilled in the art will understand that any system configured to perform the steps of method 900 in any technically feasible order is within the scope of this disclosure.

[0055] Method 900 begins at step 902, where BVH builder 450 identifies a bounding box surface area weighted centroid for a group of primitives. This centroid is centroid 507 in Figures 5A and 5B, and identifying this centroid is described elsewhere herein. A group of primitives is a group of primitives bounded by the bounding boxes of a box node, such as the top node of a BVH or a different box node of a BVH.

[0056] In step 904, the BVH builder 450 generates candidate partitions at the centroids. The candidate partitions define geometric subgroups. In one example, the candidate partitions are performed by dividing the geometry in planes parallel to each of the axes (x, y, z) that pass through the centroid 507.

[0057] In step 906, the BVH builder 450 identifies the candidate partition with the smallest surface area bounding box. For each partition, the geometries are divided into two groups, each on a different side of the plane. An axis-aligned bounding box is then determined for each group, with each box enclosing all the geometries in that group. The partition with the smallest sum of the surface areas of the two bounding boxes is the identified candidate partition.

[0058] In step 908, the BVH builder 450 generates nodes containing the geometry of the identified candidate division subgroups. In one example, if the group contains one primitive, the BVH builder 450 generates a triangle node for the group. If the group contains two or more primitives, the BVH builder 450 generates a box node having a bounding box that bounds the two or more primitives. The BVH builder 450 also adds a node reference to the box node associated with the divided geometry, where the generated node reference points to the newly generated node.

[0059] The BVH builder 450 repeats the method 900 to generate the complete BVH. In one example, the BVH builder 450 repeats the method 900 until all groups have been split and a triangle node exists at the bottom node of each branch of the BVH.

[0060] It should be understood that many variations are possible based on the disclosure herein, and although features and elements are described above in particular combinations, each feature or element can be used alone without other features and elements, or in various combinations with or without other features and elements.

[0061] The provided methods can be implemented in a general-purpose computer, processor, or processor core. Suitable processors include, by way of example, a general-purpose processor, a special-purpose processor, a conventional processor, a digital signal processor (DSP), multiple microprocessors, one or more microprocessors in association with a DSP core, a controller, a microcontroller, an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) circuit, any other type of integrated circuit (IC), and / or a state machine. Such processors can be fabricated by configuring a manufacturing process using the results of processed hardware description language (HDL) instructions and other intermediate data (instructions that can be stored on a computer-readable medium), including a netlist. The result of such processing can be a mask work that is used in a subsequent semiconductor manufacturing process to produce a processor implementing features of the present disclosure.

[0062] The methods or flow diagrams provided herein may be implemented in a computer program, software, or firmware embodied in a non-transitory computer-readable storage medium for execution by a general-purpose computer or processor. Examples of non-transitory computer-readable storage media include read only memory (ROM), random access memory (RAM), registers, cache memory, semiconductor memory devices, magnetic media such as internal hard disks and removable disks, magneto-optical media, and optical media such as CD-ROM disks and digital versatile disks (DVDs).

Claims

1. 1. A method for performing a ray tracing operation, comprising: Identifying a bounding box surface area weighted centroid of a group of primitives associated with a bounding box of a bounding volume hierarchy (BVH); generating candidate partitions defining geometric subgroups at the centroids; identifying a candidate partition having a minimum surface area bounding box; generating nodes of the BVH that include the geometries of the geometric subgroups of the identified candidate partitions; method.

2. Identifying the bounding box surface area weighted centroids of the group of primitives comprises: identifying a point defined by a bounding box weighted average of centroid positions of the group of primitives; 10. The method of claim 1.

3. generating the candidate partitions identifying a plurality of subdivision planes parallel to the coordinate axes and intersecting the centroid; generating a plurality of subgroups of primitives from the group of primitives, the subgroups being defined based on which side of a subdivision plane the primitives lie on; 10. The method of claim 1.

4. Identifying the candidate partition having the smallest surface area bounding box comprises: For each candidate split, identifying a bounding box that bounds all primitives on each side of a subdivision plane of the candidate division; adding the surface areas of the bounding boxes to obtain a total surface area of ​​the candidate partition; selecting the candidate partition having the smallest total surface area; 10. The method of claim 1.

5. generating the node generating a leaf node for each geometric subgroup containing one primitive, and generating a box node for each geometric subgroup containing two or more primitives; 10. The method of claim 1.

6. compressing triangle nodes of the BVH by combining triangle nodes having triangles that share a vertex.

10. The method of claim 1.

7. converting the BVH to an integrated BVH by integrating box nodes and levels of the BVH to generate integrated box nodes.

10. The method of claim 1.

8. and repeating the steps of identifying the bounding box surface area weighted centroids, generating the candidate partitions, identifying the candidate partitions, and generating nodes to generate a plurality of box nodes for the BVH.

10. The method of claim 1.

9. generating the plurality of box nodes of the BVH until all bottom nodes of all branches of the BVH are a single geometric node.

9. The method of claim 8.

10. 1. A device configured to construct a bounding volume hierarchy (BVH), comprising: a memory for storing the BVH; a BVH builder; The BVH builder identifying a bounding box surface area weighted centroid of a group of primitives associated with a bounding box of the BVH; generating candidate partitions defining geometric subgroups at the centroids; identifying a candidate partition having a minimum surface area bounding box; generating a node of the BVH that includes the geometry of the geometric subgroup of the identified candidate partition; configured to: device.

11. Identifying the bounding box surface area weighted centroids of the group of primitives comprises: identifying a point defined by a bounding box weighted average of centroid positions of the group of primitives; The device of claim 10.

12. generating the candidate partitions identifying a plurality of subdivision planes parallel to the coordinate axes and intersecting the centroid; generating a plurality of subgroups of primitives from the group of primitives, the subgroups being defined based on which side of a subdivision plane the primitives lie on; The device of claim 10.

13. Identifying the candidate partition having the smallest surface area bounding box comprises: For each candidate split, identifying a bounding box that bounds all primitives on each side of a subdivision plane of the candidate division; adding the surface areas of the bounding boxes to obtain a total surface area of ​​the candidate partition; selecting the candidate partition having the smallest total surface area; The device of claim 10.

14. generating the node generating a leaf node for each geometric subgroup containing one primitive, and generating a box node for each geometric subgroup containing two or more primitives; The device of claim 10.

15. The BVH builder and further configured to compress the triangle nodes of the BVH by combining triangle nodes having triangles that share a vertex. The device of claim 10.

16. The BVH builder and further configured to convert the BVH to a consolidated BVH by consolidating box nodes and levels of the BVH to generate consolidated box nodes. The device of claim 10.

17. The BVH builder and further configured to repeat the steps of identifying the bounding box surface area weighted centroids, generating the candidate partitions, identifying the candidate partitions, and generating nodes to generate a plurality of box nodes for the BVH. The device of claim 10.

18. The BVH builder and generating the plurality of box nodes of the BVH until all bottom nodes of all branches of the BVH are a single geometric node.

18. The device of claim 17.

19. A computer-readable storage medium storing instructions, comprising: The instructions, when executed by a processor, Identifying a bounding box surface area weighted centroid of a group of primitives associated with a bounding box of a bounding volume hierarchy (BVH); generating candidate partitions defining geometric subgroups at the centroids; identifying a candidate partition having a minimum surface area bounding box; generating a node of the BVH that includes the geometry of the geometric subgroup of the identified candidate partition; causing the processor to execute A computer-readable storage medium.

20. Identifying the bounding box surface area weighted centroids of the group of primitives comprises: identifying a point defined by a bounding box weighted average of centroid positions of the group of primitives; 20. The computer-readable storage medium of claim 19.

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