signal receiving device

Abstract

To provide a signal receiving device that does not need to consider a jitter characteristic of a reception signal.SOLUTION: A signal receiving device according to the present invention includes a transition detection device that receives first to third input signals with different signal levels for each unit section, outputs a first comparison signal among a plurality of comparison signals by comparing whether or not the signal level of a first differential signal, which is a differential signal between the first input signal and the second input signal among the first to the third input signals, is higher than a first reference signal level, and outputs a second comparison signal among the plurality of comparison signals by comparing whether or not the signal level of the first differential signal is higher than a second reference signal level that is different from the first reference signal level; and a clock data restoration device that restores the clock signal embedded in the first to the third input signals on the basis of the first and the second comparison signals to generate a restoration clock signal.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a signal receiving device. [Background technology]

[0002] A physical interface is used to output calculated data or receive sensed data, for example, an interface conforming to the DSI (Display System Interface) standard established by the MIPI (Mobile Industry Processor Interface) Alliance is provided.

[0003] As one example, the 3-wire interface (C-PHY) defined by MIPI uses a trio of conductors rather than differential pairs to transmit information between devices. Each of the three wires can be in one of three signaling states during the transmission of a symbol on the C-PHY interface. Clock information is encoded in the sequence of symbols transmitted on the C-PHY link, and the receiver generates the clock signal from the transitions between consecutive symbols. Therefore, the role of a clock-data recovery (CDR) device to recover the maximum speed and clock information of the communication link is crucial in the C-PHY interface. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] International Publication No. 2017 / 039985 Summary of the Invention [Problem to be solved by the invention]

[0005] The present invention has been made in consideration of the above-mentioned conventional technology, and an object of the present invention is to provide a signal receiving device that does not require consideration of the jitter characteristics of the received signal when recovering data and clock from the received signal. [Means for solving the problem]

[0006] In order to achieve the above object, one aspect of the present invention provides a signal receiving device that receives first to third input signals each having a different signal level for each unit interval, compares whether a signal level of a first differential signal, which is a differential signal between the first input signal and the second input signal among the first to third input signals, is greater than a first reference signal level, and outputs a first comparison signal from among a plurality of comparison signals, and compares whether the signal level of the first differential signal is greater than a second reference signal level different from the first reference signal level, and outputs a second comparison signal from among the plurality of comparison signals; and a clock data recovery device that recovers a clock signal embedded in the first to third input signals based on the first and second comparison signals to generate a recovered clock signal.

[0007] In order to achieve the above object, a signal receiving device according to another aspect of the present invention comprises a first variable gain amplifier that amplifies the signal level of a first differential signal, which is a differential signal between a first input signal and a second input signal among first to third input signals, each having a different signal level for each unit interval, based on a first gain control signal; a first level detector that outputs a first comparison signal in response to an output of the first variable gain amplifier being greater than a first reference signal level; a clock data recovery device that recovers a clock signal embedded in the first to third input signals based on the first comparison signal to generate a recovered clock signal; and a calibration device that adjusts the first gain control signal based on the first comparison signal.

[0008] In order to achieve the above object, according to still another aspect of the present invention, a signal receiving device includes: a first differential signal which is a differential signal between a first input signal and a second input signal among first to third input signals, each having a different signal level for each unit interval; a first level detector which outputs a first comparison signal from among a plurality of comparison signals based on a first reference signal level and a second reference signal level; a second differential signal which is a differential signal between the second input signal and the third input signal; a second level detector which outputs a second comparison signal from among the plurality of comparison signals based on the first reference signal level and the second reference signal level; a third differential signal which is a differential signal between the third input signal and the first input signal; and a third level detector which outputs a third comparison signal from among the plurality of comparison signals based on the first reference signal level and the second reference signal level; an SR latch which outputs wire state information of the first to third input signals based on the plurality of comparison signals; and a plurality of OR gates which restore clock signals embedded in the first to third input signals based on the plurality of comparison signals to generate restored clock signals. [Effects of the Invention]

[0009] According to the present invention, it is possible to eliminate the need for additional circuits to reflect the jitter characteristics of the received signal when recovering data and clock from the received signal, thereby providing a signal receiving device that can be miniaturized without having to consider the jitter characteristics of the received signal, as well as a clock recovery method and calibration method for the same. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a conceptual block diagram of a signal receiving device according to an embodiment; [Figure 2] 2 is an exemplary circuit diagram of the transition detection device of FIG. 1. [Figure 3] FIG. 3 is a diagram for explaining first to third input signals in FIG. 2. [Figure 4] 3 is an exemplary circuit diagram of the level detector of FIG. 2. [Figure 5] 2 is an exemplary circuit diagram of the clock data recovery device of FIG. 1; [Figure 6] 2 is an exemplary block diagram of the calibration device of FIG. 1. [Figure 7] 10A and 10B are diagrams illustrating a clock recovery method and a data recovery method of a signal receiving device according to an embodiment; [Figure 8] 10A and 10B are diagrams illustrating a clock recovery method and a data recovery method of a signal receiving device according to an embodiment; [Figure 9] 10A and 10B are diagrams illustrating a clock recovery method and a data recovery method of a signal receiving device according to an embodiment; [Figure 10] 10A and 10B are diagrams illustrating a clock recovery method and a data recovery method of a signal receiving device according to an embodiment; [Figure 11] 10A and 10B are diagrams illustrating a clock recovery method and a data recovery method of a signal receiving device according to an embodiment; [Figure 12] 10A and 10B are diagrams illustrating a calibration method for a signal receiving device according to an embodiment. [Figure 13] 1 is a conceptual block diagram of an example of a signal receiving system according to one embodiment. [Figure 14] FIG. 2 is a conceptual block diagram of another example of a signal receiving system according to one embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, specific examples of embodiments of the present invention will be described in detail with reference to the drawings.

[0012] FIG. 1 is a conceptual block diagram of a signal receiving device according to an embodiment.

[0013] Referring to FIG. 1, the signal receiving device includes a transition detection device 100, a clock data recovery device 200, and a calibration device 300.

[0014] The transition detection device 100 receives first to third input signals (A, B, C), calculates a differential signal between each of the input signals (A, B, C), compares the signal level of each differential signal with a first reference signal level and a second reference signal level, and outputs a comparison signal (PAB, NAB, PBC, NBC, PCA, NCA) based on each comparison result. In this embodiment, the term "differential signal" refers to a signal generated by the difference between two specific signals. For example, a differential signal between a first input signal A and a second input signal B refers to a signal whose signal level at each timing (time) is the difference (AB) between the signal level of the first input signal A and the signal level of the second input signal B.

[0015] Specifically, the transition detection device 100 obtains a first differential signal AB, which is a differential signal between a first input signal A and a second input signal B, and then compares whether the signal level of the first differential signal AB is greater than a first reference signal level to output a first comparison signal PAB, and compares whether the signal level of the first differential signal AB is greater than a second reference signal level to output a second comparison signal NAB.Furthermore, the transition detection device 100 obtains a second differential signal BC, which is a differential signal between a second input signal B and a third input signal C, and then compares whether the signal level of the second differential signal BC is greater than the first reference signal level to output a third comparison signal PBC, and compares whether the signal level of the second differential signal BC is greater than the second reference signal level to output a fourth comparison signal NBC. Furthermore, the transition detection device 100 obtains a third differential signal CA, which is a differential signal between the third input signal C and the first input signal A, and then compares whether the signal level of the third differential signal CA is greater than the first reference signal level to output a fifth comparison signal PCA, and compares whether the signal level of the third differential signal CA is greater than the second reference signal level to output a sixth comparison signal (NCA).

[0016] In some embodiments, the first and second reference signal levels have the same absolute value but opposite polarity. For example, if the first reference signal level is +2 / 5V, the second reference signal level is −2 / 5V. Also, if the first reference signal level is +4 / 9V, the second reference signal level is −4 / 9V. The operation of the transition detection apparatus 100 will be described in more detail below.

[0017] Meanwhile, the transition detection device 100 generates a reference clock signal RCK using two of the first to third input signals (A, B, C) provided thereto, and provides the generated reference clock signal RCK to the calibration device 300.

[0018] In some embodiments, the transition detection device 100 may generate the reference clock signal RCK using the first input signal A and the second input signal B among the first to third input signals (A, B, C) provided, but the embodiments are not limited thereto.

[0019] The clock data recovery device 200 recovers the wire status information WSI using the first to sixth comparison signals (PAB to NCA) and outputs it to the decoder 400. The clock data recovery device 200 recovers the clock signal embedded in the first to third input signals (A to C) using the first to sixth comparison signals (PAB to NCA) and provides it to the decoder 400 as a recovered clock signal RECK.

[0020] The decoder 400 and the demapper 500 use the provided wire state information WSI and the recovered clock signal RECK to recover the data signals provided as the first to third input signals (A to C).

[0021] Meanwhile, the recovered clock signal RECK recovered by the clock data recovery device 200 is provided to a test driver such as the demapper 500 .

[0022] The calibration device 300 receives the reference clock signal RCK and the first to sixth comparison signals (PAB to NCA) from the transition detection device 100, and generates gain control signals (GCS1 to GCS6) based on these signals.

[0023] Specifically, the calibration device 300 generates gain control signals (GCS1, GCS2) for amplifying the first differential signal AB, gain control signals (GCS3, GCS4) for amplifying the second differential signal BC, and gain control signals (GCS5, GCS6) for amplifying the third differential signal CA, using the reference clock signal RCK and the first to sixth comparison signals (PAB to NCA). More specific operations related to this will be described later.

[0024] In some embodiments, the first to third input signals (A to C) are signals provided by a MIPI (Mobile Industry Processor Interface) C-PHY interface. Therefore, the signal receiving device is, for example, a device that receives an input signal via the MIPI C-PHY interface and recovers a clock and data from the received input signal. However, the technical concept of the present invention is not limited thereto. For example, embodiments according to the technical concept of the present invention may be adopted even when other communication interfaces are used.

[0025] In some embodiments, the transition detection device 100 and the clock data recovery device 200 are disposed in an analog circuit block of the signal receiving device. A portion of the calibration device 300 is disposed in the analog circuit block of the signal receiving device, and another portion of the calibration device 300 is disposed in a digital logic block of the signal receiving device. The decoder 400 is disposed in the digital logic block of the signal receiving device, but the embodiments are not limited thereto.

[0026] Specific embodiments of the signal receiving device will be described below with reference to FIGS. 2 to 6, but the embodiments according to the technical idea of ​​the present invention are not limited to the contents described below.

[0027] Fig. 2 is an exemplary circuit diagram of the transition detection device of Fig. 1. Fig. 3 is a diagram for explaining first to third input signals of Fig. 2. Fig. 4 is an exemplary circuit diagram of a level detector of Fig. 2. Fig. 5 is an exemplary circuit diagram of the clock data recovery device of Fig. 1. Fig. 6 is an exemplary block diagram of the calibration device of Fig. 1.

[0028] Referring to FIG. 2, the transition detection device 100 includes first to third input terminals (INA to INC) to which first to third input signals (A to C) are respectively input.

[0029] A first input signal A is provided to the first input terminal INA, a second input signal B is provided to the second input terminal INB, and a third input signal C is provided to the third input terminal INC. A resistor R and a capacitor C are connected to each of the first to third input terminals (INA to INC) for receiving signals, as shown in FIG.

[0030] Referring to FIG. 3, the first to third input signals (A to C) have different signal levels for each unit interval.

[0031] Specifically, the first to third input signals (A to C) each have one of the signal levels of 3 / 4V, 1 / 2V, and 1 / 4V.

[0032] For example, in unit interval UI1, the first input signal A has a signal level of 1 / 4 V, the second input signal B has a signal level of 3 / 4 V, and the third input signal C has a signal level of 1 / 2 V. That is, the first to third input signals (A to C) do not have the same signal level in each unit interval (UI1 to UI5), but rather have different signal levels.

[0033] Meanwhile, when at least two of the first to third input signals (A to C) are changed in a unit interval (UI1 to UI5), their signal levels are changed. When the first to third input signals (A to C) have different signal levels in their respective unit intervals (UI1 to UI5), if the unit interval (UI1 to UI5) is changed, the first to third input signals (A to C) will have different signal levels in their respective unit intervals (UI1 to UI5) only if the signal level of one input signal is changed and the signal level of at least one other input signal is changed. Therefore, when the unit interval (UI1 to UI5) is changed, the signal levels of at least two of the first to third input signals (A to C) are changed.

[0034] In some embodiments, the first to third input signals (A to C) have a signal level of any one of 3 / 4V, 1 / 2V, and 1 / 4V, for example, because the first to third input signals (A to C) are signals provided by a MIPI C-PHY interface.

[0035] Referring again to FIG. 2, the transition detection apparatus 100 includes continuous time linear equalizers (CTLE1 to CTLE3), differential amplifiers (DA1 to DA3), and digitally controlled variable gain amplifiers (DCVGA1 to DCVGA6).

[0036] The first digitally controlled variable gain amplifier DCVGA1 amplifies the first differential signal AB in response to the gain control signal GCS1 and outputs the first comparison input signal +(AB) without phase change. The first level detector LD1 compares the signal level of the first comparison input signal +(AB) with a first reference signal level Vth to output a first comparison signal PAB.

[0037] The second digitally controlled variable gain amplifier DCVGA2 amplifies the first differential signal AB in response to the gain control signal GCS2, inverts its phase, and outputs the result as a second comparison input signal −(AB).The second level detector LD2 compares the signal level of the second comparison input signal −(AB) with the first reference signal level Vth to determine whether it is greater than the first reference signal level Vth, and outputs a second comparison signal NAB.

[0038] Here, as described above, when the first reference signal level Vth and the second reference signal level −Vth have a relationship in which their absolute values ​​are the same but their phases are opposite, the second comparison input signal −(AB) has the opposite phase to the first comparison input signal +(AB), so the actual operation of the second level detector LD2 is to compare whether the signal level of the first differential signal AB is greater than the second reference signal level −Vth (i.e., whether it has a value smaller than −Vth).

[0039] That is, the actual operation of the second level detector LD2 differs from the operation of the first level detector LD1 in that it compares the signal level of the first differential signal AB with the second reference signal level −Vth and outputs the second comparison signal NAB. However, by configuring the circuit as shown in the drawing, the first level detector LD1 and the second level detector LD2 can perform the same operation as each other and achieve their purpose.

[0040] The third digitally controlled variable gain amplifier DCVGA3 amplifies the second differential signal BA in accordance with the gain control signal GCS3 and outputs the amplified signal as a third comparison input signal+(BC) with no phase change. The third level detector LD3 compares the signal level of the third comparison input signal+(BC) with the first reference signal level Vth to output a third comparison signal PBC.

[0041] The fourth digitally controlled variable gain amplifier DCVGA4 amplifies the second differential signal BC in response to the gain control signal GCS4, inverts its phase, and outputs it as a fourth comparison input signal −(BC). The fourth level detector LD4 compares whether the signal level of the fourth comparison input signal −(BC) is greater than the first reference signal level Vth and outputs a fourth comparison signal NBC. Again, the actual operation of the fourth level detector LD4 is to compare whether the signal level of the second differential signal BC is greater than the second reference signal level −Vth (i.e., whether it has a value less than −Vth). However, by configuring the circuit as shown in the drawing, the third level detector LD3 and the fourth level detector LD4 can perform the same operation and achieve their purpose.

[0042] The fifth digitally controlled variable gain amplifier DCVGA5 amplifies the third differential signal CA in response to the gain control signal GCS5 and outputs the fifth comparison input signal+(CA) without phase change. The fifth level detector LD5 compares whether the signal level of the fifth comparison input signal+(CA) is greater than the first reference signal level Vth and outputs a fifth comparison signal PCA.

[0043] The sixth digitally controlled variable gain amplifier DCVGA6 amplifies the third differential signal CA in response to a gain control signal GCS6, inverts its phase, and outputs it as a sixth comparison input signal −(CA). The sixth level detector LD6 compares whether the signal level of the sixth comparison input signal −(CA) is greater than the first reference signal level Vth, and outputs a sixth comparison signal NCA. Again, the actual operation of the sixth level detector LD6 is to compare whether the signal level of the third differential signal CA is greater than the second reference signal level −Vth (i.e., whether it has a value less than −Vth). However, by configuring the circuit as shown in the drawing, the fifth level detector LD5 and the sixth level detector LD6 can perform the same operation and achieve their purpose.

[0044] 2, the transition detection device 100 includes a comparator COMP that compares a first input signal A with a second input signal B and outputs a comparison result, and a frequency divider DIV that divides the frequency of the comparison signal output from the comparator COMP. The frequency-divided signal output from the frequency divider DIV is provided to the calibration device (300 in FIG. 1) as a reference clock signal RCK.

[0045] Although the drawings show a comparator COMP that compares a first input signal A with a second input signal B and outputs a comparison result, embodiments of the present invention are not limited to this. In some embodiments, the comparator COMP may be modified to compare a second input signal B with a third input signal C and output a comparison result, or to compare a third input signal C with the first input signal A and output a comparison result.

[0046] 4, the first level detector LD1 includes a plurality of transistors (MP1 to MP5, MN1 to MN4) for detecting the level of a provided signal. Although the drawing shows only an exemplary circuit diagram of the first level detector LD1, the other level detectors (LD2 to LD6) may employ the same or similar circuits.

[0047] The first level detector LD1 has an input terminal IN provided with the first comparison input signal (+(AB) in FIG. 2) and an output terminal OUT from which a first comparison signal PAB is output.

[0048] The transistor MP1 is gated to the ground voltage and provides the power supply voltage VDD to the output node ON. If the transistor MP1 is a PMOS transistor, the power supply voltage VDD is always provided to the output node ON.

[0049] The transistor MP4 is gated by the voltage level of the input terminal IN to provide the power supply voltage VDD to the output node OP, so that the voltage level of the output node OP varies depending on the voltage level of the first comparison input signal (+(AB) in FIG. 2).

[0050] The transistors MP5 and MN4 invert the voltage level of the output node OP and provide it to the output terminal OUT, that is, the transistors MP5 and MN4 form an inverter.

[0051] The transistors (MP2, MP3, MN1, MN2, MN3) amplify the voltage level difference between the output nodes OP and ON in response to a first comparison input signal (+(AB) in FIG. 2) provided to the input terminal IN. Specifically, when the voltage level (or signal level, hereinafter referred to as voltage level) of the first comparison input signal (+(AB) in FIG. 2) is greater than the threshold voltage Vth of the transistor MN3, the transistor MN3 is turned on, amplifying the voltage level difference between the output nodes OP and ON. Conversely, when the voltage level of the first comparison input signal (+(AB) in FIG. 2) is less than the threshold voltage Vth of the transistor MN3, the transistor MN3 is not turned on, and the output nodes OP and ON maintain substantially similar voltage levels. Therefore, the voltage level difference between the output nodes OP and ON is not amplified.

[0052] In some embodiments, the threshold voltage Vth that turns on transistor MN3 is the first reference signal level Vth and the second reference signal level −Vth that the transition detection circuit (100 in FIG. 1) compares with the first to third input signals (A, B, C). That is, as the threshold voltage Vth of transistor MN3 increases, the first reference signal level Vth and the second reference signal level −Vth that the transition detection circuit (100 in FIG. 1) compares with the first to third input signals (A, B, C) also increase, and as the threshold voltage Vth of transistor MN3 decreases, the first reference signal level Vth and the second reference signal level −Vth that the transition detection circuit (100 in FIG. 1) compares with the first to third input signals (A, B, C) also decrease.

[0053] The transistor MP2 is gated to the voltage level of the output node OP to provide the power supply voltage VDD to the output node ON, and the transistor MP3 is gated to the voltage level of the output node ON to provide the power supply voltage VDD to the output node OP.

[0054] Transistor MN1 is gated to the voltage level of output node OP to connect output node ON to transistor MN3, and transistor MN2 is gated to the voltage level of output node ON to connect output node OP to transistor MN3. When the voltage level of the first comparison input signal (+(AB) in FIG. 2) becomes greater than the threshold voltage Vth of transistor MN3, transistor MN3 is turned on and output nodes OP and ON are grounded.

[0055] In some embodiments, transistors MP2 and MP3 have an asymmetric structure, and transistors MN1 and MN2 have an asymmetric structure, in order to amplify the voltage level difference between output nodes OP and ON.

[0056] For example, the size of transistor MP2 is different from the size of transistor MP3, and the size of transistor MN1 is different from the size of transistor MN2. Specifically, in some embodiments, if the size of transistor MP3 is 1, the size of transistor MP2 is M (M is a natural number greater than 1), and if the size of transistor MN1 is 1, the size of transistor MN2 is N (N is a natural number greater than 1).

[0057] For example, the number of transistors MP2 and MP3 may be different, and the number of transistors MN1 and MN2 may be different. Specifically, in some embodiments, if the number of transistors MP3 is 1, the number of transistors MP2 is M, and if the number of transistors MN1 is 1, the number of transistors MN2 is N.

[0058] Also, in some embodiments, transistors MP2 and MP3 are asymmetrical in both size and number, and transistors MN1 and MN2 are asymmetrical in both size and number.

[0059] Next, an exemplary circuit of a clock data recovery device will be described with reference to FIGS.

[0060] 1 and 5, the clock data recovery device 200 includes a plurality of pulse generators (PG1 to PG6), a plurality of OR gates (OR1 to OR9), and a plurality of SR latches (NOR1 to NOR6).

[0061] The OR gates (OR7, OR8, OR9) form a clock recovery path, and the OR gates (OR1 to OR6) and the SR latches (NOR1 to NOR6) form a data recovery path.

[0062] The plurality of pulse generators (PG1 to PG6) receive the first to sixth comparison signals (PAB, NAB, PBC, NBC, PCA, and NCA), respectively, and generate short pulses. Here, the rising edges of the short pulses generated by the pulse generators (PG1 to PG6) correspond to the rising edges of the first to sixth comparison signals (PAB, NAB, PBC, NBC, PCA, and NCA). That is, when the rising edges of the first to sixth comparison signals (PAB, NAB, PBC, NBC, PCA, and NCA) are generated, the rising edges of the pulse generators (PG1 to PG6) are also generated.

[0063] As described above, the rising edges of the first to sixth comparison signals (PAB, NAB, PBC, NBC, PCA, NCA) are generated at the time when the first to third differential signals (AB, BC, CA) become greater than the first reference signal level Vth or the second reference signal level −Vth in accordance with the operations of the first to sixth level detectors (LD1 to LD6 in FIG. 2 ), and therefore the rising edges of the short pulses generated by the pulse generators (PG1 to PG6) are also generated at the time when the first to third differential signals (AB, BC, CA) become greater than the first reference signal level Vth or the second reference signal level −Vth.

[0064] The OR gate OR1 performs an OR operation on the short pulses generated by the pulse generators (PG1, PG4, PG6), and the OR gate OR2 performs an OR operation on the short pulses generated by the pulse generators (PG2, PG3, PG5). The operation results of the OR gates OR1 and OR2 are input to an SR latch consisting of NOR gates (NOR1, NOR2) and are output as the Wire State Bit (WSB1) of the first input signal (A in Figure 1).

[0065] The OR gate OR3 performs an OR operation on the short pulses generated by the pulse generators (PG2, PG3, PG6), and the OR gate OR4 performs an OR operation on the short pulses generated by the pulse generators (PG1, PG4, PG5). The operation results of the OR gates OR3 and OR4 are input to an SR latch consisting of NOR gates (NOR3, NOR4) and are output as the wire state bit WSB2 of the second input signal (B in Figure 1).

[0066] The OR gate OR5 performs an OR operation on the short pulses generated by the pulse generators (PG2, PG4, PG5), and the OR gate OR6 performs an OR operation on the short pulses generated by the pulse generators (PG1, PG3, PG6). The operation results of the OR gates OR5 and OR6 are input to an SR latch consisting of NOR gates (NOR5, NOR6) and are output as the wire state bit WSB3 of the third input signal (C in Figure 1).

[0067] The wire status information WSI shown in FIG. 1 is made up of such wire status bits (WSB1 to WSB3).

[0068] Meanwhile, OR gate OR7 ORs the short pulses generated by pulse generators PG1, PG2, and PG3, and OR gate OR8 ORs the short pulses generated by pulse generators PG4, PG5, and PG6. OR gate OR9 ORs the outputs of OR gate OR7 and OR gate OR8. The output of OR gate OR9 is provided to, for example, a test driver (500 in FIG. 1) in the form of a recovered clock signal RECK.

[0069] When examining the structure of such a clock recovery path, the recovered clock signal RECK is generated so that its rising edge corresponds to the earliest rising edge among the first to sixth comparison signals (PAB, NAB, PBC, NBC, PCA, NCA). When only one of the first to sixth comparison signals (PAB, NAB, PBC, NBC, PCA, NCA) has a rising edge in one unit period, the rising edge of the recovered clock signal RECK is formed to correspond to the rising edge of the comparison signal having a rising edge among the first to sixth comparison signals (PAB, NAB, PBC, NBC, PCA, NCA).

[0070] Next, an exemplary configuration of the calibration device will be described with reference to FIGS.

[0071] 1 and 6, the calibration device 300 includes a counter 310 that counts first to sixth comparison signals (PAB, NAB, PBC, NBC, PCA, NCA), and a calibration logic 320 that provides control signals (EN, Reset) to the counter 310 and adjusts gain control signals (GCS1 to GCS6) using the counting result CR output by the counter 310.

[0072] In some embodiments, counter 310 is located in an analog circuit block of the signal receiving device and calibration logic 320 is located in a digital logic block of the signal receiving device, although embodiments are not limited thereto.

[0073] The counter 310 counts the first through sixth comparison signals (PAB, NAB, PBC, NBC, PCA, and NCA) and outputs a counting result CR based on the counted signals. In some embodiments, the counter 310 counts the number of signals among the first through sixth comparison signals (PAB, NAB, PBC, NBC, PCA, and NCA) that are at a high logic level and outputs the counting result CR based on the counted signals. Specifically, the counter 310 outputs a counting result CR of a first level (e.g., a low level) when the number of signals among the first through sixth comparison signals (PAB, NAB, PBC, NBC, PCA, and NCA) that are at a high logic level is less than six, and outputs a counting result CR of a second level (e.g., a high level) when the number of signals among the first through sixth comparison signals (PAB, NAB, PBC, NBC, PCA, and NCA) that are at a high logic level is six or more, but the embodiment is not limited thereto.

[0074] The calibration logic 320 provides an enable signal EN to the counter 310 to enable the counter 310, and provides a reset signal Reset to reset the counter 310. The calibration logic 320 then adjusts the gain control signals (GCS1 to GCS6) based on the counting result CR.

[0075] In some embodiments, the calibration logic 320 increases the magnitude of the gain control signals (GCS1 to GCS6) while a counting result CR of a first level (e.g., low level) is provided, thereby gradually amplifying the magnitude of the first to third differential signals (AB, BC, CA), and when a counting result CR of a second level (e.g., high level) is provided, the calibration logic 320 maintains the magnitude of the gain control signals (GCS1 to GCS6) and stops amplifying the magnitude of the first to third differential signals (AB, BC, CA). This will be described in more detail below.

[0076] Hereinafter, the clock recovery method and data recovery method of the signal receiving device described above will be described with reference to FIGS.

[0077] 7 to 11 are diagrams for explaining a clock recovery method and a data recovery method of a signal receiving device according to an embodiment.

[0078] Referring to FIG. 7, when the first to third input signals (A to C) provided via the MIPI C-PHY interface have different signal levels for each unit section as shown in FIG. 3, the first to third differential signals (AB, BC, CA) have signal levels as shown in FIG. 7.

[0079] For example, if a differential signal having a magnitude of 1 / 2V or 1 / 2V is defined as a strong signal, and a differential signal having a magnitude of 1 / 4V or 1 / 4V is defined as a weak signal, the first to third differential signals (AB, BC, CA) are composed of one strong signal and two weak signals per unit section.

[0080] For example, referring to Figure 7, when the wire state is +x, the first differential signal AB is 1 / 2V and is therefore a strong signal, and the second and third differential signals (BC, CA) are -1 / 4V and are therefore weak-weak signals. Also, when the wire state is -y, the second differential signal BC is -1 / 2V and is therefore a strong signal, and the first and third differential signals (AB, CA) are +1 / 4V and are therefore weak-weak signals. In this way, the first to third differential signals (AB, BC, CA) are always composed of one strong signal and two weak signals per unit interval.

[0081] Therefore, as shown in Figure 8, when the first reference signal level +Vth is set to a value between the strong signal value (+1 / 2V) and the weak signal value (+1 / 4V), and the second reference signal level -Vth is set to a value between the strong signal value (-1 / 2V) and the weak signal value (-1 / 4V), the magnitude of only one differential signal per unit interval (UI11 to UI18) is greater than the first reference signal level +Vth and the second reference signal level -Vth, and the magnitudes of the remaining two differential signals are smaller than the first reference signal level +Vth and the second reference signal level -Vth.

[0082] That is, in each unit interval (UI11 to UI18), a transition occurs in which only one of the first to third differential signals (AB, BC, CA) becomes greater than the first reference signal level +Vth and the second reference signal level -Vth. When using this characteristic to restore the clock signal embedded in the first to third input signals (A to C), there is no need to consider the jitter characteristics of the received signal, because only one transition occurs in each unit interval (UI11 to UI18).

[0083] If the reference signal level is set differently and two or more transitions occur per unit interval (UI11 to UI18), the jitter characteristics due to the different transition timings must be taken into consideration in order to recover the clock signals embedded in the first to third input signals (A to C) from these transitions, which requires additional circuits (e.g., delay circuits, signal masking circuits, etc.) to adjust the jitter characteristics.

[0084] However, in the signal receiving device according to this embodiment, since multiple transitions with respect to the reference signal level do not occur, there is no need to consider the jitter characteristics of the received signal when restoring the clock signals embedded in the first to third input signals (A to C), and no additional circuitry is required to adjust the jitter characteristics, which allows the signal receiving device to be made smaller.

[0085] Hereinafter, the operation of the signal receiving device in the unit interval UI11 of FIG. 8 will be described with reference to FIGS.

[0086] 7 and 8, the wire state is +y in unit section UI11, so the first input signal A has a magnitude of 1 / 2V (to be precise, the signal swings to have a magnitude of 1 / 2V, but for ease of explanation, only the maximum value is mentioned), the second input signal B has a magnitude of 3 / 4V, and the third input signal C has a magnitude of 1 / 4V.

[0087] In response to these first to third input signals (A to C), the first differential signal AB has a magnitude of -1 / 4V (to be precise, the signal swings to have a magnitude of 1 / 2V, but for convenience of explanation, only the maximum value will be mentioned), the second differential signal BC has a magnitude of +1 / 2V, and the third differential signal CA has a magnitude of -1 / 4V.

[0088] Referring to FIG. 9, a first digitally controlled variable gain amplifier DCVGA1 provides a first differential signal AB having a magnitude of -1 / 4V to a first level detector LD1, and a second digitally controlled variable gain amplifier DCVGA2 changes the phase of the first differential signal AB having a magnitude of -1 / 4V and provides a signal having a magnitude of 1 / 4V to a second level detector LD2.

[0089] The third digitally controlled variable gain amplifier DCVGA3 provides a second differential signal BC having a magnitude of 1 / 2V to the third level detector LD3, and the fourth digitally controlled variable gain amplifier DCVGA4 changes the phase of the second differential signal BC having a magnitude of 1 / 2V and provides a signal having a magnitude of -1 / 2V to the fourth level detector LD4.

[0090] The fifth digitally controlled variable gain amplifier (DCVGA5) provides a third differential signal CA having a magnitude of -1 / 4V to the fifth level detector LD5, and the sixth digitally controlled variable gain amplifier DCVGA6 changes the phase of the third differential signal CA having a magnitude of -1 / 4V and provides a signal having a magnitude of 1 / 4V to the sixth level detector LD6.

[0091] 4, 9, and 10, a signal that does not reach the threshold voltage Vth of transistor MN3 is provided to the input terminal IN of the first and second level detectors (LD1-LD2) and the fifth and sixth level detectors (LD5-LD6). Therefore, transistor MN3 is not turned on, and the voltage level difference between the output nodes (ON, OP) is not amplified. Therefore, no rising edges are generated in the first and second comparison signals (PAB, NAB) and the fifth and sixth comparison signals (PCA, NCA) output by the first and second level detectors (LD1-LD2) and the fifth and sixth level detectors (LD5-LD6).

[0092] 4, 9, and 11, a signal greater than the threshold voltage Vth of transistor MN3 is applied to input terminal IN of third and fourth level detectors LD3-LD4. Therefore, transistor MN3 is turned on at time T1 when the magnitude of the signal applied to input terminal IN exceeds the threshold voltage Vth of transistor MN3.

[0093] When transistor MN3 is turned on, the voltage level of output node OP drops due to the asymmetrical structure between transistors MP2 and MP3 and the asymmetrical structure between transistors MN1 and MN2. Conversely, the voltage level of output node ON remains constant. Therefore, the voltage difference between the output nodes ON and OP is amplified, and a rising edge is generated by the inverter in the signal output to output terminal OUT. That is, a rising edge is generated in the third and fourth comparison signals PBC and NBC output from the third and fourth level detectors LD3 and LD4. Then, at time T2, when the magnitude of the signal provided to input terminal IN falls below the threshold voltage Vth of transistor MN3, transistor MN3 is turned off, and a falling edge is generated in the signal output to output terminal OUT.

[0094] The first and second comparison signals (PAB, NAB) and the fifth and sixth comparison signals (PCA, NCA) in which no rising edge is generated, and the third and fourth comparison signals (PBC, NBC) in which a rising edge is generated are input to the clock data recovery device 200 shown in FIG. 5 and used to generate wire status bits (WSB1 to WSB3) and a recovered clock signal RECK.

[0095] Specifically, the clock data recovery device 200 generates predetermined short pulses from the first and second comparison signals (PAB, NAB) and the fifth and sixth comparison signals (PCA, NCA) in which no rising edge is generated and the third and fourth comparison signals (PBC, NBC) in which a rising edge is generated, and uses the generated short pulses to generate a status bit WSB1 having a value of 0, a status bit WSB2 having a value of 1, a status bit WSB3 having a value of 0, and a recovered clock signal RECK having a rising edge corresponding to the rising edge of the third comparison signal PBC, as shown in FIG. 8.

[0096] The operation of the signal receiving device in other unit sections (UI12 to UI18) of Figure 8 that have not been described can also be easily inferred by a person with ordinary knowledge in this technical field from the above description, so duplicated description will be omitted.

[0097] Hereinafter, the calibration method of the above-mentioned signal receiving device will be described with reference to FIG.

[0098] Referring to FIG. 12, the first to third input signals (A to C) include a preamble section, a sync-word section, a packet data section, and a post section.

[0099] The preamble section is composed of multiple groups each containing seven consecutive "3" symbols, and during the six unit sections, the first to third differential signals (AB, BC, CA) have the same pattern of weak high, strong high, weak high, weak low, weak low, strong low, weak low.

[0100] The calibration device (300 in FIG. 6) according to this embodiment performs calibration to adjust the gain control signals (GCS1 to GCS6 in FIG. 6) in the preamble section.

[0101] Specifically, the gain control signals (GCS1 to GCS6 in FIG. 6) are adjusted to continuously amplify the magnitudes of the first to third differential signals (AB, BC, CA) over a plurality of periods (S1 to S6), and the gain control signals (GCS1 to GCS6 in FIG. 6) are adjusted until the amplified first to third differential signals (AB, BC, CA) all become greater than the first reference signal level Vth and / or the second reference signal level −Vth. This operation is performed, for example, by counting the first to sixth comparison signals (PAB, NAB, PBC, NBC, PCA, NCA) as described above.

[0102] If the gains of the digitally controlled variable gain amplifiers (DCVGA1 to DCVGA6) are not adjusted in response to environmental changes such as operating temperature, a transition may not be detected even if a strong signal is generated because the magnitude of the strong signal does not reach the first and second reference signal levels (+Vth, -Vth). Therefore, in the signal receiving device according to this embodiment, calibration is performed taking environmental changes into consideration before the clock data recovery operation is fully performed, thereby ensuring reliability through transition detection.

[0103] Hereinafter, with reference to FIGS. 13 and 14, a signal receiving system according to several embodiments employing such a signal receiving device will be described.

[0104] FIG. 13 is a conceptual block diagram of an example of a signal receiving system according to one embodiment.

[0105] Referring to FIG. 13, the signal receiving system includes an application processor 1000 and a display driver IC 1100.

[0106] The application processor 1000 generates image display data IDD to be displayed to a user, etc., and provides this to the display driver IC 1100.

[0107] Specifically, the application processor 1000 includes a transmitter (Tx) 1010 for transmitting image display data IDD, and provides the image display data IDD to the display driver IC 1100 via the transmitter 1010 .

[0108] The display driver IC 1100 includes a receiver (Rx) 1110 for receiving image display data IDD, and receives the image display data IDD from the application processor 1000 through the receiver 1110 .

[0109] In some embodiments, a MIPI C-PHY interface is employed between the transmitter 1010 and the receiver 1110, and the receiver 1110 includes the signal receiving device described above.

[0110] FIG. 14 is a conceptual block diagram of another example of a signal receiving system according to one embodiment.

[0111] Referring to FIG. 14, the signal receiving system includes an image sensor 2000 and an application processor 2100.

[0112] The image sensor 2000 senses an image using, for example, a camera module, and then generates image sensing data ISD based on the sensed image. The generated image sensing data ISD is provided to the application processor 2100.

[0113] Specifically, the image sensor 2000 includes a transmitter (Tx) 2010 that transmits image sensing data ISD, and provides the image sensing data ISD to the application processor 2100 via the transmitter 2010 .

[0114] The application processor 2100 includes a receiver (Rx) 2110 for receiving image sensing data ISD, and receives the image sensing data ISD from the image sensor 2000 via the receiver 2110.

[0115] In some embodiments, a MIPI C-PHY interface is employed between such a transmitter 2010 and a receiver 2110, and the receiver 2110 includes the signal receiving device described above.

[0116] As described above, the calibration device 300 and the counter 310 included in the calibration device 300 are arranged in the analog circuit block of the signal receiving device, and the calibration device 300 and the calibration logic 320 of the decoder 400 are arranged in the digital logic block of the signal receiving device.

[0117] The analog circuit blocks and digital logic blocks may be implemented with special-purpose processing circuitry. For example, the analog circuit blocks may be implemented with a field-programmable analog array (FPAA) or other analog circuitry, and the digital logic blocks may be implemented with logic circuitry, a hardware / software combination such as a software-executed processor, or a combination thereof and memory. For example, more specifically, the processing circuitry may include a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), etc.

[0118] The processing circuit is a special-purpose processing circuit that recovers data and clock from a received signal without considering the jitter characteristics of the received signal and calibrates a signal receiving device. Thus, the special-purpose processing circuit can recover data and clock from a received signal without requiring additional circuitry to reflect the jitter characteristics of the received signal, thereby enabling a reduction in size.

[0119] Although the embodiments of the present invention have been described in detail above with reference to the drawings, the present invention is not limited to the above-described embodiments and can be modified in various ways without departing from the technical concept of the present invention. [Explanation of symbols]

[0120] 100 Transition detection device 200 Clock Data Recovery Device 300 Calibration Device 310 Counter 320 Calibration Logic 400 decoder 500 Demapper 1000, 2100 Application Processor 1010, 2010 Transmitter (Tx) 1100 Display driver IC 1110, 2110 Receiver (Rx) 2000 image sensors A, B, C 1st to 3rd input signals COMP comparator CTLE1~CTLE3 Continuous-time linear equalizers CR counting results DA1~DA3 Differential amplifier DCVGA1~DCVGA6 1st to 6th digitally controlled variable gain amplifiers DIV divider GCS1~GCS6 Gain control signals INA, INB, INC 1st to 3rd input terminals LD1~LD6 1st to 6th level detectors NOR1 to NOR6 SR latch ON, OP output node OR1~OR9 OR gates PAB, NAB, PBC, NBC, PCA, NCA 1st to 6th comparison signals PG1~PG6 Pulse Generator RCK Reference clock signal RECK Recovered clock signal WSB1~WSB3 Wire Status Bits WSI Wire Status Information

Claims

1. a transition detection device that receives first to third input signals having different signal levels for each unit section, compares output signal levels of first to third differential signals, which are differential signals between the first to third input signals and which are different from each other, with a first reference signal level, and compares inverted output signal levels of the first to third differential signals with a second reference level corresponding to an inverted signal level of the first reference signal level, to output a plurality of comparison signals, which are first to sixth comparison signals; a clock data recovery device that recovers the clock signal embedded in the first to third input signals based on the plurality of comparison signals to generate a recovered clock signal; the first to third differential signals are each composed of one strong signal having a large differential signal value and two weak signals having a differential signal value smaller than that of the strong signal for each unit section; A signal receiving device, characterized in that a second reference signal level corresponding to the first reference signal level and the inverted signal level is set to a value between the value of the strong signal and the value of the weak signal.

2. 2. The signal receiving device of claim 1, wherein the first to third input signals are signals provided by a Mobile Industry Processor Interface (MIPI) C-PHY interface.

3. the absolute values ​​of the first reference signal level and the second reference signal level are the same; 2. The signal receiving device according to claim 1, wherein the first reference signal level and the second reference signal level have opposite polarities.

4. The transition detection device includes the plurality of comparison signals: comparing an output signal level of the first differential signal, which is a differential signal between the first input signal and the second input signal, with the first reference signal level to output the first comparison signal; comparing an inverted output signal level of the first differential signal with the second reference signal level to output the second comparison signal; comparing an output signal level of the second differential signal, which is a differential signal between the second input signal and the third input signal, with the first reference signal level to output the third comparison signal; and comparing an inverted output signal level of the second differential signal with the second reference signal level to output the fourth comparison signal; 2. The signal receiving device according to claim 1, wherein an output signal level of the third differential signal, which is a differential signal between the third input signal and the first input signal, is compared with the first reference signal level to output the fifth comparison signal, and an inverted output signal level of the third differential signal is compared with the second reference signal level to output the sixth comparison signal.

5. 5. The signal receiving device according to claim 4, further comprising a calibration device that counts each of the first to sixth comparison signals and adjusts first to sixth gain control signals used to amplify each of the output signals and inverted output signals of the first to third differential signals.

6. the unit interval includes a first unit interval, In the first unit period, the first input signal has a first signal level, the second input signal has a second signal level different from the first signal level, and the third input signal has a third signal level different from the first and second signal levels; 2. The signal receiving device according to claim 1, wherein the first reference signal level is set to one of a value between the first signal level and the second signal level and a value between the second signal level and the third signal level.

7. the second signal level is lower than the first signal level; the third signal level is lower than the second signal level; 7. The signal receiving device according to claim 6, wherein the first reference signal level is set to a value between the second signal level and the third signal level.

8. The transition detection device includes: first, third, and fifth variable gain amplifiers that amplify the output signal levels of the first to third differential signals based on first, third, and fifth gain control signals, respectively; and second, fourth, and sixth variable gain amplifiers that amplify inverted output signal levels of the first to third differential signals based on second, fourth, and sixth gain control signals, respectively.

9. The transition detection device includes: first, third, and fifth level detectors for outputting the first, third, and fifth comparison signals in response to the outputs of the first, third, and fifth variable gain amplifiers being greater than the first reference signal level; 9. The signal receiving device according to claim 8, further comprising second, fourth, and sixth level detectors that output the second, fourth, and sixth comparison signals in response to the outputs of the second, fourth, and sixth variable gain amplifiers being greater than the second reference signal level.

10. 9. The signal receiving device according to claim 8, further comprising a calibration device that adjusts the first to sixth gain control signals based on the first to sixth comparison signals.

11. the transition detection device generates a reference clock signal based on the first to third input signals provided; 11. The signal receiving device according to claim 10, wherein the calibration device adjusts the first to sixth gain control signals based on the reference clock signal and the first to sixth comparison signals.

12. The first level detector comprises: a first transistor having a gate receiving an output of the first variable gain amplifier and grounding a first output node and a second output node; a second transistor having a gate receiving a voltage level of the first output node and providing a power supply voltage to the second output node; a third transistor having a gate receiving a voltage level of the second output node and providing the power supply voltage to the first output node; a fourth transistor having a gate for receiving the voltage level of the first output node and connecting the second output node to the first transistor; 10. The signal receiving device according to claim 9, further comprising a fifth transistor having a gate receiving a voltage level of the second output node and connecting the first output node to the first transistor.

13. 13. The signal receiving device according to claim 12, wherein the first reference signal level is a threshold voltage of the first transistor.

14. 13. The signal receiving device according to claim 12, wherein the fourth transistor and the fifth transistor have different sizes.

15. the first to third input signals include a preamble section, a sync word section, a packet data section, and a post section; 11. The signal receiving device of claim 10, wherein the calibration device adjusts the first to sixth gain control signals in the preamble section.

16. The clock data recovery device includes: first, third, and fifth pulse generators that generate first, third, and fifth short pulses based on the first, third, and fifth comparison signals, respectively; second, fourth, and sixth pulse generators that generate second, fourth, and sixth short pulses based on the second, fourth, and sixth comparison signals, respectively; first to third SR latches for outputting wire state information of the first to third input signals based on the first to sixth short pulses; 10. The signal receiving device according to claim 9, further comprising a plurality of OR gates that output the recovered clock signal based on the first to sixth short pulses.

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