Design condition calculation system and semiconductor device manufacturing method

Abstract

To provide an appropriate design value for a power device quickly and at low costs.SOLUTION: A design condition calculation system comprises an optimization calculation unit for calculating a first parameter and a second parameter so as to satisfy a predetermined condition using models constructed by a model construction unit. Of the models constructed by the model construction unit, a first conversion model provided at a front stage converts at least either of the first and second parameters to a physical property value to be input to a characteristic regression model, the characteristic regression model is provided at the middle stage and converts an unobservable physical property value to an unobservable theoretical characteristic value, and a second conversion model provided at a rear stage converts the theoretical characteristic value to an actual characteristic value. The optimization calculation unit uses the constructed models and takes fixed values set at parts of the first and second parameters as a constraint condition to calculate the first and second parameters which are not the constraint condition so as to satisfy a condition based on one or a combination of a value and a range of a third parameter.SELECTED DRAWING: Figure 1B-1

Description

[Technical Field]

[0001] The present invention relates to a design condition calculation system for supporting the design of semiconductor devices, and more particularly to a technology for supporting the design of manufacturing parameters for power semiconductor devices. [Background technology]

[0002] Power semiconductor devices require high breakdown voltage, low on-resistance, and low switching loss, but silicon (Si) power elements, which are currently the mainstream, are approaching their theoretical performance limits. Silicon carbide (SiC) has a dielectric breakdown field strength approximately one order of magnitude greater than that of Si. Therefore, by making the drift layer that maintains the breakdown voltage approximately one-tenth thinner and increasing the impurity concentration by approximately 100 times, it is theoretically possible to reduce element resistance by more than three orders of magnitude. Furthermore, because the band gap is approximately three times larger than that of Si, high-temperature operation is also possible. As such, SiC semiconductor elements are expected to exceed the performance of Si semiconductor devices, and development of SiC power semiconductor devices is underway.

[0003] The following prior art exists as background art in this technical field: Patent Document 1 (JP 2020-184123 A) describes a circuit design device that includes an operation unit and a storage unit for inputting the circuit configuration of a circuit to be designed, the names of circuit characteristic items of the circuit to be designed, and the names of elements that constitute the circuit to be designed, a simulation unit that generates element values ​​of each circuit element and corresponding characteristic values ​​of each circuit characteristic item by simulating the circuit to be designed while changing the element values ​​of each circuit element, and a design processing unit that performs deep learning using the element values ​​of the circuit elements and the characteristic values ​​of the corresponding circuit characteristic items in a learning mode, and generates at least one of element values ​​corresponding to the characteristic values ​​and characteristic values ​​corresponding to the element values ​​through regression analysis in a design mode.

[0004] Patent Document 2 (JP 2012-150574 A) describes a simulation linking method including a semiconductor device equivalent circuit model setting step of obtaining device characteristics from the output of a semiconductor device simulation, at least device characteristics required for a semiconductor device equivalent circuit model used in circuit simulation, in order to perform simulation linking, and an information feedback step provided with a knowledge database for evaluating the output of the circuit simulation and, if there is a problem with the performance as a product, estimating information for optimizing at least the semiconductor device structure from the output of the circuit simulation and feeding it back to the semiconductor device simulation. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Publication No. 2020-184123 [Patent Document 2] Japanese Patent Application Laid-Open No. 2012-150574 Summary of the Invention [Problem to be solved by the invention]

[0006] To control large amounts of power, power semiconductor devices must satisfy many performance requirements, including on-resistance, short-circuit time, threshold voltage, breakdown voltage, switching loss, and dielectric film reliability. Many of these parameters are in a trade-off relationship, and a design that is appropriate for the application in which they are used must be sought within that trade-off. Furthermore, in recent years, device structures, processes, and circuit structures have become more complex, resulting in a large number of parameters being involved in the design. Therefore, it is necessary to optimize the design, materials, and fabrication conditions of the device, as well as the system, in an integrated manner, taking into account the characteristics of the semiconductor device and the application in which the semiconductor device is used, such as on-resistance, short-circuit time, threshold voltage, breakdown voltage, switching loss, and dielectric film reliability. Establishing such an optimization system requires the creation of highly accurate regression models of the device and circuit through simulation.

[0007] On the other hand, the power semiconductor devices targeted by this invention cannot predict their characteristics with high accuracy using existing simulations alone. This is because, while a large amount of data has been accumulated for Si, making it possible to predict physical properties by manual calculation, SiC has a short history, making it difficult to predict physical properties such as scattering cross section and mobility. In addition, because simulations used in regression models calculate relationships between unobservable parameters, it is necessary to build a model that can be calculated using observable data.

[0008] The present invention aims to provide, quickly and at low cost, suitable design values ​​for power devices that satisfy many characteristics required for applications, even for SiC semiconductor devices. [Means for solving the problem]

[0009] A representative example of the invention disclosed in the present application is as follows: That is, a design condition calculation system includes an arithmetic device that executes predetermined processing, an input unit to which data is input, and a storage device accessible by the arithmetic device, wherein the input unit receives inputs of a first parameter representing at least one of a material, a manufacturing process, and a design of a semiconductor device, a second parameter representing at least one of a material, a manufacturing process, and a design of a circuit on which the semiconductor device is mounted, and a third parameter representing at least one characteristic of the semiconductor device and the circuit on which the semiconductor device is mounted, and the design condition calculation system includes an optimization calculation unit in which the arithmetic device calculates the first parameter and the second parameter so as to satisfy predetermined conditions using a model constructed by a model construction unit, and the models constructed by the model construction unit include a first conversion model provided in a preceding stage, a second conversion model provided in a succeeding stage, and a combination of the first conversion model and the second conversion model. the first conversion model converts at least one of the first parameter and the second parameter into a physical property value to be input to the characteristic regression model, the characteristic regression model converts an unobservable physical property value into an unobservable theoretical property value, and the second conversion model converts a theoretical property value into an actual property value; and the optimization calculation unit uses the constructed model to calculate the first parameter and the second parameter that are not a constraint condition, using fixed values ​​set for some of the first parameter and the second parameter as constraint conditions, so as to satisfy a condition defined by one or a combination of the value and range of the third parameter, and outputs the calculated first parameter and second parameter. [Effects of the Invention]

[0010] According to one aspect of the present invention, it is possible to quickly and inexpensively provide appropriate design values ​​for a power device that satisfies many characteristics required for an application. Objects, configurations, and effects other than those described above will become apparent from the following description of the embodiments. [Brief explanation of the drawings]

[0011] [Figure 1A] 1 is a diagram illustrating a configuration of a design condition calculation system according to an embodiment of the present invention. [Figure 1B-1] 1 is a flowchart of a process for calculating design conditions by the design condition calculation system according to the embodiment of the present invention. [Figure 1B-2] 1 is a flowchart of a process for calculating design conditions by the design condition calculation system according to the embodiment of the present invention. [Figure 1C-1] 1 is a flowchart of a process for calculating design conditions by the design condition calculation system according to the embodiment of the present invention. [Figure 1C-2] 1 is a flowchart of a process for calculating design conditions by the design condition calculation system according to the embodiment of the present invention. [Figure 2] FIG. 10 is a diagram illustrating an example of an input screen according to the embodiment of the present invention. [Figure 3] FIG. 2 is a diagram illustrating a configuration of a model construction unit according to an embodiment of the present invention. [Figure 4] FIG. 2 is a diagram illustrating a calculation method executed by an optimization calculation unit according to an embodiment of the present invention. [Figure 5] 1 is a flowchart of a manufacturing process of a trench MIS FET. [Figure 6A] FIG. 10 is a diagram showing an example of an input screen according to the first embodiment. [Figure 6B] FIG. 10 is a diagram showing an example of an input screen according to the first embodiment. [Figure 7] FIG. 10 is a diagram showing an example of a corrector 1 that constitutes the front stage of the model construction unit of the second embodiment. [Figure 8] FIG. 10 is a diagram showing an example of a corrector 1 that constitutes the front stage of the model construction unit of the third embodiment. [Figure 9] FIG. 10 is a diagram showing an example of a corrector 1 that constitutes the front stage of the model construction unit of the third embodiment. [Figure 10] FIG. 10 is a diagram illustrating an example of a model construction unit according to a fourth embodiment. [Figure 11] FIG. 11 is a diagram showing the cooperation between a design condition calculation system and a semiconductor manufacturing device according to a fifth embodiment. [Figure 12A] 13 is a flowchart of a process for calculating design conditions by the design condition calculation system according to the sixth embodiment. [Figure 12B] 13 is a flowchart of a process for calculating design conditions by the design condition calculation system according to the sixth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0012] Hereinafter, a design condition calculation system 100 for a power semiconductor device according to an embodiment of the present invention will be described in detail with reference to the drawings.

[0013] FIG. 1A is a diagram showing the configuration of a design condition calculation system 100. As shown in FIG.

[0014] The design condition calculation system 100 of this embodiment has a characteristic regression model constructed by simulation in the middle layer, and constructs a highly accurate regression model by a model construction unit 102 having a physical property calculation model (corrector 1) in the previous stage and a physical quantity calculation model (corrector 2) in the subsequent stage.

[0015] The design condition calculation system 100 is configured by a computer having a calculation unit 101, a data storage unit 104, a communication unit 105, an operation unit 106, an output unit 107, and an input / output unit 108. The calculation unit 101, the data storage unit 104, the communication unit 105, and the input / output unit 108 are connected via a bus.

[0016] The calculation unit 101 is a processing unit (CPU) that executes programs stored in a memory (not shown). The calculation unit 101 executes various programs to realize the functions of the various functional units (e.g., the model construction unit 102, the optimization calculation unit 103, etc.) of the design condition calculation system 100. Note that part of the processing performed by the calculation unit 101 by executing the programs may be executed by a hardware calculation device such as an ASIC or FPGA.

[0017] The memory includes a ROM, which is a non-volatile storage element, and a RAM, which is a volatile storage element. The ROM stores unchanging programs (e.g., BIOS), etc. The RAM is a high-speed, volatile storage element such as a DRAM (Dynamic Random Access Memory), and temporarily stores programs executed by the computing unit 101 and data used during program execution.

[0018] The data storage unit 104 is a large-capacity, non-volatile storage device configured, for example, by a magnetic storage device (HDD), a flash memory (SSD), etc. The data storage unit 104 also stores data used by the calculation unit 101 when executing a program, and the program executed by the calculation unit 101. That is, the program is read from the data storage unit 104, loaded into memory, and executed by the calculation unit 101, thereby realizing each function of the design condition calculation system 100.

[0019] The communication unit 105 is a network interface device that controls communication with other devices in accordance with a predetermined protocol.

[0020] The operation unit 106 is composed of input devices such as a keyboard, a mouse, and a touch panel, and provides an input interface for receiving operations from an operator. The output unit 107 is composed of output devices such as a display device and a printer, and provides an output interface for outputting the execution results of the program in a format that can be viewed by the operator. The input / output unit 108 is an interface for transferring data input to the operation unit 106 to a bus. Note that a user terminal connected to the design condition calculation system 100 via a network may provide the operation unit and the output unit. In this case, the design condition calculation system 100 may have a web server function, and the user terminal may access the design condition calculation system 100 using a predetermined protocol (for example, http).

[0021] The program executed by the calculation unit 101 is provided to the design condition calculation system 100 via a removable medium (CD-ROM, flash memory, etc.) or a network, and is stored in a non-volatile data storage unit 104, which is a non-transitory storage medium. For this reason, the design condition calculation system 100 may have an interface for reading data from removable media.

[0022] The design condition calculation system 100 is a computer system configured on one physical computer or on multiple logically or physically configured computers, and may operate on a virtual computer constructed on multiple physical computer resources. For example, the model construction unit 102 and the optimization calculation unit 103 may each operate on separate physical or logical computers, or multiple units may be combined to operate on a single physical or logical computer.

[0023] 1B-1, 1B-2, 1C-1, and 1C-2 are flowcharts of the process of calculating design conditions by the design condition calculation system 100. Figures 1B-1 and 1C-1 show the process when the model construction unit 102 is inside the design condition calculation system 100, while Figures 1B-2 and 1C-2 show the process when the model construction unit 102 is outside the design condition calculation system 100.

[0024] First, in step 1, explanatory variables and objective variables are input to the operation unit 106, and in step 2, the operation content is displayed on the output unit 107. The input explanatory variables include values ​​or value ranges of device materials, device fabrication conditions, device structure, circuit materials, circuit fabrication conditions, and circuit structure. Objective variables include values ​​or value ranges of device characteristics and circuit characteristics. Then, in step 3, the data storage unit 104 stores the input data.

[0025] Next, in step 4, the model construction unit 102 creates a regression model for the power semiconductor device and the power semiconductor device mounted circuit using the explanatory variables and the target variables based on the data stored in the data storage unit 104. In the example shown in FIGS. 1B-1 and 1C-1, the model construction unit 102 is provided in the design condition calculation system 100. The model construction unit 102 creates a regression model in accordance with the input content each time an input is made to the operation unit 106, and stores the created regression model in the data storage unit 104. The created regression model may also be directly input to the calculation unit 101 without being stored in the data storage unit 104.

[0026] Next, in step 5, the calculation unit 101 uses a regression model to calculate the relationship between the explanatory variables stored in the data storage unit 104 and the objective variables multiple times, with the values ​​of the explanatory variables stored in the data storage unit 104 as constraint conditions and the value of the objective variable as a target, to find optimal values ​​for the explanatory variables for which values ​​that satisfy the objective variable conditions are not specified. Then, in step 6, the calculation unit 101 stores the optimal values ​​of the explanatory variables and the objective variable values ​​at that time in the data storage unit 104. The processing in steps 5 and 6 is repeatedly executed until a predetermined termination condition is met. The termination condition may be that the objective variable has reached a target value, but may also be that the number of calculations or the calculation time has reached an upper limit. Then, in step 7, the output unit 107 outputs the optimal values ​​of the explanatory variables stored in the data storage unit 104 and the objective variable values ​​at that time.

[0027] In the examples shown in FIGS. 1B-2 and 1C-2, one or more regression models created in advance by a model construction unit 102 provided outside the design condition calculation system 100 are registered in a database outside the design condition calculation system 100, such as a cloud. Since regression models differ depending on the device type, it is preferable to create multiple regression models in advance and store them outside the design condition calculation system 100. In step 5, the calculation unit 101 acquires the regression models from the database via the communication unit 105 and stores them in the data storage unit 104. The calculation unit 101 uses the regression models stored in the data storage unit 104 to find optimal values ​​of explanatory variables that satisfy the conditions of the target variable. The calculation unit 101 may acquire the regression models acquired from the database directly from the database without storing them in the data storage unit 104. The design condition calculation system 100 is capable of communicating with external devices via a network.

[0028] As mentioned above, the regression model and the optimum calculation result may be stored in the data storage unit 104 after each calculation, but since the amount of data becomes enormous as the amount of calculation increases, it is not necessary to store them in the data storage unit 104 each time. On the other hand, if the regression model is obtained from the database via the communication unit 105 every time, the amount of communication increases and the speed decreases, so it is advisable to determine access to the data storage unit 104 depending on the amount of data to be handled.

[0029] FIG. 2 is a diagram showing an example of an input screen displayed on the output unit for inputting explanatory variables and objective variables into the operation unit 106 in steps 1 and 2. In FIG.

[0030] In the input screen shown in FIG. 2 , the type of explanatory variable to be specified can be selected in a pull-down input field 8 in the input section. If further narrowing of conditions is required, lower-level conditions can be specified in a pull-down input field 9 below the pull-down input field 8. The number of pull-down input fields for specifying the type of explanatory variable may be three or more. The pull-down input fields 8 and 9 preferably allow selection from the device material, device fabrication conditions, device structure, circuit material, circuit fabrication conditions, and circuit structure of the semiconductor device, as well as the device material, device fabrication conditions, device structure, circuit material, circuit fabrication conditions, and circuit structure of the circuit on which the semiconductor device is mounted. For example, if device fabrication conditions are selected as the explanatory variable, a process to be specified within the device fabrication process can be selected. If device structure is selected as the explanatory variable, the type of structure can be specified. In this way, when conditions are specified in the pull-down input field 8 or the pull-down input fields 8 and 9, pre-registered variables are displayed on the input screen, and a fixed value or range of the variable can be specified by operating the fix checkbox. Variables for which a fixed value or value range (maximization, minimization, or both) is specified become constraints during optimization. On the other hand, it is not necessary to enter values ​​for the variables; if no values ​​are entered, the optimization calculation will find the optimal value for the target variable.

[0031] In addition, the type of objective variable to be specified can be selected in the pull-down input field 11 in the output section, and the target value or target value range (maximization, minimization, or both) or a combination thereof can be entered on the input screen. The pull-down input field 11 should preferably be able to select from device characteristics, circuit characteristics, etc. If a target value, range, maximum / minimum, or other condition or combination thereof is not entered, the variable will be calculated at an arbitrary value in the optimization calculation. If a target value, range, maximum / minimum, or other condition or combination thereof is entered, it will become a condition when deriving an objective variable for which a fixed value is not specified in the input section.

[0032] When the parameters are input, the optimization calculation unit 103 uses the input parameter values ​​or ranges as constraint conditions and the parameter values ​​and ranges input to the output section as objective variables to find parameters for which values ​​are not specified among the parameters input to the input section by optimization calculation. For example, when values ​​are specified as shown in FIG. 2, the optimization calculation unit 103 calculates the drift layer concentration in the input section as 1×10 16 While maintaining this, we aim to obtain the optimum values ​​for the JFET length and channel length that minimize the on-resistance while maintaining the breakdown voltage in the output section at 1200V or more, the threshold voltage at 3V to 8V, and the gate breakdown voltage at 25V or more.

[0033] The left area of ​​the input screen may display information about the conditions specified in the pull-down input field 8 or the pull-down input fields 8 and 9. For example, in the input screen shown in the figure, the device structure TED-MOS has been selected, so the structure of the TED-MOS FET is displayed.

[0034] FIG. 3 is a diagram showing the configuration of the model construction unit 102.

[0035] The model construction unit 102 constructs a regression model using explanatory variables and target variables input to the operation unit 106. The model construction unit 102 is configured with multiple layers, roughly divided into a front-stage, middle layer, and rear-stage. Note that while FIG. 3 illustrates the model construction unit 102 configured with three layers, i.e., a front-stage, middle layer, and rear-stage, the model construction unit 102 may be configured with four or more layers. The model construction unit 102 receives parameters (parameters of the semiconductor device and parameters of the circuit mounted on the semiconductor device) input to the input section and outputs selectable parameters in the output section, thereby relating the respective parameters.

[0036] The first stage, a physical property calculation model (corrector 1), converts the parameters entered in the input section into the physical property values ​​used in the simulation. For example, the physical property values ​​used in the simulation are unobservable physical properties, such as the trap amount and mobility at the oxide film interface, relative to the oxide film fabrication conditions (such as the oxide film quality, thickness, and annealing amount) as input values. In addition to the aforementioned, unobservable physical properties converted by the physical property calculation model include hole and electron mobility, scattering cross section, trap density in the oxide film, interface state density, Auger and SRH recombination rate, lifetime, saturated drift velocity, thermal conductivity, defect density, impurity concentration considering activation rate, design values ​​considering mask misalignment, geometry (trench angle, oxide film thickness, etc.) that changes depending on fabrication conditions, and material (source contact material). In particular, since theoretical formulas cannot be used to predict mobility, interface traps, and activation rate for SiC, the physical property calculation model by corrector 1 in the first stage is extremely effective. Furthermore, the input values ​​to be corrected do not necessarily have to be unobservable physical properties; observable physical properties can also be used. For example, when a design value is input, the aperture width actually created using a mask in a photolithography process may be used as the corrected variable.

[0037] Furthermore, in power semiconductor devices using non-Si compounds, traps form at the interface with the oxide film, causing threshold voltage fluctuations and reduced switching speed. Because power semiconductor devices control high voltages, threshold voltage fluctuations reduce switching speed, posing safety and power loss problems. Furthermore, mobility is important because resistance reduction is necessary to reduce power loss. However, mobility within a device is lower than bulk mobility, making it difficult to predict mobility based on theoretical characteristics. Furthermore, power semiconductor devices are prone to high internal electric fields, and the presence of traps in the oxide film significantly reduces the reliability of the oxide film. Furthermore, there is no established model for the diffusion mechanism when impurities are implanted into a device. In particular, in power devices, the impurity concentration is increased to reduce on-resistance, resulting in a significant difference between the actual impurity concentration and the activated impurity concentration.

[0038] The variables corrected in the physical property calculation model in the previous stage are related to theoretical properties in the middle layer. For example, the middle layer creates data by performing multiple physical simulations, and then uses the created data to efficiently build a characteristic regression model through spiral learning. By modeling the middle layer rather than simply simulating it, backpropagation from the input in the previous stage to the output in the subsequent stage becomes possible, enabling the physical property calculation model to be learned.

[0039] The theoretical characteristics obtained in the intermediate layer are converted into measurable physical quantities in the subsequent physical quantity calculation model (corrector 2). For example, corrector 2 performs the following conversion to calculate observable physical quantities. Converts the internal temperature of a semiconductor into short circuit resistance Add the offset resistance to the on-resistance during measurement Corrects the effect of measurement-induced contact resistance on the theoretically derived on-resistance of semiconductor devices In particular, for MIS FETs (Metal-Insulator-Semiconductor FETs) with trenches, the reliability of the gate insulating film is calculated from the electric field strength applied to the corners of the trench. Calculates switching loss and switching time from the external resistance of the semiconductor device circuit and the capacitance inside the semiconductor device. - Calculates short circuit time from saturation current characteristics during short circuit

[0040] In particular, the measurable physical quantities may include on-resistance, threshold voltage, breakdown voltage, and insulation film reliability as output of power semiconductor device characteristics, and may include short-circuit withstand capability and switching loss as characteristics of the semiconductor device mounted circuit. These measurable physical quantities may be derived from the characteristic regression model in the middle stage, but by deriving them using the corrector 2, a faster regression model can be constructed.

[0041] In this way, the corrector 2 can convert a certain physical quantity into an actual physical quantity that is the same physical quantity, and can also derive a different physical quantity from a certain physical quantity. In particular, in a MIS FET structure with an oxide film, the dielectric breakdown strength of SiC is about one order of magnitude higher than that of Si, so the electric field strength in the oxide film is high and the reliability of the oxide film becomes important. On the other hand, there are various indicators of the reliability of the oxide film, and since it also affects the yield, it is difficult to derive it by theoretical calculation, and it is essential to derive it using the corrector 2. In addition, there is a phenomenon in which the threshold shifts depending on the quality of the insulating film. Positive Bias-Temperature Instability (PBTI) and Negative Bias-Temperature Instability (NBTI) However, the exact causes of these phenomena have not been elucidated, and since there is no accurate theoretical model, they must be derived using a corrector 2.

[0042] The front stage (corrector 1 based on a physical property calculation model), the middle layer (characteristic regression model), and the rear stage (corrector 2 based on a physical quantity calculation model) may each be a learning model constructed by learning.

[0043] The simulations used in the regression model in the intermediate layer of the model construction unit 102 involve unobservable parameters, but the front-stage corrector 1 and rear-stage corrector 2 can construct a highly accurate model that can input and output observable data.

[0044] 3 is described as a diagram showing the configuration of the model construction unit 102, but since the model construction unit 102 and the model constructed by the model construction unit 102 realize the same input and output, if the model constructed by the model construction unit 102 is configured as a neural network, it can also be said to be a diagram showing the configuration of this neural network. In this respect, Figures 7 to 10, which will be described later, can also be said to be diagrams showing the configuration of a model.

[0045] FIG. 4 is a diagram showing a calculation method executed by the optimization calculation unit 103.

[0046] The optimization calculation unit 103 uses the regression model constructed by the model construction unit 102 to inputThe parameter thus determined is used as a response variable, and an optimization calculation is performed to find an optimal value for a parameter that has not been specified among the parameters entered in the input section so as to satisfy the condition of the response variable. In the optimization calculation, the relationship between the explanatory variables and the response variable is calculated multiple times from the regression model so that the parameters entered in the multiple input sections satisfy the conditions of the multiple parameters specified in the output section, and the explanatory variables that optimize the response variable are found. By performing such repeated calculations, it is possible to derive complex conditions for the design, materials, and manufacturing conditions of a semiconductor device and a circuit equipped with the semiconductor device that would not be conceived by humans.

[0047] There are many types of optimization calculation methods that can be adopted by the optimization calculation unit 103, and the present invention does not require any particular optimization method to be limited. Therefore, an example will be described in which the Newton method, which is a common optimization calculation method and will be described later with reference to Figures 12A and 12B, is adopted.

[0048] For example, in FIG. 12A and FIG. 12B, in step 2, an arbitrary response variable is designated as a minimum value on the input screen (FIG. 2), and the minimum value is calculated by Newton's method. The response variable and the explanatory variables are related by a regression model created by the model construction unit 102, and in FIG. 12A and FIG. 12B, the explanatory variables corresponding to the inputs α1, α2, ... in FIG. 3 are designated as x(x teeth(It may be a vector of multiple variables.) The objective variable corresponding to the output β in FIG. 3 is denoted as y, and one of the regression models created by the model construction unit 102 is y = g(x). In other words, using a regression model, the objective variable y can be calculated for any explanatory variable x, and by sequential calculation, y can be calculated for a certain x, and an explanatory variable x can be derived whose objective variable y best matches the conditions of the objective variable entered on the input screen. When using Newton's method to find the explanatory variable x that minimizes the objective variable y, a tangent to the function at a certain search point xk for the regression model y = g(x) is found, and the direction in which y decreases based on the slope of the tangent is set as the search direction. Next, the value of y at point xk+1 where the tangent intersects the x-axis is derived from the regression model y = g(x), and the tangent to the function at xk+1 is found to determine the search direction. This process is repeated until the conditions of y are met. In the example shown in Figure 4, the point where the slope of the tangent line changes from positive to negative is the point where the value of the objective variable y is minimum, and the value of x at this time is the optimal calculation result, which becomes the desired material, manufacturing conditions, and design of the power semiconductor device and the circuit on which the power semiconductor device is mounted.

[0049] Next, the manufacturing process of the trench MIS FET will be described with reference to FIG.

[0050] First, in step A, a SiC bulk substrate (e.g., 4H-SiC, 1e18, Si-face, 4° off-axis) is prepared. The SiC bulk substrate may be a substrate fabricated using a sublimation method, a substrate fabricated using a solution method, a substrate fabricated using a gas growth method, or a substrate already having an epitaxially grown layer laminated thereon. Chemical mechanical polishing (CMP) may be performed before the growth of the epitaxial layer. The substrate concentration may be 1e18 to 1e21. The crystal type may be 4H-SiC, 6H, or 3C. The plane may be the Si-face, C-face, or any other plane orientation. Preferably, a substrate with an off-axis angle is used, but a just-oriented substrate may also be used. The type, concentration, plane, off-axis angle, etc. of the substrate prepared in step A may be optimized for the semiconductor material by the design condition calculation system 100 of this embodiment.

[0051] Next, in step B, an epitaxial growth layer is formed. For example, SiH4 and C3H8 are heated to a temperature of 1500°C or higher using H2 as a carrier gas to perform epitaxial growth, forming an epitaxial layer. The concentration and thickness of the epitaxial layer to be formed vary depending on the device to be fabricated, but the concentration should be approximately 1e14 to 1e18, and the thickness should be several μm to several tens of μm. Also, a high-concentration buffer layer may be formed before forming the epitaxial layer. The concentration of the buffer layer should be approximately 1e18. The epitaxial layer is also referred to as a drift layer. The growth conditions (temperature, carrier gas, purge gas, other device conditions), concentration, thickness, etc. of the epitaxial layer and buffer layer may be optimized for the semiconductor material using the design condition calculation system 100 of this embodiment.

[0052] Next, in step C, ion implantation regions are formed. Step C is a step required for the SiC power semiconductor device described later in Example 5. For example, P-type implanted ions may be aluminum or boron, and N-type implanted ions may be nitrogen or phosphorus. In the drift layer, a P-type body region (p), potential fixing region (p++), and guard region (p), as well as an N-type source region (n++), current diffusion region (n+), and JFET region (n- to n+) are formed by ion implantation. The body region may be formed by P-type epitaxial growth. Note that the polarity may be reversed between P-type and N-type. "-" and "+" are symbols that indicate the relative impurity concentration of n-type or p-type conductivity, and for example, the concentration of n-type impurities increases in the order of "n--", "n-", "n", "n+", and "n++".

[0053] The source region and the potential clamping region are formed in contact with the wafer surface. The body region is in contact with the source region and is formed deeper than the source region. Furthermore, the body region is electrically connected to the potential clamping region. The current spreading region is in contact with the body region and is formed deeper than the body region. The guard region is in contact with the current spreading region and is formed deeper than the current spreading region. Furthermore, the guard region is electrically connected to the potential clamping region. The JFET region is a region sandwiched between the guard regions that connects the current spreading region and the drift region, and ion implantation may be performed to reduce resistance. Note that the example shown in Figure 5 is a minimum configuration that allows MOS operation, so a structure that adds functions such as a termination region may be fabricated.

[0054] The mask conditions (type, thickness, fabrication conditions, mask removal conditions, etc.) and implantation conditions (ion species, implantation energy, number of implantation stages, implantation angle, etc.) used during ion implantation may be optimized in terms of fabrication conditions using the system of the present invention, and the implantation depth, implantation region, impurity concentration, etc. may be optimized in terms of design and structure using the design condition calculation system 100 of this embodiment.

[0055] Next, in step D, a carbon film of a cap material for impurity activation annealing is deposited around the silicon carbide substrate and the silicon carbide epitaxial layer, and impurity activation annealing is performed at a temperature of, for example, 1600 to 1800°C. The carbon layer of the cap material is then removed by oxygen plasma ashing. A thermal oxide film may then be formed, and the thermal oxide film may be removed using a diluted hydrofluoric acid solution to clean the surface. The type of cap material, annealing temperature, annealing time, conditions for the cap material removal method, and the type, shape, thickness, and other formation and removal conditions of the thermal oxide film may be optimized conditions for fabrication using the design condition calculation system 100 of this embodiment.

[0056] Next, in step E, a trench is formed. For example, a trench is formed by etching, which penetrates the source region, the body region, and the current diffusion region and has a bottom that fits within the guard region. Thereafter, a thermal oxide film may be formed, and the thermal oxide film may be removed using a diluted hydrofluoric acid solution to clean the etched surface. The mask conditions (type, thickness, fabrication conditions, mask removal conditions) used in the etching, the etching conditions (etching time, etching gas type, applied voltage, etc.), and the post-etching treatment (type, shape, thickness, other fabrication conditions, removal conditions, etc. of the thermal oxide film) may be optimized in terms of fabrication conditions by the design condition calculation system 100 of this embodiment. Furthermore, the depth, width, shape, etc. of the trench may be optimized in terms of design and structure by the design condition calculation system 100 of this embodiment.

[0057] Next, in step F, a gate insulating film is formed on the semiconductor. For example, the gate insulating film is formed from a SiO2 film by thermal CVD. The thickness of the gate insulating film is, for example, about 0.005 to 0.15 μm. After depositing a gate electrode made of an n-type polycrystalline silicon film with a thickness of about 100 to 300 nm, an interlayer film is preferably formed to cover the gate electrode. The types of gate insulating film, gate electrode, and interlayer film, their fabrication conditions (fabrication method, etc.), annealing temperature, annealing time, conditions for the capping material removal method, the type of thermal oxide film, and other formation and removal conditions may be optimized in terms of fabrication conditions by the design condition calculation system 100 of this embodiment. The shape, thickness, etc. of the gate insulating film and thermal oxide film may be optimized in terms of design and structure by the design condition calculation system 100 of this embodiment.

[0058] Next, in step G, various electrodes are formed. For example, to make contact between the source region and the potential fixing region, the interlayer film is etched using a resist as a mask to form contact holes, and silicide metal is deposited. After that, annealing is performed at 700°C to 1000°C to silicide the metal, forming a source-base common contact. After that, to make contact with the gate electrode, the interlayer film is etched to form a gate contact hole.

[0059] Next, a source electrode is formed. At the same time, the drain region on the back surface is silicided to form a drain contact, and then a drain contact electrode is formed. Metal materials such as Ni and Al are preferably used for the silicide metal, source electrode, and drain contact electrode. After that, a surface protection film made of an insulator is formed to cover the entire surface to protect the device, and wiring to the electrodes is performed, completing the semiconductor device.

[0060] The interlayer film etching conditions (etching time, etching gas type, applied voltage, etc.), contact and electrode conditions (metal material, silicide annealing temperature, etc.), and insulating film and wiring manufacturing conditions may be optimized in terms of manufacturing conditions by the design condition calculation system 100 of this embodiment, and the electrode and contact regions, ranges, etc. may be optimized in terms of design and structure by the design condition calculation system 100 of this embodiment.

[0061] Next, a specific example to which the design condition calculation system 100 of the above-described embodiment is applied will be described.

[0062] Example 1 The design condition calculation system 100 of this embodiment calculates the optimum conditions for a trench MIS FET, which has a structure that allows the channel structure and JFET structure to be designed independently, as a power semiconductor device, and an inverter circuit equipped with a trench MIS FET.

[0063] An example of the input screen for this embodiment will be described with reference to FIGS. 6A and 6B. The semiconductor device to be optimized in this embodiment is a silicon carbide semiconductor device having a trench MIS FET structure. For example, on the input screen, variables that do not need to be changed in the design, such as trench depth and drift concentration, can be specified as fixed values ​​of 0 or 1 or more. Meanwhile, variables that are not set as fixed values, such as the design of the JFET region of the n-type epitaxial layer between the trenches and the channel design corresponding to the trench width and depth, are optimized. In particular, the trench MIS FET structure optimized in this embodiment uses the trench as a channel, and the JFET region is formed separately from the trench. This allows the channel and JFET to be designed independently, enabling a design that avoids the commonly problematic trade-off between on-resistance and short-circuit withstand capability. Therefore, in the example shown in FIGS. 6A and 6B, the values ​​of the objective variables were set to minimize on-resistance and ensure short-circuit withstand capability for a sufficient time (3 μs or more) for the application circuit. The conditions, such as the type and number of variables, are not limited to those shown in FIGS. 6A and 6B.

[0064] As described above, according to the design condition calculation system 100 of the first embodiment, as shown in the first embodiment, it is possible to optimize and design the trench MIS FET structure of the semiconductor device to be optimized, and it is possible to easily achieve a design that satisfies the requirements for both the short circuit time and the on-resistance.

[0065] <Example 2> The design condition calculation system 100 of this embodiment calculates the optimum conditions for heat and noise, which are problems specific to power semiconductor devices whose materials are not limited to SiC and which are used for power conversion.

[0066] In this embodiment, power semiconductor devices made of Si, SiC, or other materials are optimized. Because power semiconductor devices are used for power conversion and handle large amounts of power, heat and noise are important from the perspectives of safety and operational life, preventing malfunctions. It is particularly difficult to identify the source of noise—whether it is a device or a circuit—and identifying the cause relies on the experience and knowledge of engineers. Therefore, the present invention is highly effective in the design of power semiconductor devices and applications incorporating power semiconductor devices.

[0067] FIG. 7 illustrates an example of the corrector 1, which constitutes the front stage of the model construction unit 102 in this embodiment. The corrector 1 is configured with one or more layers. While FIG. 7 illustrates a four-layer configuration, other numbers of layers may be used. Among these layers, in this embodiment, one or more layers include a thermal characteristic regression model created by spiral learning using thermal simulation. For example, when variables defining the module structure are input into the design and structure of a semiconductor device-mounted circuit in the input, the variables defining the module structure are converted into circuit components such as heat capacity and thermal resistance by the thermal characteristic regression model layer. In this embodiment, in addition to the parameters shown in FIG. 7, parameters that cause heat and noise, and parameters affected by heat and noise, may be input or output.

[0068] Example 3 In this embodiment, the corrector 1 is configured with one or more layers, and at least one layer is configured with an encoder that extracts features using a physical formula that represents the physical properties of a semiconductor and reduces dimensions. This enables correction based on the physical formula and prevents overfitting.

[0069] 8 is a diagram showing an example of the corrector 1 constituting the front stage of the model construction unit 102 in this embodiment. As an example of input dimension reduction by the encoder, application to the design values ​​of a device structure will be described. In the drain current equation for a MOS FET, the channel width W and channel length L may differ from the design values ​​due to mask misalignment in the photolithography process, but since they contribute to the current in the equation below, the channel width W and channel length L correlate with the output on-resistance and the feature quantity W / L. I ds =μ eff C ox W / L(V g -V th )V ds

[0070] Therefore, by calculating the above equation using an encoder present in one or more layers of the corrector 1 at the previous stage, the feature W / L can be extracted and the feature W / L can be corrected to obtain a correct output. Such an encoder is not limited to a physical equation; it can also be extracted using an autoencoder that performs learning by inputting the same values ​​into the input and output, as shown in Figure 9. Also, as described above, an encoder using a physical equation and an encoder constructed by learning can also be applied to the corrector 2 at the subsequent stage.

[0071] Example 4 In this embodiment, the actual characteristics of the semiconductor device corrected by the corrector 2 are treated as the intermediate layer.

[0072] FIG. 10 is a diagram showing an example of the model construction unit 102 of this embodiment.

[0073] In the fourth embodiment, the intermediate layer is composed of a characteristic regression model, a corrector 2A, and a circuit characteristic model.

[0074] The parameters of the semiconductor device and the parameters of the circuit on which the semiconductor device is mounted, which are input on the input screen, are input separately to correctors 1A and 1B, respectively. Corrector 1A converts parameters representing at least one of the semiconductor device's material, manufacturing process, and design into unobservable physical property values. As shown in Figure 3, the characteristic regression model converts the unobservable physical property values ​​of the semiconductor device into unobservable theoretical characteristic values, and corrector 2A converts the unobservable theoretical characteristic values ​​of the semiconductor device into measurable physical quantities.

[0075] Because the actual characteristics of the semiconductor device corrected by the corrector 2 are treated as an intermediate layer, the device characteristics are not correlated with the materials, fabrication process, design, or structure of the mounted circuit, but are related only to variables converted from device input values ​​that clearly relate to the device characteristics. Furthermore, the circuit characteristics are not directly related to device-related variables, but are associated with the characteristics β1, β2, ... of the mounted semiconductor device. Therefore, the characteristic regression model is created primarily by learning through device simulation, and the circuit characteristic model is created primarily by learning through circuit simulation in which the device characteristics are replaced with an equivalent circuit, and parameters representing at least one of the materials, fabrication process, and design of the circuit mounted with the semiconductor device are converted into theoretical characteristic values ​​of the circuit mounted with the semiconductor device. The circuit characteristic model may correlate the output values ​​of the characteristic regression model with observed quantities of the characteristics of the semiconductor device. For example, when on-resistance is considered as an observable quantity of the characteristics of a semiconductor device, the values ​​input as the design and structural conditions of the semiconductor device mounted circuit are converted by corrector 1 to obtain the characteristics of the semiconductor device, such as on-resistance, resistance caused by the module structure, and circuit resistance, which are then converted by corrector 2B into characteristics of the semiconductor device mounted circuit, and then converted into actual measured values ​​of the semiconductor device mounted circuit using a circuit characteristic model.

[0076] The corrector 2B converts the theoretical characteristic values ​​of the circuit in which the semiconductor device is mounted into observable characteristic values ​​of the circuit.

[0077] In this way, by not taking into account correlations that do not have a direct correlation in advance and by making inferences based on only some correlations, it is possible to create a model that is easier to learn and avoids over-learning.

[0078] <Example 5> In this embodiment, a method for fabricating a SiC power semiconductor device and a circuit equipped with the SiC power semiconductor device will be described. As described above with reference to Fig. 5 for fabricating a trench MIS FET, the method for fabricating a semiconductor device of this embodiment fabricates a semiconductor device using fabrication conditions optimized for design and structure by the design condition calculation system 100 of the above-described embodiment.

[0079] The input values ​​on the input screen can be optimized by inputting process conditions such as the etching time and voltage for creating a trench, the type of oxide film, and the pressure during oxide film creation. Furthermore, if the corrector 1 of the model construction unit 102 created by learning is installed in a semiconductor manufacturing device, physical property values ​​such as mobility can be calculated from manufacturing conditions such as the amount of mask misalignment in the photolithography process and the conditions of the oxide film creation process, and the learning results of the corrector 1 can be fed back to the manufacturing device that creates the semiconductor device.

[0080] In this way, by using the design condition calculation system 100 of this embodiment, as shown in FIG. 11, by linking the semiconductor manufacturing equipment with the design condition calculation system 100, it becomes possible to manufacture under optimal conditions for various device conditions.

[0081] Example 6 In the above-described first to fifth embodiments, the model construction unit 102 constructs a regression model in advance based on a pre-trained learning model. On the other hand, in this embodiment, even if the regression model constructed by pre-training does not have sufficient accuracy, the result of the optimization calculation is fed back to reconstruct the regression model, and the optimization calculation is repeated while increasing the accuracy of the regression model.

[0082] 12A and 12B are flowcharts of the process in which the design condition calculation system 100 of this embodiment calculates the design conditions.

[0083] In this embodiment, if the objective variable obtained after the optimization calculation does not satisfy a certain standard, a physical simulation related to the optimized design is rerun, and the result is fed back to the characteristic regression model in the intermediate layer of the model construction unit 102 for re-learning, thereby constructing a more accurate regression model and performing the optimization calculation. In the example shown in FIGS. 12A and 12B , optimization is performed so that the difference between the objective variable βi and the target value ans, which is the condition for the objective variable entered on the input screen, is smaller than a predetermined threshold ε. That is, in step 8, it is determined whether the difference between the objective variable βi and the target value ans is greater than a predetermined threshold ε. If the difference between the objective variable βi and the target value ans is greater than the predetermined threshold ε, the input value optimized in the optimization calculation is fed back to the model construction unit 102, the fed-back input value is converted by the corrector 1 in the upstream stage of the model construction unit 102, a physical simulation is performed near the converted physical property value of the fed-back input value, and the physical property value and the theoretical property value obtained in the physical simulation are fed back to the characteristic regression model in the model construction unit 102 to construct a new characteristic regression model. The optimization calculation is then performed again using the new characteristic regression model. The result of the optimization calculation is judged again in step 8, and if the difference between the objective variable βi and the target value ans is greater than the predetermined threshold ε, the calculation process is repeated. If the difference between the calculated objective variable βi and the target value ans is smaller than the predetermined threshold ε, the iterative process is terminated and the optimization calculation result is displayed.

[0084] As shown in the sequence diagram of FIG. 12B, the optimization calculation, physical simulation, and model construction may be repeated the same number of times. However, as long as the optimization calculation is performed at least once, the regression model and conditions for the optimization calculation may be extracted multiple times. For example, if the number of optimization calculations or the time required for the optimization calculation are specified in advance, and an explanatory variable that can derive a target variable βi whose difference from the target value ans is smaller than ε cannot be found within the specified number of optimization calculations or the specified time, the model may be reconstructed. Also, in this embodiment, as in the first embodiment, the number of times data is stored in the data storage unit 104 is not limited to the number described above. Furthermore, the processing of the model construction unit 102 (step 4) and the physical simulation (step 9) may be performed outside the design condition calculation system 100 (e.g., on the cloud).

[0085] As described above, by feedback to the model construction of the optimization calculation, even if the number of simulation data in pre-training is small and the accuracy of the characteristic regression model in the intermediate layer of the pre-trained model construction unit 102 is low, simulation data in a range close to the desired design is added by feedback, thereby improving the accuracy of the regression model in a range close to the optimization calculation result, and also improving the calculation accuracy of the explanatory variables that derive the desired objective variable. In Figure 12A, the condition for the iterative calculation is that the difference between the objective variable βi and the target value ans is smaller than a predetermined threshold ε, but the condition for the iterative calculation is not limited to this, and the minimum, maximum, one value, or a range of values ​​can be specified on the input screen.

[0086] As described above, the design condition calculation system 100 according to the embodiment of the present invention includes an arithmetic device (calculation unit 101) that executes predetermined processing, an input unit (input / output unit 108) to which data is input, and a storage device (data storage unit 104) that can be accessed by the arithmetic device, and the input unit receives inputs of a first parameter that represents at least one of a material, a manufacturing process, and a design of a semiconductor device, a second parameter that represents at least one of a material, a manufacturing process, and a design of a circuit on which the semiconductor device is mounted, and a third parameter that represents at least one characteristic of the semiconductor device and the circuit on which the semiconductor device is mounted. The design condition calculation system 100 includes an optimization calculation unit 103 in which the arithmetic device calculates the first parameter and the second parameter so as to satisfy predetermined conditions using a model constructed by a model construction unit. The model constructed by the model construction unit 102 includes a first conversion model (corrector 1 that is a physical property calculation model) provided in the preceding stage, a second conversion model (corrector 2 that is a physical quantity calculation model) provided in the succeeding stage, and the The optimization calculation unit 103 uses the constructed model to calculate the first and second parameters that are not constraint conditions, using fixed values ​​set for some of the first and second parameters as constraint conditions, so as to satisfy one or a combination of the value and range of the third parameter, and outputs the calculated first and second parameters, thereby making it possible to provide an optimized design that satisfies numerous characteristics in power devices tailored to application requirements quickly and at low cost.Furthermore, while the simulation used in the characteristic regression model can only calculate the relationship between unobservable parameters, a highly accurate model of observable data can be constructed using the front-stage corrector 1 and the back-stage corrector 2. Furthermore, by creating a model, characteristics can be predicted with high accuracy without having to perform time-consuming simulations each time.

[0087] The present invention is not limited to the above-described embodiments, but includes various modifications and equivalent configurations within the spirit and scope of the appended claims. For example, the above-described embodiments have been described in detail to clearly explain the present invention, and the present invention is not necessarily limited to configurations including all of the described configurations. Furthermore, part of the configuration of one embodiment may be replaced with the configuration of another embodiment. Furthermore, the configuration of another embodiment may be added to the configuration of one embodiment. Furthermore, part of the configuration of each embodiment may be added, deleted, or replaced with other configurations.

[0088] Furthermore, the aforementioned configurations, functions, processing units, processing means, etc. may be realized in part or in whole in hardware, for example by designing them as integrated circuits, or may be realized in software by having a processor interpret and execute a program that realizes each function.

[0089] Information such as programs, tables, and files that realize each function can be stored in a storage device such as a memory, a hard disk, or an SSD (Solid State Drive), or in a recording medium such as an IC card, an SD card, or a DVD.

[0090] In addition, the control lines and information lines shown are those that are considered necessary for explanation, and do not necessarily represent all the control lines and information lines that are necessary for implementation. In reality, it can be assumed that almost all components are interconnected. [Explanation of symbols]

[0091] 100 Design Condition Calculation System 101 Computational Units 102 Model Building Units 103 Optimization Computation Unit 104 Data Storage Unit 105 Communications Department 106 Operation section 107 Output section 108 Input / Output Unit

Claims

1. A design condition calculation system, The system includes a computing device that executes predetermined processing, an input unit to which data is input, and a storage device that can be accessed by the computing device, the input unit receives input of a first parameter representing at least one of a material, a manufacturing process, and a design of the semiconductor device, a second parameter representing at least one of a material, a manufacturing process, and a design of a circuit on which the semiconductor device is mounted, and a third parameter representing at least one characteristic of the semiconductor device and the circuit on which the semiconductor device is mounted; the design condition calculation system includes an optimization calculation unit configured to calculate the first parameters and the second parameters using a model constructed by a model construction unit so as to satisfy predetermined conditions; The model constructed by the model construction unit is a first conversion model provided in a preceding stage, a second conversion model provided in a succeeding stage, and a characteristic regression model provided between the first conversion model and the second conversion model; the first parameter and the second parameter are input, and the third parameter is output, thereby relating the respective parameters; the first conversion model converts at least one of the first parameter and the second parameter into a physical property value to be input to the characteristic regression model; The property regression model converts unobservable physical property values ​​into unobservable theoretical property values; the second conversion model converts theoretical characteristic values ​​into actual characteristic values; The optimization calculation unit using the constructed model, calculating the first parameters and the second parameters that are not constraint conditions so as to satisfy a condition based on one or a combination of the value and range of the third parameter, with fixed values ​​set as part of the first parameters and the second parameters as constraint conditions; A design condition calculation system that outputs the calculated first and second parameters.

2. 2. The design condition calculation system according to claim 1, a model construction unit that is provided outside the design condition calculation system, and that calculates the first parameter and the second parameter, which are not the constraint conditions, by using a regression model created by the model construction unit that is provided outside the design condition calculation system.

3. 2. The design condition calculation system according to claim 1, The design condition calculation system is characterized in that the first parameter includes at least one of the physical property values ​​of the semiconductor device, that is, mobility, effective impurity concentration, interface state, and oxide film trap density.

4. 2. The design condition calculation system according to claim 1, The design condition calculation system is characterized in that the third parameter includes at least one of characteristics related to a power semiconductor device or a power semiconductor device mounted circuit, including on-resistance, short-circuit tolerance, threshold voltage, frequency band, withstand voltage, switching loss, and insulating film reliability.

5. 5. The design condition calculation system according to claim 4, the third parameter includes an on-resistance and a short-circuit withstand capability, The optimization calculation unit calculates the first parameter and the second parameter that improve the trade-off between the on-resistance and the short-circuit tolerance in a silicon carbide semiconductor device that allows the structure of a JFET region and the structure of a channel region to be designed independently.

6. 2. The design condition calculation system according to claim 1, the first transformation model includes one or more layers; A design condition calculation system, characterized in that one or more layers included in the first conversion model are thermal characteristic regression models learned by thermal simulation.

7. 2. The design condition calculation system according to claim 1, the first transformation model includes one or more layers; A design condition calculation system characterized in that one or more layers included in the first transformation model are encoders that extract features of at least some of the first parameters and the second parameters and reduce the dimensions of the input parameters.

8. 8. The design condition calculation system according to claim 7, The design condition calculation system is characterized in that the encoder extracts feature quantities using physical formulas that represent physical properties of semiconductors.

9. 8. The design condition calculation system according to claim 7, A design condition calculation system characterized in that the encoder is an autoencoder that learns using the same values ​​for input and output values.

10. 2. The design condition calculation system according to claim 1, the front stage of the model construction unit includes the first transformation model and a third transformation model; an intermediate layer of the model building unit includes the characteristic regression model, the second transformation model, and a circuit characteristic model; the latter stage of the model building unit includes a fourth transformation model; the first conversion model converts the first parameter into an unobservable physical property value of the semiconductor device to be input to the characteristic regression model; the characteristic regression model converts unobservable physical property values ​​of the semiconductor device into unobservable theoretical characteristic values; the second conversion model converts unobservable theoretical characteristic values ​​of the semiconductor device into actual characteristic values; the circuit characteristic model converts the actual characteristic values ​​of the semiconductor device output by the second conversion model and the second parameters into theoretical characteristic values ​​of a circuit mounted on the semiconductor device; the third conversion model converts the second parameters into unobservable physical property values ​​of a circuit mounted on the semiconductor device to be input to the circuit characteristic model; The design condition calculation system is characterized in that the fourth conversion model converts theoretical characteristic values ​​of a circuit mounted on a semiconductor device outputted by the circuit characteristic model into actual characteristic values.

11. 2. The design condition calculation system according to claim 1, the first conversion model is implemented in a semiconductor manufacturing device connected to the design condition calculation system, The semiconductor manufacturing device calculates processing conditions using the first conversion model.

12. 2. The design condition calculation system according to claim 1, The computing device After the first parameter and the second parameter that are not constraints are calculated, comparing the third parameter with a target value; a design condition calculation system characterized in that, when the third parameter does not satisfy a predetermined condition for the target value, the input value and output value of the optimization calculation unit are fed back to learn and reconstruct the characteristic regression model.

13. A manufacturing method for manufacturing a semiconductor device under conditions of first parameters output by a design condition calculation system, comprising: The design condition calculation system is configured by a computer having an arithmetic unit that executes predetermined processing, an input unit to which data is input, and a storage device that can be accessed by the arithmetic unit, the input unit receives input of a first parameter representing at least one of a material, a manufacturing process, and a design of the semiconductor device, a second parameter representing at least one of a material, a manufacturing process, and a design of a circuit on which the semiconductor device is mounted, and a third parameter representing at least one characteristic of the semiconductor device and the circuit on which the semiconductor device is mounted; the design condition calculation system includes an optimization calculation unit configured to calculate the first parameters and the second parameters using a model constructed by a model construction unit so as to satisfy predetermined conditions; The regression model constructed by the model construction unit is a first conversion model provided in a preceding stage, a second conversion model provided in a succeeding stage, and a characteristic regression model provided between the first conversion model and the second conversion model; the first parameter and the second parameter are input, and the third parameter is output, thereby relating the respective parameters; the first conversion model converts at least one of the first parameter and the second parameter into a physical property value to be input to the characteristic regression model; The regression model converts unobservable physical property values ​​into unobservable theoretical property values; the second conversion model converts theoretical characteristic values ​​into actual characteristic values; The optimization calculation unit using the constructed model, calculating the first parameters and the second parameters that are not constraint conditions so as to satisfy a condition based on one or a combination of the value and range of the third parameter, with fixed values ​​set as part of the first parameters and the second parameters as constraint conditions; A method for manufacturing a semiconductor device, comprising: outputting the calculated first parameter and second parameter.

Images