Semiconductor device with integrated current sensor

Abstract

To provide a semiconductor device with an integrated current sensor.SOLUTION: A semiconductor device includes: a power device region 102 including first trenches 108 and second trenches 110 extending lengthwise in parallel with one another with semiconductor mesas 112 between adjacent ones of the trenches, each first trench including a gate electrode G at a first potential and each second trench including a field plate S at a second potential; and a current sense region 104 formed in a semiconductor substrate. A subset of the first trenches, a subset of the second trenches and a subset of the semiconductor mesas are common to both the current sense region and the power device region. The second trenches are interrupted along opposite first side S1 and second side S2 of the current sense region such that the field plates are interrupted between the power device region and the current sense region.SELECTED DRAWING: Figure 1A

Description

[Background technology]

[0001] Current mirrors are widely used as current sensors for power transistors such as power MOSFETs (metal-oxide-semiconductor field-effect transistors), IGBTs (insulated gate bipolar transistors), SiC power transistors, etc. The source / emitter potential applied to the chip (die) is separated into two parts within the active device area to allow separate contacts to the current sensing pad and the main source / emitter pad. In the case of transistor cells with a stripe trench configuration, there is a problem in isolating the current mirror cell from the power transistor (load) cell. By using cross trenches, the isolation between the sensing and power device cells is improved without reducing the heat, current, and, in the case of IGBTs, electron-hole plasma coupling.

[0002] In some approaches, the p-type body doping is disrupted, for example by lithography, in the region of the semiconductor mesa that separates the power device region from the current sense region. In the case of striped contacts, the contact stripe must also be disrupted between the power device and current sense regions. In some cases, the device may have a trench, with the polysilicon in the trench contacted to the load source / emitter potential, while the semiconductor mesa in the current sense region is contacted to the sense source / emitter potential. This configuration results in undesirable capacitive coupling between the primary (load) cell and the current sense cell.

[0003] The above-described approaches require relatively complex isolation structures between the main (load) cell and the current-sensing cell, since different accumulation and inversion layers may occur at the gate depending on the operating point. Furthermore, there may be parasitic pnp structures along the semiconductor mesa, which further complicates the device design. Summary of the Invention [Problem to be solved by the invention]

[0004] Therefore, there is a need for an improved isolation approach between main (load) transistor cells and current sensing cells integrated within the same semiconductor device. [Means for solving the problem]

[0005] According to one embodiment of a semiconductor device, the semiconductor device includes: a power device region formed in a semiconductor substrate and including a plurality of first trenches and a plurality of second trenches extending parallel to one another in a longitudinal direction, with a semiconductor mesa between adjacent ones of the trenches, each first trench including a gate electrode at a first potential and each second trench including a field plate at a second potential; and a current sense region formed in the semiconductor substrate, wherein a subset of the first trenches, a subset of the second trenches, and a subset of the semiconductor mesas are common to both the current sense region and the power device region, and the second trenches are split along opposite first and second sides of the current sense region, thereby splitting the field plate between the power device region and the current sense region.

[0006] According to one embodiment of a method for fabricating a semiconductor device, the method includes forming a power device region in a semiconductor substrate, the power device region including a plurality of first trenches and a plurality of second trenches extending parallel to one another in a longitudinal direction, a semiconductor mesa between adjacent ones of the trenches, each first trench including a gate electrode at a first potential and each second trench including a field plate at a second potential; and forming a current sense region in the semiconductor substrate, a subset of the first trenches, a subset of the second trenches, and a subset of the semiconductor mesas being common to both the current sense region and the power device region, wherein forming the power device includes forming the second trenches to be split along opposite first and second sides of the current sense region, whereby the field plate is split between the power device region and the current sense region.

[0007] Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings.

[0008] The elements of the drawings are not necessarily to scale relative to each other. Like reference symbols designate corresponding like parts. Features of the various illustrated embodiments may be combined unless they are mutually exclusive. The embodiments are shown in the drawings and described in detail in the following description. [Brief explanation of the drawings]

[0009] [Figure 1A] FIG. 1A illustrates a partial plan view of one embodiment of a semiconductor device. [Figure 1B] FIG. 1B shows a cross-sectional view of the semiconductor device along the line labeled AA' in FIG. 1A. [Figure 1C] FIG. 1C shows a cross-sectional view of the semiconductor device along the line labeled BB' in FIG. 1A. [Figure 2A] FIG. 2A shows a partial plan view of another embodiment of a semiconductor device. [Figure 2B] FIG. 2B shows a cross-sectional view of the semiconductor device along the line labeled CC' in FIG. 2A. [Figure 2C] FIG. 2C shows a cross-sectional view of the semiconductor device along the line labeled DD' in FIG. 2A. [Figure 3] FIG. 3 shows a partial plan view of another embodiment of a semiconductor device. [Figure 4] FIG. 4 illustrates a simplified plan view of one embodiment of gate trenches and emitter / source trenches in the boundary region between the power device region and the current sensing region of a semiconductor device. [Figure 5] FIG. 5 illustrates a simplified plan view of another embodiment of gate trenches and emitter / source trenches in the boundary region between the power device region and the current sensing region of a semiconductor device. DETAILED DESCRIPTION OF THE INVENTION

[0010] Described herein are embodiments for improving isolation between main (load) transistor cells and current sense cells integrated within the same semiconductor device. The embodiments include trench isolation and cross trench, which may be used separately or in combination with each other. The trench isolation approach involves separating trenches assigned to the main (load) emitter / source potential in the power device region of the device from trenches assigned to the sense pad potential in the current sense region of the device. The cross trench approach involves using cross trenches to isolate the body region of the main power transistor from the body region of the current sense device in a manner that simplifies isolation chaining along the mesa / trench and minimizes parasitic coupling. Again, the trench isolation and cross trench approaches may be used separately or in combination with each other.

[0011] In either case, the isolation techniques described herein decouple the equipotentials (gate potential and / or source / emitter potential) along the semiconductor mesa and / or along the source / emitter trenches, better isolating the current sensing device from the main power transistor. In some embodiments, two lithography process steps typically required for body and mesa implants can be eliminated. Furthermore, higher ESD (electrostatic discharge) intensity was observed in the current sensing region of the device when the source / emitter trenches in the current sensing region were set to the sense pad potential. This is due to better synchronization of the trench and mesa potentials in the current sensing region.

[0012] Described next with reference to the figures are exemplary embodiments of techniques for improving isolation between main (load) transistor cells and current sensing cells integrated within the same semiconductor device.

[0013] Figure 1A shows a partial plan view of one embodiment of a semiconductor device 100. Figure 1B shows a cross-sectional view of the semiconductor device 100 along the line labeled A-A' in Figure 1A. Figure 1C shows a cross-sectional view of the semiconductor device 100 along the line labeled B-B' in Figure 1A.

[0014] The semiconductor device 100 includes a power device region 102 and a current sensing region 104 formed in a semiconductor substrate 106. The semiconductor substrate 106 may include one or more of a variety of semiconductor materials used to form semiconductor devices such as power MOSFETs, IGBTs, SiC transistors, etc. For example, the semiconductor substrate 106 may include silicon (Si), silicon carbide (SiC), germanium (Ge), silicon germanium (SiGe), gallium nitride (GaN), gallium arsenide (GaAs), and the like. The semiconductor substrate 106 may be a bulk semiconductor material or may include one or more epitaxial layers grown on a bulk semiconductor material.

[0015] First trenches 108 and second trenches 110 are formed in a semiconductor substrate 106 and extend parallel to one another along their length, with semiconductor mesas 112 confined between adjacent ones of the trenches 108, 110. Each first trench 108 includes a gate electrode "G" at a first potential and separated from the semiconductor substrate 106 by a gate dielectric 107. Each second trench 110 includes a field plate "S" at a second potential and separated from the semiconductor substrate 106 by a field dielectric 109. The potentials may be different or independent. For example, the first potential may be a gate potential and the second potential may be a source or emitter potential. In any event, a subset of the first trenches 108, a subset of the second trenches 110, and a subset of the semiconductor mesas 112 are common to or shared by both the current sensing region 104 and the power device region 102.

[0016] Power transistor cells are formed in the power device region 102, and current sensing cells are formed in the current sensing region 104. For example, power MOSFET cells, IGBT cells, SiC transistor cells, etc. may be formed in the power device region 102. The current sensing cells reflect the current flowing in the power device region 102.

[0017] 1A-1C is shown as an IGBT device having a plurality of striped cells defined by striped first and second trenches 108, 110 and striped semiconductor mesas 112. The current sensing region 104 has the same cell-based configuration as the power device region 102, but may have a configuration having fewer cells than the power device region 102, for example, 1 / 10, 1 / 100, 1 / 1000, or even fewer cells.

[0018] In the case of an IGBT device, the power transistor cells in the power device region 102 and the current sensing cells in the current sensing region 104 further include an emitter region 114 of a first conductivity type, a body region 116 of a second conductivity type opposite the first conductivity type, a drift zone 118 of the first conductivity type, and a collector region 120 of the second conductivity type. A channel arises in the body region 116 along the gate trench 108, providing a conductive connection between the emitter region 114 and the drift zone 118 within both the power device region 102 and the current sensing region 104. The channel is controlled by a voltage applied to the gate electrode "G." The IGBT device may further include a field stop region 122 of the first conductivity type between the drift zone 118 and the collector region 120, the field stop region 122 having a higher doping concentration than the drift zone 118.

[0019] Other types of power transistors may be implemented in power device region 102. For example, a power MOSFET or a SiC transistor may be implemented in power device region 102. In the case of a power MOSFET or a SiC transistor, collector region 120 of the second conductivity type is replaced by a drain region of the first conductivity type, field stop region 122 is omitted, and emitter region 114 becomes a source region instead. Still other types of power transistors may be implemented in power device region 102, such as, for example, a JFET (junction field-effect transistor) device.

[0020] As described above, the current sensing device formed in the current sensing region 104 of the semiconductor substrate 106 reflects the current flowing in the power device region 102 and typically has the same cell configuration as the main power transistor, albeit with fewer cells. The first and second conductivity types depend on whether the semiconductor device 100 is a p-channel or n-channel device. For n-channel devices, the first conductivity type is n-type and the second conductivity type is p-type. For p-channel devices, the first conductivity type is p-type and the second conductivity type is n-type.

[0021] A first metal wiring layer 124 on the backside of the semiconductor substrate 106 provides collector / drain potentials to the cells of both the main power transistor and the current sense device. A second metal wiring layer 126, separated from the frontside of the semiconductor substrate 106 by at least one interlayer insulating film 128, provides gate potentials to the cells of both the main power transistor and the current sense device, provides emitter / source potentials to the cells of the main power transistor, and provides current sense connections to the cells of the current sense device formed in the current sense region 104.

[0022] 1A , providing an unobstructed view of the power device region 102 and current sense region 104 formed in the semiconductor substrate 106. As indicated by the dashed box in FIG. 1A , the second metal wiring layer 126 may include a first contact pad “main source / emitter pad” 130 electrically connected to both the semiconductor mesa 112 and the field plate “S” in the power device region 102 of the semiconductor substrate 106 through corresponding openings in the interlayer dielectric 128, and a second contact pad 132 “current sense pad” separate from the first contact pad 130 and electrically connected to both the semiconductor mesa 112 and the field plate “S” in the current sense region 104 of the semiconductor substrate 106 through an additional opening in the interlayer dielectric 128.

[0023] 1A and 1C, the second trench 110 divides the current sensing region 104 along opposing first and second sides S1, S2, thereby dividing the field plate "S" between the power device region 102 and the current sensing region 104. The field plate "S" and emitter / source region 114 in the power device region 102 are connected to a first contact pad 130 of the second metal wiring layer 126 through a first opening in the interlayer dielectric 128, and the field plate "S" and emitter / source region 114 in the current sensing region 104 are connected to a second contact pad 132 of the second metal wiring layer 126 through a second opening in the interlayer dielectric 128.

[0024] By ensuring that the field plate "S" and emitter / source region 114 in the current sensing region 104 are at the same potential as the second contact pad 132, no potential difference will develop between the semiconductor mesa 112 and the field plate "S" in the current sensing region 104, avoiding capacitive coupling with the power device region 102 that could otherwise create interference / noise in the dynamic performance of the current sensor. This is particularly beneficial during switching times (unsteady state) and whenever the source / emitter paths of the main power transistor and the current sensor are parasitically mismatched.

[0025] Switching speed / gradient, e.g., dV / dt in the range of 0.5 to 50 V / ns and di / dt in the range of 0.1 to 30 A / ns, is important for power transistors, which typically switch in the microsecond range. For example, for a 500 A load current and a 1:1000 current sense area ratio, the sense current is approximately 0.5 A. The load and sense currents are switched off simultaneously, resulting in the main power transistor having a switching speed 1000 times faster. di / dt can be high in conjunction with stray inductance and can lead to overvoltages that can cause mismatch between the source / emitter potentials of the main power transistor and the current sense device. These problems are avoided by connecting the field plate "S" and emitter / source regions 114 in the current sense region 104 to the same potential as the second contact pad 132 of the second metal wiring layer 126.

[0026] Disconnecting the second trench 110 along the opposing first and second sides S1, S2 of the current sensing region 104 and connecting the field plate "S" and emitter / source region 114 in the current sensing region 104 to the same potential as the second contact pad 132 also resulted in a measured improvement in ESD (electrostatic discharge) human body model performance; in this case, higher durability was observed, including at least 2 kV of isolation between the second contact pad 132 and the main transistor emitter / source potential.

[0027] The second trench 110 may be separated along opposite first and second sides S1, S2 of the current sense region 104 using a photomask that prevents etching of the second trench 110 into the semiconductor substrate 106 in the target area. The emitter / source region 112 is also separated along the first and second sides S1, S2 of the current sense region 104 in FIGS. 1A-1C , thereby separating the emitter / source region 112 between the power device region 102 and the current sense region 104.

[0028] 1A-1C , dopants of the second conductivity type may be omitted from the semiconductor mesa 112 or may be offset by dopants of the first conductivity type in the peripheral region 134 that laterally surrounds the current sense region 104. According to this embodiment, the body region 116 is discontinuous between the power device region 102 and the current sense region 104, providing further decoupling. The emitter / source regions 114 of both the main power transistor and the current sensor may be formed by implanting dopants of the first conductivity type into the semiconductor mesa 112 in the power device region 102 and in the current sense region 104. The body regions 116 of both the main power transistor and the current sensor may be formed by implanting dopants of the second conductivity type into the semiconductor mesa 112 in the power device region 102 and in the current sense region 104.

[0029] The body region 116 may be disrupted in the peripheral region 134 that laterally surrounds the current sense region 104, for example, by omitting dopants of the second conductivity type from the semiconductor mesa 112 in the peripheral region 134 using a photolithographic mask during formation of the body region 116. In another embodiment, the implantation of the body region is not blocked in the peripheral region 134, but instead the dopants of the second conductivity type are offset by the dopants of the first conductivity type in the peripheral region 134, for example, by implanting the dopants of the first type in the peripheral region 134 at the same or a higher concentration than the dopants of the second type.

[0030] Figure 2A shows a partial plan view of another embodiment of a semiconductor device 200. Figure 2B shows a cross-sectional view of the semiconductor device 200 along the line labeled CC' in Figure 2A. Figure 2C shows a cross-sectional view of the semiconductor device 200 along the line labeled D-D' in Figure 2A.

[0031] 2A-2C is similar to the semiconductor device 100 shown in FIGS. 1A-1C. However, the semiconductor device 200 shown in FIGS. 2A-2C further includes a first intersecting trench 202 connecting the first trenches 108 in the peripheral region 134 where the second trenches 110 are separated along the first side S1 of the current sensing region 104. The semiconductor device 200 shown in FIGS. 2A-2C also includes a second intersecting trench 204 connecting the first trenches 108 in the peripheral region 134 where the second trenches 110 are separated along the second side S2 of the current sensing region 104.

[0032] According to the embodiment shown in Figures 2A-2C, the first intersecting trench 202, the second intersecting trench 204, the first trench 108' disposed closest to the third side S3 of the current sensing region 104, and the first trench 108'' disposed closest to the fourth side S4 of the current sensing region 104 opposite the third side S3 are all connected to each other and laterally surround the current sensing region 104, such that the body region 116 in the current sensing region 104 is separated from the body region 116 in the power device region 102 by the trenches 202, 204, 108', 108'' that laterally surround the current sensing region 104. Body region, and therefore source / emitter, isolation is provided between the power device region 102 and the current sense region 104 by trenches 202, 204, 108', 108'', and by dielectric isolation 107, 109 that can withstand a wide range of operating conditions.

[0033] Additional steps need not necessarily be taken to omit or offset the second conductivity type dopants in the peripheral region 134 that laterally surrounds the current sense region 104 to effect decoupling of the body regions between the power device region 102 and the current sense region 104, eliminating two lithography process steps. That is, the body region 116 of the power device region 102 may extend into the peripheral region 134 that laterally surrounds the current sense region 104, but is still separated from the body region 116 in the current sense region 104 by the trench structures 202, 204, 108′, 108″ that laterally surround the current sense region 104 because the trench structures 202, 204, 108′, 108″ can extend deeper into the semiconductor substrate 106 than the body region 116, as shown in FIGS. 2B and 2C .

[0034] FIG. 3 illustrates a partial plan view of another embodiment of a semiconductor device 300. The semiconductor device 300 illustrated in FIG. 3 is similar to the semiconductor device 200 illustrated in FIGS. 2A-2C, except that an additional level of isolation is provided by dividing the first trench 108 along opposing first and second sides S1, S2 of the current sensing region 104. The first trench 108 is divided at first and second division regions, and the second trench 110 is divided at third and fourth division regions, which are laterally offset from the third and fourth division regions along the length of the trenches 108, 110. The first trench 108 can be divided using lithography by preventing etching of the first trench 108 into the semiconductor substrate 106 in the target area.

[0035] 3, the metal wiring layer 126 above the semiconductor substrate 106 also includes a first gate runner 302 disposed over the first region where the first trench 108 is disrupted. Only the outline of the gate runner 302 is shown in FIG. 3 to provide an unobstructed view of the power device region 102 and the current sense region 104 formed within the semiconductor substrate 106.

[0036] The first trench 108 is divided beneath a first gate runner 302. A gate potential is provided by the first gate runner 302 to both segments of the first trench 108 in this region, but the first trench 108 is otherwise divided within the semiconductor substrate 106 in this region. The gate electrode "G" within the divided first trench 108 in the first region is electrically connected to the first gate runner 302 at both ends 304, 306 of the division through corresponding openings in the interlayer dielectric 128 that separate the metal wiring layer 126 from the semiconductor substrate 106. In one embodiment, the first gate runner 302 is interposed between a first contact pad 130 and a second contact pad 132 of the metal wiring layer 126. In order to provide an unobstructed view of the power device region 102 and the current sensing region 104 formed in the semiconductor substrate 106, only the outlines of the first contact pad 130 and the second contact pad 132 are shown in FIG. 3.

[0037] Metal wiring layer 126 may further include at least one additional gate runner separate from first gate runner 302. To provide redundant electrical connectivity for gate electrode "G" in power device region 102, gate electrode "G" in power device region 102 is electrically connected to both first gate runner 302 and the at least one additional gate runner. Figure 3 is a partial plan view, and therefore the at least one additional gate runner is out of view, but may be located on another portion of semiconductor substrate 106 to provide another gate connection point for gate electrode "G" in power device region 102.

[0038] The semiconductor device 300 may include a first intersecting trench 308 connecting the first trenches 108 in the region where the second trench 110 is separated along the first side S1 of the current sensing region 104, and a second intersecting trench 310 connecting the first trenches 108 in the region where the second trench 110 is separated along the second (opposite) side S2 of the current sensing region 104. The first intersecting trench 308, the second intersecting trench 310, the first trench 108' disposed closest to the third side S3 of the current sensing region 104, and the first trench 108'' disposed closest to the fourth side S4 of the current sensing region 104 opposite the third side S3 laterally surround the current sensing region 104, such that the body region 116 in the current sensing region 104 is separated from the body region 116 in the power device region 102 by the trenches 308, 310, 108', 108'' that laterally surround the current sensing region 104.

[0039] According to one embodiment, a third intersection trench 312 extends parallel to and is adjacent to the second intersection trench 310. The third interconnect trench 312 connects the gate electrode “G” in the first trench 108 in the region where the second trench 110 is separated along the second side S2 of the current sensing region 104 at a first end 314 of the separation. The second interconnect trench 310 connects the gate electrode “G” in the first trench 108 in the region where the second trench 110 is separated along the second side S2 of the current sensing region 104 at a second end 316 of the separation opposite the first end 314.

[0040] Separating the power device region 102 and the current sensing region 104 by having the first trench 108 along the second side S2 of the current sensing region 104 and intersecting the gate electrode "G" provides gate contact redundancy in that the gate electrode "G" in the first trench 108 is contacted in multiple locations, for example, via the first gate runner 302 along the first side S1 of the current sensing region 104 and the second side S2 of the current sensing region 104.

[0041] 4 shows a simplified plan view of another embodiment of the first trench 108 and the second trench in the boundary region between the power device region 102 and the current sensing region 104, with the trench electrodes and doped device regions omitted for ease of illustration. According to this embodiment, the second trench 110 is divided in a staggered manner in a direction (x-direction in FIG. 4) perpendicular to the longitudinal extension (y-direction in FIG. 4) of the trenches 108, 110. The first trenches are connected between the staggered divisions of the second trench 110 in a ladder-like manner along the widthwise extension (x-direction in FIG. 4) of the trenches 108, 110.

[0042] 5 shows a simplified plan view of another embodiment of a first trench 108 and a second trench in the boundary region between the power device region 102 and the current sense region 104, with the trench electrodes and doped device regions omitted for ease of illustration. According to this embodiment, the first and second trenches 108, 110 in the current sense region 104 are offset or shifted by one trench position in the length direction of the trenches 108, 110 (the y-direction in FIG. 5 ) relative to the first and second trenches 108, 110 in the power device region 102.

[0043] Although the present disclosure is not so limited, the following numbered examples illustrate one or more aspects of the present disclosure. [Example]

[0044] Example 1. A semiconductor device comprising: a power device region formed in a semiconductor substrate, the power device region including a plurality of first trenches and a plurality of second trenches extending parallel to one another in a longitudinal direction, a semiconductor mesa between adjacent ones of the trenches, each first trench including a gate electrode at a first potential, and each second trench including a field plate at a second potential; and a current sensing region formed in the semiconductor substrate, wherein a subset of the first trenches, a subset of the second trenches, and a subset of the semiconductor mesas are common to both the current sensing region and the power device region, and the second trenches are split along opposing first and second sides of the current sensing region, thereby splitting the field plate between the power device region and the current sensing region.

[0045] Example 2. The semiconductor device of Example 1, further including a metal wiring layer above the semiconductor substrate, the metal wiring layer including a first contact pad electrically connected to both the semiconductor mesa and the field plate in the power device region, and a second contact pad separate from the first contact pad and electrically connected to both the semiconductor mesa and the field plate in the current sensing region.

[0046] Example 3. The semiconductor device of Examples 1 or 2, wherein the semiconductor mesa includes a source or emitter region formed by a dopant of a first conductivity type and a body region formed by a dopant of a second conductivity type opposite the first conductivity type, the dopant of the second conductivity type being omitted from the semiconductor mesa or being offset by dopants of the first conductivity type in a peripheral region laterally surrounding the current sensing region.

[0047] Example 4. The semiconductor device of any of Examples 1-3, further including a first intersection trench connecting the first trenches in a region where the second trenches are separated along a first side of the current sense region, and a second intersection trench connecting the first trenches in a region where the second trenches are separated along a second side of the current sense region, wherein the semiconductor mesa includes a source or emitter region of a first conductivity type and a body region of a second conductivity type opposite the first conductivity type, and the first intersection trench, the second intersection trench, the first trench disposed nearest a third side of the current sense region, and the first trench disposed nearest a fourth side of the current sense region opposite the third side laterally surround the current sense region, whereby the body region in the current sense region is separated from the body region in the power device region by the trench laterally surrounding the current sense region.

[0048] Example 5. The semiconductor device of any of Examples 1-4, wherein the first trench is interrupted along the first and second sides of the current sensing region.

[0049] Example 6. The semiconductor device of example 5, wherein the first trench is separated at first and second separation regions, and the second trench is separated at third and fourth separation regions, the first and second separation regions being laterally offset from the third and fourth separation regions along the length of the trench.

[0050] Example 7. The semiconductor device of Example 5 or 6, further comprising a metal wiring layer above the semiconductor substrate, the metal wiring layer comprising a first contact pad electrically connected to both the semiconductor mesa and the field plate in the power device region, a second contact pad separate from the first contact pad and electrically connected to both the semiconductor mesa and the field plate in the current sensing region, and a first gate runner disposed over the first region where the first trench is separated, the gate electrode in the first trench separated in the first region being electrically connected to the first gate runner at both ends of the separation.

[0051] Example 8. The semiconductor device of Example 7, wherein the first gate runner is interposed between the first contact pad and the second contact pad.

[0052] Example 9. The semiconductor device of Example 7 or 8, wherein the metal wiring layer further includes at least one additional gate runner separate from the first gate runner, and the gate electrode in the first trench is electrically connected to the at least one additional gate runner.

[0053] Example 10. The semiconductor device of any of Examples 5-9, further including a first intersection trench connecting the first trenches in a region where the second trenches are separated along a first side of the current sense region, and a second intersection trench connecting the first trenches in a region where the second trenches are separated along a second side of the current sense region, wherein the semiconductor mesa includes a source or emitter region of a first conductivity type and a body region of a second conductivity type opposite the first conductivity type, and the first intersection trench, the second intersection trench, the first trench disposed nearest a third side of the current sense region, and the first trench disposed nearest a fourth side of the current sense region opposite the third side laterally surround the current sense region, whereby the body region in the current sense region is separated from the body region in the power device region by the trench laterally surrounding the current sense region.

[0054] Example 11. The semiconductor device of Example 10, further including a third intersecting trench extending parallel to and adjacent to the second intersecting trench, wherein the third interconnect trench connects the gate electrodes in the first trench in the region where the second trench is separated along the second side of the current sensing region at a first end of the separation, and the second interconnect trench connects the gate electrodes in the first trench in the region where the second trench is separated along the second side of the current sensing region at a second end of the separation opposite the first end.

[0055] Example 12. A method of fabricating a semiconductor device, the method including: forming a power device region in a semiconductor substrate, the power device region including a plurality of first trenches and a plurality of second trenches extending parallel to one another in a longitudinal direction, a semiconductor mesa between adjacent ones of the trenches, each first trench including a gate electrode at a first potential, and each second trench including a field plate at a second potential; and forming a current sense region in the semiconductor substrate, the current sense region including a subset of the first trenches, a subset of the second trenches, and a subset of the semiconductor mesas being common to both the current sense region and the power device region, and forming the power device includes forming the second trenches to be split along opposing first and second sides of the current sense region, whereby the field plate is split between the power device region and the current sense region.

[0056] Example 13. The method of Example 12, further comprising forming a metal wiring layer above the semiconductor substrate, the metal wiring layer comprising a first contact pad electrically connected to both the semiconductor mesa and the field plate in the power device region, and a second contact pad separate from the first contact pad and electrically connected to both the semiconductor mesa and the field plate in the current sensing region.

[0057] Example 14. The method of Example 12 or 13, further comprising: implanting dopants of a first conductivity type into the semiconductor mesa to form a source or emitter region; implanting dopants of a second conductivity type opposite the first conductivity type into the semiconductor mesa to form a body region; and omitting the dopants of the second conductivity type from the semiconductor mesa or offsetting the dopants of the second conductivity type by dopants of the first conductivity type in a peripheral region laterally surrounding the current sensing region.

[0058] Example 15. The method of any of Examples 12-14, further comprising: forming a first intersection trench connecting the first trenches in a region where the second trenches are separated along a first side of the current sense region; and forming a second intersection trench connecting the first trenches in a region where the second trenches are separated along a second side of the current sense region, wherein the first intersection trench, the second intersection trench, the first trench disposed nearest a third side of the current sense region, and the first trench disposed nearest a fourth side of the current sense region opposite the third side laterally surround the current sense region, thereby separating the body region in the current sense region from the body region in the power device region by the trench laterally surrounding the current sense region.

[0059] Example 16. The method of any of Examples 12-15, further comprising forming a first trench such that the first trench is separated along the first and second sides of the current sensing region.

[0060] Example 17. The method of Example 16, further comprising: forming a metal wiring layer above the semiconductor substrate, the metal wiring layer including a first contact pad electrically connected to both the semiconductor mesa and the field plate in the power device region, a second contact pad separate from the first contact pad and electrically connected to both the semiconductor mesa and the field plate in the current sensing region, and a first gate runner disposed over a first region where the first trench is separated; and electrically connecting a gate electrode in the first trench separated in the first region to the first gate runner at both ends of the separation.

[0061] Example 18. The method of example 17, wherein the first gate runner is interposed between the first contact pad and the second contact pad.

[0062] Example 19. The method of Example 17 or 18, wherein the metal wiring layer further includes at least one additional gate runner separate from the first gate runner, and the method further includes electrically connecting the gate electrode in the first trench to the at least one additional gate runner.

[0063] Example 20. The method of any of Examples 16-19, further comprising: forming a first intersection trench connecting the first trenches in a region where the second trenches are separated along a first side of the current sense region; and forming a second intersection trench connecting the first trenches in a region where the second trenches are separated along a second side of the current sense region, wherein the first intersection trench, the second intersection trench, the first trench disposed nearest a third side of the current sense region, and the first trench disposed nearest a fourth side of the current sense region opposite the third side laterally surround the current sense region, thereby separating the body region in the current sense region from the body region in the power device region by the trenches laterally surrounding the current sense region.

[0064] Example 21. The method of Example 20, further comprising: forming a third intersection trench extending parallel to and adjacent to the second intersection trench; connecting, via a third interconnect trench, the gate electrodes in the first trench in the region where the second trench is separated along the second side of the current sensing region at a first end of the separation; and connecting, via a second interconnect trench, the gate electrodes in the first trench in the region where the second trench is separated along the second side of the current sensing region at a second end of the separation opposite the first end.

[0065] Terms such as "first," "second," and the like are used to describe various elements, regions, areas, etc., and are also not intended to be limiting. Like terms refer to like elements throughout this description.

[0066] As used herein, the terms "having," "containing," "including," "comprising," and the like are open-ended terms indicating the presence of stated elements or features, but not excluding additional elements or features. The articles "a," "an," and "the" are intended to include both the plural and the singular unless the context clearly dictates otherwise.

[0067] While specific embodiments have been illustrated and described herein, it will be understood by those skilled in the art that various alternative and / or equivalent implementations may be substituted for the specific embodiments illustrated and described without departing from the scope of the invention. This application is intended to cover any adaptations or variations of the specific embodiments described herein. Therefore, it is intended that the invention be limited only by the claims and their equivalents. [Explanation of symbols]

[0068] 100, 200, 300 semiconductor devices 102 Power Devices 104 Current sensing area 106 Semiconductor substrate 107 Gate insulating film 108, 108', 108'' First trench 109 Field insulating film 110 Second Trench 112 Semiconductor Mesa 114 Emitter / Source Region 116 Body area 118 Drift Zone 120 Collector Region 122 Field Stop Region 124 First metal wiring layer 126 Second Metal Wiring Layer 128 Interlayer insulating film 130 first contact pad 132 Second Contact Pad 134 Surrounding Area 202, 308 First Intersection Trench 204, 310 Second cross trench 302 First Gate Runner 304, 306 End 312 Third Intersection Trench 314 First End 316 Second End S1 First aspect S2 Second Aspect S3 The third aspect S4 The Fourth Aspect

Claims

1. a power device region formed in a semiconductor substrate, the power device region including a plurality of first trenches and a plurality of second trenches extending parallel to one another in a longitudinal direction, a semiconductor mesa between adjacent ones of the trenches, each first trench including a gate electrode at a first potential and each second trench including a field plate at a second potential; a current sensing region formed in the semiconductor substrate; Including, a subset of the first trenches, a subset of the second trenches, and a subset of the semiconductor mesas are common to both the current sensing region and the power device region; each of the second trenches is split at two locations along first and second opposing parallel sides of the current sensing region, thereby splitting the field plate between the power device region and the current sensing region.

2. 2. The semiconductor device of claim 1, further comprising a metal wiring layer over the semiconductor substrate, the metal wiring layer comprising: a first contact pad electrically connected to both the semiconductor mesa and the field plate in the power device region; and a second contact pad separate from the first contact pad and electrically connected to both the semiconductor mesa and the field plate in the current sensing region.

3. 2. The semiconductor device of claim 1, wherein the semiconductor mesa includes a source or emitter region formed with dopants of a first conductivity type and a body region formed with dopants of a second conductivity type opposite the first conductivity type, the dopants of the second conductivity type being omitted from the semiconductor mesa or offset by the dopants of the first conductivity type in a peripheral region laterally surrounding the current sensing region.

4. a first intersection trench connecting the first trench in a region where the second trench is interrupted along the first side of the current sensing region; a second intersecting trench connecting the first trench in a region where the second trench is interrupted along the second side of the current sensing region; further comprising the semiconductor mesa includes a source or emitter region of a first conductivity type and a body region of a second conductivity type opposite the first conductivity type; 2. The semiconductor device of claim 1, wherein the first intersection trench, the second intersection trench, the first trench disposed nearest a third side of the current sense region, and the first trench disposed nearest a fourth side of the current sense region opposite the third side laterally surround the current sense region, such that the body region in the current sense region is separated from the body region in the power device region by the trenches laterally surrounding the current sense region.

5. The semiconductor device of claim 1 , wherein the first trench is interrupted along the first and second sides of the current sensing region.

6. 6. The semiconductor device of claim 5, wherein the first trench is separated by first and second separation regions, the second trench is separated by third and fourth separation regions, and the first and second separation regions are laterally offset from the third and fourth separation regions along the length of the trench.

7. further comprising a metal wiring layer above the semiconductor substrate; The metal wiring layer a first contact pad electrically connected to both the semiconductor mesa and the field plate within the power device region; a second contact pad separate from the first contact pad and electrically connected to both the semiconductor mesa and the field plate within the current sensing region; and a first gate runner disposed over a first region where the first trench is divided; Including, 6. The semiconductor device of claim 5, wherein the gate electrode in the first trench that is separated in the first region is electrically connected to the first gate runner at both ends of the separation.

8. 8. The semiconductor device of claim 7, wherein the first gate runner is interposed between the first contact pad and the second contact pad.

9. The metal wiring layer further comprising at least one additional gate runner separate from the first gate runner; The semiconductor device of claim 7 , wherein the gate electrode in the first trench is electrically connected to the at least one additional gate runner.

10. a first intersection trench connecting the first trench in a region where the second trench is interrupted along the first side of the current sensing region; a second intersecting trench connecting the first trench in a region where the second trench is interrupted along the second side of the current sensing region; further comprising the semiconductor mesa includes a source or emitter region of a first conductivity type and a body region of a second conductivity type opposite the first conductivity type; 6. The semiconductor device of claim 5, wherein the first intersection trench, the second intersection trench, the first trench disposed nearest a third side of the current sense region, and the first trench disposed nearest a fourth side of the current sense region opposite the third side laterally surround the current sense region, such that the body region in the current sense region is separated from the body region in the power device region by the trenches laterally surrounding the current sense region.

11. a third intersecting trench extending parallel to and adjacent to the second intersecting trench; a third interconnect trench connecting the gate electrodes in the first trenches in the region where the second trench is separated along the second side of the current sensing region at a first end of the separation; 11. The semiconductor device of claim 10, wherein a second interconnect trench connects the gate electrodes in the first trenches in the region where the second trench is interrupted along the second side of the current sensing region at a second end of the interruption opposite the first end.

12. 1. A method of fabricating a semiconductor device, the method comprising: forming a power device region in a semiconductor substrate, the power device region including a plurality of first trenches and a plurality of second trenches extending parallel to one another in a longitudinal direction, a semiconductor mesa between adjacent ones of the trenches, each first trench including a gate electrode at a first potential and each second trench including a field plate at a second potential; forming a current sensing region in the semiconductor substrate, wherein a subset of the first trenches, a subset of the second trenches, and a subset of the semiconductor mesas are common to both the current sensing region and the power device region; Including, forming the power device region includes forming each of the second trenches to be split in two along first and second opposing parallel sides of the current sense region, thereby causing the field plate to be split between the power device region and the current sense region.

13. 13. The method of claim 12, further comprising forming a metal wiring layer over the semiconductor substrate, the metal wiring layer including a first contact pad electrically connected to both the semiconductor mesa and the field plate in the power device region, and a second contact pad separate from the first contact pad and electrically connected to both the semiconductor mesa and the field plate in the current sensing region.

14. implanting dopants of a first conductivity type into the semiconductor mesa to form a source or emitter region; implanting dopants of a second conductivity type opposite to the first conductivity type into the semiconductor mesa to form a body region; omitting the dopants of the second conductivity type from the semiconductor mesa or offsetting the dopants of the second conductivity type by the dopants of the first conductivity type in a peripheral region laterally surrounding the current sensing region; The method of claim 12 further comprising:

15. forming a first intersection trench connecting the first trench in a region where the second trench is interrupted along the first side of the current sensing region; forming a second intersecting trench connecting the first trench in a region where the second trench is interrupted along the second side of the current sensing region; further comprising 13. The method of claim 12, wherein the first intersection trench, the second intersection trench, the first trench disposed nearest a third side of the current sense region, and the first trench disposed nearest a fourth side of the current sense region opposite the third side laterally surround the current sense region, whereby a body region within the current sense region is separated from a body region within the power device region by the trenches laterally surrounding the current sense region.

16. The method of claim 12 , further comprising forming the first trench so that it is separated along the first and second sides of the current sensing region.

17. forming a metal wiring layer over the semiconductor substrate, the metal wiring layer including: a first contact pad electrically connected to both the semiconductor mesa and the field plate in the power device region; a second contact pad separate from the first contact pad and electrically connected to both the semiconductor mesa and the field plate in the current sensing region; and a first gate runner disposed over a first region where the first trench is separated; electrically connecting the gate electrode in the first trench separated in the first region to the first gate runner at both ends of the separation; 17. The method of claim 16, further comprising:

18. 18. The method of claim 17, wherein the first gate runner is interposed between the first contact pad and the second contact pad.

19. the metal wiring layer further includes at least one additional gate runner separate from the first gate runner, and the method further comprises:

18. The method of claim 17, further comprising electrically connecting the gate electrode in the first trench to the at least one additional gate runner.

20. forming a first intersection trench connecting the first trench in a region where the second trench is interrupted along the first side of the current sensing region; forming a second intersecting trench connecting the first trench in a region where the second trench is interrupted along the second side of the current sensing region; further comprising 17. The method of claim 16, wherein the first intersection trench, the second intersection trench, the first trench disposed nearest a third side of the current sense region, and the first trench disposed nearest a fourth side of the current sense region opposite the third side laterally surround the current sense region, whereby a body region within the current sense region is separated from a body region within the power device region by the trenches laterally surrounding the current sense region.

21. forming a third intersection trench extending parallel to and adjacent to the second intersection trench; connecting, via a third interconnect trench, the gate electrode in the first trench in the region where the second trench is separated along the second side of the current sensing region at a first end of the separation; connecting, via a second interconnect trench, the gate electrode in the first trench in the region where the second trench is separated along the second side of the current sensing region at a second end of the separation opposite the first end; 21. The method of claim 20, further comprising:

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