Power Conversion Device

Abstract

To provide a power conversion device that can reduce costs.SOLUTION: A power conversion device includes a multilevel converter and a general-purpose microcontroller. The multilevel converter is connected to a three-phase AC power source to which a load is connected in parallel with the load, and each phase of the three-phase AC power source has a cluster consisting of a plurality of unit converters connected in series. The general-purpose microcontroller includes: a conversion unit that converts detection signals for the current flowing through the load and the voltage of the three-phase AC power source from analog to digital or from digital to analog; a main control unit for setting the output voltage of each cluster necessary for suppressing harmonic components contained in the current flowing through the load on the basis of the output of the conversion unit; and a generation unit for generating a control signal for each unit converter according to the setting of the main control unit.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] An embodiment of the present invention relates to a power conversion device that is connected in parallel to a three-phase AC power supply to which a load is connected. [Background technology]

[0002] BACKGROUND ART Power conversion devices such as active filters are known that are connected in parallel to a three-phase AC power supply to which a load such as an air conditioner is connected, and that suppress harmonic components contained in the current flowing through the load. This power conversion device includes, for example, a multilevel converter, which has a cluster formed by connecting a plurality of unit converters in series for each phase of a three-phase AC power supply, and outputs a compensation current for suppressing harmonic components in the current flowing through a load. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2013-255422 [Patent Document 2] International Publication No. 2020 / 016960 [Non-patent literature]

[0004] [Non-Patent Document 1] IEEJ Transactions on Electrical Engineering, Vol. 128, No. 7, pp. 957-965, 2008 Summary of the Invention [Problem to be solved by the invention]

[0005] The power conversion device includes a controller for controlling the switching of each unit converter of the multilevel converter. This controller is expensive because it is designed specifically to suit the individual specifications of the multilevel converter, which is a major factor in increasing costs.

[0006] An object of the embodiments of the present invention is to provide a power conversion device that can reduce costs. [Means for solving the problem]

[0007] A power conversion device according to an embodiment includes a multilevel converter connected in parallel to a three-phase AC power supply to which a load is connected, the multilevel converter having a cluster formed by connecting a plurality of unit converters in series for each phase of the three-phase AC power supply; and a general-purpose microcontroller including: a conversion unit that performs analog-to-digital conversion of detection signals for a current flowing through the load and a voltage of the three-phase AC power supply; a main control unit that sets, based on the output of the conversion unit, an output voltage of each cluster required to suppress harmonic components contained in the current flowing through the load; and a generation unit that generates a control signal for each unit converter in accordance with the setting of the main control unit. Each of the unit converters consists of multiple switch elements and one capacitor, and selectively outputs multiple levels of DC voltage by switching each switch element. The microcontroller is a general-purpose first microcontroller that controls unit converters of each cluster whose number of series-connected stages is up to a specified value, and a general-purpose second microcontroller that controls unit converters of each cluster whose number of series-connected stages exceeds the specified value. The conversion unit is a first conversion unit housed in the first microcontroller that performs analog-to-digital conversion on a detection signal for a current flowing through the load, a detection signal for a current flowing between the multilevel converter and each power line of the three-phase AC power supply, a detection signal for the phase of the power supply voltage of the three-phase AC power supply, and a detection signal for the capacitor voltage in the unit converters whose number of series-connected stages is up to the specified value, and a second conversion unit housed in the second microcontroller that performs analog-to-digital conversion on a detection signal for the capacitor voltage in the unit converters whose number of series-connected stages exceeds the specified value. The main control unit is contained in the first microcontroller and sets the output voltage of each cluster required to suppress harmonic components contained in the current flowing to the load based on the output of the first conversion unit and the output of the second conversion unit.The generating unit is a first generating unit contained in the first microcontroller, and generates switching control signals for unit converters up to the specified value by performing pulse width modulation for each cluster to compare the voltage level of a carrier signal corresponding to unit converters whose number of series-connected stages exceeds the specified value with the output voltage level set by the main control unit, out of a plurality of carrier signals that are the same number as the number of series-connected stages of each unit converter in each cluster but have different phases from each other; and a second generating unit contained in the second microcontroller, and generates switching control signals for unit converters whose number of series-connected stages exceeds the specified value by performing pulse width modulation for each cluster to compare the voltage level of a carrier signal corresponding to unit converters whose number of series-connected stages exceeds the specified value with the output voltage level set by the main control unit. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a block diagram showing the configuration of a first embodiment. [Figure 2] FIG. 2 is a block diagram showing the configuration of each unit converter according to the first embodiment. [Figure 3] FIG. 3 is a diagram showing an on / off pattern of switching by pseudo three-level modulation according to the first embodiment. [Figure 4] FIG. 4 is a diagram showing generation of a control signal by PWM modulation for each cluster in the first embodiment. [Figure 5] FIG. 2 is a block diagram showing the configuration of a main control unit of the microcontroller according to the first embodiment. [Figure 6] FIG. 4 is a diagram showing the timing of A / D conversion and duty calculation in the first embodiment. [Figure 7] FIG. 10 is a block diagram showing the configuration of second and third embodiments. [Figure 8] FIG. 10 is a block diagram showing the configuration of each unit converter and an auxiliary switch circuit according to a third embodiment. [Figure 9] FIG. 10 is a diagram showing a specific configuration of an auxiliary switch circuit according to a third embodiment. [Figure 10] 10 is a time chart showing the relationship between each control signal and the operation of the auxiliary switch circuit according to the third embodiment. [Figure 11] 11 is a diagram showing the operation of each switch element and the current path when A1, A4="1" and A2, A3="0" in FIG. 10. [Figure 12] 11 is a diagram showing the operation of each switch element and the current path when A1, A3="0" and A2, A4="1" in FIG. 10. [Figure 13] 11 is a diagram showing the operation of each switch element and the current path when A1, A3="1" and A2, A4="0" in FIG. 10. [Figure 14] 11 is a diagram showing the operation of each switch element and the current path during the dead time when A1="1" and A2 to A4="0" in FIG. 10. [Figure 15] FIG. 11 is a diagram showing the configuration of a modified example of the auxiliary switch circuit in the third embodiment. [Figure 16] 10A and 10B are diagrams showing another example of the operation of each switch element and a current path according to the third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] [1] A first embodiment of the present invention will be described with reference to the drawings. 1, a load according to this embodiment, such as an air conditioner 2, is connected to power supply lines Lu, Lv, and Lw of a three-phase AC power supply 1. The air conditioner 2 includes a rectifier circuit 3 that rectifies power supply voltages Eu, Ev, and Ew using a plurality of bridge-connected diodes, a capacitor 5 that receives the output voltage of this rectifier circuit 3 via a DC reactor 4, an inverter 6 that converts the voltage of this capacitor 5 into an AC voltage of a predetermined frequency and outputs it, and a compressor motor 7 that operates using the output of this inverter 6.

[0010] A power conversion device 10 of this embodiment is connected to the power supply lines Lu, Lv, and Lw in a parallel relationship with the air conditioner 2.

[0011] The power conversion device 10 is a so-called active filter and includes reactors 11u, 11v, and 11w, a multilevel converter 20 connected to power supply lines Lu, Lv, and Lw via these reactors 11u, 11v, and 11w, a detection unit 12 located on the power supply lines Lu, Lv, and Lw closer to the air conditioner 2 than the connection position of the multilevel converter 20 and detecting currents (load currents) Iu, Iv, and Iw flowing to the air conditioner 2, a detection unit 13 detecting currents (compensation currents) Icu, Icv, and Icw flowing in the current path between the power supply lines Lu, Lv, and Lw and the multilevel converter 20, a detection unit 14 detecting the phases of power supply voltages Eu, Ev, and Ew of the three-phase AC power supply 1, and a general-purpose microcontroller (first microcontroller) 40 that controls the multilevel converter 20 in accordance with the detection results of these detection units 12, 13, and 14, and supplies compensation currents for suppressing harmonic components of the current flowing to the air conditioner 2 to the power supply lines Lu, Lv, and Lw.

[0012] The multilevel converter 20 has clusters 21u, 21v, and 21w that selectively generate and output three or more levels of DC voltage for each phase of the three-phase AC power supply 1. One end of each of these clusters 21u to 21w is connected to power supply lines Lu to Lw, and the other ends of each of the clusters 21u to 21w are interconnected (star-connected).

[0013] Cluster 21u is a so-called multi-series converter cluster configured by serially connecting (cascading) a plurality of unit converters (cells) S1, S2, and S3, each of which selectively generates and outputs a multi-level (multi-level) DC voltage by switching. By adding together the output voltages (cell output voltages) Vcu1, Vcu2, and Vcu3 of unit converters S1 to S3, cluster 21u generates and outputs an AC voltage Vcu0 (=Vcu1+Vcu2+Vcu3) with a waveform close to a sine wave to reduce harmonics.

[0014] Clusters 21v and 21w are also multi-series converter clusters configured by serially connecting a plurality of unit converters S1, S2, S3, each of which selectively generates and outputs multiple levels of DC voltage by switching, and by adding together the output voltages Vcv1 to Vcv3, Vcw1 to Vcw3 of the unit converters S1 to S3, they generate and output AC voltages Vcv0 (= Vcv1 + Vcv2 + Vcv3), Vcw0 (= Vcw1 + Vcw2 + Vcw3) with waveforms close to sine waves to reduce harmonics.

[0015] The AC voltages Vcu0, Vcv0, Vcw0 are output from the clusters 21u to 21w, and are supplied to the compensation current power supply lines Lu to Lw for suppressing harmonic components contained in the load currents Iu to Iw.

[0016] The configuration of the unit converters S1 to S3 is shown in FIG. The unit converter S1 includes a first switching leg (first series circuit) consisting of switch elements Q1 and Q2 connected in series, a second switching leg (second series circuit) consisting of switch elements Q3 and Q4 connected in series and connected in parallel to the first switching leg, a capacitor C connected in parallel to the second switching leg, and a voltage detector 22 that detects the voltage (capacitor voltage) Vc across the capacitor C. The interconnection point of switch elements Q1 and Q2 and the interconnection point of switch elements Q3 and Q4 serve as output terminals, and the converter selectively generates and outputs a multi-level (positive, zero, negative) DC voltage Vcu1 by combining an operation of turning one of switch elements Q1 and Q2 on and the other off and an operation of turning one of switch elements Q3 and Q4 on and the other off. Each of switch elements Q1 to Q4 is a MOSFET with a freewheeling diode D, but other semiconductor switching elements, such as IGBTs, may also be used.

[0017] The unit converters S2 and S3 have the same configuration as the unit converter S1, and selectively generate and output multi-level DC voltages Vcu2 and Vcu3, respectively.

[0018] During the positive level period of the AC voltage Eu, by turning on the switch elements Q2 and Q4 of the unit converter S1 and turning off the switch elements Q1 and Q3, a bypass current path for the capacitor C is formed through the switch elements Q2 and Q4 as shown by the solid arrows, and a zero-level cell output voltage Vcu1 (=0) is generated at the output terminal. During the positive level period of the AC voltage Eu, by turning on the switch elements Q1 and Q3 of the unit converter S2 and turning off the switch elements Q2 and Q4, a bypass current path for the capacitor C is formed through the switch elements Q1 and Q3 as shown by the solid arrows, and a zero-level cell output voltage Vcu2 (=0) is generated at the output terminal. There are two ways to generate the zero-level cell output voltage: turning on the switch elements Q2 and Q4 as in the unit converter S1, or turning on the switch elements Q1 and Q3 as in the unit converter S2, and either method can be used.

[0019] During a period when the AC voltage Eu is at a positive level, by turning on switch elements Q1 and Q4 of unit converter S3 and turning off switch elements Q2 and Q3, a current path to capacitor C is formed through switch elements Q1 and Q4 as shown by the solid arrows, and a positive-level cell output voltage Vcu3 (= +Vc) based on the voltage Vc of capacitor C is generated at the output terminal. Also, during a period when the AC voltage Eu is at a negative level, by turning on switch elements Q2 and Q3 of unit converter S3 and turning off switch elements Q1 and Q4, a current path to capacitor C is formed through switch elements Q2 and Q3 as shown by the dashed arrows, and a negative-level cell output voltage Vcu3 (= -Vc) based on the voltage Vc of capacitor C is generated at the output terminal.

[0020] Here, the on / off switching of switch elements Q1 to Q4 to obtain multiple levels of cell output voltage Vcu1 from unit converter S1 is performed using three-level modulation (hereinafter referred to as "pseudo three-level modulation switching") that reduces the number of wirings for on / off command signals, as disclosed in Japanese Patent Application Publication No. 2021-166430 (Patent Application No. 2020-068470) invented by the present inventors. The relationship between the on / off pattern of switch elements Q1 to Q4 in this pseudo three-level modulation switching and cell output voltage Vcu1 is shown in Figure 3.

[0021] The microcontroller (first microcontroller) 40 is a general-purpose microcontroller for inverter control, such as that installed in the air conditioner 2, and is composed of an A / D conversion unit (first conversion unit) 41, a main control unit 42, a PWM generation unit (first generation unit) 43, and a clock generation unit 44 housed in a single integrated circuit, and performs pseudo three-level modulation switching using pulse width modulation (PWM) as shown in Figure 4.

[0022] The A / D conversion unit 41 performs analog-to-digital conversion on the detection signals of the detection unit 12 that detects the load currents Iu, Iv, and Iw, the detection signals of the detection unit 13 that detects the compensation currents Icu, Icv, and Icw, the detection signals of the detection unit 14 that detect the phases of the power supply voltages Eu, Ev, and Ew, and the detection signals (detection signals of the voltage detector 22) for the capacitor voltages Vc of the unit converters S1 to S3.

[0023] The main control unit 42 sets the output voltages (AC voltages) Vcu0 to Vcw0 of the clusters 21u to 21w necessary for suppressing harmonic components contained in the load currents Iu to Iw based on the output of the A / D conversion unit 41. That is, the main control unit 42 sets an AC voltage command value Vcu sin θ for causing the cluster 21u to generate and output the AC voltage Vcu0 having substantially the same waveform as the power supply voltage Eu, an AC voltage command value Vcv sin(θ-2π / 3) for causing the cluster 21v to generate and output the AC voltage Vcv0 having substantially the same waveform as the power supply voltage Ev, and an AC voltage command value Vcw sin(θ+2π / 3) for causing the cluster 21w to generate and output the AC voltage Vcw0 having substantially the same waveform as the power supply voltage Ew. The AC voltage command values ​​Vcu sin θ, Vcv sin(θ-2π / 3), and Vcw sin(θ+2π / 3) are shifted in phase from one another by 120°.

[0024] The PWM generation unit 43 generates switching control signals Gu1 to Gu3' (described later) for the unit converters S1 to S3 of the clusters 21u to 21w in accordance with the levels (respective AC voltage command values) of the output voltages Vcu0 to Vcw0 set by the main control unit 42. That is, the PWM generation unit 43 generates switching control signals (also referred to as drive signals or gate signals) Gu1, Gu1' for the switch elements Q1 to Q4 of the unit converters S1 to S3 by pulse width modulation that compares the voltage levels of triangular wave carrier signals V1, V2, V3, which are the same number as the number of series-connected stages of the unit converters S1 to S3 in the cluster 21u and have different phases, with the voltage level of the AC voltage command value Vcu sin θ. Similarly, PWM generation unit 43 generates switching control signals Gu2, Gu2', Gu3, and Gu3' for switch elements Q1 to Q4 of unit converters S1 to S3 of clusters 21v and 21w by pulse width modulation that compares the voltage levels of carrier signals V1, V2, and V3 with the voltage levels of AC voltage command values ​​Vcv sin(θ-2π / 3) and Vcw sin(θ+2π / 3), respectively. The phases of carrier signals V1, V2, and V3 are shifted by 120° (=360° / 3), which is the value obtained by dividing one cycle (360°) by the number of stages "3" of series-connected unit converters S1 to S3.

[0025] The control signal (first control signal) Gu1 is supplied to the two unit converters S1 and S2 in the first and second stages, which are adjacent to each other in the series connection of the unit converters S1 to S3, and turns on and off the switch element Q1 in the unit converter S1 and the switch element Q4 in the unit converter S2 in sync with each other. The control signal (second control signal) Gu1' is the logical level of the control signal Gu1 inverted by an inverter 23 (a complementary signal of Gu1), and like the control signal Gu1, is supplied to the two unit converters S1 and S2 in the first and second stages, and turns on and off the switch element Q2 in the unit converter S1 and the switch element Q3 in the unit converter S2 in sync with each other. Note that "inversion" here refers to the state of the drive signal that forms the basis for each switching element Q1 to Q4; in actual driving of the switching elements Q1 to Q4, a dead time period is provided between switches in which the two elements that perform complementary operations are simultaneously turned off to prevent them from being turned on at the same time, i.e., short-circuited.

[0026] The control signal (third control signal) Gu2 is supplied to the unit converters S2 and S3 in the second and third (Nth) stages adjacent to each other in the series connection of the unit converters S1 to S3, and turns on and off the switch element Q1 in the unit converter S2 and the switch element Q4 in the unit converter S3 in sync with each other. The control signal (fourth control signal) Gu2' is the logical level of the control signal Gu2 inverted by an inverter 23 (a complementary signal of Gu2), and like the control signal Gu2, is supplied to the two unit converters S2 and S3 in the second and third stages, and turns on and off the switch element Q2 in the unit converter S2 and the switch element Q3 in the unit converter S3 in sync with each other.

[0027] The control signal (fifth control signal) Gu3 is supplied to the two unit converters S3 and S1 in the third and first stages of the series connection of the unit converters S1 to S3, and turns on and off the switch element Q1 in the unit converter S3 and the switch element Q4 in the unit converter S1 in synchronous with each other. The control signal (sixth control signal) Gu3' is the logical level of the control signal Gu3 inverted by an inverter 23 (a complementary signal of Gu3), and like the control signal Gu3, is supplied to the two unit converters S3 and S1 in the third and first stages, and turns on and off the switch element Q2 in the unit converter S3 and the switch element Q3 in the unit converter S1 in synchronous with each other.

[0028] When generating these control signals Gu1 to Gu3', the PWM generating unit 43 ensures dead time between the on and off states of the switch elements Q1 and Q2 arranged in series with each other in the unit converters S1 to S3, and between the on and off states of the switch elements Q3 and Q4 arranged in series with each other, during which they are in the off state to prevent short circuits.

[0029] The clock generating unit 44 generates a control clock signal necessary for the operation of the microcontroller 40 .

[0030] The main control unit 42 includes a voltage control unit 42a and a current control unit 42b shown in FIG. 5 as main components for setting the AC voltage command values ​​Vcu sin θ, Vcv sin(θ−2π / 3), and Vcw sin(θ+2π / 3).

[0031] The voltage control unit 42a performs individual balance control to individually balance the capacitor voltages Vc of the unit converters S1 to S3 in the clusters 21u to 21w, collective capacitor voltage control to make all average values ​​of the capacitor voltages Vc of the unit converters S1 to S3 in the clusters 21u to 21w follow a predetermined target value, and inter-phase balance control to balance the average values ​​of the capacitor voltages Vc of the unit converters S1 to S3 in the clusters 21u to 21w for each phase.

[0032] The current control unit 42b performs dq transformation on the detected load currents Iu, Iv, and Iw through a low-pass filter and inputs the output result to the low-pass filter to extract the DC component. Furthermore, the current control unit 42b extracts harmonic components by subtracting the extracted DC component from the dq-transformed output, and calculates current command values ​​for the compensation currents Icu, Icv, and Icw based on the extracted harmonic components and the calculation results of the capacitor voltage collective control and the interphase balance control. The current control unit 42b then inputs the difference between the calculated current command value and the actually detected values ​​of the compensation currents Icu, Icv, and Icw to a current controller and performs inverse dq transformation on the output of the current controller. The main control unit 42 adds the calculation result of the individual balance control to this inverse dq transformation, and divides the sum by the capacitor voltage Vc of each of the unit converters S1 to S3 in the clusters 21u, 21v, and 21w to obtain the AC voltage command values ​​Vcu sinθ, Vcv sin(θ-2π / 3), and Vcw sin(θ+2π / 3), which are duty command values.

[0033] FIG. 6 shows the timing of the A / D conversion process by the A / D converter 41 and the duty calculation by the main controller 42, taking as an example PWM control for the cluster 21u. If the frequency of carrier signals V1, V2, and V3 is Fc [Hz] and duty calculation is performed by interrupt processing at the timing of the peaks or valleys of the waveforms of carrier signals V1, V2, and V3, the operation frequency of the duty calculation will be 6Fc [Hz]. The main control unit 42 starts analog-to-digital conversion processing at or near the timing of the valleys of the carrier signal waveform, thereby fetching necessary information related to current and voltage, performs duty calculation based on the fetched information, sets the calculation result in an internal PWM output register, and reflects (updates) the set content as a new duty command value at the timing of the peaks of the carrier signal waveform.

[0034] As described above, by using a general-purpose microcontroller 40 for inverter control, such as that installed in the air conditioner 2, as a controller for switching control of the multilevel converter 20, costs can be reduced compared to using a controller specially designed to match the specifications of the multilevel converter 20.

[0035] [2] Second embodiment When the three-phase AC power supply 1 and the power supply lines Lu, Lv, and Lw are a high-voltage AC system, in order to enable the active filter 10 to withstand high voltages, it is necessary to increase the withstand voltage of each switch element of the multilevel converter 20 and / or increase the number of series-connected stages of each unit converter for each cluster in the multilevel converter 20. However, since the on-resistance and recovery charge amount of the switch element are proportional to the withstand voltage of the switch element, there is a problem in that using switch elements with a high withstand voltage increases losses.

[0036] Increasing the number of stages in which each unit converter is connected in series makes it possible to connect the active filter 10 to a high-voltage AC system without employing switching elements with high voltage resistance, that is, without increasing losses. However, if the number of stages in which each unit converter is connected in series is large, it becomes difficult to control all of the unit converters using only a general-purpose microcontroller 40. The second embodiment addresses this issue.

[0037] 7, cluster 21u connects n (more than three) unit converters S1 to Sn in series and adds together the output voltages Vcu1 to Vcun of the unit converters to generate and output AC voltage Vcu0 having a waveform close to a sine wave for reducing harmonics. Clusters 21v and 21w also connect n unit converters S1 to Sn in series and add together the output voltages Vcv1 to Vcvn and Vcw1 to Vcwn of the unit converters to generate and output AC voltages Vcv0 and Vcw0 having waveforms close to a sine wave for reducing harmonics.

[0038] The active filter 10 includes a general-purpose microcontroller (first microcontroller) 40 as a master controller for controlling switching of the multilevel converter 20, the master controller controlling unit converters S1 to S3 having a specified number of stages in series connection, for example, up to "3," and a general-purpose microcontroller (second microcontroller) 50 as a slave controller subordinate to the microcontroller 40, the slave controller controlling unit converters S4 to Sn having a number of stages in series connection exceeding the specified value.

[0039] As in the first embodiment, the microcontroller 40 is a general-purpose microcontroller for inverter control that is mounted on the air conditioner 2 and that includes an A / D conversion unit (first conversion unit) 41, a main control unit 42, a PWM generation unit (second generation unit) 43, and a clock generation unit 44 on a single integrated circuit. The microcontroller 50 is a general-purpose microcontroller for inverter control that is mounted on the air conditioner 2 and that includes an A / D conversion unit (second conversion unit) 51 and a PWM generation unit (second generation unit) 52 on a single integrated circuit.

[0040] As in the first embodiment, the A / D conversion unit 41 of the microcontroller 40 performs analog / digital conversion on the detection signals of the detection unit 12 that detects the load currents Iu to Iw, the detection signals of the detection unit 13 that detects the compensation currents Icu to Icw, the detection signals of the detection unit 14 that detects the phases of the power supply voltages Eu to Ew, and the detection signals (detection signals of the voltage detector 22) for the capacitor voltages Vc of the unit converters S1 to S3 whose number of stages in series connection is up to the specified value.

[0041] The A / D conversion unit 51 of the microcontroller 50 performs analog-to-digital conversion on the detection signals (detection signals of the voltage detector 22) for the capacitor voltages Vc of the unit converters S4 to Sn whose number of series-connected stages exceeds the above-mentioned specified value, and sends the converted output to the main control unit 42 of the microcontroller 40.

[0042] The main control unit 42 of the microcontroller 40 sets the output voltages (AC voltages) Vcu0 to Vcw0 of the clusters 21u to 21w required to suppress harmonic components contained in the load currents Iu to Iw based on the outputs of the A / D conversion units 41, 51. That is, the main control unit 42 sets an AC voltage command value Vcu sin θ for causing the cluster 21u to generate and output an AC voltage Vcu0 having substantially the same waveform as the power supply voltage Eu, an AC voltage command value Vcv sin(θ-2π / 3) for causing the cluster 21v to generate and output an AC voltage Vcv0 having substantially the same waveform as the power supply voltage Ev, and an AC voltage command value Vcw sin(θ+2π / 3) for causing the cluster 21w to generate and output an AC voltage Vcw0 having substantially the same waveform as the power supply voltage Ew.

[0043] The PWM generating unit 43 of the microcontroller 40 generates switching control signals for the unit converters S1 to S3 by performing pulse width modulation for each cluster 21u to 21w, comparing the voltage levels of three carrier signals corresponding to the unit converters S1 to S3 whose number of series-connected stages is up to the specified value, out of n carrier signals that are the same number as the number "n" of series-connected stages of the unit converters S1 to Sn in the clusters 21u to 21w but have different phases from each other, with the levels of the output voltages Vcu0 to Vcw0 (each AC voltage command value) set by the main control unit 42.

[0044] The PWM generating unit 52 of the microcontroller 50 generates switching control signals for the unit converters S4 to Sn by performing pulse width modulation for each cluster 21u to 21w, which compares the voltage levels of the “n-3” carrier signals corresponding to the unit converters S4 to Sn whose number of series-connected stages exceeds the above-mentioned specified value with the levels of the output voltages Vcu0 to Vcw0 set by the main control unit 42 (each AC voltage command value).

[0045] The clock generating unit 44 of the microcontroller 40 generates a control clock signal for the microcontroller 40 and a control clock signal for the microcontroller 50. For example, the clock generating unit 44 generates a control clock signal for the microcontroller 40 and sends the control clock signal directly to the microcontroller 50. The microcontroller 50 receives the control clock signal sent from the clock generating unit 44 as the control clock signal for the microcontroller 50.

[0046] The clock generating unit 44 may be configured to generate a control clock signal for the microcontroller 40, and to divide the frequency of the control clock signal and send it to the microcontroller 50. In this case, the microcontroller 50 multiplies the frequency-divided signal sent from the clock generating unit 44 to a predetermined frequency and takes it in as the control clock signal for the microcontroller 50.

[0047] The control clock signal generated by the clock generating unit 44 has a high frequency of several MHz, and if sent to the microcontroller 50 as is, it may have a negative effect on external devices as noise. In contrast, if the control clock signal generated by the clock generating unit 44 is divided to lower its frequency and then sent to the slave microcontroller 50, the negative effect on external devices can be reduced. The microcontroller 50 multiplies the received control clock signal to the same frequency as the control clock signal used by the microcontroller 40, or multiplies the received control clock signal to a frequency that is an integer fraction of the control clock signal used by the microcontroller 40. In this case, the power consumption of the microcontroller 50 can be reduced.

[0048] As described above, by increasing the number of stages of series connection of each unit converter for each cluster in the multilevel converter 20, it becomes possible to connect the active filter 10 to a high-voltage AC system without employing switching elements with high voltage resistance, that is, without incurring increased losses.

[0049] In particular, two general-purpose microcontrollers 40, 50 for inverter control, such as those installed in the air conditioner 2, are used as controllers for switching control of the multilevel converter 20, so even if the number of stages of series connection of each unit converter in the multilevel converter 20 is large, all unit converters of the multilevel converter 20 can be appropriately controlled while reducing costs.

[0050] Furthermore, if the detection signals of each voltage detector 22 in unit converters S1 to S3 are combined by a multiplexer and supplied to the microcontroller 40, and the detection signals of each voltage detector 22 in unit converters S4 to Sn are combined by a multiplexer and supplied to the microcontroller 50, it is possible to reduce the number of ports provided in the microcontrollers 40 and 50.

[0051] Although the example has been described in which two general-purpose microcontrollers are used, a configuration using three or more general-purpose microcontrollers may also be used.

[0052] [3] Third embodiment As in the second embodiment, when the number of stages of series connection of each unit converter in the multilevel converter 20 is large, the number of voltage detectors 22 that detect the capacitor voltage Vc of each unit converter also increases, posing a problem of increased costs. The third embodiment addresses this issue.

[0053] 7, among the unit converters S1 to Sn of cluster 21u, one auxiliary switch circuit 30 is provided for each of a plurality of unit converters, for example, for every two unit converters whose number of stages in series connection is adjacent to each other. Similarly, among the unit converters S1 to Sn of clusters 21v and 21w, one auxiliary switch circuit 30 is provided for each of a plurality of unit converters, for example, for every two unit converters whose number of stages in series connection is adjacent to each other.

[0054] FIG. 8 shows the configuration of two unit converters S1 and S2 whose serial connection stages are adjacent to each other, and the configuration of one auxiliary switch circuit 30 provided for the unit converters S1 and S2. The unit converter S1 includes switch elements Q1 to Q4, a capacitor C, and a voltage detector 22, as well as drive units (gate amplifiers) 25a, 25b, 25c, and 25d that respectively turn on and off the switch elements Q1 to Q4 in response to control signals A1 to A4 supplied from a microcontroller 40, and a power supply unit 24 that converts the voltage Vc of the capacitor C into a DC voltage (operating voltage) Vdd required for the operation of the drive units 25a to 25d.

[0055] The unit converter S2 includes switch elements Q1 to Q4, a capacitor C, drive units 25a to 25d that respectively turn on and off the switch elements Q1 to Q4 in accordance with the control signals A1 to A4, and a power supply unit 24 that converts the voltage Vc of the capacitor C into a DC voltage Vdd required for the operation of the drive units 25a to 25d, but does not include a voltage detector 22.

[0056] The control signals A1 to A4 are generated by the PWM generation unit 44 of the microcontroller 40. The control signal A1 turns on and off the switch element (first switch element) Q1 of each of the unit converters S1 and S2 via the drive unit 25a. The control signal A2 turns on and off the switch element (second switch element) Q2 of each of the unit converters S1 and S2 via the drive unit 25b. The control signal A3 turns on and off the switch element (third switch element) Q3 of each of the unit converters S1 and S2 via the drive unit 25c. The control signal A4 turns on and off the switch element (fourth switch element) Q4 of each of the unit converters S1 and S2 via the drive unit 25d.

[0057] The auxiliary switch circuit 30 includes an inverting circuit 31 that inverts the logical level of the control signal A2, an auxiliary switch element (first auxiliary switch element) T1 that responds to the output signal of this inverting circuit 31, an inverting circuit 32 that inverts the logical level of the control signal A4, an auxiliary switch element (second auxiliary switch element) T2 that responds to the output signal of this inverting circuit 32, and a passive element R, and is configured by connecting the auxiliary switch elements T1 and T2 in series via the passive element R, and is connected between the negative terminals of the capacitors C of the unit converters S1 and S2 (the source terminals of the switch elements Q2 and Q4). With this circuit configuration, the auxiliary switch circuit 30 operates as a bidirectional switch.

[0058] 9, the inverting circuit 31 includes a switch element 31t that operates in response to a control signal A2, and controls the DC voltage Vdd applied between the gate and source of the auxiliary switch element T1 from the power supply unit 24 of the unit converter S1 by the operation of the switch element 31t in response to the control signal A2. When the control signal A2 is at a logical "1" level, the switch element 31t turns on, the gate-source voltage of the auxiliary switch element T1 becomes low, and the auxiliary switch element T1 turns off. When the control signal A2 is at a logical "0" level, the switch element 31t turns off, the gate-source voltage of the auxiliary switch element T1 becomes high, and the auxiliary switch element T1 turns on.

[0059] 9, the inverting circuit 32 includes a switch element 32t that operates in response to a control signal A4, and controls the DC voltage Vdd applied between the gate and source of the auxiliary switch element T2 from the power supply unit 24 of the unit converter S2 by the operation of the switch element 32t in response to the control signal A4. When the control signal A4 is at a logical "1" level, the switch element 32t turns on, the gate-source voltage of the auxiliary switch element T2 becomes low, and the auxiliary switch element T2 turns off. When the control signal A4 is at a logical "0" level, the switch element 32t turns off, the gate-source voltage of the auxiliary switch element T2 becomes high, and the auxiliary switch element T2 turns on.

[0060] The auxiliary switch circuit 30 balances the capacitor voltage Vc of the unit converter S1 and the capacitor voltage Vc of the unit converter S2 through the auxiliary switch elements T1 and T2 and the passive element R. The passive element R is a resistor.

[0061] By balancing the capacitor voltages Vc of the two unit converters S1 and S2 driven by common control signals A1 to A4 using the auxiliary switch circuit 30, the capacitor voltages Vc of the unit converters S1 and S2 can be detected using only one voltage detector 22 of the unit converter S1.

[0062] The magnitude of the current flowing through the auxiliary switching elements T1 and T2 can be adjusted by adjusting the resistance value of passive element R, which is a resistor. That is, decreasing the resistance value of passive element R increases the current flowing through the auxiliary switching elements T1 and T2, and increasing the resistance value of passive element R decreases the current flowing through the auxiliary switching elements T1 and T2. If the current flowing through the auxiliary switching elements T1 and T2 is large, it may cause losses in the auxiliary switching circuit 30 or malfunctions in the components of the auxiliary switching circuit 30, so it is desirable for the resistance value of passive element R to be large.

[0063] The relationship between the logic levels ("1" or "0") of the control signals A1 to A4, the operation of the auxiliary switch elements T1 and T2, and the current (balancing circuit current) Ir flowing through the auxiliary switch circuit 30 is shown in the time chart of Fig. 10. The relationship between the logic levels of the control signals A1 to A4 and the operation of each switch element of the unit converters S1 and S2, the operation of the auxiliary switch elements T1 and T2, and the current paths in the unit converters S1 and S2 and the auxiliary switch circuit 30 is shown in Figs.

[0064] When A1="1", A2="0", A3="0", A4="1", as shown in Fig. 11, the switch elements Q1 and Q4 of unit converters S1 and S2 turn on and the switch elements Q2 and Q3 turn off, and the auxiliary switch element T1 turns on and the auxiliary switch element T2 turns off. As a result, as shown by the dashed arrow in Fig. 11, current flows through the path passing through the switch element Q1 of unit converter S1 → capacitor C of unit converter S1 → switch element Q4 of unit converter S1 → switch element Q1 of unit converter S2 → capacitor C of unit converter S2 → switch element Q4 of unit converter S2, and the capacitors C of unit converters S1 and S2 are charged. Because the auxiliary switch element T2 is off, no current flows through the auxiliary switch circuit 30.

[0065] Next, when A1="0", A2="1", A3="0", A4="1", as shown in Fig. 12, the switch elements Q2 and Q4 of the unit converters S1 and S2 turn on and the switch elements Q1 and Q3 turn off, and the auxiliary switch element T1 turns on and the auxiliary switch element T2 turns off. As a result, as shown by the dashed arrow in Fig. 12, current flows through the path passing through the switch element Q2 of the unit converter S1 → the switch element Q4 of the unit converter S1 → the switch element Q2 of the unit converter S2 → the switch element Q4 of the unit converter S2. No current flows through the capacitors C of the unit converters S1 and S2. No current flows through the auxiliary switch circuit 30 either.

[0066] In this case, a dead time (A1, A2, A3="0", A4="1") is secured between the time when A2 changes from "0" to "1" and switch element Q2 is turned on, and the time when A1 changes from "1" to "0" and switch element Q1 is turned off, in order to prevent a short circuit caused by switch elements Q1 and Q2 being turned on simultaneously.

[0067] Next, when A1="1", A2="0", A3="0", A4="1", the state of each switch element and the current flow become as shown in Figure 11. In this case, a dead time (A1 to A3="0", A4="1") is secured between the time when A1 changes from "0" to "1" and switch element Q1 turns on, and the time when A2 changes from "1" to "0" and switch element Q2 turns off, in order to prevent a short circuit caused by switch elements Q1 and Q2 turning on simultaneously.

[0068] Next, when A1="1", A2="0", A3="1", A4="0", the switch elements Q1 and Q3 of unit converters S1 and S2 turn on, the switch elements Q2 and Q4 turn off, and the auxiliary switch elements T1 and T2 turn on, as shown in Fig. 13. This causes current to flow through the path passing through the switch element Q1 of unit converter S1 → the switch element Q3 of unit converter S1 → the switch element Q1 of unit converter S2 → the switch element Q3 of unit converter S2, as shown by the dashed arrow in Fig. 13.

[0069] In this case, a dead time (A1="1", A2 to A4="0") is ensured between the time when A3 changes from "0" to "1" and switching element Q3 turns on, and the time when A4 changes from "1" to "0" and switching element Q4 turns off, to prevent a short circuit caused by switching elements Q3 and Q4 turning on simultaneously. Also, when switching element Q3 of unit converter S1 and switching element Q1 of unit converter S2 are turned on, the positive terminals of the capacitors C of each of unit converters S1 and S2 become conductive, and when auxiliary switching elements T1 and T2 are turned on, the negative terminals of the capacitors C of each of unit converters S1 and S2 become conductive, and the capacitors C of each of unit converters S1 and S2 are connected in parallel with each other. This parallel connection causes the capacitors C of each of unit converters S1 and S2 to charge and discharge with each other, and the respective capacitor voltages Vc become balanced.

[0070] For example, if the capacitor voltage Vc of unit converter S1 is lower than the capacitor voltage Vc of unit converter S2, as shown by the dashed arrow in Figure 13, part of the current flowing from switch element Q1 to switch element Q3 of unit converter S1 flows to the positive terminal of capacitor C of unit converter S1, charging capacitor C of that unit converter S1. The current that has passed through capacitor C of unit converter S1 flows as balancing circuit current Ir through auxiliary switch element T1, passive element R, and auxiliary switch element T2 to the negative terminal of capacitor C of unit converter S2. Capacitor C of unit converter S2 discharges, and this discharge current joins the current flowing toward switch element Q3 of unit converter S2. Due to this charging and discharging, the capacitor voltage Vc of unit converter S1 changes upward and the capacitor voltage Vc of unit converter S2 changes downward, and when the respective capacitor voltages Vc are balanced to the same value, the balancing circuit Ir becomes zero.

[0071] Because the capacitor voltages Vc of the unit converters S1 and S2 are balanced to the same value, the capacitor voltages Vc of the unit converters S1 and S2 can be detected with just one voltage detector 22 provided in the unit converter S1. The remaining unit converters S3 to Sn can also detect the capacitor voltages Vc of the unit converters S3 to Sn with a smaller number of voltage detectors 22. The smaller number of voltage detectors 22 allows for cost reduction.

[0072] Next, when A1="1", A2="0", A3="0", and A4="1", the state of each switch element and the current flow become as shown in Fig. 11. In this case, a dead time (A1="1", A2 to A4="0") is secured between the time when A4 changes from "0" to "1" and switch element Q4 turns on, and the time when A3 changes from "1" to "0" and switch element Q3 turns off, in order to prevent a short circuit caused by switch elements Q3 and Q4 being turned on simultaneously.

[0073] During this dead time (A1="1", A2 to A4="0"), as shown in FIG. 14, the switch element Q1 of unit converters S1 and S2 turns on, the switch elements Q2, Q3, and Q4 turn off, and the auxiliary switch elements T1 and T2 turn on. As a result, as shown by the dashed arrow in FIG. 14, a current (pulse-shaped current) flows through the path from the switch element Q1 of unit converter S1 → capacitor C of unit converter S1 → auxiliary switch element T1 → passive element R → auxiliary switch element T2 → freewheel diode D of the switch element Q4 of unit converter S2. Note that in FIG. 10, the current Ir during the balancing period and the dead times before and after it is shown as the same value, but the value of the current Ir during the balancing period changes depending on the balancing situation, and it may also flow negatively (in the reverse direction).

[0074] As shown in FIG. 15, the auxiliary switch circuit 30 includes an inverting circuit 31, an auxiliary switch element T1, an inverting circuit 32, an auxiliary switch element T2, and a passive element R, and may also include a synchronization control circuit (first synchronization control circuit) 33 that controls the gate input to the auxiliary switch element T1 in synchronization with a control signal A1, and a synchronization control circuit (second synchronization control circuit) 34 that controls the gate input to the second auxiliary switch element in synchronization with a control signal A3.

[0075] The synchronization control circuit 33 is a photocoupler (first photocoupler) that responds to the control signal A1. It comprises a photodiode 33a that emits light when the control signal A1 is at logic "1," and a phototransistor 33b that is turned on by the emission of light from the photodiode 33a and outputs a DC voltage Vdd as a gate signal to the auxiliary switch element T1. The synchronization control circuit 33 forcibly turns off the auxiliary switch element T1 during the dead time [A1 to A3="0", A4="1"]. By forcibly turning off the auxiliary switch element T1, it is possible to cut off unnecessary pulse-like current that flows through the auxiliary switch circuit 30 during that dead time. Cutting off unnecessary pulse-like current reduces losses.

[0076] The synchronization control circuit 34 is a photocoupler (second photocoupler) that responds to the control signal A3. It is composed of a photodiode 34a that emits light when the control signal A3 is logic "1," and a phototransistor 34b that is turned on by the emission of light from the photodiode 34a and outputs a DC voltage Vdd as a gate signal to the auxiliary switch element T2. The synchronization control circuit 34 forcibly turns off the auxiliary switch element T2 during the dead time [A1="1", A2 to A4="0"]. By forcibly turning off the auxiliary switch element T2, it is possible to cut off unnecessary pulse-like current that flows through the auxiliary switch circuit 30 during that dead time. Cutting off unnecessary pulse-like current reduces losses.

[0077] As an example of control not shown in the time chart of Fig. 10, there is a case where switch elements Q2 and Q3 of unit converters S1 and S2 are turned on, switch elements Q1 and Q4 are turned off, and auxiliary switch elements T1 and T2 are turned off, as shown in Fig. 16. In this case, as shown by the dashed lines in Fig. 16, discharge paths for capacitors C of unit converters S1 and S2 are formed through switch elements Q2 and Q3. No current flows through auxiliary switch circuit 30.

[0078] The above-described embodiments and modifications are presented as examples and are not intended to limit the scope of the invention. These embodiments and modifications can be embodied in various other forms, and various omissions, rewritings, and modifications can be made without departing from the spirit of the invention. These embodiments and modifications are included within the spirit of the invention, and are also included in the scope of the inventions described in the claims and their equivalents. [Explanation of symbols]

[0079] 1...Three-phase AC power supply, Lu, Lv, Lw...Power line, 2...Air conditioner (load), 10...Power conversion device (active filter), 11u, 11v, 11w...Reactor, 20...Multilevel converter, 21u, 21v, 21w...Cluster, S1 to Sn...Unit converter, Q1 to Q4...Switch element, C...Capacitor, 22...Voltage detector, 30...Auxiliary switch circuit, 40...Microcontroller (first microcontroller), 41...A / D converter, 42...Main control unit, 43...PWM generation unit, 44...Clock generation unit, 50...Microcontroller (second microcontroller).

Claims

1. a multilevel converter connected in parallel to a three-phase AC power supply to which a load is connected, the multilevel converter having a cluster formed by series connection of a plurality of unit converters for each phase of the three-phase AC power supply; a general-purpose microcontroller including: a conversion unit that performs analog-to-digital conversion of detection signals for the current flowing through the load and the voltage of the three-phase AC power supply; a main control unit that sets the output voltage of each cluster required to suppress harmonic components contained in the current flowing through the load based on the output of the conversion unit; and a generation unit that generates control signals for each unit converter in accordance with the setting of the main control unit; Equipped with each of the unit converters comprises a plurality of switch elements and one capacitor, and selectively outputs a plurality of levels of DC voltage by switching each of the switch elements; the microcontrollers are a general-purpose first microcontroller that controls, among the unit converters of each cluster, unit converters whose number of stages in series connection is up to a specified value; and a general-purpose second microcontroller that controls, among the unit converters of each cluster, unit converters whose number of stages in series connection is more than the specified value; the conversion unit is a first conversion unit contained in the first microcontroller and performs analog-to-digital conversion on a detection signal regarding the current flowing through the load, a detection signal regarding the current flowing between the multilevel converter and each power supply line of the three-phase AC power supply, a detection signal regarding the phase of the power supply voltage of the three-phase AC power supply, and a detection signal regarding the voltage of the capacitor in the unit converters whose number of stages in the series connection is up to the specified value; and a second conversion unit contained in the second microcontroller and performs analog-to-digital conversion on a detection signal regarding the voltage of the capacitor in the unit converters whose number of stages in the series connection is more than the specified value; the main control unit is housed in the first microcontroller and sets an output voltage of each cluster necessary to suppress harmonic components contained in the current flowing through the load based on an output of the first conversion unit and an output of the second conversion unit; the generating unit is a first generating unit housed in the first microcontroller, which performs pulse width modulation for each cluster to compare the voltage level of a carrier signal corresponding to unit converters whose number of series-connected stages exceeds the specified value with an output voltage level set by the main control unit, among a plurality of carrier signals that are the same in number as the number of serially connected stages of each unit converter in each cluster but have different phases from each other; and a second generating unit housed in the second microcontroller which performs pulse width modulation for each cluster to compare the voltage level of a carrier signal corresponding to unit converters whose number of series-connected stages exceeds the specified value with an output voltage level set by the main control unit, among the plurality of carrier signals, to generate switching control signals for unit converters whose number of series-connected stages exceeds the specified value. Power conversion device.

2. the first microcontroller includes a clock generating unit that generates a control clock signal for the first microcontroller and a control clock signal for the second microcontroller; The power conversion device according to claim 1 .

3. the first microcontroller includes a clock generating unit that generates a control clock signal for the first microcontroller and sends the control clock signal to the second microcontroller; the second microcontroller receives the control clock signal sent from the first microcontroller as a control clock signal for the second microcontroller; The power conversion device according to claim 1 .

4. the first microcontroller includes a clock generating unit that generates a control clock signal for the first microcontroller and divides the control clock signal to send it to the second microcontroller; the second microcontroller multiplies the divided control clock signal sent from the first microcontroller to a predetermined frequency and takes in the multiplied signal as a control clock signal for the second microcontroller; The power conversion device according to claim 1 .

5. each of the unit converters includes a first series circuit formed by connecting first and second switch elements in series, a second series circuit formed by connecting third and fourth switch elements in series and connected in parallel to the first series circuit, and a capacitor connected in parallel to this second series circuit, and selectively outputs DC voltages of multiple levels by a combination of an operation of turning on one of the first and second switch elements and turning off the other, and an operation of turning on one of the third and fourth switch elements and turning off the other, the generation unit generates a first control signal that commonly turns on and off the first switch elements in a plurality of unit converters among the unit converters for each cluster; a second control signal that commonly turns on and off the second switch elements in the plurality of unit converters; a third control signal that commonly turns on and off the third switch elements in the plurality of unit converters; and a fourth control signal that commonly turns on and off the fourth switch elements in the plurality of unit converters, an auxiliary switch circuit comprising a bidirectional first auxiliary switch element responsive to an inverted signal of the second control signal and a bidirectional second auxiliary switch element responsive to an inverted signal of the fourth control signal, connected in series via a passive element, and connected between the negative terminals of the capacitors in the plurality of unit converters; a voltage detection unit that is connected to both ends of one of the capacitors in the plurality of unit converters and detects the voltage of the one capacitor as the voltage of each of the capacitors in the plurality of unit converters; Further provided with The power conversion device according to claim 1 .

6. the passive element is a resistor; The power conversion device according to claim 5 .

7. the auxiliary switch circuit includes a first inverting switch element that generates the inverted signal of the second control signal, and a second inverting switch element that generates the inverted signal of the fourth control signal. The power conversion device according to claim 5 .

8. The auxiliary switch circuit includes a first synchronization control circuit that controls a gate input to the first auxiliary switch element in synchronization with the first control signal, and a second synchronization control circuit that controls a gate input to the second auxiliary switch element in synchronization with the third control signal. The power conversion device according to claim 5 .

9. the first synchronization control circuit is a first photocoupler responsive to the first control signal; the second synchronization control circuit is a second photocoupler responsive to the third control signal; The power conversion device according to claim 8 .

10. each cluster of the multilevel converter includes one end connected to each power supply line of the three-phase AC power supply and the other end being star-connected to each other; The power conversion device according to claim 1 .

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