Cooperative Power Supply System

Abstract

We will realize a power supply system for computers that uses solar cells with high efficiency and stability. [Solution] This power supply system uses feedback control to prioritize power supply from solar cells, and supplies only the shortfall from the computer (PC). The wiring inside the PC is adjusted so that power from the solar cell (PV) 11 is converted only once, and no voltage conversion is performed in the PC power supply. In addition, in the coordinated power supply, the front stage is divided into two systems to ensure a sufficient static margin, and the rear stage is made up of an nMOS inverter circuit or the like to ensure a sufficient dynamic margin and stable operation. Furthermore, a delay circuit allows it to be linked to the PC's power interface.

Description

[Technical Field]

[0001] The present invention relates to a DC power supply system that utilizes natural energy, and more particularly to a DC power supply system that stably supplies power to precision equipment such as PCs (personal computers). [Background technology]

[0002] Although most electronic devices today operate on direct current, most electronic devices use alternating current (AC) power, which is why most electronic devices convert AC power to DC. To convert AC power to DC, AC-DC converters, especially those used in PC (computer) power supplies and AC (Alternative Current) adapters, are usually used.

[0003] In recent years, renewable energy sources such as solar cells have become more common. The electricity generated by solar cells is DC in its natural state. Because the electricity supplied by electric power companies is AC, it is inevitable that PC (computer) power supplies and AC (Alternative Current) adapters that use AC-DC converters are used. However, nowadays, it is common for the DC electricity generated by solar cells to be converted to AC using a power conditioner, and then converted back to DC using a personal computer power supply or AC adapter.

[0004] The efficiency of converting direct current generated by solar cells into alternating current is, for example, about 80%. The efficiency of converting back to direct current is also about 80%. As a result, only 64% of the power generated by solar cells can actually be used by electronic devices. 36% of the power generated by solar cells is lost during the conversion process and is not used effectively.

[0005] Therefore, Patent Document 1 and other documents describe a method in which electricity generated by natural energy sources such as solar cells is used as direct current without first being converted to alternating current. [Patent Document 1] Patent Publication No. 2013-90560

[0006] This method describes that power generated by natural energy sources such as solar cells is used preferentially as DC, and that power shortages are taken into consideration and supplied from an AC power source. Summary of the Invention [Problem to be solved by the invention]

[0007] This method does not incorporate any measures to ensure stable operation of electronic devices using DC power. When used as a power source for 12V (volts) or the like used inside a computer (PC), there is a question as to whether it will operate stably. Will the method in Patent Document 1 operate stably? It probably will.

[0008] The reason for this is that a storage battery, an electric double layer capacitor, or a storage battery and an electric double layer capacitor are connected to the DC section. It is believed that the method of Patent Document 1 operates stably thanks to such a power storage device.

[0009] So, are such storage devices necessary? Normally, even in a DC power supply system using small-scale natural energy, storage batteries cost more than several tens of thousands of yen and reach the end of their lifespan in a few years. Storage batteries have a relatively short lifespan, and depreciation costs are often relatively high. As for electric double-layer capacitors, while they have a relatively long lifespan, they are relatively expensive to ensure sufficient capacity. Therefore, it would be better if a DC power supply system using natural energy that can operate without large-capacity storage devices could be realized.

[0010] Therefore, the object of the present invention is to provide a DC power supply system that can efficiently utilize DC power from solar cells and stably supply power such as 12V (volts) that can be used inside a computer (PC) without the need for a large-capacity storage device such as a storage battery or electric double layer capacitor. [Means for solving the problem]

[0011] The DC power supply system of the present invention comprises: a first node, a second node, a third node, a fourth node, a first DC / DC converter, a first switching element or group of switching elements, and a second switching element or group of switching elements; a potential of the first node is output to the second node by the first DC / DC converter, the first switching element or switching element group is connected between the second node and the fourth node, and the second switching element or switching element group is connected between the third node and the fourth node; the first switching element or switching element group has a completely off state, a completely on state, and other intermediate states between on and off, and changes in an analog manner from on to off and from off to on according to a voltage at a control terminal of the first switching element or switching element group; the second switching element or switching element group has a completely off state, a completely on state, and other intermediate states between on and off, and changes in an analog manner from on to off and from off to on according to a voltage at a control terminal of the second switching element or switching element group; When the potential of the first node is equal to or less than a first constant potential value, the first switching element or switching element group is turned off and the second switching element or switching element group is turned on; when the potential of the first node is equal to or greater than the first constant potential value and equal to or less than a second constant potential value, the first switching element or switching element group is turned on and the second switching element or switching element group is turned on; when the potential of the first node is equal to or greater than the second constant potential value, the first switching element or switching element group is turned on and the second switching element or switching element group is turned off; when the potential of the first node suddenly drops from a state exceeding the second constant potential value to a state below the first constant voltage value, the first switching element or switching element group starts from an on state and the second switching element or switching element group is off, the first switching element turns on and the second switching element or switching element group turns on, thereafter the first switching element or switching element group turns off and the second switching element or switching element group turns on, When the potential of the first node suddenly rises from a state below the first constant potential value to a voltage exceeding the second constant voltage value, the first switching element or switching element group starts in an off state and the second switching element or switching element group is on, the first switching element turns on and the second switching element or switching element group turns on, and then the first switching element or switching element group turns on and the second switching element or switching element group turns off. It is characterized by: [Effects of the Invention]

[0012] The DC power supply system of the present invention makes it possible to efficiently utilize electric power, especially DC power from solar cells, and to stably supply power such as 12V (volts) that can be used inside a computer (PC).In addition, since only the computer (PC) part needs to be modified, there is no need to modify the commercial power supply (100V, etc.) power system of the entire home or building, making it easy to introduce. [Brief explanation of the drawings]

[0013] [Figure 1] FIG. 1 is a block diagram of a first embodiment of the present invention. [Figure 2] FIG. 2 is a circuit diagram of a cooperative power supply circuit according to a first embodiment of the present invention. [Figure 3] FIG. 3 is an example of a circuit diagram of a DC-DC converter. [Figure 4]Figure 4 is an example of a circuit diagram inside a computer (PC) power supply. [Figure 5] FIG. 5 is an example of a circuit diagram of an inverter. [Figure 6] FIG. 6 is a circuit diagram showing a basic cooperative power supply. [Figure 7] FIG. 7 is a current graph showing cooperative power supply. [Figure 8] Figure 8 shows the voltage-current characteristics and voltage-power characteristics of a solar cell. [Figure 9] FIG. 9 is a simplified circuit diagram illustrating cooperative power supply. [Figure 10] Figure 10 shows the circuits used for inverter comparison and the simulation results (circuit A). [Figure 11] Figure 11 shows the circuits used for inverter comparison and the simulation results (circuit I). [Figure 12] FIG. 12 shows the circuit used for inverter comparison and the simulation results (circuit 3). [Figure 13] Figure 13 shows the circuits used for inverter comparison and the simulation results (circuit diagram). [Figure 14] FIG. 14 shows the circuit used for inverter comparison and the simulation results (circuit O). [Figure 15] Figure 15 shows the circuits used for inverter comparison and the simulation results (circuit). [Figure 16] FIG. 16 is an explanatory diagram of cases where a reverse current prevention diode is necessary and not necessary. [Figure 17] FIG. 17 is a circuit diagram of the part that is linked to the power button of a computer (PC). [Figure 18] Figure 18 shows the pin assignment for the CPU power connector. [Figure 19] Figure 19 shows the pin assignment for the storage power connector. [Figure 20] Figure 20 shows the pin assignment for the motherboard power connector. [Figure 21] Figure 21 shows the pin assignment for the graphics board power connector. [Figure 22] FIG. 22 is a diagram showing the relationship between the power connector and the circuit of the present invention. [Figure 23] FIG. 23 is a second block diagram of the present invention.

[0014] [First embodiment] The first embodiment relates to a cooperative power supply system. First, circuit connections will be explained, followed by an explanation of operation. After that, each related technology and each element technology will be explained.

[0015] First, the circuit connections will be explained. Figure 1 is a block diagram of a first embodiment of the present invention. The DC power supply system of the first embodiment is composed of a solar cell 11, a main circuit 12, a computer (PC) power supply 13, a commercial power supply 14, a CPU 15, a motherboard 16, storage 17, and a GPU 18.

[0016] The positive side of the solar cell 11 is connected to the main circuit 12 via a terminal 201. The negative side of the solar cell 11 is connected to the main circuit 12 via a terminal 202.

[0017] The positive side of the commercial power supply 14 is connected to the computer (PC) power supply 13. The negative side of the commercial power supply 14 is connected to the computer (PC) power supply 13. The normal 12V output of the computer (PC) power supply is connected to the main circuit 12 via terminal 206. The normal 5V output of the computer (PC) power supply is connected to the main circuit 12 via terminal 210. The normal 3.3V output of the computer (PC) power supply is connected to the motherboard 16 and storage 17. The GND of the computer (PC) power supply is connected to the main circuit 12 via terminal 205.

[0018] The normal 12V output of the main circuit 12 is connected to the CPU 15, motherboard 16, storage 17, and GPU 18 via terminal 204. The normal 5V output of the main circuit 12 is connected to the motherboard 16 and storage 17 via terminal 208. The GND of the main circuit 12 is connected to the CPU 15, motherboard 16, storage 17, and GPU 18 via terminal 207.

[0019] 2 is a circuit diagram of the main circuit 12. The main circuit 12 includes a terminal 201, a terminal 202, a terminal 203, a terminal 204, a terminal 205, a terminal 206, a terminal 207, a terminal 208, a terminal block 210, a capacitor 101, a resistor 102, a capacitor 103, an nMOS field effect transistor 104, a resistor 105, a resistor 106, a resistor 107, an nMOS inverter 108, a pMOS inverter 109, a pMOS inverter 110, a capacitor 121, a DC-DC converter 122, a capacitor 123, a diode 124, a pMOS field effect transistor 125, a pMOS field effect transistor 126, a It is composed of a transistor 126, a diode 128, an nMOS inverter 129, an nMOS inverter 130, a capacitor 131, a capacitor 132, a capacitor 133, a capacitor 141, a DC-DC converter 142, a capacitor 143, a diode 144, a pMOS field effect transistor 145, a pMOS field effect transistor 146, a pMOS field effect transistor 147, a diode 148, an nMOS inverter 149, an nMOS inverter 150, a capacitor 151, a capacitor 152, and a capacitor 153.

[0020] The contents of the nMOS inverter 108, pMOS inverter 109, pMOS inverter 110, nMOS inverter 129, nMOS inverter 130, nMOS inverter 149, and nMOS inverter 150 will be described with reference to FIG. 5. The contents of the nMOS inverter 108 are as shown in FIG. 5(a). The contents of the pMOS inverter 109 are as shown in FIG. 5(b). The contents of the pMOS inverter 110 are as shown in FIG. 5(b). The contents of the nMOS inverter 129 are as shown in FIG. 5(a). The contents of the nMOS inverter 130 are as shown in FIG. 5(a). The contents of the nMOS inverter 149 are as shown in FIG. 5(a). The contents of the nMOS inverter 150 are as shown in FIG. 5(a).

[0021] Terminal 201 is connected to the positive side of capacitor 101, one end of resistor 105, the input of DC / DC converter 122, the positive side of capacitor 141, and the input of DC / DC converter 142. Terminal 202 is a GND and is connected to many elements, but is omitted due to the large number of connections. Terminal 203 is connected to one end of resistor 102. Terminal 204 is connected to the source of pMOS field-effect transistor 127, the anode of diode 128, and the positive side of capacitor 133. Terminal 205 is a GND and is connected to many elements, but is omitted due to the large number of connections. Terminal 206 is connected to the source of pMOS field-effect transistor 126, the drain of pMOS field-effect transistor 127, and the positive side of capacitor 132. Terminal 207 is a GND and is connected to many elements, but is omitted due to the large number of connections. Terminal 208 is connected to the source of pMOS field-effect transistor 147, the anode of diode 148, and the positive side of capacitor 153. Terminal 210 is a GND and is connected to many elements, but due to the large number of connections, they are not shown here.

[0022] The positive side of capacitor 101 is connected to terminal 201 , one end of resistor 102 , one end of resistor 105 , the positive side of capacitor 121 , the input of DC / DC converter 122 , the positive side of capacitor 141 , and the input of DC / DC converter 142 .

[0023] The delay circuit 102-1 is composed of a resistor 102 and a capacitor 103. One end of the resistor 102 is connected to the positive side of the capacitor 101, one end of the resistor 105, the positive side of the capacitor 121, the input of the DC-DC converter 122, the positive side of the capacitor 141, and the input of the DC-DC converter 142. The other end of the resistor 102 is connected to the positive side of the capacitor 103 and the gate of the nMOS field-effect transistor 104. The positive side of the capacitor 103 is connected to one end of the resistor 102 and the gate of the nMOS field-effect transistor 104. The negative terminal of the capacitor 103 is connected to GND. The source of the field-effect transistor 104 is connected to GND. The gate of the field-effect transistor 104 is connected to one end of the resistor 102 and the positive side of the capacitor 103. The drain of the field-effect transistor 104 is connected to one end of the resistor 105, one end of the resistor 106, and the input of the pMOS inverter 110.

[0024] The resistive voltage divider 106-1 is composed of resistors 105, 106, and 107. One end of resistor 105 is connected to terminal 201, the positive side of capacitor 101, the input of DC / DC converter 122, the positive side of capacitor 141, and the input of DC / DC converter 142. The other end of resistor 105 is connected to the source of nMOS field-effect transistor 104, one end of resistor 106, and the input of pMOS inverter 110. One end of resistor 106 is connected to the drain of nMOS field-effect transistor 104, one end of resistor 105, and the input of pMOS field-effect transistor 110. The other end of resistor 106 is connected to one end of resistor 107 and the input of nMOS inverter 108. One end of resistor 107 is connected to one end of resistor 106 and the input of nMOS inverter 108. The other end of resistor 107 is connected to GND.

[0025] The input of the nMOS inverter 108 is connected to resistors 106 and 107. The output of the nMOS field effect transistor 108 is connected to the input of a pMOS field effect transistor 109. The VDD terminal of the nMOS inverter 108 is connected to the cathode of a diode 124, the cathode of a diode 128, the VDD terminal of a pMOS field effect transistor 109, the VDD terminal of a pMOS field effect transistor 110, the VDD terminal of a pMOS field effect transistor 109, the VDD terminal of an nMOS field effect transistor 129, the VDD terminal of an nMOS field effect transistor 130, and the positive terminal of a capacitor 131. VSS of the nMOS field effect transistor 108 is connected to GND.

[0026] The input of the pMOS inverter 109 is connected to the output of the nMOS inverter 108. The output of the pMOS inverter 109 is connected to the input of the nMOS inverter 129 and the input of the nMOS inverter 149. The VDD terminal of the pMOS inverter 109 is connected to the cathode of the diode 124, the cathode of the diode 128, the VDD terminal of the nMOS inverter 108, the VDD terminal of the pMOS inverter 110, the VDD terminal of the pMOS inverter 109, the VDD terminal of the nMOS inverter, the VDD terminal of the nMOS inverter 130, and the positive terminal of the capacitor 131. VSS of the pMOS inverter 109 is connected to GND.

[0027] The input of the pMOS inverter 110 is connected to one end of the resistor 105 and one end of the resistor 106. The output of the pMOS inverter 110 is connected to the input of the nMOS inverter 130 and the input of the nMOS inverter 150. The VDD terminal of the pMOS inverter 110 is connected to the cathode of the diode 124, the cathode of the diode 128, the VDD terminal of the nMOS field effect transistor 108, the VDD terminal of the pMOS field effect transistor 109, the VDD terminal of the nMOS field effect transistor 129, the VDD terminal of the nMOS field effect transistor 130, and the positive terminal of the capacitor 131. The VSS of the pMOS field effect transistor 110 is connected to GND.

[0028] The input of the nMOS field effect transistor 129 is connected to the output of the pMOS field effect transistor 109 and the input of the nMOS field effect transistor 149. The output of the nMOS field effect transistor 129 is connected to the gate of the pMOS field effect transistor 125 and the gate of the pMOS field effect transistor 126. The VDD terminal of the nMOS inverter 129 is connected to the cathode of the diode 124, the cathode of the diode 128, the VDD terminal of the nMOS inverter 108, the VDD terminal of the pMOS inverter 109, the VDD terminal of the pMOS inverter 110, the VDD terminal of the nMOS inverter 130, and the positive terminal of the capacitor 131. VSS of the nMOS field effect transistor 129 is connected to GND.

[0029] The input of the nMOS inverter 130 is connected to the output of the pMOS inverter 110 and the input of the nMOS inverter 150. The output of the nMOS inverter 130 is connected to the gate of the pMOS inverter 127. The VDD terminal of the nMOS inverter 130 is connected to the cathode of the diode 124, the cathode of the diode 128, the VDD terminal of the nMOS inverter 108, the VDD terminal of the pMOS inverter 109, the VDD terminal of the pMOS inverter 110, the VDD terminal of the nMOS inverter 129, and the positive terminal of the capacitor 131. VSS of the nMOS inverter 130 is connected to GND.

[0030] The input of DC / DC converter 122 is connected to terminal 201, the positive side of capacitor 101, one end of resistor 105, capacitor 121, the positive side of capacitor 141, and the input of DC / DC converter 142. The output of DC / DC converter 122 is connected to the positive terminal of capacitor 123, the anode of diode 124, and the source of pMOS field effect transistor 125. The GND terminal of DC / DC converter 122 is connected to GND.

[0031] The positive terminal of capacitor 121 is connected to the input of DC-DC converter 122, terminal 201, the positive side of capacitor 101, one end of resistor 105, the positive side of capacitor 141, and the input of DC-DC converter 142. The negative terminal of capacitor 121 is connected to GND.

[0032] The positive terminal of the capacitor 123 is connected to the output of the DC-DC converter 122, the anode of the diode 124, and the source of the pMOS field effect transistor 125. The negative terminal of the capacitor 123 is connected to GND.

[0033] The anode of diode 124 is connected to the output of DC-DC converter 122, the anode of capacitor 123, and the source of pMOS field effect transistor 125. The cathode of diode 124 is connected to the VDD terminal of nMOS inverter 108, the VDD terminal of pMOS inverter 109, the VDD terminal of pMOS inverter 110, the VDD terminal of nMOS inverter 129, and the VDD terminal of nMOS inverter 130.

[0034] The source of the pMOS field effect transistor 125 is connected to the output of the DC-DC converter 122, the positive terminal of the capacitor 123, and the anode of the diode 124. The gate of the pMOS field effect transistor 125 is connected to the gate of the pMOS field effect transistor 126 and the output of the nMOS inverter 129. The drain of the pMOS field effect transistor 125 is connected to the drain of the pMOS field effect transistor 126.

[0035] The source of the pMOS field effect transistor 126 is connected to the drain of the pMOS field effect transistor 127, the positive terminal of the capacitor 132, and the terminal 206. The gate of the pMOS field effect transistor 126 is connected to the gate of the pMOS field effect transistor 125 and the output of the nMOS inverter 129. The drain of the pMOS field effect transistor 126 is connected to the drain of the pMOS field effect transistor 125.

[0036] The source of the pMOS field effect transistor 127 is connected to the terminal 204, the anode of the diode 128, and the positive terminal of the capacitor 133. The gate of the pMOS field effect transistor 127 is connected to the output of the nMOS field effect transistor 130. The drain of the pMOS field effect transistor 127 is connected to the source of the pMOS field effect transistor 126, the positive terminal of the capacitor 132, and the terminal 206.

[0037] The anode of the diode 128 is connected to the terminal 204 and the source of the nMOS field effect transistor 127. The cathode of the diode 128 is connected to the cathode of the diode 124, the VDD terminal of the nMOS inverter 108, the VDD terminal of the nMOS inverter 109, the VDD terminal of the nMOS inverter 110, the VDD terminal of the nMOS inverter 129, the VDD terminal of the nMOS inverter 130, and the positive terminal of the capacitor 131.

[0038] The positive terminal of the capacitor 131 is connected to the cathode of the diode 128, the cathode of the diode 124, the VDD terminal of the nMOS inverter 108, the VDD terminal of the pMOS inverter 109, the VDD terminal of the pMOS inverter 110, the VDD terminal of the nMOS inverter 129, and the VDD terminal of the nMOS inverter 130. The negative terminal of the capacitor 131 is connected to GND.

[0039] The positive terminal of the capacitor 132 is connected to the source of the pMOS field effect transistor 126, the drain of the pMOS field effect transistor 127, and the terminal 206. The negative terminal of the capacitor 132 is connected to GND.

[0040] The positive terminal of the capacitor 133 is connected to the source of the pMOS field effect transistor 127, the terminal 204. The negative terminal of the capacitor 133 is connected to GND.

[0041] The source of terminal 204 is connected to the source of pMOS field effect transistor 127, the anode of diode 128, and the positive terminal of capacitor 133. Terminal 205 is connected to GND. Terminal 206 is connected to the source of pMOS field effect transistor 126, the drain of pMOS field effect transistor 127, and the positive terminal of capacitor 132. Terminal 207 is connected to GND.

[0042] The positive terminal of capacitor 141 is connected to the positive terminal of capacitor 121, the input of DC / DC converter 122, terminal 201, the positive side of capacitor 101, one end of resistor 105, and the input of DC / DC converter 142. The negative terminal of capacitor 141 is connected to GND.

[0043] The input of DC-DC converter 142 is connected to the positive terminal of capacitor 121, the input of DC-DC converter 122, terminal 201, the positive side of capacitor 101, one end of resistor 105, and the positive terminal of capacitor 141. The output of DC-DC converter 142 is connected to the positive side of capacitor 143, the anode of diode 144, and the source of pMOS field effect transistor 145. The GND of DC-DC converter 142 is connected to GND.

[0044] The positive terminal of the capacitor 143 is connected to the output of the DC-DC converter 142, the anode of the diode 144, and the source of the pMOS field effect transistor 145. The negative terminal of the capacitor 143 is connected to GND. The anode of diode 144 is connected to the output of DC-DC converter 142, the positive terminal of capacitor 143, and the source of pMOS field effect transistor 145. The cathode of diode 144 is connected to the cathode of diode 148, the positive terminal of nMOS inverter 149, and the positive terminal of nMOS inverter 150.

[0045] The source of the pMOS field effect transistor 145 is connected to the output of the DC-DC converter 142, the positive terminal of the capacitor 143, and the anode of the diode 144. The gate of the pMOS field effect transistor 145 is connected to the gate of the pMOS field effect transistor 146 and the output of the nMOS inverter 149. The drain of the pMOS field effect transistor 145 is connected to the drain of the pMOS field effect transistor 146.

[0046] The source of the pMOS field effect transistor 146 is connected to the drain of the pMOS field effect transistor 147, the positive side of the capacitor 152, and the terminal 210. The gate of the pMOS field effect transistor 146 is connected to the gate of the pMOS field effect transistor 145 and the output of the nMOS inverter 149. The drain of the pMOS field effect transistor 146 is connected to the drain of the pMOS field effect transistor 145.

[0047] The source of the pMOS field effect transistor 147 is connected to the anode of the diode 148, the positive terminal of the capacitor 153, and the terminal 208. The gate of the pMOS field effect transistor 147 is connected to the output of the nMOS inverter 150. The drain of the pMOS field effect transistor 147 is connected to the source of the pMOS field effect transistor 146, the positive side of the capacitor 152, and the terminal 210.

[0048] The anode of the diode 148 is connected to the source of the pMOS field effect transistor 147, the positive side of the capacitor 153, and the terminal 208. The cathode of the diode 148 is connected to the cathode of the diode 144, the VDD of the nMOS inverter 149, and the VDD of the nMOS inverter 150.

[0049] The input of the nMOS inverter 149 is connected to the output of the pMOS inverter 109 and the input of the nMOS inverter 129. The output of the nMOS inverter 149 is connected to the gate of the pMOS field effect transistor 145 and the gate of the pMOS field effect transistor 146. The VDD of the nMOS inverter 149 is connected to the cathode of the diode 144, the cathode of the diode 148, the VDD of the nMOS inverter 150, and the positive side of the capacitor 151. The VSS of the nMOS inverter 149 is connected to GND.

[0050] The input of the nMOS inverter 150 is connected to the output of the pMOS inverter 110 and the input of the nMOS inverter 130. The output of the nMOS inverter 150 is connected to the gate of the pMOS field effect transistor 147. The VDD of the nMOS inverter 150 is connected to the cathode of the diode 144, the cathode of the diode 148, the VDD of the nMOS inverter 149, and the positive side of the capacitor 151. The VSS of the nMOS inverter 150 is connected to GND.

[0051] The positive terminal of the capacitor 151 is connected to the cathode of the diode 144, the cathode of the diode 148, the VDD of the nMOS inverter 149, and the VDD of the nMOS inverter 150. The negative terminal of the capacitor 151 is connected to GND.

[0052] The positive side of the capacitor 152 is connected to the source of the pMOS field effect transistor 146, the drain of the pMOS field effect transistor 147, and the terminal 210. The negative terminal of the capacitor 152 is connected to GND.

[0053] The positive terminal of the capacitor 153 is connected to the source of the pMOS field effect transistor 147, the anode of the diode 148, and the terminal 208. The negative terminal of the capacitor 153 is connected to GND.

[0054] Terminal 208 is connected to the source of pMOS field effect transistor 147, the anode of diode 148, and the positive terminal of capacitor 153. Terminal 210 is connected to the source of field effect transistor 146, the drain of field effect transistor 147, and the positive terminal of capacitor 152.

[0055] Figure 3 shows an example of the internal circuitry of the DC-DC converters 122 and 142. The DC-DC converters 121 and 141 are composed of a pMOS field-effect transistor 201, a controller 202, a diode 203, an inductor 204, a resistor 205, and a resistor 206. Capacitors 121 and 141 and capacitors 123 and 143 have been explained in Figure 2, but are also shown in Figure 3 because they are important for the operation of the DC-DC converter.

[0056] The positive terminal of the capacitor 121 is connected to the source of the pMOS field effect transistor 201. The negative terminal of the capacitor 121 is connected to GND.

[0057] The source of the pMOS field effect transistor 201 is connected to the positive terminal of the capacitor 121. The gate of the pMOS field effect transistor 201 is connected to the output of the controller 202. The drain of the pMOS field effect transistor 201 is connected to the cathode of the diode 203 and one end of the inductor 204.

[0058] The anode of the diode 203 is connected to GND, and the cathode of the diode 203 is connected to the drain of the pMOS field effect transistor 201 and one end of the inductor 204.

[0059] One end of the inductor 204 is connected to the drain of the pMOS field effect transistor 201 and the cathode of the diode 203. The other end of the inductor 204 is connected to one end of the resistor 205 and the positive sides of the capacitors 123 and 143.

[0060] One end of resistor 205 is connected to one end of inductor 204 and the positive sides of capacitors 123 and 143. The other end of resistor 205 is connected to one end of resistor 206 and the input of controller 202.

[0061] One end of resistor 206 is connected to one end of resistor 205 and the input of controller 202. The other end of resistor 206 is connected to GND.

[0062] The positive sides of the capacitors 123 and 143 are connected to one end of the inductor 204 and one end of the resistor 205. The negative sides of the capacitors 123 and 143 are connected to GND.

[0063] 4 shows an example of the internal configuration of a power supply for a computer (PC). The power supply for a computer (PC) 300 is composed of terminals 206, 210, 207, diodes 301, 302, 303, 304, capacitors 305, 306, transformer 307, controller 308, capacitor 309, DC-DC converter 310, and ultra-low-voltage converter 311.

[0064] The anode of diode 301 is connected to the anode of diode 302. The cathode of diode 301 is connected to the anode of diode 303, the positive side of capacitor 305, and the positive side of the primary side of transformer 307.

[0065] The anode of diode 302 is connected to the anode of diode 301. The cathode of diode 302 is connected to the anode of diode 304 and one end of switch 312.

[0066] The anode of the diode 303 is connected to the cathode of the diode 301, the positive side of the capacitor 305, and one end of the transformer 307. The cathode of the diode 304 is connected to the cathode of the diode 303.

[0067] The positive side of capacitor 305 is connected to the cathode of diode 301, the anode of diode 303, and the positive side of transformer 307. The negative side of capacitor 305 is connected to the cathode of diode 302, the anode of diode 304, and one end of switch 312.

[0068] The anode of diode 306 is connected to the secondary positive side of transformer 307. The cathode of diode 306 is connected to the positive side of capacitor 309, the input of DC / DC converter 310, the input of DC / DC converter 311, and terminal 206.

[0069] The positive primary side of transformer 307 is connected to the cathode of diode 301, the anode of diode 303, and the positive side of capacitor 305. The negative primary side of transformer 307 is connected to one end of switching element 312. The positive secondary side of transformer 307 is connected to the anode of diode 306. The negative secondary side terminal of transformer 307 is connected to the negative side of capacitor 309, the GND of DC-DC converter 310, the GND of DC-DC converter 311, and terminal 207.

[0070] One end of the switching element 312 is connected to the negative primary side of the transformer 307. The other end of the switching element 312 is connected to the cathode of the diode 302, the anode of the diode 304, and the negative side of the capacitor 305. The control terminal of the switching element 312 is connected to the output of the controller 308.

[0071] The positive side of capacitor 309 is connected to the cathode of diode 306, the input of DC / DC converter 310, the input of DC / DC converter 311, and terminal 206. The negative side of capacitor 309 is connected to the secondary negative terminal of transformer 307, the GND of DC / DC converter 310, the GND of DC / DC converter 311, and terminal 207.

[0072] The input of DC-DC converter 310, the positive side of capacitor 309, is connected to the cathode of diode 306, the input of DC-DC converter 311, and terminal 206. The output of DC-DC converter 310 is connected to terminal 210. The GND of DC-DC converter 310, the negative side of capacitor 309, and the negative secondary terminal of transformer 307 are connected to the GND of DC-DC converter 311 and terminal 207.

[0073] The input of DC-DC converter 311, the positive side of capacitor 309, is connected to the cathode of diode 306, the input of DC-DC converter 310, and terminal 206. The output of DC-DC converter 311 is connected to the outside. The GND of DC-DC converter 311, the negative side of capacitor 309, and the negative secondary terminal of transformer 307 are connected to the GND of DC-DC converter 310 and terminal 207.

[0074] Terminal 206 is connected to the positive side of capacitor 309, the cathode of diode 306, the input of DC / DC converter 310, and the input of DC / DC converter 311. Terminal 210 is connected to the output of DC / DC converter 310. Terminal 207 is connected to the negative side of capacitor 309, the secondary negative terminal of transformer 307, the GND of DC / DC converter 310, and the GND of DC / DC converter 311.

[0075] Figure 5(a) is a circuit diagram of an nMOS inverter, and Figure 5(b) is a circuit diagram of a pMOS inverter.

[0076] One end of the resistor 401 is connected to the outside, and the other end of the resistor 401 is connected to the drain and output of the nMOS field effect transistor 402.

[0077] The source of the nMOS field effect transistor 402 is connected to the outside. The gate of the nMOS field effect transistor 402 is connected to the input. The drain of the nMOS field effect transistor 402 is connected to one end of the resistor 401, the output.

[0078] The source of the pMOS field effect transistor 403 is connected to the outside. The gate of the pMOS field effect transistor 403 is connected to the input. The drain of the pMOS field effect transistor 403 is connected to one end of the resistor 404, which is the output.

[0079] One end of the resistor 404 is connected to the drain and output of the pMOS field effect transistor 403. The other end of the resistor 404 is connected to the outside.

[0080] 6 is a circuit diagram showing a basic cooperative power supply. The positive side of a solar cell 511 is connected to the positive side of a resistor 501 and the input of a DC-DC converter 503. The negative side of the solar cell 511 is connected to GND.

[0081] One end of resistor 501 is connected to the positive side of solar cell 511 and the input of DC / DC converter 503. The other end of resistor 501 is connected to one end of resistor 502 and the input of inverter 506.

[0082] One end of resistor 502 is connected to one end of resistor 501 and the input of inverter 506. The other end of resistor 502 is connected to GND.

[0083] The input of DC / DC converter 503 is connected to the positive side of solar cell 511 and one end of resistor 501. The output of DC / DC converter 503 is connected to one end of switching element 504.

[0084] One end of switching element 504 is connected to the output of DC / DC converter 503. The other end of switching element 504 is connected to one end of switching element 505. A control terminal of switching element 504 is connected to the output of inverter 506 and the input of inverter 507.

[0085] One end of switching element 505 is connected to one end of switching element 504 and the positive side of object to be charged 510. The other end of switching element 505 is connected to the positive side of AC adapter 508. A control terminal of switching element 505 is connected to the output of inverter 507.

[0086] The input of the pMOS inverter 506 is connected to one end of the resistor 501 and the other end of the resistor 502. The output of the pMOS inverter 506 is connected to the control terminal of the switching element 504 and the input of the inverter 507.

[0087] The input of the pMOS inverter 507 is connected to the control terminal of the switching element 504 and the output of the inverter 506. The output of the inverter 507 is connected to the control terminal of the switching element 505.

[0088] The positive output side of AC adapter 508 is connected to switching element 505. The negative output side of AC adapter 508 is connected to GND. The positive input side of AC adapter 508 is connected to commercial power supply 509. The negative input side of AC adapter 508 is connected to GND.

[0089] The positive output side of commercial power supply 509 is connected to the positive input side of AC adapter 508. The negative output side of AC adapter 509 is connected to GND.

[0090] Figure 7 shows the relationship between the input generated current, simulated solar output current, and AC adapter output current in the cooperative charging circuit of Figure 6. The simulated solar output current extends from the bottom left to the top right. The AC adapter output current extends from the top left to the bottom right.

[0091] Figure 8 shows the relationship between the voltage across the solar cell, the current extracted from both ends of the solar cell, and the power that can be extracted from the solar cell.

[0092] Fig. 9 is a simplified diagram of the configuration in the first embodiment. Fig. 9 basically corresponds to Fig. 1 and Fig. 2, but is a diagram for understanding the outline in the process of understanding the present invention.

[0093] The configuration in the first embodiment includes a solar cell 11, resistors 105, 106, 107, a DC-DC converter 122, an inverter 108, an inverter 109, an inverter 110, an inverter 129, an inverter 130, a switching element 125-1, a switching element 127, a computer (PC) power supply 13, and a commercial AC 14.

[0094] The positive side of the solar cell 11 is connected to one end of the resistor 105 and the DC-DC converter 122. The negative side of the solar cell 11 is connected to GND.

[0095] One end of the resistor 105 is connected to the positive side of the solar cell 11 and the DC-DC converter 122. The other end of the resistor 105 is connected to one end of a resistor 106 and the input of the inverter 110.

[0096] One end of resistor 106 is connected to one end of resistor 105 and the input of inverter 110. The other end of resistor 106 is connected to one end of resistor 107 and the input of inverter 108.

[0097] One end of the resistor 107 is connected to one end of the resistor 106 and the input of the inverter 108. The other end of the resistor 107 is connected to GND.

[0098] An input of the DC-DC converter 122 is connected to the positive side of the solar cell 11 and one end of the resistor 105. An output of the DC-DC converter 122 is connected to one end of the switching element 125-1.

[0099] The input of the inverter 110 is connected to one end of the resistor 105 and one end of the resistor 106. The output of the inverter 110 is connected to the input of the inverter 130.

[0100] The input of the inverter 108 is connected to one end of the resistor 106 and one end of the resistor 107. The output of the inverter 108 is connected to the input of the inverter 109.

[0101] The input of inverter 109 is connected to the output of inverter 108. The output of inverter 109 is connected to the input of inverter 129.

[0102] The input of the inverter 130 is connected to the output of the inverter 110. The output of the inverter 130 is connected to the control terminal of the switching element 127.

[0103] The input of the inverter 129 is connected to the output of the inverter 109. The output of the inverter 129 is connected to the control terminal of the switching element 125-1.

[0104] The input of switching element 125-1 is connected to the output of DC / DC converter 122. The output of switching element 125-1 is connected to the output of switching element 127, the output of FIG. 9. The control terminal of switching element 125-1 is connected to the output of inverter 129.

[0105] An input of the switching element 127 is connected to the positive side of the computer (PC) power supply 13. An output of the switching element 127 is connected to the output of the switching element 125-1, external to Figure 9. A control terminal of the switching element 127 is connected to the inverter 130.

[0106] The positive input side of the computer (PC) power supply 13 is connected to the positive side of the commercial power supply 14. The negative input side of the computer (PC) power supply 13 is connected to the negative side of the commercial power supply 14. The positive output side of the computer (PC) power supply 13 is connected to the input of the switching element 127. The negative output side of the computer (PC) power supply 13 is connected to GND.

[0107] The positive side of the commercial power supply 14 is connected to the positive input side of the computer (PC) power supply 13. The negative side of the commercial power supply 14 is connected to the negative input side of the computer (PC) power supply 13.

[0108] Figure 10 shows the circuits used to compare inverters and the simulation results. Figure 10(a) is the circuit diagram used in the simulation of circuit 1. Figure 10(b) shows the 12V simulation results of the static characteristics of circuit 1. Figure 10(c) shows the 5V simulation results of the static characteristics of circuit 2. Figure 10(d) shows the 12V simulation results of the dynamic characteristics of circuit 3. Figure 10(e) shows the 5V simulation results of the dynamic characteristics of circuit 4. Figure 10 is the diagram used in the simulation and is not a drawing of the circuit believed to be the best, so the details of the connections will not be explained.

[0109] Figure 11 shows the circuits used to compare inverters in Circuit I and the simulation results. Figure 11(a) is the circuit diagram used in the simulation of Circuit I. Figure 11(b) shows the 12V simulation results of the static characteristics of Circuit I. Figure 11(c) shows the 5V simulation results of the static characteristics of Circuit I. Figure 11(d) shows the 12V simulation results of the dynamic characteristics of Circuit I. Figure 11(e) shows the 5V simulation results of the dynamic characteristics of Circuit I. Figure 11(a) is the diagram used in the simulation and is not a drawing of what we believe to be the best circuit, so we will not explain the details of the connections.

[0110] FIG. 12 shows the circuits used to compare inverters in circuit 1 and the simulation results. FIG. 12(a) is the circuit diagram used in the simulation of circuit 1. FIG. 12(b) is the simulation result of the static characteristics of circuit 1 at 12V. FIG. 12(c) is the simulation result of the static characteristics of circuit 1 at 5V. FIG. 12(d) is the simulation result of the dynamic characteristics of circuit 1 at 12V. FIG. 12(e) is the simulation result of the dynamic characteristics of circuit 1 at 5V. FIG. 12(a) is the diagram used in the simulation and is not a drawing of the circuit believed to be the best, so the details of the connections will not be explained.

[0111] Figure 13 shows the circuits used to compare inverters and the simulation results. Figure 13(a) is the circuit diagram used in the simulation of the circuit. Figure 13(b) is the simulation result of the static characteristics of the circuit at 12V. Figure 13(c) is the simulation result of the static characteristics of the circuit at 5V. Figure 13(d) is the simulation result of the dynamic characteristics of the circuit at 12V. Figure 13(e) is the simulation result of the dynamic characteristics of the circuit at 5V. Figure 13(a) is the diagram used in the simulation and is not a drawing of the circuit believed to be the best, so the details of the connections will not be explained.

[0112] Figure 14 shows the circuits used to compare the inverters in Circuit 1 and the simulation results. Figure 14(a) is the circuit diagram used in the simulation of Circuit 1. Figure 14(b) shows the 12V simulation results of the static characteristics of Circuit 1. Figure 14(c) shows the 5V simulation results of the static characteristics of Circuit 1. Figure 14(d) shows the 12V simulation results of the dynamic characteristics of Circuit 1. Figure 14(e) shows the 5V simulation results of the dynamic characteristics of Circuit 1. Figure 14(a) is the diagram used in the simulation and is not a drawing of what we believe to be the best circuit, so the details of the connections will not be explained.

[0113] Figure 15 shows the circuits used to compare inverters and the simulation results. Figure 15(a) is the circuit diagram used in the simulation of the circuit. Figure 15(b) shows the 12V simulation results of the static characteristics of the circuit. Figure 15(c) shows the 5V simulation results of the static characteristics of the circuit. Figure 15(d) shows the 12V simulation results of the dynamic characteristics of the circuit. Figure 15(e) shows the 5V simulation results of the dynamic characteristics of the circuit. Figure 15(a) is the diagram used in the simulation and is not a drawing of what we believe to be the best circuit, so the details of the connections will not be explained.

[0114] Figure 16 is an explanatory diagram of when a reverse current prevention diode is required and when it is not. Figure 16(a) is a schematic connection diagram of a coordinated charging system with one solar cell. A reverse current prevention diode is not required. Figure 16(b) is a schematic connection diagram of a coordinated charging system with two solar cells. A reverse current prevention diode is required for each solar cell. Figure 16(c) is a schematic connection diagram of a general independent power supply system with one solar cell. A reverse current prevention diode is required even with one solar cell. Figure 16(d) is a schematic connection diagram of a general independent power supply system with two solar cells. A reverse current prevention diode is required for each solar cell. Detailed explanation of the connections in Figure 16 is omitted.

[0115] Figure 17 is a circuit diagram of the part that links with the power button of a computer (PC). Figure 17 is a part of Figure 2. The connections of the circuit in Figure 17 have been explained in Figure 2, so explanation of the connections in Figure 17 will be omitted.

[0116] Figure 18 shows the pin assignment of a CPU power connector. As of 2025, the most common CPU power connectors are 8-pin. Therefore, this example will be explained assuming an 8-pin configuration. Although 4-pin connectors also exist, the concept is similar.

[0117] The role of pin 1 is GND, and in this embodiment, the input side is connected to 205 (GND), and the output side is connected to 207 (GND). The role of pin 2 is GND, and in this embodiment, the input side is connected to 205 (GND), and the output side is connected to 207 (GND). The role of pin 3 is GND, and in this embodiment, the input side is connected to 205 (GND), and the output side is connected to 207 (GND). The role of pin 4 is GND, and in this embodiment, the input side is connected to 205 (GND), and the output side is connected to 207 (GND).

[0118] The role of pin 5 is 12V, and in this embodiment, the input side is connected to 206 (12V), and the output side is connected to 204 (12V). The role of pin 6 is 12V, and in this embodiment, the input side is connected to 206 (12V), and the output side is connected to 204 (12V). The role of pin 7 is 12V, and in this embodiment, the input side is connected to 206 (12V), and the output side is connected to 204 (12V). The role of pin 8 is 12V, and in this embodiment, the input side is connected to 206 (12V), and the output side is connected to 204 (12V).

[0119] Thus, an 8-pin CPU power connector has four 12V pins and four GND pins, while a 4-pin CPU power connector has two 12V pins and two GND pins.

[0120] Figure 19 shows the pin assignment of a motherboard power connector. As of 2025, the most common motherboard power connectors will have a 24-pin configuration. Therefore, this example will be explained assuming a 24-pin configuration. Connectors with a 20-pin configuration also exist, but the concept is similar.

[0121] The role of pin 1 is 3.3V, and in this embodiment, it connects the input side and the output side. The role of pin 2 is 3.3V, and in this embodiment, it connects the input side and the output side. The role of pin 3 is GND, and in this embodiment, the input side is connected to 205 (GND) and the output side is connected to 207 (GND). The role of pin 4 is 5V, and in this embodiment, the input side is connected to 210 (5V) and the output side is connected to 208 (5V).

[0122] The role of pin 5 is GND, and in this embodiment, the input side is connected to 205 (GND), and the output side is connected to 207 (GND). The role of pin 6 is 5V, and in this embodiment, the input side is connected to 210 (5V), and the output side is connected to 208 (5V). The role of pin 7 is GND, and in this embodiment, the input side is connected to 205 (GND), and the output side is connected to 207 (GND). The role of pin 8 is PWR_OK (power OK), and it receives a signal indicating whether the power is on, and in this embodiment, it connects the input side and output side, and is further connected to terminal 203 toward the delay circuit.

[0123] Pin 9 is a 5VFSB (5 volt FSB) pin that provides 5V even when the computer (PC) is turned off, and in this embodiment, the input and output sides are connected. Pin 10 is a 12V pin, and in this embodiment, the input side is connected to 206 (12V), and the output side is connected to 204 (12V). Pin 11 is a 12V pin, and in this embodiment, the input side is connected to 206 (12V), and the output side is connected to 204 (12V). Pin 12 is a 3.3V pin, and the input and output sides are connected.

[0124] Pin 13 has a function of 3.3V, and in this embodiment, it connects the input side and the output side. Pin 14 has a function of -12V, and in this embodiment, it connects the input side and the output side. Pin 15 has a function of GND, and in this embodiment, the input side is connected to 205 (GND), and the output side is connected to 207 (GND). Pin 16 has a function of PS_ON (PS_ON), ​​and is a terminal for turning on the power supply, and in this embodiment, it connects the input side and the output side.

[0125] The role of pin 17 is GND, and in this embodiment, the input side is connected to 205 (GND), and the output side is connected to 207 (GND). The role of pin 18 is GND, and in this embodiment, the input side is connected to 205 (GND), and the output side is connected to 207 (GND). The role of pin 19 is GND, and in this embodiment, the input side is connected to 205 (GND), and the output side is connected to 207 (GND). The role of pin 20 is -5V, and in this embodiment, the input and output are connected.

[0126] The role of pin 21 is 5V, and in this embodiment, the input side is connected to 210 (5V), and the output side is connected to 208 (5V). The role of pin 22 is 5V, and in this embodiment, the input side is connected to 210 (5V), and the output side is connected to 208 (5V). The role of pin 23 is 5V, and in this embodiment, the input side is connected to 210 (5V), and the output side is connected to 208 (5V). The role of pin 24 is GND, and in this embodiment, the input side is connected to 205 (GND), and the output side is connected to 207 (GND).

[0127] The 20-pin motherboard power connector consists of only pins 1 to 10 and pins 13 to 22 of the 24-pin motherboard power connector.

[0128] There are six types of power supplies: 12 V, normal 5 V, always-on 5 V (5VFSB), 3.3 V, -5 V, and -12 V. In this embodiment, only 12 V and normal 5 V are used for coordinated power supply, and for always-on 5 V (5VFSB), 3.3 V, -5 V, and -12 V, the input and output are simply connected.

[0129] The reason is that 12V and regular 5V handle a lot of power, while always-on 5V (5VFSB), 3.3V, -5V, and -12V handle less power. Even if the power handled is small, if a dedicated DC-DC converter is provided, a certain amount of power is required even with no load or low load. This results in reduced power efficiency.

[0130] PWR_OK is a signal line that receives whether power is being supplied from the computer (PC) power supply. When PWR_OK is L (low), it indicates that power is being supplied from the computer (PC) power supply, and when it is H (high), it indicates that power is not being supplied from the computer (PC) power supply. A delay is created by the resistor 102, capacitor 103, and nMOS field effect transistor 104 in Figures 2 and 17. When the PWR_OK signal changes from L (low) to H (high), power supply from the solar cell 11 ends after a certain delay. When the WR_OK signal changes from H (high) to L (low), power supply from the solar cell 11 starts after a certain delay.

[0131] Figure 20 shows the wiring assignment for a storage power connector. As of 2025, the most common storage power connectors have a 5-pin connector and a 15-pin wiring configuration. Therefore, this example will be explained assuming a 5-pin connector and 15-pin wiring.

[0132] Pin 1 is 3.3V and in this embodiment connects the input side and output side. Pin 2 is 3.3V and in this embodiment connects the input side and output side. Pin 3 is 3.3V and in this embodiment connects the input side and output side. Pins 1, 2, and 3 are connected to the same wiring.

[0133] The role of pin 4 is GND, and in this embodiment, the input side is connected to 205 (GND), and the output side is connected to 207 (GND). The role of pin 5 is GND, and in this embodiment, the input side is connected to 205 (GND), and the output side is connected to 207 (GND). The role of pin 6 is GND, and in this embodiment, the input side is connected to 205 (GND), and the output side is connected to 207 (GND). Pins 4, 5, and 6 are connected to the same wiring.

[0134] The role of pin 7 is 5V, and in this embodiment, the input side is connected to 210 (5V), and the output side is connected to 208 (5V). The role of pin 8 is 5V, and in this embodiment, the input side is connected to 210 (5V), and the output side is connected to 208 (5V). The role of pin 9 is 5V, and in this embodiment, the input side is connected to 210 (5V), and the output side is connected to 208 (5V). Pins 7, 8, and 9 are connected to the same wiring.

[0135] The role of pin 10 is GND, and in this embodiment, the input side is connected to 205 (GND), and the output side is connected to 207 (GND). The role of pin 11 is GND, and in this embodiment, the input side is connected to 205 (GND), and the output side is connected to 207 (GND). The role of pin 12 is GND, and in this embodiment, the input side is connected to 205 (GND), and the output side is connected to 207 (GND). Pins 10, 11, and 12 are connected to the same wiring.

[0136] The role of pin 13 is 5V, and in this embodiment, the input side is connected to 206 (12V), and the output side is connected to 204 (12V). The role of pin 14 is 12V, and in this embodiment, the input side is connected to 206 (12V), and the output side is connected to 204 (12V). The role of pin 15 is 5V, and in this embodiment, the input side is connected to 206 (12V), and the output side is connected to 204 (12V). Pins 13, 14, and 15 are connected to the same wiring.

[0137] Storage power connectors use three types of power: 12V, 5V, and 3.3V. Of these, 3.3V is only used by some storage devices, such as 1.8-inch hard disks. Some M2-type SSDs seem to use 3.3V, but since they are powered by the motherboard, storage power connectors often do not supply 3.3V.

[0138] In this embodiment, the 12 V and 5 V voltages are supplied from a solar cell because the 12 V and 5 V voltages require large amounts of power.

[0139] Figure 21 shows the pin assignment for a graphics card power connector. As of 2025, the most common types of graphics card power connectors are the 6-pin and 8-pin types. The 6-pin type is expected to supply up to 75W of power, and the 8-pin type is expected to supply up to 150W of power.

[0140] Pin 1 functions as GND, and in this embodiment, the input side is connected to 205 (GND) and the output side is connected to 207 (GND). Pin 2 functions as SENSE, and is used to inform the graphics board of the amount of power that can be supplied. In this embodiment, the input side is connected to 205 (GND) and the output side is connected to 207 (GND). Pin 3 functions as GND, and in this embodiment, the input side is connected to 205 (GND) and the output side is connected to 207 (GND). Pin 4 functions as GND, and in this embodiment, the input side is connected to 205 (GND) and the output side is connected to 207 (GND). Pin 5 functions as SENSE, and is used to inform the graphics board of the amount of power that can be supplied. Pin 6 functions as 12V, and in this embodiment, the input side is connected to 206 (12V) and the output side is connected to 204 (12V). The role of pin 7 is 12V, and in this embodiment, the input side is connected to 206 (12V), and the output side is connected to 204 (12V). The role of pin 8 is 12V, and in this embodiment, the input side is connected to 206 (12V), and the output side is connected to 204 (12V).

[0141] Pins 2 and 5 function as SENSE pins, and connecting both to GND clearly indicates that up to 150W of power can be supplied. While I'm not sure if this is generally true, in my own experiments, I found that even when pins 2 and 5 were connected to GND, if power was not supplied to the graphics card power connector, the graphics card could be permanently damaged. Therefore, care must be taken when supplying power to a graphics card using the circuit and method of this invention.

[0142] Furthermore, graphics functions are built into many CPUs, and computers (PCs) often operate without a dedicated graphics board. Even when a dedicated graphics board is used, if the dedicated graphics board consumes little power, it can operate using only the power supplied from the motherboard, without needing to supply power using the graphics board power connector.

[0143] FIG. 22 is a diagram showing the relationship between the power connector and the circuit of the present invention.

[0144] Figure 22(a) shows only the 12V portion of the wiring between the computer (PC) power supply connected from the computer (PC) power supply and the motherboard connected to the motherboard in a conventional power supply for a motherboard. Simply, pin 10 on the computer (PC) power supply side is connected to pin 10 on the motherboard side, and pin 11 on the computer (PC) power supply side is connected to pin 11 on the motherboard side.

[0145] Figure 22(b) shows only the 12V portion of the wiring between the computer (PC) power supply connected from the computer (PC) power supply and the motherboard connected to the motherboard in the power supply for the motherboard in the present invention. Pins 10 and 11 on the computer (PC) power supply side are connected to terminal 204. Pins 10 and 11 on the motherboard side are connected to terminal 206. The solar cell is connected to terminal 201.

[0146] Switching element 127 controls the power from the computer (PC) power supply and supplies it to the motherboard side. Similarly, switching element 125-1 controls the power from solar cell 11 and supplies it to the motherboard side. Switching element 127 and switching element 125-1 combine the power from the computer (PC) power supply and the power from solar cell 11 and supply it cooperatively.

[0147] In FIG. 22, only the motherboard and 12V have been described. However, the same applies to the CPU, storage, and graphics board, and also to 5V. In the case of the present invention, 12V from the computer (PC) power supply for the CPU, storage, and graphics board is connected to terminal 204, and 12V for the CPU, storage, and graphics board is connected to terminal 206. For 5V, a similar circuit is prepared on a separate system.

[0148] The operation of the system and circuit of this embodiment will now be described. Figure 1 is a block diagram of a first embodiment of the present invention. DC power is generated in a solar cell 11 and supplied to a main circuit 12. This embodiment assumes a 12V solar cell, but the concept is similar for 24V and 48V systems.

[0149] The DC generated by the solar cell 11 has an open circuit voltage, which is the voltage when there is no load, of 21 V, and a short circuit current, which is the current when the output is short-circuited, of 5 A, for example. The values ​​given here are assumed examples, and various solar cells can be used. The DC generated by the solar cell 11 is, for example, about 17.5 V.

[0150] AC is supplied from a commercial power supply 14. The AC supplied here is 100V to 220V worldwide. It is 100V in Japan, 110V in the United States, and 220V in China. The AC supplied from the commercial power supply 14 is supplied to a computer (PC) power supply 13, which generates 12V, normal 5V, 3.3V, continuous power supply 5V, -5V, and -12V. In this embodiment, the 12V and normal 5V are supplied to a main circuit 12. The main circuit 12 receives power from a solar cell 11.

[0151] The power supplied from the solar cell 11 to the main circuit 12 is converted to 12V and 5V in the main circuit 12. In the main circuit 12, the 12V generated in the main circuit 12 and the 12V generated in the computer (PC) power supply 13 are mixed together by coordinated power supply. Coordinated power supply is a technology that mixes the power from the solar cell and the power supply for the computer (PC) using feedback control, and its characteristic is that the power from the solar cell is used preferentially, and only when the power from the solar cell is insufficient, power from the computer (PC) power supply is used.

[0152] The 12V power generated by the cooperative power supply is supplied to the CPU 15, the motherboard 16, the storage 17, and the auxiliary GPU 18. The 5V power generated by the cooperative power supply is supplied to the motherboard 16 and the storage 17.

[0153] In this embodiment, the 12V generated by the main circuit 12 and the 12V generated by the computer (PC) power supply are combined by coordinated power supply to generate coordinated 12V, and the 5V generated by the main circuit 12 and the normal 5V generated by the computer (PC) power supply are combined by coordinated power supply to generate coordinated 5V. On the other hand, for 3.3V, constant 5V supply, -5V, and -12V, coordinated power supply is not performed, and the voltage generated by the computer (PC) power supply is supplied directly to the motherboard 16 and storage 17.

[0154] The reason is that 12V and regular 5V handle a lot of power, while always-on 5V (5VFSB), 3.3V, -5V, and -12V handle less power. Even if the power handled is small, if a dedicated DC-DC converter is provided, a certain amount of power is required even with no load or low load. This reduces the overall power efficiency.

[0155] Although the always-on 5V (5VFSB), -5V, and -12V are omitted from Figure 1, the always-on 5V (5VFSB), -5V, and -12V are supplied directly to the motherboard 16 from the power supply for the computer (PC).

[0156] In this embodiment, as an example believed by the inventors to be the best, only 12V and normal 5V are coordinated for charging, while always-on 5V (5VFSB), 3.3V, -5V, and -12V are not coordinated. It is also possible to coordinate only 12V, while normal 5V, always-on 5V (5VFSB), 3.3V, -5V, and -12V do not require coordinated power supply. In this case, costs for the board, mounted components, and mounting work can be reduced, but the proportion of power consumed by the computer (PC) that can be supplied from the solar cell will be smaller.

[0157] Conversely, it is also possible to coordinate the supply of 12V, normal 5V, always-on 5V (5VFSB), and 3.3V. In this case, the cost of the board, mounted components, and mounting work will increase, but the proportion of the power consumed by the computer (PC) that can be supplied from solar cells will increase.

[0158] When cooperative charging is performed using only 12V and normal 5V, for a computer (PC) that consumes 40W when idle, 30W of the 40W of power consumption can be supplied by the solar cell 11 through cooperative power supply. The remaining 10W is the power required for always-on 5V (5VFSB), 3.3V, -5V, -12V, and for controlling the computer (PC) power supply itself. In this case, even if the solar cell generates more than 30W of power, for example 50W, only 30W of power will be used in this system, and the remaining 20W will be wasted.

[0159] When a computer (PC) is used and a load is placed on it, the power consumed by the 12V (usually 5V) increases. The power consumption of the 12V increases significantly, especially when the load increases on the CPU. Under heavy loads, a large current of 10A or 20A flows through the 12V system. In such cases, the computer (PC) consumes a large amount of power, ranging from 100W to 250W. Most of this power can be supplied by the solar cell 11 through cooperative power supply. For example, if the computer (PC) consumes 120W and the solar cell 11 can supply 110W of power through cooperative power supply, and the solar cell generates 150W, 110W of that power can be effectively utilized. For example, if the computer (PC) consumes 120W and the solar cell 11 can supply 110W of power through cooperative power supply, and the solar cell generates 70W, 70W can be effectively utilized, with the remaining 40W being supplied by the computer (PC) power supply. The power required for the other always-on 5V (5VFSB), 3.3V, -5V, and -12V is also supplied from the computer (PC) power supply. The power required to control the computer (PC) power supply is also added, and for example, about 50W is supplied from commercial power supply 14.

[0160] Next, the operation of the main circuit 12 will be explained using Figure 2. First, the explanation will be made on the assumption that the signal from the terminal 203 is L (low). Because the signal from the terminal 203 is L (low), no voltage is applied between the source and gate of the nMOS field effect transistor 104, and the operation is the same as if the nMOS field effect transistor 104 did not exist.

[0161] A voltage from the solar cell is applied between terminals 201 and 202. Resistive voltage divider 106-1 is composed of resistors 105, 106, and 107, and divides the voltage between terminals 201 and 202.

[0162] The node between resistor 106 and resistor 107 is input to nMOS inverter 108, inverted and amplified, and output. The output of nMOS inverter 108 is input to pMOS field effect transistor 109, inverted and amplified, and output. The output of pMOS field effect transistor 109 is input to nMOS field effect transistor 129 and nMOS field effect transistor 149.

[0163] The output of the nMOS field effect transistor 129 is input to the pMOS field effect transistor 125 and the pMOS field effect transistor 126. The output of the nMOS field effect transistor 149 is input to the pMOS field effect transistor 145 and the pMOS field effect transistor 146.

[0164] The node between resistors 105 and 106 is input to an nMOS inverter 110, which inverts, amplifies, and outputs the signal. The output of pMOS inverter 110 is input to nMOS inverter 130 and nMOS inverter 150.

[0165] The input to terminal 201 is converted to 12V by DC / DC converter 122 and output to node 134. The current between node 134 and node 135 is adjusted by the outputs of pMOS field effect transistor 125, pMOS field effect transistor 126, and nMOS field effect transistor 129.

[0166] The presence of two pMOS field effect transistors, pMOS field effect transistor 125 and pMOS field effect transistor 126, makes it possible to control bidirectional current. That is, when the potential of node 134 is higher than the potential of node 135, the output of nMOS field effect transistor 129 controls the current flowing from node 134 to node 135, and when the potential of node 135 is higher than the potential of node 134, the output of nMOS field effect transistor 126 controls the current flowing from node 135 to node 134.

[0167] The pMOS field effect transistor 127 adjusts the current between the node 136 and the node 135 .

[0168] The input to terminal 201 is converted to 5V by DC / DC converter 142 and output to node 154. The current between node 154 and node 155 is adjusted by pMOS field effect transistor 145 and pMOS field effect transistor 146.

[0169] The presence of two pMOS field effect transistors, pMOS field effect transistor 145 and pMOS field effect transistor 146, makes it possible to control bidirectional current. That is, when the potential of node 154 is higher than the potential of node 155, the pMOS field effect transistor 145 controls the current flowing from node 154 to node 155, and when the potential of node 155 is higher than the potential of node 154, the pMOS field effect transistor 146 controls the current flowing from node 155 to node 154.

[0170] The pMOS field effect transistor 147 controls the current between the node 156 and the node 155 .

[0171] The voltage between terminals 201 and 202 is resistively divided and inverted and amplified three times in total by nMOS inverter 108, pMOS inverter 109, and nMOS inverter 129 to control pMOS field effect transistor 125 and pMOS field effect transistor 126. The voltage between terminals 201 and 202 is resistively divided and inverted and amplified three times in total by nMOS inverter 108, pMOS inverter 109, and nMOS inverter 149 to control pMOS field effect transistor 145 and pMOS field effect transistor 146.

[0172] The voltage between terminals 201 and 202 is resistively divided and inverted and amplified twice in total by a pMOS inverter 110 and an nMOS inverter 130 to control a pMOS field effect transistor 127. The voltage between terminals 201 and 202 is resistively divided and inverted and amplified twice in total by a pMOS inverter 110 and an nMOS inverter 150 to control a pMOS field effect transistor 147.

[0173] When the voltage between terminals 201 and 202 is high, the input voltage of nMOS inverter 108 increases, the output voltage of nMOS inverter 108 decreases, the voltage of pMOS inverter 109 increases, the output voltage of nMOS inverter 129 decreases, and the pMOS field effect transistor 125 and pMOS field effect transistor 126 are turned on. When the voltage between terminals 201 and 202 is low, the input voltage of nMOS inverter 108 decreases, the output voltage of nMOS inverter 108 increases, the voltage of pMOS inverter 109 decreases, and the output voltage of nMOS inverter 129 increases, and the pMOS field effect transistor 125 and pMOS field effect transistor 126 are turned off.

[0174] When the voltage between terminals 201 and 202 is high, the input voltage of nMOS inverter 108 increases, the output voltage of nMOS inverter 108 decreases, the voltage of pMOS inverter 109 increases, the output voltage of nMOS inverter 149 decreases, and the pMOS field effect transistor 145 and pMOS field effect transistor 146 are turned on. When the voltage between terminals 201 and 202 is low, the input voltage of nMOS inverter 108 decreases, the output voltage of nMOS inverter 108 increases, the voltage of pMOS inverter 109 decreases, and the output voltage of nMOS inverter 149 increases, and the pMOS field effect transistor 145 and pMOS field effect transistor 146 are turned off.

[0175] When the voltage between terminals 201 and 202 is high, the input voltage of the pMOS inverter 110 increases, the output voltage of the pMOS inverter 110 decreases, the output voltage of the nMOS inverter 130 increases, and the pMOS field effect transistor 127 is turned off. When the voltage between terminals 201 and 202 is low, the input voltage of the pMOS inverter 110 decreases, the output voltage of the pMOS inverter 110 increases, and the output voltage of the nMOS inverter 130 decreases, and the pMOS field effect transistor 127 is turned on.

[0176] When the voltage between terminals 201 and 202 is high, the input voltage of the pMOS inverter 110 increases, the output voltage of the pMOS inverter 110 decreases, the output voltage of the nMOS inverter 150 increases, and the pMOS field effect transistor 147 is turned off. When the voltage between terminals 201 and 202 is low, the input voltage of the pMOS inverter 110 decreases, the output voltage of the pMOS inverter 110 increases, and the output voltage of the nMOS inverter 130 decreases, and the pMOS field effect transistor 127 is turned on.

[0177] The voltage between terminals 201 and 202 at the boundary between whether the pMOS field effect transistor 125 and the pMOS field effect transistor 145 are turned on or off, which is determined according to the ratio of the resistance value of resistor 105 plus the resistance value of resistor 106 to the resistance value of resistor 107, will be referred to as a first constant voltage value. Similarly, the voltage between terminals 201 and 202 at the boundary between whether the pMOS field effect transistor 127 and the pMOS field effect transistor 147 are turned on or off, which is determined according to the ratio of the resistance value of resistor 105 and the resistance value of resistor 106 plus the resistance value of resistor 107, will be referred to as a second constant voltage value.

[0178] When the voltage between the terminals 201 and 202 is greater than a first constant voltage value, the pMOS field effect transistor 125 and the pMOS field effect transistor 145 are turned on. When the voltage between the terminals 201 and 202 is less than the first constant voltage value, the pMOS field effect transistor 125 and the pMOS field effect transistor 145 are turned off.

[0179] When the voltage between the terminals 201 and 202 is greater than the second constant voltage value, the pMOS field effect transistor 127 and the pMOS field effect transistor 147 are turned off. When the voltage between the terminals 201 and 202 is less than the second constant voltage value, the pMOS field effect transistor 127 and the pMOS field effect transistor 147 are turned on.

[0180] To ensure proper operation of the system of the present invention, the second constant voltage is set higher than the first constant voltage. When the voltage between terminals 201 and 202 is lower than the first constant voltage, the pMOS field-effect transistor 125 and the pMOS field-effect transistor 145 are turned off, and the pMOS field-effect transistor 127 and the pMOS field-effect transistor 147 are turned on. When the voltage between terminals 201 and 202 is higher than the first constant voltage but lower than the second constant voltage, the pMOS field-effect transistor 125 and the pMOS field-effect transistor 145 are turned on, and the pMOS field-effect transistor 127 and the pMOS field-effect transistor 147 are turned on. When the voltage between terminals 201 and 202 is higher than the second constant voltage, the pMOS field-effect transistor 125 and the pMOS field-effect transistor 145 are turned off, and the pMOS field-effect transistor 127 and the pMOS field-effect transistor 147 are turned on.

[0181] For example, the first voltage value is 16.5V and the second constant voltage value is 17.0V. We believe that a value about 0.5V lower than the voltage at which the maximum power can be extracted from the solar cell is optimal. We believe that the second voltage value, taking into account wiring resistance, is optimally set to about 1V lower than the voltage at which the maximum power can be extracted from the solar cell. We also believe that the first voltage value, taking into account a static margin for stable operation of the computer (PC), is optimally set to about 0.5V lower than the second constant voltage value.

[0182] When the voltage between terminals 201 and 202 is near a first constant voltage value, pMOS field-effect transistors 125 and 145 are in a state intermediate between on and off. The switching elements used in locations such as 125 and 145 are preferably ones that can be in a completely off state, a completely on state, or an intermediate state between on and off.

[0183] When the voltage between terminals 201 and 202 is greater than the first constant voltage value, pMOS field effect transistor 125 and pMOS field effect transistor 145 turn on, so that the voltage from solar cell 11 via terminal 201 is converted by DC / DC converter 122, and the current flowing through pMOS field effect transistor 125 increases. As a result, the potential between terminals 201 and 202 drops and becomes smaller than the first constant voltage value, so that the voltage from solar cell 11 via terminal 201 is converted by DC / DC converter 122, and the current flowing through pMOS field effect transistor 125 decreases. As a result, a feedback occurs in which the potential between terminals 201 and 202 rises and becomes larger than the first constant voltage value.

[0184] When the voltage between terminals 201 and 202 is smaller than the second constant voltage value, pMOS field effect transistor 127 and pMOS field effect transistor 147 are turned on, and the current flowing through pMOS field effect transistor 127 increases. As a result, if the power consumed in the demand section of the computer (PC) is the same, the voltage from solar cell 11 via terminal 201 is converted by DC / DC converter 122, and the current flowing through pMOS field effect transistor 125 decreases. As a result, the potential between terminals 201 and 202 increases and becomes larger than the second constant voltage value, and the current flowing through pMOS field effect transistor 127 decreases. As a result, if the power consumed in the demand section of the computer (PC) is the same, the voltage from solar cell 11 via terminal 201 is converted by DC / DC converter 122, and the current flowing through pMOS field effect transistor 125 increases. As a result, the voltage between the terminal 201 and the terminal 202 drops and becomes smaller than the second constant voltage value, which is a feedback effect.

[0185] When the circuit of this embodiment is actually connected to a computer (PC) and operated, the following occurs.

[0186] When the solar cell is not generating power, the voltage between terminals 201 and 202 is zero. When the computer (PC) is on, power is supplied to the power demanding parts of the computer (PC), namely, CPU 15, motherboard 16, storage 17, and GPU, from the commercial power supply 14 and computer (PC) power supply 13. When the computer (PC) is off, only a constant power supply of 5V is supplied to the motherboard 16 from the commercial power supply 14 and computer (PC) power supply 13.

[0187] At this time, even if the potentials of nodes 135 and 136 are about 12 V, pMOS field effect transistor 126 blocks the reverse current, so current does not flow back from node 135 through pMOS field effect transistor 126, pMOS field effect transistor 125, DC / DC converter 122, and terminal 201 to solar cell 11. Therefore, if there is one solar cell, a reverse current prevention diode is not necessary.

[0188] When the solar cell is slightly exposed to sunlight in the early morning or evening, the voltage between terminals 201 and 202 is below a first certain value. When the computer (PC) is on, power is supplied to the power demanding parts of the computer (PC), namely, CPU 15, motherboard 16, storage 17, and GPU, from commercial power supply 14 and computer (PC) power supply 13. When the computer (PC) is off, only a constant power supply of 5V is supplied to motherboard 16 from commercial power supply 14 and computer (PC) power supply 13.

[0189] When the power generated by the solar cell is less than the power consumed by the power demanding parts of a computer (PC), namely the CPU 15, motherboard 16, and storage 17, which are 12V, usually 5V, the voltage between terminals 201 and 202 is balanced at a first constant voltage value, or at a second constant voltage value, or between the first constant voltage value and the second constant voltage value.

[0190] Whether the balance occurs at the first constant voltage value, the second constant voltage value, or somewhere between the first and second constant voltage values ​​is often determined by the magnitude relationship between the output of DC / DC converter 122 and the 12V output of computer (PC) power supply 13, and the magnitude relationship between the output of DC / DC converter 142 and the 5V output of computer (PC) power supply 13. Normally, the system of the present invention operates stably whether the balance occurs at the first constant voltage value, the second constant voltage value, or somewhere between the first and second constant voltage values, so it does not matter which one it is.

[0191] To simplify the discussion, let's assume that there is only a 12V system.

[0192] If the output of the DC-DC converter 122 is higher than the 12V (actually, it is often slightly higher) of the computer (PC) power supply 13, the power supplied from the solar cell 11 via the DC-DC converter 122 is used in preference to the power supplied from the 12V of the computer (PC) power supply 13. Note that this can be said in terms of the magnitude of the supply voltage, but control by switching control is not taken into consideration. All of the power supplied from the solar cell 11 via the DC-DC converter 122 is used by the power demand section of the computer (PC), and only the shortfall in power is supplied from the 12V of the computer (PC) power supply 13. In this case, if the power supplied from the solar cell 11 via the DC-DC converter 122 is higher than the power generated by the solar cell 11, the pMOS field-effect transistor 125 turns on, and the voltage between terminals 201 and 202 drops below the first constant voltage value. When the power supplied from the solar cell 11 via the DC-DC converter 122 is smaller than the power generated by the solar cell 11, the pMOS field-effect transistor 125 turns off, and the voltage between the terminals 201 and 202 rises and exceeds the first constant voltage value. As a result, the voltage between the terminals 201 and 202 becomes the first constant voltage value.

[0193] When the output of the DC-DC converter 122 is lower than the 12V (actually, it is often slightly higher) of the computer (PC) power supply 13, the power supplied from the 12V of the computer (PC) power supply 13 is used with priority over the power supplied from the solar cell 11 via the DC-DC converter 122. Note that this can be said in terms of the magnitude of the supply voltage, but switching control is not taken into consideration. In this case, when the voltage between terminals 201 and 202 is between the first constant voltage value and the second constant voltage value, power is supplied from the solar cell 11 via the DC-DC converter 122 and also from the 12V of the computer (PC) power supply 13. Therefore, during this period, the voltage between terminals 201 and 202 continues to rise. What happens if the voltage between terminals 201 and 202 reaches the second voltage value?

[0194] In this example, the power generated by the solar cell 11 is less than the power consumed by the 12V (usually 5V) power demands of the computer (PC), namely, the CPU 15, the motherboard 16, and the storage 17. Therefore, all of the power supplied from the solar cell 11 via the DC-DC converter 122 is used by the power demands of the computer (PC). As a result, when the voltage between the terminals 201 and 202 exceeds a second constant voltage, the pMOS field-effect transistor 127 turns off, and the current supplied from the 12V power supply 13 for the computer (PC) decreases. This increases the current supplied from the solar cell 11 via the DC-DC converter 122. As a result, the voltage between the terminals 201 and 202 decreases and falls below the second constant voltage. As a result, when the voltage between the terminals 201 and 202 falls below the second constant voltage, the pMOS field-effect transistor 127 turns on, and the current supplied from the 12V power supply 13 for the computer (PC) increases. Therefore, the current supplied from solar cell 11 via DC / DC converter 122 decreases. As a result, the voltage between terminals 201 and 202 increases and exceeds the second constant voltage value. Therefore, the voltage between terminals 201 and 202 becomes the second constant voltage value.

[0195] In addition, when the output of the DC-DC converter 122 and the 12V of the computer (PC) power supply 13 are almost the same, the voltage between the terminals 201 and 202 may be between the first constant voltage value and the second constant voltage value.

[0196] The above has been a description of the case where only the 12V system is used. When a 5V system is added, the situation becomes more complicated, but the fact remains that the voltage between terminals 201 and 202 can be balanced at a first constant voltage value, at a second constant voltage value, or at both the first and second constant voltage values.

[0197] Even in the same system, the voltage between terminals 201 and 202 may switch between being balanced at a first constant voltage value, being balanced at the first constant voltage value, and being balanced at a second constant voltage value.

[0198] As described above, when the power generated by the solar cell is less than the power consumed by the 12V (usually 5V) power demand parts of the computer (PC), namely the CPU 15, motherboard 16, and storage 17, the power supplied from the solar cell 11 via the DC-DC converter 122 and the power supplied from the commercial power supply 14 and the computer (PC) power supply 13 are coordinated to supply power to the power demand parts of the computer (PC). This is based on feedback control. The power supplied from the solar cell 11 via the DC-DC converter 122 is used preferentially, and only the power supplied from the commercial power supply 14 and the computer (PC) power supply 13 is used to meet the power demand.

[0199] This is called cooperative power supply. Cooperative power supply makes it possible to effectively use the power from solar cell 11, even without a storage battery, as long as the power is used by the consumer of solar cell 11.

[0200] When the power generated by the solar cell is greater than the power consumed by the 12V and normal 5V components of the power demanding components of the computer (PC), namely, the CPU 15, motherboard 16, and storage 17, the voltage between terminals 201 and 202 becomes equal to or greater than a second constant voltage value. When the computer (PC) is on, power is supplied from the solar cell 11 to the 12V and normal 5V components of the CPU 15, motherboard 16, storage 17, and GPU. When the computer (PC) is off, only the constant 5V power supply is supplied to the motherboard 16 from the commercial power supply 14 and computer (PC) power supply 13.

[0201] Next, the VDD power supply supplied to the nMOS inverter 108, the pMOS inverter 109, the pMOS inverter 110, the nMOS inverter 129, the nMOS inverter 130, the nMOS inverter 149, and the nMOS inverter 150 will be explained.

[0202] The VDD power supply of the nMOS inverter 108 , the pMOS inverter 109 , the pMOS inverter 110 , the nMOS inverter 129 , and the nMOS inverter 130 is connected to a node 137 .

[0203] Node 137 is connected from node 134 via diode 124 and from node 136 via diode 128. Due to diodes 124 and 128, when at least one of node 134 and node 136 is at about 12 V, node 137 appears at a value close to 12 V, or more precisely, a value obtained by subtracting the forward drop voltage of the diode from 12 V.

[0204] The VDD power supply of the nMOS inverter 149 and the nMOS inverter 150 is connected to a node 157 .

[0205] Node 157 is connected from node 154 via diode 144 and from node 156 via diode 148. When at least one of node 154 and node 156 is at about 5 V, due to diodes 144 and 148, node 157 appears at a value close to 5 V, or more precisely, a value obtained by subtracting the forward drop voltage of the diode from 5 V.

[0206] In this manner, a stable VDD power supply of approximately 12 V is supplied to the nMOS inverter 108, the pMOS inverter 109, the pMOS inverter 110, the nMOS inverter 129, and the nMOS inverter 130, and a stable VDD power supply of approximately 5 V is supplied to the nMOS inverter 149 and the nMOS inverter 150.

[0207] In addition, the nMOS inverter 149 and the nMOS inverter 150 have an inverting and amplifying function and also function as a 12V to 5V level shifter, and supply 5V L (low) and H (high) signals to the gates of the pMOS field effect transistor 145, the pMOS field effect transistor 146, and the pMOS field effect transistor 147.

[0208] The conditions required for the system of the present invention are as follows: 1. It operates efficiently. 2. Stable operation is.

[0209] In order to operate efficiently, 1A. Use highly efficient DC-DC converters 122 and 142; 1B. In the circuit of Figure 2, minimize the power consumption of parts other than the DC-DC converter. is important.

[0210] 1A. Using efficient DC / DC converters 122 and 142 is a completely separate issue and a separate technology. Therefore, this document does not discuss improving the efficiency of DC / DC converters.

[0211] DC-DC converters are mounted on small circuit boards and are commercially available for a few thousand yen with a maximum output of 240 W and a maximum efficiency of 97%. Such high-efficiency DC-DC converters can be used for DC-DC converter 122 and DC-DC converter 142.

[0212] 1B. In the circuit of FIG. 2, in order to minimize the power consumption of parts other than the DC-DC converter, it is important to reduce the current consumption of the resistive voltage divider, each inverter, capacitor, etc.

[0213] For example, when the overall resistance of the resistive voltage divider 106-1 is set to around several kΩ, it operates stably and current consumption is reduced. When the resistors in each inverter (resistors 401 and 404 in Figure 5) are set to around 100 kΩ, it operates stably and current consumption is reduced. The higher the resistance value of the resistors used, the less power consumption there is, but stability also decreases. It is a good idea to experiment to find the optimum resistance value. The optimum value differs depending on the application and mounted components.

[0214] Regarding capacitors, if the voltage applied across them is sufficiently lower than the breakdown voltage of the capacitor, the leakage current is significantly reduced. Therefore, the breakdown voltage of the capacitor should be sufficiently high.

[0215] For stable operation, 2A. Maintain a static margin 2B. Ensure dynamic margins 2C. Connect a capacitor to each point. It is important to do so.

[0216] Here, the static margin is defined as the difference between the voltage between terminals 201 and 202 at which pMOS field-effect transistor 125 switches on and off, and the voltage between terminals 201 and 202 at which pMOS field-effect transistor 127 switches on and off. In other words, it is the difference between the first constant voltage value and the second constant voltage value. It is measured in volts (V). A suitable static margin is, for example, 0.5V. While a larger static margin has the advantage of providing stable operation, it also has the disadvantage that the voltage extracted from the solar cell deviates from the optimum value, reducing the power that can be extracted from the solar cell.

[0217] A system with a static margin of around 0.5 to 0.6V was used as a normal computer (PC) for two months and did not experience a single unintended power shutdown, unintended restart, or blue screen error, whereas a system with a static margin of less than 10mV (millivolts) experienced an average of one unintended power shutdown, unintended restart, or blue screen error per day.

[0218] It is not easy to determine exactly how much static margin is needed, but it is the inventor's opinion that 0.5V is sufficient from a reliability standpoint.

[0219] The voltage between terminals 201 and 202 is resistively divided and inverted and amplified three times by nMOS inverter 108, pMOS inverter 109, and nMOS inverter 129 to control pMOS field effect transistor 125 and pMOS field effect transistor 126. The voltage between terminals 201 and 202 is resistively divided and inverted and amplified three times by nMOS inverter 108, pMOS inverter 109, and nMOS inverter 149 to control pMOS field effect transistor 145 and pMOS field effect transistor 146.

[0220] The voltage between terminals 201 and 202 is resistively divided and inverted and amplified twice by a pMOS inverter 110 and an nMOS inverter 130 to control a pMOS field effect transistor 127. The voltage between terminals 201 and 202 is resistively divided and inverted and amplified twice by a pMOS inverter 110 and an nMOS inverter 150 to control a pMOS field effect transistor 147.

[0221] In this way, by providing two amplification systems, it is possible to differentiate between the first constant voltage value, which is the voltage between the terminals 201 and 202 at the on / off boundary of the pMOS field effect transistor 125 and the pMOS field effect transistor 145, and the second constant voltage value, which is the voltage between the terminals 201 and 202 at the on / off boundary of the pMOS field effect transistor 127 and the pMOS field effect transistor 147.

[0222] The resistance value of resistor 105 is, for example, 1500 Ω, the resistance value of resistor 106 is, for example, 1847 Ω, and the resistance value of resistor 107 is, for example, 300 Ω. In this case, the first constant voltage value is, for example, 16.5 V, and the second constant voltage value is, for example, 17.0 V, although this will depend on the design of other parts and the selection of elements.

[0223] Next, we will discuss the dynamic margin. When the voltage between terminals 201 and 202 changes from a high voltage to a low voltage in a short time, pMOS field-effect transistor 125 changes from on to off, and pMOS field-effect transistor 127 changes from off to on. When the voltage between terminals 201 and 202 changes from a low voltage to a high voltage in a short time, pMOS field-effect transistor 125 changes from off to on, and pMOS field-effect transistor 127 changes from on to off.

[0224] The difference between the time when the pMOS field-effect transistor 125 changes from on to off and the time when the pMOS field-effect transistor 127 changes from off to on, the time when the pMOS field-effect transistor 125 changes from off to on and the time when the pMOS field-effect transistor 127 changes from on to off will be called the dynamic margin.

[0225] Securing a dynamic margin means making a difference between the time when the pMOS field effect transistor 125 changes from on to off and the time when the pMOS field effect transistor 127 changes from off to on, and making a difference between the time when the pMOS field effect transistor 125 changes from off to on and the time when the pMOS field effect transistor 127 changes from on to off.

[0226] One method for achieving this is to differentiate between the time it takes for the switching element to be controlled to change on and off after the voltage between terminals 201 and 202 changes from a small voltage to a large voltage in a short time, and the time it takes for the switching element to be controlled to change on and off after the voltage between terminals 201 and 202 changes from a large voltage to a small voltage in a short time, for each system.

[0227] To achieve this, it is advisable to use an nMOS inverter as the final stage of the amplification system, as shown in Figure 5(a). In an nMOS inverter as shown in Figure 5(a), when the input changes from L (low) to H (high), the potential of the output node drops sharply via the nMOS field-effect transistor 402. As a result, the speed at which the output changes from H (high) to L (low) is fast. Therefore, for example, the speed at which the pMOS field-effect transistor 125 changes from off to on is fast.

[0228] When the input changes from H (high) to L (low), the potential of the output node rises slowly via resistor 401. Therefore, the speed at which the output changes from L (low) to H (high) is slow. Therefore, for example, the speed at which pMOS field effect transistor 125 changes from on to off is slow.

[0229] where: In order to slow down the speed at which the output changes from L (low) to H (high) in Figure 5(a), it is necessary to connect capacitance to the output section of Figure 5(a). One way to do this is to connect a capacitor. However, it is possible to add a capacitance component without intentionally connecting a capacitor. Typically, pMOS field effect transistors 125 and 126 handle large currents, so the parasitic capacitance at the gate is large. For example, a parasitic capacitance of about 0.1 μF (microfarad) occurs.

[0230] Therefore, this parasitic capacitance and the resistance value of resistor 401 form a CR time constant. If the parasitic capacitance of pMOS field effect transistor 125 and pMOS field effect transistor 126 is 0.1 μF (microfarad) and the resistance value of resistor 401 is 100 kΩ (kiloohms), the time constant of the speed at which the output changes from L (low) to H (high) in Figure 5(a) is about 10 ms (milliseconds). On the other hand, since the on-resistance of nMOS field effect transistor 402 is much smaller than 100 kΩ (kiloohms), the time constant of the speed at which the output changes from H (high) to L (low) in Figure 5(a) is much smaller than 10 ms (milliseconds).

[0231] In this way, the speed at which the pMOS field effect transistor 125 changes from on to off can be made much slower than the speed at which the pMOS field effect transistor 125 changes from off to on, with a difference of at least two to three orders of magnitude or more between the two.

[0232] The pMOS field effect transistor 125, the pMOS field effect transistor 127, the pMOS field effect transistor 145, and the pMOS field effect transistor 147 can change from on to off much slower than the speed at which they change from off to on.

[0233] The nMOS inverter 129 and the nMOS inverter 130 have the following two roles. Inverting amplification L (low) to H (high) delay function

[0234] The nMOS inverter 149 and the nMOS inverter 150 have the following three roles. Inverting amplification Level Shifting L (low) to H (high) delay function

[0235] By doing so, it is possible to create a difference between the time at which the switching element to be controlled changes between on and off after the voltage between terminals 201 and 202 changes from a small voltage to a large voltage in a short time, and the time at which the switching element to be controlled changes between on and off after the voltage between terminals 201 and 202 changes from a large voltage to a small voltage in a short time, and it is possible to ensure a dynamic margin.

[0236] Stable operation was confirmed when the resistance value of resistor 401 was 100 kΩ. A higher resistance value reduces wasted power and allows for a larger difference in the time it takes to change from on to off and from off to on. However, when the resistance value of resistor 401 was increased to approximately 1 MΩ, the power from the solar cell was cut off too late, resulting in the PC power supply determining that there was no need to supply power even when output from the PC power supply was needed, and the PC power supply did not supply power. In this case, the power supply from the solar cell would stop after a long period of time, resulting in no power being supplied from either the solar cell or the PC power supply, causing the PC to shut down. Therefore, the resistance value of resistor 401 should not be too high. Accurate optimization of the resistance value of resistor 401 is considered a design issue.

[0237] By ensuring static and dynamic margins, it is possible to operate a computer (PC) stably, regardless of the power generation status of the solar cells or the power consumption of the computer's (PC's) power demand section. In the inventor's experiments, this system was introduced and no unintended shutdowns, restarts, or blue screen errors occurred for two months.

[0238] Finally, we will explain the connection of capacitors to various locations. The connection of capacitors can also be considered as part of ensuring dynamic margins. Normally, capacitors are attached to the input and output of a DC-DC converter because the converter will not function properly without them. The capacitors used for this purpose are 121, 141, 123, and 143. In addition to these minimum capacitors, there are also large-capacity capacitors 101 to stabilize the input of cooperative power supply; capacitors 131 to stabilize the VDD power supplied to nMOS inverter 108, pMOS inverter 109, pMOS inverter 110, nMOS inverter 129, and nMOS inverter 130; capacitors 151 to stabilize the VDD power supplied to nMOS inverter 149 and nMOS inverter 150; capacitors 133 and 153 to ensure stable operation when power from the computer (PC) power supply is suddenly required; and capacitors 132 and 152 to be used when power generated by cooperative power supply is suddenly required by the power demand section.

[0239] A large-capacity capacitor 101 of, for example, 10,000 μF (microfarads) is suitable for stabilizing the input of cooperative power supply. If a capacitance of this magnitude is connected, even if the wiring from the solar cell 11 is interrupted for some reason, the computer (PC) will continue to operate by switching to power supply from the computer (PC) power supply alone. While the computer (PC) may be able to operate without such a large-capacity capacitor, if the voltage between terminals 201 and 202 suddenly changes, cooperative power supply may not work even when dynamic margins are taken into account, and the computer (PC) may shut down. For this reason, a large-capacity capacitor 101 is necessary for cooperative power supply.

[0240] Additionally, it is preferable to place capacitors 121 and 141 close to the DC-DC converter input. Capacitors 121 and 141 have a smaller capacity than capacitor 101, and are preferably a combination of an electrolytic capacitor and a ceramic capacitor. Capacitors 123 and 143 are also preferably a combination of an electrolytic capacitor and a ceramic capacitor.

[0241] It is also preferable to provide a capacitor 131 for stabilizing the VDD power supply supplied to the nMOS inverter 108, the pMOS inverter 109, the pMOS inverter 110, the nMOS inverter 129, and the nMOS inverter 130, and a capacitor 151 for stabilizing the VDD power supply supplied to the nMOS inverter 149 and the nMOS inverter 150.

[0242] Capacitors 133 and 153 should also be provided to ensure stable operation when power from the computer (PC) power supply is suddenly required, and capacitors 132 and 152 should also be provided when power generated by coordinated power supply is suddenly required by the power demand section.

[0243] However, it is possible that the device will operate without capacitors 131, 151, 132, 152, 133, and 153, and they are provided to further enhance stability and reliability. Accurately determining the capacitance of each capacitor is considered a design issue. However, we believe that ensuring that capacitor 101 has a sufficiently large capacitance may constitute part of the patentability of the device.

[0244] As described above, ensuring a static margin and a dynamic margin ensures stable operation. Connecting capacitors to each point makes operation even more stable.

[0245] Next, I will discuss power interlocking with the computer (PC). What would happen if power continued to be supplied to terminals 206 and 210 even when the computer (PC) was turned off? In that case, the power supply fan would continue to run even when the computer (PC) was turned off. This is likely to be of concern to many people. Not only that, but if power continues to be supplied to terminals 206 and 210 even when the computer (PC) is turned off, the computer (PC) may not turn on when you try to turn it on later. However, this may differ depending on the computer (PC). Therefore, when the computer (PC) is turned off, power should not be supplied to terminals 206 and 210.

[0246] To achieve this, when the inventor receives a signal to turn off the power supply to the computer (PC), he drops the node between resistors 105 and 106 to 0 V, turns off pMOS field effect transistor 125 and pMOS field effect transistor 145, and prevents power from being supplied from solar cell 11 to the power demanding parts of the computer (PC), namely CPU 15, motherboard 16, storage 17, and GPU 18. When the power supply to the computer (PC) is turned off, H (high) is supplied to terminal 203, and this signal can be used.

[0247] When H (High) is supplied to terminal 203, after a certain time has passed, nMOS field effect transistor 104 turns on. Therefore, regardless of the voltage between terminal 201 and terminal 202, the node between resistors 105 and 106 and the node between resistors 106 and 107 become approximately the same as GND, i.e., a voltage close to 0 V. As a result, the signal is inverted and amplified three times in total by nMOS inverter 108, pMOS inverter 109, and nMOS inverter 129, and H (High) is input to pMOS field effect transistor 125 and pMOS field effect transistor 126, which then turn off. The signal is inverted and amplified a total of three times by the nMOS inverter 108, the pMOS inverter 109, and the nMOS inverter 149, and H (high) is input to the pMOS field effect transistor 145 and the pMOS field effect transistor 146, which are then turned off.

[0248] Based on the same idea, the pMOS field effect transistor 127 and the pMOS field effect transistor 147 are turned on. However, if the power supply to the computer (PC) is off, no power is supplied from the computer (PC) power supply 13. Since no power is supplied from the solar cell 11, no power is supplied to the power demanding parts of the computer (PC), such as the CPU 15, motherboard 16, storage 17, and GPU 18.

[0249] On the other hand, when L (low) is supplied to terminal 203, power is supplied from the computer (PC) power supply 13, coordinated power supply from the solar cell 11 and the computer (PC) power supply 13, and power is supplied from the solar cell 11, depending on the voltage between terminals 201 and 202, and power is supplied to the power demanding parts, that is, CPU 15, motherboard 16, storage 17, and GPU 18.

[0250] Next, delay circuit 102-1 will be described. Delay circuit 102-1 includes resistor 102 and capacitor 103, and operates with a CR time constant. For example, if resistor 102 has a resistance of 100 kΩ (kiloohms) and capacitor 103 has a capacitance of 47 μF (microfarads), the CR time constant is 4.7 seconds. When the computer (PC) is turned off and the potential at terminal 203 goes high (H), the voltage across resistors 105 and 106 becomes 0 V after 3 to 5 seconds, which is the same order of time as the CR time constant. When the computer (PC) is turned on and the potential at terminal 203 goes low (L), the voltage across resistors 105 and 106 becomes the potential resulting from the voltage divided between terminals 201 and 202 after 3 to 5 seconds, which is the same order of time as the CR time constant.

[0251] Let us consider the effect of using a delay circuit in this way. When a signal to turn off the computer (PC) is received, the power from the computer (PC) power supply 13 should be turned off. However, what would happen if the power from the solar cell 11 was cut off before the power from the computer (PC) power supply 13 was turned off? In this case, the power required by the computer (PC) power supply 13 would suddenly increase, and from the computer (PC) power supply 13's perspective, this would suddenly be a large amount of power being required, so it might decide that it is not appropriate to turn off the power.

[0252] When a signal to turn on the computer (PC) is received, the power from the computer (PC) power supply 13 should be turned on. However, what happens if power is suddenly supplied from the solar cell 11 before the power from the computer (PC) power supply 13 is turned on? In this case, the power required by the computer (PC) power supply 13 suddenly decreases, and from the computer (PC) power supply 13's perspective, power is suddenly no longer needed, so it may decide that there is no need to supply power and stop supplying power. There are cases where the power from the solar cell 11 is sufficient to cover all of the power for the 12V system and the normal 5V system, but even in that case, the computer (PC) power supply 13 needs to be prepared to supply power at any time in case of a sudden increase in power demand.

[0253] In view of this, it is advisable to use a delay circuit to switch whether or not to supply power from the solar cell 11 to the power demand unit after a certain time period has elapsed when a signal to turn the computer (PC) power on or off is received.

[0254] Figure 8 shows the relationship between the voltage across the solar cell and the current and power that can be extracted. Figure 8 shows an example for a 12V system.

[0255] When the voltage across the solar cell is 0V, the maximum current flows. This current is called the short-circuit current. The current that flows remains almost constant until the voltage across the solar cell reaches approximately 17V, at which point the voltage across the solar cell decreases from around 17V, and once the voltage across the solar cell increases further, the current that flows becomes zero. The voltage at which the current that flows becomes zero is called the release voltage.

[0256] When the voltage across the solar cell is 0V, the power that can be extracted is zero. When the voltage across the solar cell is, for example, around 17.5V, the power that can be extracted is maximized, and the power that can be extracted at the open circuit voltage is zero. Taking wiring resistance into account, if power is extracted around 17V, which is slightly lower than 17.5V, which is the voltage at which the maximum power can be extracted when only the solar cell is considered, the maximum power can be extracted in an actual system with wiring resistance. In the circuit of Figure 6, if the resistance values ​​of resistors 105, 106, and 107 are adjusted so that pMOS field-effect transistors 125 and 127 switch when the output voltage of solar cell 511 is around 17V, a large amount of power can be extracted.

[0257] At night, the solar cell 11 does not generate power, and its output is zero. At this time, the input to the inverter 108 becomes low (L), the output of the inverter 108 becomes high (H), the output of the inverter 109 becomes low (L), and the output of the inverter 129 becomes high (H). As a result, the pMOS field-effect transistor 126 turns off and the pMOS field-effect transistor 127 turns on. If the switching element is configured with two pMOS field-effect transistors connected in series with their sources facing in opposite directions, when the pMOS field-effect transistor 126 is off, no current flows from right to left through the pMOS field-effect transistor 126 in Figure 2. Therefore, if the solar cell 11 is configured with a single solar cell, a reverse-current prevention diode is not necessary. The presence of a reverse-current prevention diode reduces the forward voltage by approximately 0.4 V to 1.0 V. Therefore, the absence of a reverse-current prevention diode contributes to improving the power efficiency of the system.

[0258] Unlike a normal independent power supply system, a system like the one shown in Figure 2 can operate without a 12V lead-acid battery. Therefore, there is no need for the depreciation costs of a lead-acid battery. This makes it possible to keep maintenance costs low. The part in Figure 2 can be used in combination with a PC (computer) power supply, or it can be integrated into the PC (computer) power supply. When used in combination with a PC (computer) power supply, the PC (computer) power supply can be an ATX power supply that is common as of 2025.

[0259] So, we conducted an experiment to see how much effective efficiency this system could achieve. For the experiment, we used a computer (PC) equipped with an Intel Core i5-13500 CPU and no dedicated graphics card. The experiment involved running the Uncharted Waters Online Benchmark, a benchmark test program for the Koei Tecmo game, Uncharted Waters Online, for 168 hours at a time. The first run was without simulated solar power, and the second run was with simulated solar power of up to 19V and 2A. We calculated the difference between the two and measured the cumulative power supplied. The power consumed by the computer (PC) on a 12V (normally 5V) power supply was set to be significantly greater than the power supplied by the simulated solar power source.

[0260] As a result, the power consumption was 98.15W when no power was supplied, and 65.24W when power was supplied. The difference was 32.91W. The cumulative power supplied was 31.96W. As a result, 32.91W / 31.96W=103%. The effective efficiency, defined as the power saved from commercial power / power supplied from simulated sunlight, was 103%.

[0261] This effective efficiency of 103% does not mean that the conversion efficiency of the DC-DC converter is 103%, because this definition of effective efficiency is not the definition of the conversion efficiency of the DC-DC converter itself. However, since this effective efficiency is the power that can be saved from the commercial power supply / power supplied from simulated sunlight, it is possible for this effective efficiency to exceed 100%. This result means that it is possible to save more power from the commercial power supply than is supplied by the solar panel.

[0262] The essential reason why this is possible is that while power from a commercial power source is converted once by AC-DC conversion, power from solar cells is also converted once by a DC-DC converter. Therefore, if the efficiency of DC-DC conversion from solar cells is higher than the efficiency of AC-DC conversion from commercial power, the effective efficiency, defined as the power saved from commercial power divided by the power supplied from simulated sunlight, can exceed 100%. In reality, the main circuit 12 itself consumes power, and the efficiency is, for example, about 2% lower than the difference between the efficiency of AC-DC conversion from commercial power and the efficiency of DC-DC conversion from solar cells. However, if the efficiency of DC-DC conversion from solar cells is sufficiently higher than the efficiency of AC-DC conversion from commercial power, it can still exceed 100%.

[0263] To give a clearer understanding, let's use a specific example. Assume the AC-DC conversion efficiency of the commercial power supply is 88%, the DC-DC conversion efficiency is 92%, 30W is supplied from the solar cell, and the main circuit 12 itself does not consume any power. In this case, let's assume that the amount of power saved by the solar cell out of the power supplied from the commercial power supply to the 12V and normal 5V is X. Then, the amount of power saved by the solar cell out of the power supplied to the 12V and normal 5V power demand sections is X × 0.88. On the other hand, the amount of power supplied from the solar cell to the 12V and normal 5V power demand sections is 30(W) × 0.92. Since both sources are the same, X × 0.88 = 30(W) × 0.92. X = 30(W) × 0.92 / 0.88, so X exceeds 30(W). X / 30(W) = 0.92 / 0.88.

[0264] This experiment is costly and cannot be repeated. Therefore, the first experiment was conducted without supplying simulated sunlight, and the second experiment was conducted with a maximum simulated sunlight voltage of 19V and 2A. Ideally, a computer (PC) should consume a constant amount of power. However, even when running the same benchmark program, power consumption can fluctuate slightly, resulting in errors. Therefore, the effective efficiency, defined as the power saved from commercial power / power supplied by simulated sunlight, may not be 103% or may even be less than 100%. However, in principle, it could exceed 100%. Thus, the effective efficiency, defined as the power saved from commercial power / power supplied by simulated sunlight, can exceed 100%.

[0265] From here, we will explain the related technologies. Figure 3 shows an example of the inside of a DC-DC converter. There are insulated and non-insulated DC-DC converters. Non-insulated DC-DC converters are available in step-up and step-down types. A non-insulated step-down type is suitable for converting a voltage of around 17V from a solar cell to 12V or 5V. The example shown in Figure 3 is a non-insulated step-down DC-DC converter.

[0266] The principle will be briefly explained. When the switching element is turned on by the output L (low) of the controller 202, current flows from the input to the output via the switching element 201 and the inductor 204. When the switching element 201 is turned off by the output H (high) of the controller 202, current flows from VSS to the output via the diode 203 and the inductor 204.

[0267] Since there is a current that flows from VSS via diode 203 and inductor 204, in the case of a step-down type, the current is larger at the output than at the input, but the voltage is smaller at the output than at the input.

[0268] Since controller 202 turns switching element 201 on and off at several hundred kHz (kilohertz), inductor 204 can be small, and capacitors 123 and 143 connected to the output do not need to have very large capacitances, allowing the DC-DC converter to be made compact.

[0269] Capacitors 123 and 143 are connected to the output side, and capacitors 121 and 141 are also connected to the input side. Normally, both an electrolytic capacitor and a ceramic capacitor are required on the input side, and an electrolytic capacitor is required on the output side. Note that the ceramic capacitor may be integrated with the DC-DC converter.

[0270] The output voltage is divided by resistors 205 and 206 and the divided voltage is input to the controller and fed back. Usually, the output voltage can be set by adjusting the resistance value of one or both of resistors 205 and 206. The resistance value of one or both of resistors 205 and 206 is designed to match the specifications of the DC-DC converter.

[0271] DC-DC converter 122 outputs 12 V, and DC-DC converter 142 outputs 5 V. Because the output voltages are different, the ratio of the resistance values ​​of resistors 205 and 206 in DC-DC converter 122 is set to be different from the ratio of the resistance values ​​of resistors 205 and 206 in DC-DC converter 142.

[0272] 4 is an example of a circuit diagram inside a power supply for a computer (PC). The input of the power supply for a computer (PC) is rectified by a full-wave rectifier consisting of diodes 301, 302, 303, 304 and capacitor 305.

[0273] The voltage is then stepped down by transformer 307, switching element 312, controller 308, diode 306, and capacitor 309. Switching element 312 is turned on and off by a signal controlled by controller 308, changing the current on the primary side. The current that appears on the secondary side is rectified by diode 306, and only forward current of diode 306 appears. This is then smoothed by capacitor 309. In this way, a lower voltage appears on the secondary side than on the primary side. Normally, a larger current is generated on the secondary side than on the primary side. As a result, 12 V appears between terminals 207 and 206.

[0274] DC-DC converter 310 generates 5V between terminal 207 and terminal 210. DC-DC converter 311 generates 3.3V. In this example, 5V and 3.3V are generated from 12V. However, 5V and 3.3V may also be generated directly from the primary side.

[0275] Figure 5 is a circuit diagram of an inverter. Figure 5(a) is a circuit diagram of an nMOS inverter circuit. The output is inverted with respect to the input. In other words, if the input is H (high), the output becomes L (low), and if the input is L (low), the output becomes H (high). The output changes quickly from H (high) to L (low), but it changes slowly from L (low) to H (high). When the output changes from L (low) to H (high), the product of the capacitance connected to the output and the resistance value of resistor 401 becomes the CR time constant.

[0276] Figure 5(b) is a circuit diagram of a pMOS inverter circuit. The output is inverted relative to the input. In other words, if the input is H (high), the output becomes L (low), and if the input is L (low), the output becomes H (high). The output changes slowly from H (high) to L (low), but quickly from L (low) to H (high). When the output changes from H (high) to L (low), the product of the capacitance connected to the output and the resistance value of resistor 404 becomes the CR time constant.

[0277] Each elemental technology will be further explained. Figure 6 is a simple example of cooperative power supply. Cooperative power supply was explained in Figure 2, but Figure 6 explains an even simpler example of cooperative power supply. Figure 6 shows an example in which power from a solar cell is converted to 5V and used for USB charging. The reason for giving this example is that there are experimental results that have actually obtained the characteristics of cooperative power supply. Figure 9 shows the same circuit as Figure 2, but in a more simplified form. Figure 2 accurately describes the details, but the details make it difficult to see the essence. Figure 9 was included with the aim of aiding understanding rather than providing a detailed description.

[0278] Figure 6 shows a simple example of cooperative power supply. Power from solar cell 511 is converted to 5V by DC-DC converter 503. Commercial AC power 509 is converted to 5V by AC adapter 508. The 5V originating from solar cell 511 and the 5V originating from the commercial AC power are mixed via switching element 504 and switching element 505, and output to smartphone 510 to be charged.

[0279] The output voltage of solar cell 511 is resistively divided by resistors 501 and 502, inverted and amplified by inverter 506, and controls switching element 504. The output voltage is also input to inverter 507, where it is further inverted and amplified, and controls switching element 505.

[0280] When the output voltage of solar cell 511 increases, the input to inverter 506 increases, the output of inverter 506 decreases, and the output of inverter 507 increases. As a result, switching element 504 turns on and switching element 505 turns off. As a result, the power required by smartphone 510 to be charged is supplied more from the power originating from solar cell 511 and less from the power originating from commercial AC power 509. As a result, the output voltage of solar cell 511 decreases.

[0281] When the output voltage of solar cell 511 decreases, the input to inverter 506 decreases, the output of inverter 506 increases, and the output of inverter 507 decreases. As a result, switching element 504 turns off and switching element 505 turns on. As a result, the power required by smartphone 510 to be charged is supplied less from the power originating from solar cell 511 and more from the power originating from commercial AC power 509. As a result, the output voltage of solar cell 511 increases.

[0282] This feedback allows the smartphone 510 to be charged to be supplied with an appropriate power distribution from power originating from the solar cell 511 and power originating from the commercial AC power 509. When the power originating from the solar cell 511 increases, the power originating from the commercial AC power 509 decreases, and when the power originating from the solar cell 511 decreases, the power originating from the commercial AC power 509 increases.

[0283] Coordinated power supply is -A technology that combines power from solar cells and commercial AC power. -It is based on feedback control, - Prioritize the use of power from solar cells, and use commercial AC power only if there is a shortage. It can be said that.

[0284] FIG. 7 shows the relationship between the current generated by solar cell 511, the simulated solar output current, and the AC adapter output current. The simulated solar output current is the current flowing through switching element 504, and the AC adapter output current is the current flowing through switching element 505. It should be noted that the current generated by solar cell 511 is the current in a 12V system, and the simulated solar output current and the AC adapter output current are the current in a 5V system. In this way, as the current generated by solar cell 511 increases, the simulated solar output current increases and the AC adapter output current decreases. As the current generated by solar cell 511 decreases, the simulated solar output current decreases and the AC adapter output current increases.

[0285] Figure 8 shows the relationship between the voltage across the solar cell and the current and power that can be extracted. Figure 8 shows an example for a 12V system.

[0286] When the voltage across the solar cell is 0V, the maximum current flows. This current is called the short-circuit current. The current that flows remains almost constant until the voltage across the solar cell reaches approximately 17V, at which point the voltage across the solar cell decreases from around 17V, and once the voltage across the solar cell increases further, the current that flows becomes zero. The voltage at which the current that flows becomes zero is called the release voltage.

[0287] When the voltage across the solar cell is 0V, the power that can be extracted is zero. When the voltage across the solar cell is, for example, around 17.5V, the power that can be extracted is maximized, and at the open voltage, the power that can be extracted is zero. Taking wiring resistance into consideration, the maximum power can be extracted by extracting power around 17V, which is slightly lower than 17.5V, which is the maximum power that can be extracted when only the solar cell is considered. In the circuit of Figure 6, if the resistance values ​​of resistors 501 and 502 are adjusted so that switching elements 504 and 505 switch on and off when the output voltage of solar cell 511 is around 17V, a large amount of power can be extracted.

[0288] At night, the solar cell 511 does not generate power, and its output is zero. At that time, the input to the inverter 506 becomes L (low), the output of the inverter 506 becomes H (high), and the output of the inverter 507 becomes L (low). As a result, the switching sled 504 turns off and the switching element 505 turns on. If the switching element is configured with two pMOS field-effect transistors connected in series with their sources facing in opposite directions, when the switching sled 504 is off, no current flows from right to left through the switching element 504 in Figure 6. Therefore, if the solar cell 511 is configured with a single solar cell, a reverse current prevention diode is not necessary. The presence of a reverse current prevention diode would reduce the forward voltage by approximately 0.4 V to 1.0 V. Therefore, the absence of a reverse current prevention diode contributes to improving the power efficiency of the system.

[0289] Unlike a normal independent power supply system, the system shown in Figure 6 can operate without a 12V lead-acid battery. Therefore, there is no need for the depreciation costs of a lead-acid battery. This allows for low maintenance costs.

[0290] Figure 9 shows the same circuit as Figure 2 in a simplified form. Power from solar cell 11 is converted to 12V by DC-DC converter 122. Commercial AC power 14 is converted to 12V by computer (PC) power supply 13. The 12V originating from solar cell 11 and the 12V originating from commercial AC power are mixed via switching element 125-1 and switching element 127, and output to the power demand section of the computer (PC).

[0291] The output voltage of solar cell 11 is resistively divided by resistors 501 and 502, inverted and amplified in three stages by inverters 108, 109, and 129, and controls switching element 125-1. Also, the output voltage of solar cell 511 is resistively divided by resistors 501 and 502, inverted and amplified in two stages by inverters 110 and 130, and controls switching element 127.

[0292] When the output voltage of solar cell 11 increases, the input to inverter 108 increases, the output of inverter 108 decreases, the output of inverter 109 increases, and the output of inverter 129 decreases. Furthermore, when the output voltage of solar cell 11 increases, the input to inverter 110 increases, the output of inverter 110 decreases, and the output of inverter 130 increases. As a result, switching element 125-1 turns on and switching element 127 turns off. As a result, the power required by the power demand section is supplied more from the power originating from solar cell 11 and less from the power originating from commercial AC power 14. As a result, the output voltage of solar cell 11 decreases.

[0293] When the output voltage of solar cell 11 decreases, the input to inverter 108 decreases, the output of inverter 108 increases, the output of inverter 109 decreases, and the output of inverter 129 increases. Furthermore, when the output voltage of solar cell 11 decreases, the input to inverter 110 decreases, the output of inverter 110 increases, and the output of inverter 130 decreases. As a result, switching element 125-1 turns off and switching element 127 turns on. As a result, the power required by the power demand section is supplied less from the power originating from solar cell 11 and more from the power originating from commercial AC power 14. As a result, the output voltage of solar cell 11 increases.

[0294] This feedback allows the power demand section to be supplied with an appropriate power distribution from the power originating from solar cell 11 and the power originating from commercial AC power 14. When the power originating from solar cell 11 increases, the power originating from commercial AC power 14 decreases, and when the power originating from solar cell 11 decreases, the power originating from commercial AC power 14 increases.

[0295] This is similar to the case of Figure 6 in that a large amount of power can be extracted from the solar cell by setting the switching elements 125-1 and 127 to turn on and off at a voltage slightly lower than the voltage at which the maximum power can be extracted from the solar cell itself, and that a reverse current prevention diode is not required when there is only one solar cell due to the characteristics of the control circuit. Figures 6 and 9 are drawings for the purpose of understanding, so Figure 2 should be primarily used for interpreting the claims.

[0296] Figures 10 (Circuit A), 11 (Circuit I), 12 (Circuit U), 13 (Circuit E), 14 (Circuit O), and 15 (Circuit K) show the results of simulations conducted with various circuit configurations and examining static and dynamic margins. As already mentioned, ensuring sufficient static and dynamic margins is important for stable computer operation. (a) shows the circuit diagram used in the simulation, (b) the static characteristics of the 12V system, (c) the static characteristics of the 5V system, (d) the dynamic characteristics of the 12V system, and (e) the dynamic characteristics of the 5V system. Note that the explanation will be given using the corresponding components in Figure 2.

[0297] Figures 10 (Circuit A), 11 (Circuit I), and 12 (Circuit U) show cases where the amplification stages are separate in the amplification series that control switching elements 125, 126, and 127, while Figures 13 (Circuit E), 14 (Circuit O), and 15 (Circuit K) show cases where the amplification stages are shared by the amplification series of two switching elements. Figures 10 (Circuit A) and 13 (Circuit E) show cases where the final stage of each amplification series is an nMOS inverter, Figures 11 (Circuit I) and 14 (Circuit O) show cases where the final stage of each amplification series is a CMOS inverter, and Figures 12 (Circuit U) and 15 (Circuit K) show cases where the final stage of each amplification series is a pMOS inverter. Figure 10 (Circuit A) is the configuration adopted in Figure 2.

[0298] First, let's look at the static margin. In (b) and (c) of Figures 10, 11, 12, 13, 14, and 15, the vertical axis represents the source-gate voltage of the pMOS field-effect transistor 125 and the source-gate voltage of the pMOS field-effect transistor 127. Therefore, in (b) and (c) of Figures 10, 11, 12, 13, 14, and 15, when the voltage is high, the pMOS field-effect transistor 125 and the pMOS field-effect transistor 127 turn on. A large static margin means that the input voltage range (output voltage of the solar cell 511) at which both the pMOS field-effect transistor 125 and the pMOS field-effect transistor 127 turn on is large. A sufficient static margin means that the input voltage range (output voltage of the solar cell 511) at which both the pMOS field-effect transistor 125 and the pMOS field-effect transistor 127 turn on is sufficient.

[0299] The condition for the pMOS field effect transistor 125 and the pMOS field effect transistor 127 to be turned on is that the source-gate voltage is equal to or higher than the threshold, for example, 3V or higher.

[0300] 10(b) and 10(c), when the input voltage, i.e., the voltage between terminals 201 and 202 in FIG. 2, is small and falls below a first constant voltage value, the 12V control PV side, i.e., pMOS field-effect transistor 125, is turned off, and the 12V control computer (PC) power supply side, i.e., pMOS field-effect transistor 127, is turned on. When the input voltage, i.e., the voltage between terminals 201 and 202 in FIG. 2, rises and is between the first constant voltage value and a second constant voltage value, the 12V control PV side, i.e., pMOS field-effect transistor 125, is turned on, and the 12V control computer (PC) power supply side, i.e., pMOS field-effect transistor 127, is turned on. When the input voltage, i.e., the voltage between terminals 201 and 202 in FIG. 2, further rises and exceeds a second constant voltage value, the 12V control PV side, i.e., pMOS field-effect transistor 125, is turned on, and the 12V control computer (PC) power supply side, i.e., pMOS field-effect transistor 127, is turned off. In the case of FIG. 10, a static margin is secured.

[0301] 11(b) and 11(c), when the input voltage, i.e., the voltage between terminals 201 and 202 in FIG. 2, is small and falls below a first constant voltage value, the 12V control PV side, i.e., pMOS field-effect transistor 125, is turned off, and the 12V control computer (PC) power supply side, i.e., pMOS field-effect transistor 127, is turned on. When the input voltage, i.e., the voltage between terminals 201 and 202 in FIG. 2, rises and is between the first constant voltage value and a second constant voltage value, the 12V control PV side, i.e., pMOS field-effect transistor 125, is turned on, and the 12V control computer (PC) power supply side, i.e., pMOS field-effect transistor 127, is turned on. When the input voltage, i.e., the voltage between terminals 201 and 202 in FIG. 2, further rises and exceeds a second constant voltage value, the 12V control PV side, i.e., pMOS field-effect transistor 125, is turned on, and the 12V control computer (PC) power supply side, i.e., pMOS field-effect transistor 127, is turned off. In the case of Figure 11, the line on the 12V control computer (PC) power supply side changes gradually, but a certain degree of static margin is secured.

[0302] 12(b) and 12(c), when the input voltage, i.e., the voltage between terminals 201 and 202 in FIG. 2, is small and falls below a first constant voltage value, the 12V control PV side, i.e., pMOS field-effect transistor 125, is turned off, and the 12V control computer (PC) power supply side, i.e., pMOS field-effect transistor 127, is turned on. When the input voltage, i.e., the voltage between terminals 201 and 202 in FIG. 2, rises and is between the first constant voltage value and a second constant voltage value, the 12V control PV side, i.e., pMOS field-effect transistor 125, is turned on, and the 12V control computer (PC) power supply side, i.e., pMOS field-effect transistor 127, is turned on. When the input voltage, i.e., the voltage between terminals 201 and 202 in FIG. 2, further rises and exceeds a second constant voltage value, the 12V control PV side, i.e., pMOS field-effect transistor 125, is turned on, and the 12V control computer (PC) power supply side, i.e., pMOS field-effect transistor 127, is turned off. In the case of FIG. 12, a static margin is secured.

[0303] 13(b) and 13(c) show that when the input voltage, i.e., the voltage between terminals 201 and 202 in FIG. 2, is small, the 12V control PV side, i.e., pMOS field effect transistor 125, is off, and the 12V control computer (PC) power supply side, i.e., pMOS field effect transistor 127, is on. When the input voltage, i.e., the voltage between terminals 201 and 202 in FIG. 2, rises, the 12V control PV side, i.e., pMOS field effect transistor 125, is on, and the 12V control computer (PC) power supply side, i.e., pMOS field effect transistor 127, is off. In the case of FIG. 13, a sufficient static margin is not ensured.

[0304] 14(b) and 14(c) show that when the input voltage, i.e., the voltage between terminals 201 and 202 in FIG. 2, is small, the 12V control PV side, i.e., pMOS field effect transistor 125, is off, and the 12V control computer (PC) power supply side, i.e., pMOS field effect transistor 127, is on. When the input voltage, i.e., the voltage between terminals 201 and 202 in FIG. 2, rises, the 12V control PV side, i.e., pMOS field effect transistor 125, is on, and the 12V control computer (PC) power supply side, i.e., pMOS field effect transistor 127, is off. In the case of FIG. 14, a sufficient static margin is not ensured.

[0305] 15(b) and 15(c) show that when the input voltage, i.e., the voltage between terminals 201 and 202 in FIG. 2, is small, the 12V control PV side, i.e., pMOS field effect transistor 125, is off, and the 12V control computer (PC) power supply side, i.e., pMOS field effect transistor 127, is on. When the input voltage, i.e., the voltage between terminals 201 and 202 in FIG. 2, rises, the 12V control PV side, i.e., pMOS field effect transistor 125, is on, and the 12V control computer (PC) power supply side, i.e., pMOS field effect transistor 127, is off. In the case of FIG. 15, a sufficient static margin is not ensured.

[0306] What can be said from Figure 10 (Circuit A), Figure 11 (Circuit I), Figure 12 (Circuit C), Figure 13 (Circuit E), Figure 14 (Circuit O), and Figure 15 (Circuit K) is that static margin can be secured by having the first and second stages of amplification separately and independently and adjusting the resistance values. In other words, from the perspective of securing static margin, the first and second stages of amplification should be secured separately and independently, as in Figure 10 (Circuit A), Figure 11 (Circuit I), and Figure 12 (Circuit C).

[0307] Next, let's look at the dynamic margin. In (d) and (e) of Figures 10, 11, 12, 13, 14, and 15, the vertical axis represents the source-gate voltage of the pMOS field-effect transistor 125 and the source-gate voltage of the pMOS field-effect transistor 127. Therefore, in (d) and (e) of Figures 10, 11, 12, 13, 14, 15, and 16, when the voltage is high, the pMOS field-effect transistor 125 and the pMOS field-effect transistor 127 turn on. A large dynamic margin means that both the pMOS field-effect transistor 125 and the pMOS field-effect transistor 127 are on for a long time. A sufficient dynamic margin means that both the pMOS field-effect transistor 125 and the pMOS field-effect transistor 127 are on for a sufficient time.

[0308] In (d) and (e) of Figures 10, 11, 12, 13, 14, and 15, the simulation is performed under the assumption that the input voltage (output voltage of solar cell 11) is 0V from time 0 (seconds) to 0.05 (seconds), the input voltage (output voltage of solar cell 11) is 19V from time 0.05 (seconds) to 0.10 (seconds), the input voltage (output voltage of solar cell 11) is 0V from time 0.10 (seconds) to 0.15 (seconds), and the input voltage (output voltage of solar cell 11) is 19V from time 0.15 (seconds) to 0.20 (seconds).

[0309] In the steady state, from time 0 (seconds) to 0.05 (seconds), the 12V control PV side, i.e., the pMOS field effect transistor 125, is off and the 12V control computer (PC) power supply side, i.e., the pMOS field effect transistor 127, is on. From time 0.05 (seconds) to 0.10 (seconds), the 12V control PV side, i.e., the pMOS field effect transistor 125, is on and the 12V control computer (PC) power supply side, i.e., the pMOS field effect transistor 127, is off. From time 0.10 (seconds) to 0.15 (seconds), the 12V control PV side, i.e., the pMOS field effect transistor 125, is off and the 12V control computer (PC) power supply side, i.e., the pMOS field effect transistor 127, is on; from time 0.15 (seconds) to 0.20 (seconds), the 12V control PV side, i.e., the pMOS field effect transistor 125, is on and the 12V control computer (PC) power supply side, i.e., the pMOS field effect transistor 127, is off.

[0310] The differences between (d) and (e) in Figures 10, 11, 12, 13, 14, and 15 appear in the transient state.

[0311] 10(d) and 10(e), immediately after the input voltage (output voltage of solar cell 11) changes from 0 V to 19 V, the 12V control PV side, i.e., pMOS field-effect transistor 125, is on and the 12V control computer (PC) power supply side, i.e., pMOS field-effect transistor 127, is on; the 12V control PV side, i.e., pMOS field-effect transistor 125, is on and the 12V control computer (PC) power supply side, i.e., pMOS field-effect transistor 127, is off. Immediately after the input voltage (output voltage of solar cell 11) changes from 19 V to 0 V, the 12V control PV side, i.e., pMOS field-effect transistor 125, is on and the 12V control computer (PC) power supply side, i.e., pMOS field-effect transistor 127, is on; the 12V control PV side, i.e., pMOS field-effect transistor 125, is off and the 12V control computer (PC) power supply side, i.e., pMOS field-effect transistor 127, is on. In a transient state, there are times when both pMOS field-effect transistors are on. When the voltage between the source and gate of the two pMOS field-effect transistors is on at about 3V or higher, as shown in Figure 10(d)(e), there is a time period of about 0.01 seconds (10 milliseconds) or more during which both pMOS field-effect transistors are on. Therefore, it is believed that a sufficient dynamic margin is secured.

[0312] 11(d) and 11(e), immediately after the input voltage (output voltage of solar cell 11) changes from 0 V to 19 V, the 12V control PV side, i.e., pMOS field effect transistor 125, is on, and the 12V control computer (PC) power supply side, i.e., pMOS field effect transistor 127, is not on; instead, the 12V control PV side, i.e., pMOS field effect transistor 125, is on, and the 12V control computer (PC) power supply side, i.e., pMOS field effect transistor 127, is off. Immediately after the input voltage (output voltage of solar cell 11) changes from 19 V to 0 V, the 12V control PV side, i.e., pMOS field effect transistor 125, is on, and the 12V control computer (PC) power supply side, i.e., pMOS field effect transistor 127, is not on; instead, the 12V control PV side, i.e., pMOS field effect transistor 125, is off, and the 12V control computer (PC) power supply side, i.e., pMOS field effect transistor 127, is on. In a transient state, there is almost no time when both pMOS field-effect transistors are on. Therefore, it is believed that the dynamic margin is not sufficiently secured.

[0313] 12(d) and 12(e), immediately after the input voltage (output voltage of solar cell 11) changes from 0 V to 19 V, there is a state in which the 12V control PV side, i.e., pMOS field effect transistor 125, is off and the 12V control computer (PC) power supply side, i.e., pMOS field effect transistor 127, is off; there is a state in which the 12V control PV side, i.e., pMOS field effect transistor 125, is on and the 12V control computer (PC) power supply side, i.e., pMOS field effect transistor 127, is off. Immediately after the input voltage (output voltage of solar cell 11) changes from 19 V to 0 V, there is a state in which the 12V control PV side, i.e., pMOS field effect transistor 125, is off and the 12V control computer (PC) power supply side, i.e., pMOS field effect transistor 127, is off; there is a state in which the 12V control PV side, i.e., pMOS field effect transistor 125, is off and the 12V control computer (PC) power supply side, i.e., pMOS field effect transistor 127, is on. In a transient state, there are times when both pMOS field-effect transistors are turned off. When the voltage between the source and gate of the two pMOS field-effect transistors is turned on at approximately 3 V or higher, as shown in Figure 12(d)(e), there is a time of approximately 0.01 seconds (10 milliseconds) or more during which both pMOS field-effect transistors are turned off. Since it is out of the question for both to be turned off, it is believed that the dynamic margin is not sufficiently secured.

[0314] 13(d) and 13(e), immediately after the input voltage (output voltage of solar cell 11) changes from 0 V to 19 V, the 12V control PV side, i.e., pMOS field effect transistor 125, is on and the 12V control computer (PC) power supply side, i.e., pMOS field effect transistor 127, is on; the 12V control PV side, i.e., pMOS field effect transistor 125, is on and the 12V control computer (PC) power supply side, i.e., pMOS field effect transistor 127, is off. Immediately after the input voltage (output voltage of solar cell 511) changes from 19 V to 0 V, the 12V control PV side, i.e., pMOS field effect transistor 125, is on and the 12V control computer (PC) power supply side, i.e., pMOS field effect transistor 127, is on; the 12V control PV side, i.e., pMOS field effect transistor 125, is off and the 12V control computer (PC) power supply side, i.e., pMOS field effect transistor 127, is on. In a transient state, there are times when both pMOS field-effect transistors are on. When the voltage between the source and gate of the two pMOS field-effect transistors is on at about 3V or higher, as shown in Figure 13(d)(e), there is a time period of about 0.01 seconds (10 milliseconds) or more during which both pMOS field-effect transistors are on. Therefore, it is believed that a sufficient dynamic margin is secured.

[0315] 14(d) and 14(e), immediately after the input voltage (output voltage of solar cell 11) changes from 0 V to 19 V, the 12V control PV side, i.e., pMOS field effect transistor 125, is on, and the 12V control computer (PC) power supply side, i.e., pMOS field effect transistor 127, is not on; instead, the 12V control PV side, i.e., pMOS field effect transistor 125, is on, and the 12V control computer (PC) power supply side, i.e., pMOS field effect transistor 127, is off. Immediately after the input voltage (output voltage of solar cell 511) changes from 19 V to 0 V, the 12V control PV side, i.e., pMOS field effect transistor 125, is on, and the 12V control computer (PC) power supply side, i.e., pMOS field effect transistor 127, is not on; instead, the 12V control PV side, i.e., pMOS field effect transistor 125, is off, and the 12V control computer (PC) power supply side, i.e., pMOS field effect transistor 127, is on. In a transient state, there is almost no time when both pMOS field-effect transistors are on. Therefore, it is believed that the dynamic margin is not sufficiently secured.

[0316] 15(d) and 15(e), immediately after the input voltage (output voltage of solar cell 11) changes from 0 V to 19 V, there is a state in which the 12V control PV side, i.e., pMOS field effect transistor 125, is off and the 12V control computer (PC) power supply side, i.e., pMOS field effect transistor 127, is off; there is a state in which the 12V control PV side, i.e., pMOS field effect transistor 125, is on and the 12V control computer (PC) power supply side, i.e., pMOS field effect transistor 127, is off. Immediately after the input voltage (output voltage of solar cell 11) changes from 19 V to 0 V, there is a state in which the 12V control PV side, i.e., pMOS field effect transistor 125, is off and the 12V control computer (PC) power supply side, i.e., pMOS field effect transistor 127, is off; there is a state in which the 12V control PV side, i.e., pMOS field effect transistor 125, is off and the 12V control computer (PC) power supply side, i.e., pMOS field effect transistor 127, is on. In a transient state, there are times when both pMOS field-effect transistors are turned off. When the voltage between the source and gate of the two pMOS field-effect transistors is turned on at approximately 3 V or higher, Figure 15(d)(e) shows that there is a time of approximately 0.01 seconds (10 milliseconds) or more during which both pMOS field-effect transistors are turned off. Since it is out of the question for both to be turned off, it is believed that the dynamic margin is not sufficiently secured.

[0317] 10, 11, 12, 13, 14, and 15 show that the final stage, i.e., the inverter directly driving the pMOS field effect transistor 125 and the pMOS field effect transistor 127, can ensure a dynamic margin if it is an nMOS inverter. In the case of a CMOS inverter, it can be said that the dynamic margin cannot be ensured if it is a pMOS inverter. The final stage, i.e., the inverter directly driving the pMOS field effect transistor 125 and the pMOS field effect transistor 127, should be an nMOS inverter.

[0318] Although no comparative experiment was conducted, the reason why 108 is an nMOS inverter, 109 is a pMOS inverter, and 110 is a pMOS inverter in FIG. 2 will be explained below.

[0319] By doing so, when the pMOS field effect transistor 125 changes from off to on, the signal is transmitted at high speed by the field effect transistors in the nMOS inverter 108, pMOS inverter 109, and nMOS inverter 129, and the pMOS field effect transistor 125 quickly changes from off to on. On the other hand, when the pMOS field effect transistor 125 changes from on to off, the signal is transmitted slowly by the resistors in the nMOS inverter 108, pMOS inverter 109, and nMOS inverter 129, and the pMOS field effect transistor 125 slowly changes from on to off.

[0320] By doing so, when the pMOS field effect transistor 127 changes from off to on, a signal is transmitted at high speed by the field effect transistors in the pMOS inverter 110 and nMOS inverter 129, and the pMOS field effect transistor 127 quickly changes from off to on. On the other hand, when the pMOS field effect transistor 127 changes from on to off, a signal is transmitted slowly by the resistors in the pMOS inverter 110 and nMOS inverter 130, and the pMOS field effect transistor 127 slowly changes from on to off.

[0321] By doing this, pMOS field effect transistor 125 and pMOS field effect transistor 127 change from off to on quickly and from on to off slowly. This allows the dynamic margin to be maximized. However, if the final stages 129 and 130 are nMOS inverters, it is believed that it makes little difference whether 108, 109, and 110 are nMOS inverters or pMOS inverters. Therefore, it is important to ensure that the final stages 129, 130, 149, and 150 are nMOS inverters in order to ensure the dynamic margin.

[0322] From the above, the circuit in Figure 10 can be said to be the optimal of the six circuit configurations, as it can secure both static and dynamic margins. In other words, the first stage is independent and the resistance value of the resistive voltage divider circuit is optimized to secure a static margin, and the final stage is an nMOS inverter to secure a dynamic margin. In this way, stable operation is possible even with changes in the power generation status of various solar cells and changes in the power consumption status of the computer (PC)'s power demands: CPU 15, motherboard 16, storage 17, and GPU 18.

[0323] Figure 16 is an explanatory diagram of when a reverse current prevention diode is required and when it is not. Figure 16(a) is a diagram explaining that a reverse current prevention diode is not required in the case of a coordinated charging system with one solar cell. The circuit 12 of the present invention is inserted between the solar cell 11 and the computer (PC) power supply 13, but a reverse current prevention diode is not required between the solar cell 11 and the circuit of the present invention to allow current to flow only in the direction from the solar cell 11 to the circuit of the present invention.

[0324] 2, when the solar cell is not generating power, the voltage between terminals 201 and 202 is zero. When the computer (PC) is on, power is supplied to the power demanding parts of the computer (PC), namely, CPU 15, motherboard 16, storage 17, and GPU, from commercial power supply 14 and computer (PC) power supply 13. When the computer (PC) is off, only a constant power supply of 5V is supplied to motherboard 16 from commercial power supply 14 and computer (PC) power supply 13.

[0325] At this time, even if the potentials of nodes 135 and 136 are about 12 V, pMOS field effect transistor 126 blocks the reverse current, so current does not flow back from node 135 through pMOS field effect transistor 126, pMOS field effect transistor 125, DC / DC converter 122, and terminal 201 to solar cell 11. Therefore, if there is one solar cell, a reverse current prevention diode is not necessary.

[0326] 2, when the output voltage of the solar cell 11 is small, the connection between the solar cell 11 and the node 135 is cut off, and therefore a reverse current prevention diode is not required. Therefore, as in FIG. 16(a), a reverse current prevention diode is not required.

[0327] Figure 16(b) is a diagram explaining why a reverse current prevention diode is necessary in a cooperative charging system with two solar cells. When there are two solar cells as in Figure 16(b), there may be cases where one solar cell is generating power and the other is not. In this case, without a reverse current prevention diode, current will flow from the generating solar cell to the non-generating solar cell, preventing that current from being supplied to the power demand section. Therefore, when there are two solar cells, a reverse current prevention diode is necessary. Even in this case, in the circuit of Figure 2, if the output voltage of solar cell 11 is small, the connection between solar cell 11 and node 135 is blocked, so no current will flow back from node 135 to solar cell 11.

[0328] FIG. 16(c) is a diagram explaining why a reverse current prevention diode is necessary in an independent power supply system with one solar cell. The independent power supply system is a system that stores power from solar cell 11 in lead-acid battery 23 and supplies the power to a power demand unit when needed. For this reason, a storage battery such as lead-acid battery 23 is necessary. Without reverse current prevention diode 21, when solar cell 11 is not generating power, a reverse current would flow from the storage battery to solar cell 11, causing the power stored in the storage battery to leak out. For this reason, a reverse current prevention diode is necessary in an independent power supply system with one solar cell.

[0329] FIG. 16(d) is a diagram explaining why a reverse current prevention diode is necessary in an independent power supply system with two solar cells. The independent power supply system stores power from solar cell 11 in lead-acid battery 23 and supplies the power to a power demand unit when needed. Therefore, a storage battery such as lead-acid battery 23 is necessary. Without reverse current prevention diode 21, when solar cell 11 is not generating power, a reverse current would flow from the storage battery to solar cell 11, causing the power stored in the storage battery to leak. In addition, without reverse current prevention diode, current would flow from the solar cell that is generating power to the solar cell that is not generating power, preventing that current from being supplied to the power demand unit. Therefore, a reverse current prevention diode is also necessary in an independent power supply system with two solar cells.

[0330] In conclusion, in a cooperative power supply system with one solar cell, the reverse current prevention diode that is required in many systems is not necessary. Reverse current prevention diodes have a forward effect voltage, which causes the voltage to drop by about 0.4V to 1.0V. If reverse current prevention diodes are not required, this voltage drop does not occur, power loss can be prevented, and this contributes to improving the efficiency of the system.

[0331] Figure 17 shows a circuit for interlocking the power supply with a computer (PC). What would happen if power continued to be supplied to terminals 206 and 210 even when the computer (PC) was turned off? In that case, the power supply fan would continue to run even when the computer (PC) was turned off. This would be of concern to many people. Furthermore, if power continued to be supplied to terminals 206 and 210 even when the computer (PC) was turned off, the computer (PC) might not turn on when you try to turn it on later. However, this may differ depending on the computer (PC). For this reason, power should not be supplied to terminals 206 and 210 when the computer (PC) is turned off.

[0332] To achieve this, when the inventor receives a signal to turn off the power to the computer (PC), he drops the node between resistor 105 and resistor 106 to 0V, turns off pMOS field effect transistor 125 and pMOS field effect transistor 145, and prevents power from being supplied from solar cell 11 to the power demanding parts of the computer (PC), namely CPU 15, motherboard 16, storage 17, and GPU 18. When a command to turn off the power to the computer (PC) arrives, H (high) is supplied to terminal 203, and this signal can be used.

[0333] When H (High) is supplied to terminal 203, after a certain time has passed, nMOS field-effect transistor 104 turns on. Therefore, regardless of the voltage between terminals 201 and 202, the node between resistors 105 and 106 becomes approximately the same as GND, i.e., a voltage near 0V. As a result, the signal is inverted and amplified three times in total by nMOS inverter 108, pMOS inverter 109, and nMOS inverter 129, and H (High) is input to pMOS field-effect transistor 125 and pMOS field-effect transistor 126, turning off pMOS field-effect transistor 125 and pMOS field-effect transistor 126. The signal is inverted and amplified three times in total by nMOS inverter 108, pMOS inverter 109, and nMOS inverter 149, and H (High) is input to pMOS field-effect transistor 145 and pMOS field-effect transistor 146, turning off pMOS field-effect transistor 145 and pMOS field-effect transistor 146.

[0334] Based on the same idea, the pMOS field effect transistor 127 and the pMOS field effect transistor 147 are turned on. However, if the power supply to the computer (PC) is off, no power is supplied from the computer (PC) power supply 13. Since no power is supplied from the solar cell 11, no power is supplied to the power demanding parts of the computer (PC), such as the CPU 15, motherboard 16, storage 17, and GPU 18.

[0335] On the other hand, when L (low) is supplied to terminal 203, power is supplied from the computer (PC) power supply 13, coordinated power supply from the solar cell 11 and the computer (PC) power supply 13, and power is supplied from the solar cell 11, depending on the voltage between terminals 201 and 202, and power is supplied to the power demanding parts, that is, CPU 15, motherboard 16, storage 17, and GPU 18.

[0336] Next, delay circuit 102-1 will be described. Delay circuit 102-1 includes resistor 102 and capacitor 103, and operates with a CR time constant. For example, if resistor 102 has a resistance of 100 kΩ (kiloohms) and capacitor 103 has a capacitance of 47 μF (microfarads), the CR time constant is 4.7 seconds. When the computer (PC) is turned off and the potential at terminal 203 goes high (H), the voltage across resistors 105 and 106 becomes 0 V after 3 to 5 seconds, which is the same order of time as the CR time constant. When the computer (PC) is turned on and the potential at terminal 203 goes low (L), the voltage across resistors 105 and 106 becomes the potential resulting from the voltage divided between terminals 201 and 202 after 3 to 5 seconds, which is the same order of time as the CR time constant.

[0337] Let us consider the effect of using a delay circuit in this way. When a signal to turn off the computer (PC) is received, the power from the computer (PC) power supply 13 should be turned off. However, what would happen if the power from the solar cell 11 was cut off before the power from the computer (PC) power supply 13 was turned off? In this case, the power required by the computer (PC) power supply 13 would suddenly increase, and from the computer (PC) power supply 13's perspective, this would suddenly be a large amount of power being required, so it might decide that it is not appropriate to turn off the power.

[0338] When a signal to turn on the computer (PC) is received, the power from the computer (PC) power supply 13 should be turned on. However, what happens if the power from the solar cell 11 suddenly increases before the power from the computer (PC) power supply 13 is turned on? In this case, the power required by the computer (PC) power supply 13 suddenly decreases, and from the computer (PC) power supply 13's perspective, it suddenly no longer needs power, so it may decide that it no longer needs to supply power and stop supplying power. There are cases where the power from the solar cell 11 is sufficient to cover all of the power for the 12V system and the normal 5V system, but even in that case, the computer (PC) power supply 13 needs to be prepared to supply power at any time in case of a sudden increase in power demand.

[0339] In view of this, it is advisable to use a delay circuit to switch whether or not to supply power from the solar cell 11 to the power demand unit after a certain time period has elapsed when a signal to turn the computer (PC) power on or off is received.

[0340] Figure 18 shows the pin assignment for the CPU power connector. Figure 19 shows the pin assignment for the storage power connector. Figure 20 shows the pin assignment for the motherboard power connector. Figure 21 shows the pin assignment for the graphics card power connector.

[0341] Figures 18, 19, 20, and 21 show the specifications of the power connectors for the parts that require power inside the computer (PC) and the connections in this system. Details of the connections have already been explained, so they will not be repeated here.

[0342] There are six types of power supplies: 12V, normal 5V, always-on 5V (5VFSB), 3.3V, -5V, and -12V. In this embodiment, only 12V and normal 5V are used for coordinated power supply, and for always-on 5V (5VFSB), 3.3V, -5V, and -12V, the input and output are simply connected. There is a degree of freedom in the design as to the extent to which coordinated power supply is used, so it is not necessarily the case that only 12V and normal 5V are used for coordinated power supply.

[0343] Figure 22 shows an example of how to wire the power supply of a motherboard between the computer (PC) power supply and the motherboard. This example shows only the 12V part.

[0344] Figure 22(a) shows an example of how to wire between the computer (PC) power supply and the motherboard in a typical PC motherboard power wiring. Number 10 on the computer (PC) power supply side is connected to number 10 on the motherboard side, and number 10 on the computer (PC) power supply side is connected to number 10 on the motherboard side.

[0345] 22(b) shows an example of wiring between the computer (PC) power supply side and the motherboard side in the computer (PC) of the present invention. A switching element 127 is arranged between No. 10 and No. 11 on the computer (PC) power supply side and No. 10 and No. 11 on the motherboard side. In addition, a solar cell 11 is connected to No. 10 and No. 11 on the motherboard side via a DC-DC converter 122 and a switching element 125-1.

[0346] Terminals 10 and 11 on the computer (PC) power supply side are connected to the circuit of the present invention at terminal 204. Terminals 10 and 11 on the motherboard side are connected to the circuit of the present invention at terminal 206. Solar cell 11 is connected to the circuit of the present invention at terminal 201. Switching element 127 is connected to the outside of the circuit of the present invention at terminals 204 and 206. DC-DC converter 122 is connected to the outside of the circuit of the present invention at terminal 201. Switching element 125-1 is connected to the outside of the circuit of the present invention at terminal 206.

[0347] By appropriately controlling switching element 125-1 and switching element 127, the power from the computer (PC) power supply and solar cell 11 is mixed through coordinated power supply and supplied to numbers 10 and 11 on the motherboard side. This coordinated power supply uses the power from solar cell 511 with priority, and only the shortfall is supplied from the computer (PC) power supply side.

[0348] This embodiment assumes one solar cell and one computer (PC). Such a small-scale system is suitable for generating electricity on the balcony of an ordinary home.

[0349] Now, among the above explanations, the parts that are particularly patentable are summarized below. 1. Coordinated power supply is performed and only the computer (PC) part is modified. 2. Ensure static and dynamic margins. 3. A delayed power control signal from the computer (PC) controls whether power is supplied from the solar cell.

[0350] Coordinated power supply in 1 is -A technology that combines power from solar cells and commercial AC power. -It is based on feedback control, - Prioritize the use of power from solar cells, and use commercial AC power only if there is a shortage. That is it.

[0351] This allows the power from the solar cells to be used effectively when there is demand for power, even without a storage battery. This eliminates the need for depreciation costs for the storage battery. Furthermore, by using a power conditioner, the power from the solar cells can be supplied to the power demand section of a computer (PC) without first passing through 100V AC. The power from the solar cells only needs to be converted once by a DC-DC converter, and the voltage difference during conversion is small. This provides an advantage in terms of efficiency, improving efficiency. If the DC-DC converter is more efficient than the conversion efficiency from commercial 100V AC, it may be possible to save more power from commercial 100V AC than the power from the solar cells. Furthermore, since only the computer (PC) section needs to be modified, and there is no need to modify the power system of the entire home or building, the barrier to adoption is low.

[0352] 2. Ensuring static and dynamic margins is important for stable operation. This invention may not have been realized until now because of issues with stable operation. The static margin can be achieved by changing the decision voltage of the first stage of amplification between the system from the solar cell and the system from the PC power supply, and the dynamic margin can be achieved by using an nMOS inverter for the final stage that directly drives the switching element.

[0353] 3. By controlling whether to supply power from the solar cell using a delayed power control signal from the computer (PC), it becomes possible to operate the computer (PC) power switch, control the power from software, go into standby, or go into standby mode when there is no input for a certain period of time. This may have been a barrier that prevented it from being realized until now.

[0354] This embodiment realizes a power system for computers that uses natural energy and can achieve high efficiency and stable operation. High efficiency is achieved by obtaining power from solar cells in one go with a small voltage difference, extracting power at a voltage close to the voltage at which maximum power can be extracted, and eliminating the need for a reverse current prevention diode. Stable operation is achieved by ensuring static and dynamic margins. In terms of a computer power supply system, it is also possible to ensure compatibility with computer power control. Furthermore, the barrier to adoption is low because only the computer (PC) part needs to be modified, and there is no need to modify the power system of the entire home or building.

[0355] [Second embodiment] The second embodiment relates to a cooperative power supply system network. First, the circuit connections will be explained, and then the features will be explained. The second embodiment is an example in which two computers are connected to two solar cells. However, it is assumed that many computers are connected to many solar cells.

[0356] First, the circuit connections will be described. Figure 23 is a block diagram of a first embodiment of the present invention. The DC power supply system of the first embodiment is composed of a solar cell 11, a main circuit 12, a computer (PC) power supply 13, a commercial power supply 14, a CPU 15, a motherboard 16, storage 17, a GPU 18, a reverse current prevention diode 2901, a solar cell 2011, a main circuit 2012, a computer (PC) power supply 2013, a commercial power supply 2014, a CPU 2015, a motherboard 2016, storage 2017, a GPU 2018, and a reverse current prevention diode 2902.

[0357] The positive side of the solar cell 11 is connected to a reverse current prevention diode 2901. The negative side of the solar cell 11 is connected to the main circuit 12 via a terminal 202.

[0358] The anode of the reverse current prevention diode 2901 is connected to the solar cell 11. The cathode of the reverse current prevention diode 2901 is connected to the main circuit 12 via the terminal 201, and to the main circuit 2012 via the terminal 2201.

[0359] The positive side of the commercial power supply 14 is connected to the computer (PC) power supply 13. The negative side of the commercial power supply 14 is connected to the computer (PC) power supply 13. The normal 12V output of the computer (PC) power supply is connected to the main circuit 12 via terminal 206. The normal 5V output of the computer (PC) power supply is connected to the main circuit 12 via terminal 210. The normal 3.3V output of the computer (PC) power supply is connected to the motherboard 16 and storage 17. The GND of the computer (PC) power supply is connected to the main circuit 12 via terminal 205.

[0360] The normal 12V output of the main circuit 12 is connected to the CPU 15, motherboard 16, storage 17, and GPU 18 via terminal 204. The normal 5V output of the main circuit 12 is connected to the motherboard 16 and storage 17 via terminal 208. The GND of the main circuit 12 is connected to the CPU 15, motherboard 16, storage 17, and GPU 18 via terminal 207.

[0361] The second embodiment is an example in which two computers are connected to two solar cells. There are two computer (PC) power supplies, two main circuits, and two power demand units for the computers (PCs), and there are also two solar cells. Reverse current prevention diodes 2901 and 2902 are connected to each solar cell. These reverse current prevention diodes prevent current from flowing backward from one solar cell through the other solar cell.

[0362] The output of the two solar cells is shared to supply power to two main boards, a power supply for computers (PCs), and power demand sections. Compared to two systems where one solar cell supplies power to one main board, a power supply for computers (PCs), and power demand sections, a system where the output of two solar cells is shared to supply power to two main boards, a power supply for computers (PCs), and power demand sections allows for power interchange, which increases the power utilization rate.

[0363] This system network is assumed to have many computers connected to many solar cells. Therefore, the expected usage is many solar cells, main boards, computer (PC) power supplies, and power demand units, and it is relatively flexible even if the power generation status of each solar cell or the power required by each power demand unit differs.

[0364] The first embodiment assumes one solar cell and one computer (computer (PC)). Such a small-scale system is suitable for generating electricity on the balcony of an average household, but a system using multiple solar cells and multiple computers is suitable for an entire home, office building, commercial facility, school, etc. The cooperative power supply system assumes that the generated electricity will be used immediately. Therefore, it is suitable for locations where there is daytime electricity demand for computers. Since people are often in office buildings, commercial facilities, schools, etc. during the day, this system is suitable for installation in office buildings, commercial facilities, schools, etc. during the day. Furthermore, the voltage of the solar cell assumed is higher than in the first embodiment, and 48V, for example, would be suitable.

[0365] When comparing the first and second embodiments, the main advantage of the second embodiment is that it allows power interchange, and the main disadvantage is that a reverse current prevention diode is required. In addition to the advantages of the first embodiment, the second embodiment realizes a cooperative power supply system network that allows power interchange.

[0366] The advantages over Patent Document 1 are as follows: 1. The area outside the section that individually supports PCs (computers) is made up of commercial AC wiring and DC wiring from solar cells, which is typical as of 2025, so the wiring used when using commercial AC can be used as is. The only thing that changes from when only commercial AC is used is the section that individually supports PCs (computers). The power supply for PCs (computers) can also be used as is. There is no need to completely replace the indoor wiring. Also, because coordinated power supply is used without using storage batteries, there are no depreciation costs for storage batteries. 2. Static and dynamic margins are secured to ensure stable operation of the PC (computer). 3. It provides a simple way to link with the PC (computer) power button. [Industrial Applicability]

[0367] The system for one solar cell and one computer given in the first embodiment is suitable for generating electricity on the balcony of an ordinary home, etc. The system using multiple solar cells and multiple computers given in the second embodiment is suitable for an entire house, office building, commercial facility, school, etc. [Explanation of symbols]

[0368] 11 Solar cells 12 Main Circuit 13 Power supply for computer (PC) 14 Commercial exchange 15 CPU 16 Motherboard 17. Storage 18 GPU 201, 202, 203, 204, 206, 207, 208, 210 terminals

[0369] 101, 121, 123, 131, 132, 133, 141, 143, 151, 152, 153 capacitors 102, 105, 106, 107 resistor 104 nMOS field-effect transistor 108, 129, 130, 149, 150 nMOS inverter 109, 110 pMOS inverter 122 DC-DC converter (12V output) 142 DC-DC converter (5V output) 125, 126, 127, 145, 146, 147 pMOS field-effect transistors 124, 128, 144, 148 diodes 134, 135, 136, 154, 155, 156 nodes 102-1 Delay circuit 106-1 Resistor voltage divider circuit

[0370] 201 pMOS field-effect transistor 202 Controller 203 Diode 204 Inductor 205, 206 resistor 301, 302, 303, 304 Diodes 305, 309 capacitors 307 Transformer 312 Switching element 308 Controller 310 DC-DC converter (5V) 311 DC-DC converter (3.3V)

[0371] 401, 404 resistor 402 nMOS field-effect transistor 403 pMOS field-effect transistor 501, 502 resistor 503 DC-DC converter 503 504, 505 Switching elements 506, 507 inverter 508 AC adapter 509 Commercial AC power supply 510 Charging target (smartphone, etc.)

[0372] 125-1 Switching element

[0373] 1005, 1006, 1007, 1008-1, 1009-2, 1010-2, 1029-1, 1030-1, 1049-1, 1050-1 Resistor 1008-2, 1029-2, 1030-2, 1049-2, 1050-2 nMOS field effect transistors 1009-1, 1010-1 pMOS field effect transistor 1034, 1036, 1054, 1056 capacitors 1035, 1037, 1055, 1057 voltage measurement points

[0374] 1105, 1106, 1107, 1108-1, 1109-2, 1110-2 resistor 1108-2, 1129-2, 1130-2, 1149-2, 1150-2 nMOS field effect transistors 1109-1, 1110-1, 1129-1, 1130-1, 1149-1, 1150-1 pMOS field effect transistors 1134, 1136, 1154, 1156 capacitors 1135, 1137, 1155, 1157 Voltage measurement points

[0375] 1205, 1206, 1207, 1208-1, 1209-2, 1210-2, 1229-2, 1230-2, 1249-2, 1250-2 Resistor 1208-2 nMOS field effect transistor 1209-1, 1210-1, 1229-1, 1230-1, 1249-1, 1250-1 pMOS field effect transistors 1234, 1236, 1254, 1256 capacitors 1235, 1237, 1255, 1257 voltage measurement points

[0376] 1305, 1307, 1308-1, 1309-1, 1329-1, 1330-2, 1349-1, 1350-1 resistor 1308-2, 1309-2, 1329-2, 1330-2, 1349-2, 1350-2 nMOS field effect transistors 1334, 1336, 1354, 1356 capacitors 1335, 1337, 1355, 1357 voltage measurement points

[0377] 1405, 1407, 1408-1, 1409-1, resistor 1408-2, 1409-2, 1429-2, 1430-2, 1449-2, 1450-2 nMOS field effect transistors 1429-1, 1430-1, 1449-1, 1450-1 pMOS field effect transistors 1434, 1436, 1454, 1456 capacitors 1435, 1437, 1455, 1457 voltage measurement points

[0378] 1505, 1507, 1508-1, 1509-1, 1529-2, 1530-2, 1549-2, 1550-2 resistor 1508-2, 1509-2 nMOS field effect transistors 1529-1, 1530-1, 1549-1, 1550-1 pMOS field effect transistors 1534, 1536, 1554, 1556 capacitors 1535, 1537, 1555, 1557 voltage measurement points

[0379] 11, 11-2 Solar cells 12 Circuit of the present invention (main circuit) 13 Power supply for computer (PC) 14 Commercial AC power supply 21-1, 21-2 Reverse current prevention diode 22 General charge controller 23 Lead acid battery

[0380] 2011 Solar Cell 2012 Main Circuit 2013 Computer (PC) power supply 2015 CPU 2016 Motherboard 2017 Storage 2018 GPU 2201, 2202, 2203, 2204, 2206, 2207, 2208, 2210 terminals 2901, 2902 Reverse current prevention diodes

Claims

1. a first node, a second node, a third node, a fourth node, a first DC / DC converter, a first switching element or group of switching elements, and a second switching element or group of switching elements; a potential of the first node is output to the second node by the first DC / DC converter, the first switching element or switching element group is connected between the second node and the fourth node, and the second switching element or switching element group is connected between the third node and the fourth node; the first switching element or switching element group has a completely off state, a completely on state, and other intermediate states between on and off, and changes in an analog manner from on to off and from off to on according to a voltage at a control terminal of the first switching element or switching element group; the second switching element or switching element group has a completely off state, a completely on state, and other intermediate states between on and off, and changes in an analog manner from on to off and from off to on according to a voltage at a control terminal of the second switching element or switching element group; When the potential of the first node is equal to or less than a first constant potential value, the first switching element or group of switching elements is turned completely off and the second switching element or group of switching elements is turned completely on; when the potential of the first node is equal to or greater than a third constant potential value and equal to or less than a fourth constant potential value, the first switching element or group of switching elements is turned completely on and the second switching element or group of switching elements is turned completely on; when the potential of the first node is equal to or greater than a second constant potential value, the first switching element or group of switching elements is turned completely on and the second switching element or group of switching elements is turned completely off; the third constant voltage value is greater than the first constant voltage value, the fourth constant voltage value is greater than the third constant voltage value, and the second constant voltage value is greater than the fourth constant voltage value; when the potential of the first node suddenly drops from a state exceeding the second constant potential value to a state below the first constant voltage value, the first switching element or switching element group starts from an on state and the second switching element or switching element group is off, the first switching element turns on and the second switching element or switching element group turns on, thereafter the first switching element or switching element group turns off and the second switching element or switching element group turns on, When the potential of the first node suddenly rises from a state below the first constant potential value to a voltage exceeding the second constant potential value, the first switching element or switching element group starts in an off state and the second switching element or switching element group is on, the first switching element turns on and the second switching element or switching element group turns on, and then the first switching element or switching element group turns on and the second switching element or switching element group turns off. A power supply device characterized by:

2. further comprising a fifth node, a sixth node, a first amplifier circuit or group of amplifier circuits, a second amplifier circuit or group of amplifier circuits, a third amplifier circuit, a fourth amplifier circuit, and a resistive voltage divider; the first node is resistively divided by the resistive voltage divider and connected to a fifth node, the first node is resistively divided by the resistive voltage divider and connected to a sixth node, the fifth node passes through zero or more amplification stages, is amplified by a third amplification circuit, and is connected to a control terminal of a first switching element or switching element group, the sixth node passes through zero or more amplification stages, is amplified by a fourth amplification circuit, and is connected to a control terminal of a second switching element or switching element group, the third amplifier circuit includes an nMOS field effect transistor and a resistor, and the fourth amplifier circuit includes an nMOS field effect transistor and a resistor; The fifth node and the sixth node are different nodes, and the third amplifier circuit and the fourth amplifier circuit are different individual circuits.

2. The power supply device according to claim 1.

3. further comprising an eighth node, a ninth node, a first delay circuit, and a third switching element or group of switching elements; The eighth node is connected to the input of the first delay circuit, the ninth node is connected to the output of the delay circuit, and the ninth node is connected to a control terminal of a third switching element or switching element group, and when the potential of the ninth node is within a specific potential range, the first switching element or switching element group is turned off and the second switching element or switching element group is turned on.

3. The power supply device according to claim 2.

4. the eighth node is connected to the input of the first delay circuit; When the state of the eighth node is at a first potential, the potential of the fifth node is determined by the first node, when the state of the eighth node is at the first potential, the potential of the sixth node is determined by the first node, when the state of the eighth node is at a second potential, the potential of the fifth node becomes a third potential, and when the state of the eighth node is at a second potential, the potential of the sixth node becomes a third potential; When the state of the eighth node changes from a first potential to a second potential, after a first constant time delay, the potential of the fifth node changes from a state determined by the first node to a third potential; when the state of the eighth node changes from the first potential to the second potential, after a first constant time delay, the potential of the sixth node changes from a state determined by the first node to a third potential; when the state of the eighth node changes from the second potential to the first potential, after a first constant time delay, the potential of the fifth node changes from the third potential to a state determined by the first node; and when the state of the eighth node changes from the second potential to the first potential, after a first constant time delay, the potential of the sixth node changes from the third potential to a state determined by the first node.

4. The power supply device according to claim 3.

5. The first node is connected to a power generation device using natural energy, the third node is connected to a node converted from an AC power source, and the fourth node is connected to a power demand portion within a computer (PC), and on a path from the power generation device using natural energy via the first node, via a first DC / DC converter, via the second node, via a first switching element or group of switching elements, to the fourth node, only one DC-to-DC voltage conversion is performed by the first DC / DC converter, and no other power conversion is performed, and power converted from AC and input via the third node is converted from AC to DC only once, and is converted from DC to DC zero or one time.

5. The power supply device according to claim 4.

6. The eighth node is connected to a signal that changes depending on at least one of the information from the power button of the computer (PC), the reset button of the computer (PC), and information input to the operating system on the computer (PC).

6. The power supply device according to claim 5.

7. One or more capacitors are connected to the first node, one or more capacitors are connected to the second node, one or more capacitors are connected to the third node, and one or more capacitors are connected to the fourth node.

7. The power supply device according to claim 6.

8. 8. The power supply device according to claim 7, wherein the power from the fourth node is supplied to at least a motherboard of a computer (PC) and a storage device.

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