Device and method for creating a protective layer for interconnects and devices in packaged quantum structures

Abstract

The semiconductor device comprises a first chip layer having a first chip layer front surface and a first chip layer back surface, a qubit chip layer having a qubit chip layer front surface operably coupled to the first chip layer front surface using a set of bump bonds, and a qubit chip layer back surface, a set of through silicon vias (TSVs) connected to at least one of the first chip layer back surface or the qubit chip layer back surface, and a cap wafer metal bonded to at least one of the qubit chip layer back surface or the first chip layer back surface.

Description

[Technical Field]

[0001] This disclosure relates to the use of superconducting through-silicon vias (TSVs) to access high-quality surfaces on the backside of qubit or interposer wafers. Metallic bonding is used to attach a specialized cap wafer to the top of a thinned qubit wafer, creating a completely sealed metallic channel within which long-distance connections are fabricated. [Background technology]

[0002] Quantum computing, broadly speaking, is the use of quantum mechanical phenomena to perform computing and information processing functions. Quantum computers operate on quantum bits, which contain superpositions of both 0 and 1, and can entangle multiple quantum bits to use interference. A qubit (e.g., a quantum binary digit) is a quantum mechanical analog of a classical bit. Superconducting qubits can exhibit quantum mechanical behavior at the macroscopic level (e.g., facilitating quantum information processing), offering a promising path to fully operational quantum computers. Superconducting qubits are multilevel systems, with the two lowest energy levels (0 and 1) constituting a qubit. One of the challenges in quantum computing is protecting quantum information (e.g., qubit states) and mitigating errors during dynamic quantum computations. Typical quantum circuit packaging includes two chips joined by bump bonding, with only the inward-facing surfaces utilized for device and signal transmission / readout. The qubit chip surfaces are utilized for the qubits and the interconnects that enable the qubits to be entangled. While it is possible to mix functions between these two layers, the crossing pattern of lines means that bump bonds are often utilized to provide crossovers at various locations. Having only two high-quality surfaces arranged with vertical connections limits the types of structures that can be built. For example, in one non-limiting scenario, with nearest-neighbor couplings implemented on the qubit surface, adding a second set of connections to more distant qubits requires transferring coupling lines up to the interposer surface and back down to the qubit surface to achieve the crossover. This can lead to increased signal crosstalk, as the couplings are potentially of lower quality and the layout becomes significantly more complex. Summary of the Invention

[0003] The following presents a summary to provide a basic understanding of one or more embodiments of the present invention. This summary is not intended to identify key or critical elements or to delineate the scope of particular embodiments or the claims. Its sole purpose is to present concepts in a simplified form as a prelude to the more detailed description that is presented later. In one or more embodiments described herein, a system, computer-implemented method, apparatus, and / or computer program product facilitates accessing a high-quality surface on the backside of a qubit or interposer wafer using superconducting through-silicon vias. A metal bond is utilized as a special cap wafer on top of the thinned qubit wafer, forming a completely sealed metal channel with long-distance connections fabricated within.

[0004] According to one embodiment, a device includes a first chip layer with a first chip layer front surface and a first chip layer back surface; a qubit chip layer with a qubit chip layer front surface operably coupled to the first chip layer front surface using a set of bump bonds, and a qubit chip layer back surface; a set of through silicon vias (TSVs) connected to at least one of the first chip layer back surface or the qubit chip layer back surface; and a cap wafer metal bonded to at least one of the qubit chip layer back surface or the first chip layer back surface.

[0005] In an optional aspect, the first chip is an interposer chip.

[0006] In an optional aspect, the at least one of the qubit chip layer back surface or the first chip layer back surface is operably coupled to a filter.

[0007] In an optional aspect, the at least one of the qubit chip layer backside or the first chip layer backside is operably coupled to a qubit feed line.

[0008] In an optional aspect, the at least one of the qubit chip layer backside or the first chip layer backside is operably coupled to a resonator.

[0009] In an optional aspect, the at least one of the qubit chip layer backside or the first chip layer backside is operably coupled to a coupler.

[0010] In another embodiment, the Q factor associated with the interconnection of the device is at least 100,000.

[0011] In yet another embodiment, the Q factor associated with the device interconnections is in the range of approximately 500,000 to 20,000,000.

[0012] According to one embodiment, a method includes forming a first chip layer having a first chip layer front surface and a first chip layer back surface; forming a set of bump bonds on the first chip layer front surface; forming a qubit chip layer having a qubit chip layer front surface operably coupled to the first chip layer front surface using the set of bump bonds, and a qubit chip layer back surface; forming a set of through silicon vias (TSVs) connected to at least one of the first chip layer back surface or the qubit chip layer back surface; and forming a cap wafer metal bonded to at least one of the qubit chip layer back surface or the first chip layer back surface.

[0013] In an optional aspect, the method further comprises coupling the at least one of the qubit chip layer backside or the first chip layer backside to a filter.

[0014] In an optional aspect, the method further comprises coupling the qubit chip layer backside or the first chip layer backside to a qubit feed line.

[0015] In an optional aspect, the method further comprises coupling the qubit chip layer backside or the first chip layer backside to a resonator.

[0016] In an optional aspect, the method further comprises coupling the qubit chip layer backside or the first chip layer backside to a coupler. [Brief explanation of the drawings]

[0017] [Figure 1] 1 illustrates a block diagram of an exemplary system implementation according to an embodiment.

[0018] [Figure 2] 1 illustrates an exemplary quantum circuit packaging according to an embodiment.

[0019] [Figure 3] 1 illustrates an exemplary qubit chip surface top grating according to an embodiment.

[0020] [Figure 4] 1 illustrates an exemplary flowchart for creating a protected layer for interconnects and devices in a packaged structure, according to an embodiment.

[0021] [Figure 5] 1 shows an exemplary schematic diagram of a multi-layer superconducting device according to an embodiment.

[0022] [Figure 6] 1 illustrates a block diagram of an exemplary non-limiting operating environment in which one or more embodiments described herein may be facilitated.

[0023] [Figure 7] 1 illustrates a block diagram of an exemplary non-limiting cloud computing environment in accordance with one or more embodiments of the present disclosure.

[0024] [Figure 8]FIG. 1 illustrates a block diagram of exemplary non-limiting abstraction model layers in accordance with one or more embodiments of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0025] The following detailed description is illustrative only and is not intended to limit the embodiments and / or the application or uses of the embodiments. Furthermore, there is no intention to be bound by any express or implied information presented in the preceding Summary section or Detailed Description section. One or more embodiments will now be described with reference to the drawings, in which like reference numerals are used to refer to like elements throughout. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a more thorough understanding of one or more embodiments. It will be apparent, however, that in various instances one or more embodiments may be practiced without these specific details.

[0026] The present disclosure generally relates to systems, devices, and methods that utilize superconducting TSVs to access high-quality surfaces on the backside of qubit or interposer wafers. To protect the new surface from proximity to lossy materials such as adhesives or silicon oxide, metal bonds are formed on a specialized cap wafer on top of the thinned qubit wafer, creating completely sealed metal channels within which long-distance connections are fabricated.

[0027] Quantum computing utilizes qubits as its essential units instead of classical computing bits. A qubit (e.g., a quantum binary digit) is the quantum mechanical equivalent of a classical bit. While a classical bit can be in only one of two basis states (e.g., 0 or 1), a qubit can be in a superposition of its basis states (e.g., α|0>+β|1>, where α and β are |α| 2 +|β| 2= 1), which theoretically allows some qubits to hold exponentially more information than the same number of classical bits. Thus, quantum computers (e.g., computers that use qubits instead of simply classical bits) could theoretically rapidly solve problems that would be extremely difficult for classical computers. A classical computer's bits are simple binary digits, either 0 or 1. Nearly any device with two distinct states—switches, valves, magnets, coins, etc.—can function to represent a classical bit. Qubits, with their quantum mystique, can occupy a superposition of 0 and 1 states. Qubits cannot have intermediate values ​​such as 0.63; when a qubit's state is measured, the result is either 0 or 1. However, during the course of a computation, a qubit can function as if it were a mixture of, for example, 63 percent 0 and 37 percent 1 states. A typical quantum program requires coordination of the quantum and classical parts of the computation. With quantum programs, it is useful to identify the processes and abstractions involved in specifying a quantum algorithm, convert the algorithm into an executable form, run experiments or simulations, and analyze the results. A concept throughout these processes is the use of intermediate representations. The intermediate representation (IR) of a computation is neither its source language description nor the target machine instructions, but something in between. A compiler may use several IRs during the process of transforming and optimizing a program. The input is source code describing the quantum algorithm and compile time parameters. The output is a combination of quantum / classical programs expressed using high-level IR. The difference between quantum and classical computers is that quantum computers are probabilistic; therefore, measurements of algorithm outputs provide a good solution within a confidence interval specific to the algorithm. The computation is then repeated until a solution with satisfactory probability can be achieved.

[0028] By processing information using the laws of quantum mechanics, quantum computers offer novel means for performing computational tasks, such as molecular computing, optical photonics, optimization, and many more. Many algorithms have been introduced to efficiently perform such computational tasks. Many promising solid-state implementations of qubits have also been demonstrated, including superconducting qubits of various flavors, spin qubits, and charge qubits in various material systems. Typical quantum circuit packaging includes two chips with only the inward-facing surfaces utilized for device and signal transmission / readout. The qubit-chip surface is utilized for the qubits and the interconnects that enable entanglement of the qubits. The interposer surface is utilized for the readout resonator, filters, and supply and readout lines. While it is possible to mix functions between these two layers, the crossover pattern of the respective lines means that bump bonds are utilized to provide crossovers at these locations. Having only two high-quality surfaces arranged with vertical connections limits the types of structures that can be constructed. For example, it is difficult to arrange more complex interaction schemes (e.g., to allow distant qubits to couple together) using only two surfaces. With nearest-neighbor coupling implemented on the qubit surface, adding a second set of connections to a more distant qubit requires transferring coupling lines up to the interposer surface and back to the qubit surface to achieve the crossover, which can lead to increased signal crosstalk due to potentially lower quality coupling and significantly more complex layout.

[0029] Generally, there are various processes used to form microchips that are packaged into integrated circuits (ICs). In particular, semiconductor doping is the modification of electrical properties by doping, for example, transistor sources and drains, generally by diffusion and / or ion implantation. Also, both conductor (e.g., polysilicon, aluminum, copper, etc.) and insulator (e.g., various forms of silicon dioxide, silicon nitride, etc.) films are used. By creating structures of these various components, various transistors can be constructed and wired together to form the complex circuits of modern microelectronic devices. One of the fundamental manufacturing processes is semiconductor lithography, in which patterns on a semiconductor substrate are formed for subsequent transfer of the patterns to the substrate.

[0030] Semiconductor devices are used in a variety of electronic and electro-optical applications. Integrated circuits are typically formed from various circuit configurations of semiconductor devices, such as transistors, capacitors, resistors, and conductive interconnect layers formed on a semiconductor wafer. In the semiconductor manufacturing process, the conductive interconnect layers are fabricated on a single wafer along with the semiconductor devices. The interconnect layers are connected by a network of holes (or vias) formed throughout the IC. In particular, a through-silicon via (TSV) is an electrical contact that passes completely through the semiconductor wafer.

[0031] Fabricating a complex structure of conductive interconnect layers and vias within an IC is a process-intensive and cost-sensitive portion of semiconductor IC manufacturing. Accordingly, embodiments herein propose utilizing superconducting TSVs to access a high-quality surface on the backside of a qubit or interposer wafer. To protect the new surface from proximity to lossy materials such as adhesives or silicon oxide, a metal bond is formed on a specialized cap wafer to the top of the thinned qubit wafer, creating a completely sealed metal channel within which long-distance connections are fabricated. Embodiments facilitate a second interconnect layer for long-distance bus connections in addition to the nearest-neighbor connections already present on the qubit bottom surface.

[0032] FIG. 1 illustrates a block diagram of an exemplary system 100 capable of accessing and processing data using the illustrated variable computation component according to one or more embodiments described herein. System 100 can evaluate and identify large amounts of data of various formats, use machine learning, and facilitate the training of neural networks or other types of models. System 100 can also generate predictive recommendations at an individual level in the context of one or more embodiments described herein. Aspects of the systems (e.g., system 100, etc.), devices, or processes described in this disclosure may constitute machine-executable components embodied within a machine, e.g., embodied in one or more computer-readable medium(s) associated with one or more machines. Such components, when executed by one or more machines (e.g., computers, computing devices, virtual machines, etc.), may cause the machine to perform the operations described herein. Repeated descriptions of similar elements used in one or more embodiments described herein have been omitted for purposes of brevity.

[0033] System 100 can facilitate the evaluation and identification of large amounts of data in various formats. System 100 can also generate predictive recommendations at an individual level that provide context according to one or more embodiments described herein. Aspects of the systems (e.g., system 100, etc.), devices, or processes described in this disclosure may constitute machine-executable components embodied within a machine, e.g., embodied in one or more computer-readable medium(s) associated with one or more machines. Such components, when executed by one or more machines (e.g., computers, computing devices, virtual machines, etc.), can cause the machine to perform the described operations. Repeated descriptions of similar elements used in one or more embodiments described herein have been omitted for the sake of brevity.

[0034] System 100 may optionally include a server device, one or more networks, and one or more devices (not shown). System 100 may also include or otherwise be associated with quantum circuit 104 incorporating quantum circuit package 106 that may operably couple various components shown in more detail in Figures 2, 3, and 5, including, but not limited to, a first chip layer with a first chip layer front surface and a first chip layer back surface, a qubit chip layer with a qubit chip layer front surface and a qubit chip layer back surface operably coupled to the first chip layer front surface with a set of bump bonds, a set of through silicon vias (TSVs) connected to at least one of the first chip layer back surface or the qubit chip layer back surface, and a cap wafer metallized to at least one of the qubit chip layer back surface or the first chip layer back surface.

[0035] In one implementation, quantum circuit 104 incorporates semiconductor package structure 200 shown in FIG. 2 , which includes first chip layer 206 having a front surface and a first chip layer back surface using a first chip layer (or interposer chip 206). Qubit chip layer 108 has a qubit chip layer front surface and a qubit chip layer back surface, with the qubit chip layer front surface operably coupled to the first chip layer front surface using a set of bump bonds 204. For example, in connection with an oscillator or resonator, the quality (Q) factor associated with the device interconnect is approximately 100,000, and is in the range of approximately 500,000 to 2,000,000. In other examples, such as interconnects, this is characterized by loss. One of the qubit chip layer back surface or the first chip layer back surface may be operably coupled to a filter, qubit feed line, resonator, or coupler (not shown). A set of through-silicon vias (TSVs) may be connected to at least one of the first chip layer backside or the qubit chip layer backside, and a cap wafer metal may be bonded to at least one of the qubit chip layer backside or the first chip layer backside. In a non-limiting scenario, a plurality of qubits in the qubit chip layer are on the exposed surface. The set of qubits in the qubit chip layer may also be connected by a plurality of in-plane buses and a plurality of buried layer buses, the plurality of in-plane buses being on the first qubit chip surface and the plurality of buried layer buses being on the second qubit chip surface. The cap wafer employs at least one cavity including a metal coating inside the cavity, the metal coating being the same or a different metal as the bonding metal, which may contact the bonding metal to provide a solid ground. The interconnect material may also be comprised of at least one of InSn, PbSn, SnAgCu, InBiSn, InSnAg, SnAg, InAg, or any suitable material.

[0036] In certain non-limiting implementations, TSVs are formed by, for example, opening through a semiconductor wafer at desired locations and then filling the vias with a conductive material to provide solid metal contacts extending from the front side of the wafer to the back side of the wafer. Some considerations when forming TSVs include a conductive metal fill in the vias that is substantially coplanar with the front side and back side of the wafer to be compatible with downstream processing techniques. It is desirable to fill the vias with conductive material so that there are no voids to minimize manufacturing issues. It is also desirable to facilitate TSV manufacturing methods and structures that utilize high-purity, low-void conductive materials and that are less dependent on the aspect ratio of the vias than known techniques. Accordingly, embodiments provide improved techniques for creating protected layers for interconnects and devices in packaged structures. In these embodiments, TSVs connect multiple qubits through a buried metallization layer over which coplanar waveguide (CPW) or stripline connections are formed along with metal-metal junctions between two wafers. Adding to the complexity, multiple qubits reside on the exposed surface and are connected by both multiple in-plane buses and multiple buried-layer buses. The multiple in-plane buses reside on the first qubit chip surface, while the multiple buried-layer buses reside on the second qubit chip surface. In this three-sided structure consisting of the interposer, qubit chip, and buried layer, a cavity is etched into the silicon cap to facilitate space for connecting lines. The cavity allows for shielding of bus lines or other devices, which is achieved by a metal coating inside the cavity. This forms a complete Faraday cage around the protected bus or device.

[0037] System 100 may be any suitable computing device or set of computing devices that may be communicatively coupled to devices, non-limiting examples of which may include, but are not limited to, a server computer, a computer, a mobile computer, a mainframe computer, an automated test system, a network storage device, a communications device, a web server device, a network switching device, a network routing device, a gateway device, a network hub device, a network bridge device, a control system, or any other suitable computing device. A device may be any device that can communicate information with system 100 and / or any other suitable device that can use information provided by system 100. It should be understood that system 100, components, models, or devices may be provided with communications components (not shown) that enable communication between systems, components, models, devices, etc. over one or more networks.

[0038] The various components of system 100 may be connected either directly or through one or more networks. Such networks may include wired and wireless networks, including, but not limited to, cellular networks, wide area networks (WANs) (e.g., the Internet), or local area networks (LANs), non-limiting examples of which include cellular, WAN, Wireless Fidelity (Wi-Fi), Wi-Max, WLAN, wireless communications, microwave communications, satellite communications, optical communications, acoustic communications, or any other suitable communications technology. Additionally, the aforementioned systems and / or devices have been described with respect to interactions between several components. It will be understood that such systems and components may include these components or designated subcomponents therein, some of the designated components or subcomponents, and / or additional components. Subcomponents may also be implemented as components communicatively coupled to other components rather than being included within a parent component. Furthermore, one or more components and / or subcomponents may be combined into a single component providing aggregate functionality. These components may also interact with one or more other components not specifically described herein for the sake of brevity, but known to those skilled in the art.

[0039] The computer processing systems, methods, apparatus, and / or computer program products of the present application may be used to solve new problems that arise through developments in technology, computers, networks, the Internet, and the like.

[0040] Quantum circuit input / output connections are increasingly required in terms of size and complexity. There are ongoing advances in 3D integration and radio-frequency packaging technologies. Other developments include room-temperature microwave devices and complex superconducting circuits in the field of circuit QED. Numerous proposals have been implemented for multilayer microwave-integrated quantum circuit architectures that adapt existing circuit designs and other fabrication techniques. Quantum information processing is rapidly developing in many implementations, particularly in superconducting quantum circuits. Superconducting quantum circuits present challenges that prevent scaling strategies similar to those of classical integrated circuits. Strong electromagnetic interactions between qubits enable efficient entanglement and control, while also making them susceptible to quantum information degradation. The resulting crosstalk results from unwanted mixing of quantum states or decoherence. Therefore, preventing crosstalk effects is desirable because high-Q qubits (Q ≈ 106-109) can also be coupled to high-speed low-Q (Q ≈ 103) elements for readout, control, and feedback. High-Q may also be limited by the quality of the TSVs themselves, due to low loss considerations.

[0041] Returning to quantum circuit packaging 200 of FIG. 2 , electronic components can generally be connected together through different technologies. One such method is through wire bonding. Wire bonding is a well-known technique for forming electrical interconnections between electronic components, such as printed circuit boards (PCBs) or integrated circuits (ICs). As shown, quantum circuit package 200 includes two chips with inward-facing surfaces utilized for device and signal transmission / readout. Quantum circuits are typically 2D arrays of qubits. This schematic is a two-stack representation in which qubit chip 202 is connected to wiring and signal processing circuit chips through interposer chip 206. Qubit chip 202 has a qubit chip surface utilized for qubits and interconnects that allow the qubits to be entangled. Interposer surface 206 is utilized for readout resonators, filters, feed, and readout lines. Bump bonds 204 are connected to qubit chip 202 and are formed from a low-temperature solder material and are sized and / or shaped to allow electrical connections to be made at the contact points. Bump bonds 204 may be used to mechanically and electrically connect electronic connectors (e.g., direct current (DC) signals and / or radio frequency (RF) signals) to the first substrate. Bump bonds 204 may also be used to mechanically and electrically connect the first substrate to a second substrate.

[0042] Mapping long-distance buses presents challenges when accessing high-quality surfaces, such as superconducting metal deposited directly on the wafer, is problematic for signal propagation. Signal quality can be characterized by the Q-factor. As mentioned above, for example, in the context of oscillators or resonators, a high Q can be limited by the quality of the TSV itself in terms of low loss. While the Q-factor is well-described for resonators, this is not the case for low-loss, low-impedance transmission lines. Qubits are typically harmonic resonators with frequencies of 4-5 GHz. The largest published devices are <100 qubits and have natural frequencies of approximately 4-5 GHz, reducing the device's amplitude. This can result in high connection losses, significantly reducing qubit coherence times and limiting their use in quantum computing. High-quality interfaces often lack oxide due to the inherent losses associated with these types of dielectric materials, which precludes any CMOS-type structures for interconnects. Having only two high-quality surfaces arranged with vertical connections limits the types of structures that can be built. For example, it is difficult to arrange more complex interaction schemes (e.g., to allow distant qubits to couple together) by using only these two surfaces. With nearest-neighbor couplings implemented on the qubit surface, adding a second set of connections to distant qubits requires transferring coupling lines up to the interposer surface and back to the qubit surface to achieve the crossover. This can lead to increased signal crosstalk, as the couplings potentially have lower quality signals and the layout becomes more complex. Therefore, embodiments herein propose an efficient method for accessing high-quality surfaces on the backside of a qubit or interposer wafer using superconducting TSVs. A multi-layer topology is proposed to ensure crosstalk is reduced and high-quality connections are created. Additionally, connections within the interposer wafer to underlying metal lines enable complex signal transfer.

[0043] Figure 3 shows an exemplary qubit chip surface top-plane lattice. In the qubit chip surface 300, the qubits are the black squares 304. The larger the chip, the more problematic this structure becomes. In the qubit chip surface 300, the red lines 302 are readout resonators. These resonators typically reside on the interposer chip 206, and these wires 302 typically allow the qubits to be programmed. Qubit connections on the qubit chip from this lattice allow the qubits to be entangled. While it is possible to mix functions between these two layers, the crossing pattern of red and black lines means that bump bonds can be used to provide crossovers at these locations. There are two challenges faced in this design: when the quantum circuit does not have a 2D nearest-neighbor lattice. The red and black layers of wiring become problematic when a qubit on the left is connected to a qubit on the right, or when a qubit on the top is connected to a qubit on the bottom. Also, by running respective buses between two distant qubits, the buses can run directly past the qubits in their way. This can introduce additional crosstalk, inadvertently applying control signals to unintended qubits, and ultimately degrade quantum computation. It becomes difficult to have tangled long-distance connections between black layers simultaneously connected to neighbors. This type of wire crossing can result in short circuits. Even when attempts have been made using bump bonds connected to the chip, this does not provide a practical topology solution. These connections are single-photon interactions between qubits, where the red signal is a high-power signal and there is a very low signal between the qubits. For example, if a program signal is chosen with a high-frequency microwave pulse, when the resonator 302 is close to the black line / qubit 304, the other qubits, which are also close, will be corrupted while attempting to program one qubit of interest. Therefore, these connections are highly susceptible to crosstalk. In one implementation, the resonator 302 in the lower-left red line originates from the qubit 304.This traverses the path between the qubits to the edge where the signal is extracted to the output. High power lines adjacent to the qubits on either side of the channel can cause crosstalk, which is seen as a constant problem.

[0044] FIG. 4 shows an exemplary flowchart 400 for creating a protected layer for interconnects and devices in a packaged structure. At 402, a first chip layer is provided having a first chip layer front surface and a first chip layer back surface. At 404, a qubit chip layer has a qubit chip layer front surface and a qubit chip layer back surface, and the qubit chip layer front surface is operably coupled to the first chip layer front surface using a set of bump bonds. At 406, a set of through-silicon vias (TSVs) is connected to at least one of the first chip layer back surface or the qubit chip layer back surface. At 408, a cap wafer metal is bonded to at least one of the qubit chip layer back surface or the first chip layer back surface. Qubits in the qubit chip layer are on the exposed surface. The sets of qubits in the qubit chip layer are connected by in-plane buses and buried layer buses. Additionally, superconducting metal is deposited directly on superconducting waivers for signal propagation. The signal quality can be characterized by a Q-factor. While Q-factors are well-described for resonators, this is not the case for low-loss, low-impedance transmission lines. As discussed above, for example, in connection with oscillators or resonators, high Q may be limited by the quality of the TSVs themselves in terms of low loss. The Q-factor associated with the device interconnects is at least 100,000. The Q-factor associated with the device interconnects is in the range of 500,000 to 2,000,000. One of the qubit chip layer backside or the first chip layer backside is operably coupled to a filter, qubit feedline, resonator, or coupler. The cap wafer comprises at least one cavity containing an interconnect material. In wire-bonded electronic components, the connection material may be comprised of at least one of gold (Au), copper (Cu), silver (Ag), aluminum (Al), or any other suitable material. The interconnect material in the proposed embodiment may consist of at least one of the following materials: InSn, PbSn, SnAgCu, InBiSn, InSnAg, SnAg, InAg or any suitable material.

[0045] FIG. 5 shows an exemplary schematic diagram of a multi-layer superconducting device 500. As shown, superconducting TSVs are utilized to access high-quality surfaces on the backside of qubits 504 or interposer chip 508. To protect the new surfaces from proximity to lossy materials such as adhesives or silicon oxide, a specialized cap wafer 502 is metallurgically bonded to the top of the thinned qubit wafer 504, forming a completely sealed metal channel within which long-distance connections are fabricated. Bump bonds 506 are also connected to the qubit chip 504. As an example, these embodiments propose enabling a second interconnect layer for long-distance bus connections in addition to the nearest-neighbor connections already present on the bottom surface of the qubits. To mitigate crosstalk, connections are made from the backside of the qubit chip 504 so that signals can traverse from the qubits all the way to the backside of the chip 504 and contact patterned, high-quality metal (superconducting metal) interconnects back to the other qubit. Several other possible geometries exist, including the use of additional layers on one or both of the backsides of the two existing chips (e.g., qubit chip 504 and interposer chip 508). These very high-quality layers have filters, qubits, feed lines, resonators, or couplers disposed therein. The metal bonds utilized to attach cap wafer 502 can be hermetic, but they may or may not be hermetic, depending on the requirements. These embodiments assume that the TSVs have low loss, the backside of qubit chip 504 is clean, and the superconducting metal and interface function effectively. This provides high-quality interconnects by connecting the TSVs to oxide-free backside pure metal. Also, to protect and prepare device 500, the handler or cap wafer 502 can be permanently attached to qubit chip 504. In these embodiments, the wiring is isolated from each other and from noise sources within the handler. The interposer chip or wafer 508 can be metal bonded to qubit chip 504, thus avoiding any oxides.

[0046] The qubits are connected by TSVs through a buried metallization layer where stripline connections are formed along with metal-metal junctions between the two wafers (qubit chip wafer and interposer chip wafer). The striplines connect to the backside of the TSVs. The cavities are etched into the silicon cap to leave space for connecting lines. Leaving physical space for cross-connecting wires is optional. The qubits are also on the exposed surface, and the qubits are connected by both in-plane buses and buried layer buses to increase complexity. Embodiments herein propose a structure where this layer can be either the qubit or interposer backside, and / or both. While previous designs primarily focus on metal-metal junctions within the cavity and coupling to the 3D cavity, these embodiments provide a novel interconnection scheme. Previous structures also focus on qubits sealed within the cavity; however, embodiments herein propose leaving the qubits on the exposed surface and coupling qubits to qubits using wires. While conventional structures explicitly utilize 3D resonant cavities, the embodiments herein utilize coplanar waveguides (CPWs). Conventional structures of qubits are on freestanding thinned substrates embedded in cavities. The embodiments herein can illustrate the transition between CPWs and TSVs for impedance matching, with an emphasis on buried layer resonators as buses.

[0047] To provide a context for various aspects of the disclosed subject matter, Figure 6 and the following discussion are intended to provide a general description of a suitable environment in which various aspects of the disclosed subject matter may be implemented. Figure 6 illustrates a block diagram of an example of a non-limiting operating environment in which one or more embodiments described herein may be facilitated. Repeated descriptions of similar elements used in other embodiments described herein are omitted for the sake of brevity.

[0048] 6, a suitable operating environment 600 for implementing various aspects of the disclosure may also include a computer 612. The computer 612 may also include a processing unit 614, a system memory 616, and a system bus 618. The system bus 618 couples system components including, but not limited to, the system memory 616 to the processing unit 614. The processing unit 614 may be any of a variety of available processors. Dual microprocessors and other multi-processor architectures may also be used as the processing unit 614. The system bus 618 may be any of several types of bus structures, including a memory bus or memory controller, a peripheral bus or external bus, and / or a local bus using any of a variety of available bus architectures, including, but not limited to, Industry Standard Architecture (ISA), Micro Channel Architecture (MSA), Enhanced ISA (EISA), Intelligent Drive Electronics (IDE), VESA Local Bus (VLB), Peripheral Component Interconnect (PCI), Card Bus, Universal Serial Bus (USB), Advanced Graphics Port (AGP), Firewire (registered trademark) (IEEE 1394), Small Computer System Interface (SCSI).

[0049] The system memory 616 may also include volatile memory 620 and nonvolatile memory 622. A basic input / output system (BIOS), containing the basic routines for transferring information between elements within the computer 612, such as during start-up, is stored in the nonvolatile memory 622. The computer 612 may also include removable / non-removable, volatile / non-volatile computer storage media. FIG. 6 illustrates, for example, disk storage 624. The disk storage 624 may also include devices such as, but not limited to, a magnetic disk drive, a floppy disk drive, a tape drive, a Jaz drive, a Zip drive, an LS-100 drive, a flash memory card, or a memory stick. The disk storage 624 may also include storage media separately from or in combination with other storage media. A removable or non-removable interface, such as interface 626, is typically used to facilitate connection of the disk storage 624 to the system bus 618. FIG. 6 also illustrates software that acts as an intermediary between a user and the basic computer resources described in the suitable operating environment 600. Such software may also include, for example, an operating system 628. Operating system 628 , which can be stored on disk storage 624 , acts to control and allocate resources of the computer 612 .

[0050] System applications 630 take advantage of the management of resources by operating system 628 through, for example, program modules 632 and program data 634 stored either in system memory 616 or on disk storage 624. It should be understood that the present disclosure may be implemented with various operating systems or combinations of operating systems. Users enter commands or information into computer 612 through input devices 636. Input devices 636 include, but are not limited to, pointing devices such as a mouse, trackball, stylus, touchpad, keyboard, microphone, joystick, gamepad, satellite dish, scanner, television tuner card, digital camera, digital video camera, and webcam. These and other input devices connect to processing unit 614 through system bus 618 via interface ports 638. Interface ports 638 include, for example, serial ports, parallel ports, game ports, and universal serial bus (USB). Output devices 640 use some of the same types of ports as input devices 636. Thus, for example, a USB port may be used to provide input to computer 612 and to output information from computer 612 to output device 640. Output adapter 642 is provided to illustrate that there are some output devices 640, such as monitors, speakers, and printers, among other output devices 640, that require special adapters. Output adapters 642 include, by way of example and not limitation, video and sound cards that provide a means of connection between output device 640 and system bus 618. It should be noted that other devices and / or systems of devices provide both input and output capabilities, such as remote computer 644.

[0051] The computer 612 may operate in a networked environment using logical connections to one or more remote computers, such as a remote computer 644. The remote computer 644 may be a computer, a server, a router, a network PC, a workstation, a microprocessor-based device, a peer device or other common network node, etc., and may typically include many or all of the elements described relative to the computer 612. For purposes of simplicity, only a memory storage device 646 is shown with the remote computer 644. The remote computer 644 is logically connected to the computer 612 through a network interface 648 and, in turn, physically connected via a communication connection 650. The network interface 648 encompasses wired and / or wireless communication networks such as a local area network (LAN), a wide area network (WAN), a cellular network, etc. LAN technologies include Fiber Distributed Data Interface (FDDI), Copper Distributed Data Interface (CDDI), Ethernet, Token Ring, etc. WAN technologies include, but are not limited to, point-to-point links, circuit-switched networks such as Integrated Services Digital Networks (ISDN) and variations thereon, packet-switched networks, and Digital Subscriber Lines (DSL). Communications connection(s) 650 refer to the hardware / software used to connect network interface 648 to system bus 618. For clarity of illustration, communications connection(s) 650 are shown internal to computer 612, but may also be external to computer 612. The hardware / software for connecting to network interface 648 may also include, by way of example only, internal and external technologies such as ordinary telephone-grade modems, cable modems, modems including DSL modems, ISDN adapters, Ethernet cards, etc.

[0052] Referring now to FIG. 7 , an exemplary cloud computing environment 750 is illustrated. As shown, the cloud computing environment 750 includes one or more cloud computing nodes 710 with which local computing devices used by cloud consumers (e.g., a personal digital assistant (PDA) or cellular phone 754A, a desktop computer 754B, a laptop computer 754C, and / or an automobile computer system 754N, etc.) may communicate. Although not shown in FIG. 7 , the cloud computing node 710 may further include a quantum platform (e.g., a quantum computer, quantum hardware, quantum software, etc.) with which the local computing devices used by the cloud consumers can communicate. The nodes 710 may communicate with each other. The nodes may be physically or virtually grouped (not shown) in one or more networks, such as a private cloud, community cloud, public cloud, or hybrid cloud, or combinations thereof, as described above. This enables the cloud computing environment 750 to provide infrastructure, platform, and / or software as a service without the cloud consumer having to maintain resources on their local computing devices. It will be understood that the types of computing devices 754A-N shown in FIG. 7 are intended to be illustrative only, and that computing node 710 and cloud computing environment 750 can communicate with any type of computerized device via any type of network and / or network-addressable connection (e.g., using a web browser).

[0053] Referring now to Figure 8, a set of functional abstraction layers provided by cloud computing environment 750 (Figure 7) is shown. It should be understood in advance that the components, layers, and functions shown in Figure 8 are intended to be illustrative only, and embodiments of the present invention are not limited thereto. As shown, the following layers and corresponding functions are provided:

[0054] Hardware and software layer 860 includes hardware and software components. Examples of hardware components include mainframe 861; RISC (reduced instruction set computer) architecture-based servers 862; servers 863; blade servers 864; storage devices 865; and network and networking components 866. In some embodiments, software components include network application server software 867, quantum platform routing software 868, and / or quantum software (not shown in FIG. 8).

[0055] The virtualization layer 870 provides an abstraction layer at which examples of virtual entities can be provided: virtual servers 871; virtual storage 872; virtual networks, including virtual private networks 873; virtual applications and operating systems 874; and virtual clients 875.

[0056] In one example, management layer 880 may provide the functions described below. Resource provisioning 881 provides dynamic procurement of computing and other resources utilized to execute tasks within the cloud computing environment. Metering and pricing 882 provides cost tracking as resources are utilized within the cloud computing environment and billing or invoicing for the consumption of these resources. In one example, these resources may include application software licenses. Security provides identity verification for cloud consumers and tasks, as well as protection for data and other resources. User portal 883 provides consumers and system administrators with access to the cloud computing environment. Service level management 884 provides allocation and management of cloud computing resources so that required service levels are met. Service level agreement (SLA) planning and fulfillment 885 provides pre-configuration and procurement of cloud computing resources where future requirements are forecasted according to SLAs.

[0057] Workload tier 890 provides examples of functions for which a cloud computing environment may be utilized. Non-limiting examples of workloads and functions that may be provided from this tier include mapping and navigation 891; software development and lifecycle management 892; virtual classroom instruction delivery 893; data analytics processing 894; transaction processing 895; and quantum state preparation software 896.

[0058] The present invention may be a system, method, apparatus and / or computer program product at any possible level of technical detail of integration. The computer program product may include a computer-readable storage medium (or media) having computer-readable program instructions for causing a processor to perform aspects of the present invention. A computer-readable storage medium may be a tangible device that can hold and store instructions for use by an instruction execution device. The computer-readable storage medium may be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of computer-readable storage media may also include portable computer diskettes, hard disks, random access memories (RAMs), read-only memories (ROMs), erasable programmable read-only memories (EPROMs or flash memories), static random access memories (SRAMs), portable compact disk read-only memories (CD-ROMs), digital versatile disks (DVDs), memory sticks, floppy disks, mechanically encoded devices such as punch cards or ridge-in-groove structures with instructions recorded thereon, and any suitable combination of the foregoing. As used herein, a computer-readable storage medium should not be construed as a transitory signal per se, such as an electric wave or other freely propagating electromagnetic wave, an electromagnetic wave propagating through a waveguide or other transmission medium (e.g., a light pulse passing through a fiber optic cable), or an electrical signal transmitted over a wire.

[0059] The computer-readable program instructions described herein may be downloaded from a computer-readable storage medium to each computing / processing device or to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. The network may include copper transmission cables, optical fiber transmissions, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface within the computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in a computer-readable storage medium within the respective computing / processing device. The computer-readable program instructions for carrying out the operations of the present invention may be either assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, configuration data for integrated circuits, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk® or C++, and procedural programming languages ​​such as the “C” programming language or similar programming languages. The computer-readable program instructions may execute entirely on the user's computer, partially on the user's computer, as a stand-alone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be to an external computer (e.g., through the Internet using an Internet Service Provider).In some embodiments, to carry out aspects of the present invention, electronic circuitry including, for example, a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA), may execute computer-readable program instructions by utilizing state information of the computer-readable program instructions to personalize the electronic circuitry.

[0060] Aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that blocks of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions. These computer-readable program instructions may be provided to a processor of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus to generate a machine, whereby the instructions, executed by the processor of the computer or other programmable data processing apparatus, create means for implementing the function / acts specified in the block or blocks of the flowchart illustrations and / or block diagrams. These computer-readable program instructions may also be stored on a computer-readable storage medium that can instruct a computer, programmable data processing apparatus, and / or other device to function in a particular manner, whereby a computer-readable storage medium having instructions stored thereon includes an article of manufacture containing instructions that implement aspects of the function / acts specified in the block or blocks of the flowchart illustrations and / or block diagrams. Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational acts to be executed on the computer, other programmable apparatus, or other device to generate a computer-implemented process, whereby the instructions executing on the computer, other programmable apparatus, or other device implement the function / acts specified in a block or blocks of the flowcharts and / or block diagrams.

[0061] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, blocks in the flowcharts or block diagrams may represent modules, segments, or portions of instructions, including one or more executable instructions for implementing specified logical functions. In some alternative implementations, the functions shown in the blocks may occur out of the order shown in the figures. For example, two blocks shown in succession may in fact be executed substantially concurrently, or the blocks may possibly be executed in the reverse order, depending on the functionality involved. It may also be noted that blocks of the block diagrams and / or flowchart diagrams, and combinations of blocks in the block diagrams and / or flowchart diagrams, may be implemented by special-purpose hardware-based systems that perform the specified functions or operations or execute a combination of special-purpose hardware and computer instructions.

[0062] While the subject matter has been described above in the general context of computer-executable instructions for a computer program product executed on a computer and / or multiple computers, those skilled in the art will recognize that the present disclosure may also be implemented in combination with other program modules. Generally, program modules include routines, programs, components, data structures, etc. that perform particular tasks and / or implement particular abstract data types. Those skilled in the art will also appreciate that the computer-implemented methods of the present invention may be practiced with other computer system configurations, including single-processor or multiprocessor computer systems, minicomputing devices, mainframe computers, computers, handheld computing devices (e.g., PDAs, phones), microprocessor-based or programmable consumer or industrial electronic devices, etc. The illustrated aspects may also be practiced in distributed computing environments where tasks are performed by remote processing devices linked through a communications network. However, some, but not all, aspects of the present disclosure may be practiced on stand-alone computers. In a distributed computing environment, program modules may be located in both local and remote memory storage devices.

[0063] As used herein, terms such as “component,” “system,” “platform,” and “interface” may refer to and / or include computer-related entities or entities associated with an operating machine having one or more specific functions. The entities disclosed herein may be hardware, a combination of hardware and software, software, or software in execution. For example, a component may be, but is not limited to, a process running on a processor, a processor, an object, an executable, a thread of execution, a program, and / or a computer. By way of example, both an application running on a server and the server may be a component. One or more components may reside within a process and / or thread of execution, and a component may be localized on one computer and / or distributed between two or more computers. In another example, each component may execute from various computer-readable media having various data structures stored thereon. A component may communicate via local and / or remote processes, for example, according to signals comprising one or more data packets (e.g., data from one component interacting with another component in a local system, a distributed system, and / or with another system via signals over a network such as the Internet). As another example, a component may be a device having a particular function provided by mechanical parts operated by electrical or electronic circuitry operated by a software or firmware application executed by a processor. In such cases, the processor may be internal or external to the device and may execute at least a portion of the software or firmware application.As yet another example, a component may be a device that provides a particular functionality without mechanical parts through electronic components, which may include a processor or other means for executing software or firmware that provides at least part of the functionality of the electronic component. In one aspect, a component may emulate an electronic component via a virtual machine, for example, within a cloud computing system.

[0064] Additionally, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or." That is, unless otherwise specified or clear from context, "X uses A or B" is intended to mean either of the natural inclusive permutations. That is, if X uses A, X uses B, or X uses both A and B, "X uses A or B" is satisfied under any of the foregoing examples. Also, the articles "a" and "an" as used in this specification and the accompanying drawings should generally be construed to mean "one or more" unless otherwise specified or clear from context that the singular form is referred to. As used herein, the terms "example" and / or "exemplary" are utilized to mean serving as an example, instance, or illustration. For the avoidance of doubt, the subject matter disclosed herein is not limited to such examples. Additionally, any aspect or design described herein as "example" and / or "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects or designs, and is not intended to exclude equivalent exemplary structures and techniques known to those skilled in the art.

[0065] The term "processor" as used herein may refer to virtually any computing processing unit or device, including, but not limited to, a single-core processor; a single processor with software multithreading execution capabilities; a multi-core processor; a multi-core processor with software multithreading execution capabilities; a multi-core processor with hardware multithreading technology; a parallel platform; and a parallel platform with distributed shared memory. Additionally, a processor may refer to an integrated circuit, an application-specific integrated circuit (ASIC), a digital signal processor (DSP), a field programmable gate array (FPGA), a programmable logic controller (PLC), a complex programmable logic device (CPLD), discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. Furthermore, a processor may utilize nanoscale architectures, such as, but not limited to, molecular and quantum dot-based transistors, switches, and gates, to optimize space utilization or improve performance of user equipment. A processor may also be implemented as a combination of computing processing units. In this disclosure, terms such as "store," "storage," "data store," "data storage," "database," and substantially any other information storage component associated with the operation and functionality of a component are utilized to refer to a "memory" or a "memory component" entity embodied in a component that includes memory. It should be understood that memory and / or memory components described herein may be either volatile memory or non-volatile memory, or may include both volatile and non-volatile memory.By way of example, and not limitation, non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable ROM (EEPROM), flash memory, or non-volatile random access memory (RAM) (e.g., ferroelectric RAM (FeRAM)). Volatile memory may include RAM, which may act as external cache memory, for example. By way of example, and not limitation, RAM is available in many forms, including synchronous RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), SyncLink DRAM (SLDRAM), direct Rambus RAM (DRRAM), direct Rambus dynamic RAM (DRDRAM), and Rambus dynamic RAM (RDRAM). Additionally, the disclosed memory components of systems or computer-implemented methods herein are intended to include, without being limited to, these and any other suitable types of memory.

[0066] The foregoing includes merely exemplary systems and computer-implemented methods. Of course, for purposes of describing this disclosure, it is not possible to describe every conceivable combination of components or computer-implemented methods, but one of ordinary skill in the art may recognize that many further combinations and permutations of the present disclosure are possible. Furthermore, to the extent that terms such as "including," "having," and "comprising" are used in the detailed description, claims, appendices, and drawings, such terms are intended to be inclusive in the same manner as the term "comprising" is interpreted when used as a transitional phrase in the claims.

[0067] The description of various embodiments is presented for illustrative purposes and is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations may be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles of the embodiments, practical applications or technical improvements found in the market, or to enable those skilled in the art to understand the embodiments disclosed herein.

Claims

1. a first chip layer having a first chip layer front surface and a first chip layer back surface; a qubit chip layer having a qubit chip layer front surface operably coupled to the first chip layer front surface using a set of bump bonds, and a qubit chip layer back surface; a set of through silicon vias (TSVs) connected to at least one of the first chip layer backside or the qubit chip layer backside; and a cap wafer metal bonded to at least one of the qubit chip layer backside or the first chip layer backside; Equipped with a device, wherein a set of qubits in the qubit chip layer are connected by a plurality of in-plane buses and a plurality of buried layer buses, wherein the plurality of in-plane buses are on a surface of the qubit chip layer and the plurality of buried layer buses are in a buried layer of the qubit chip layer.

2. The device of claim 1 , wherein the at least one of the qubit chip layer backside or the first chip layer backside is operably coupled to a filter.

3. The device of claim 1 or 2, wherein the at least one of the qubit chip layer backside or the first chip layer backside is operably coupled to a qubit feed line.

4. The device of claim 1 , wherein the at least one of the qubit chip layer backside or the first chip layer backside is operably coupled to a resonator.

5. 5. The device of claim 1, wherein the at least one of the qubit chip layer backside or the first chip layer backside is operably coupled to a coupler.

6. 6. The device of claim 1, wherein the cap wafer metal has at least one cavity with a metal coating inside the cavity, the metal coating being the same or a different metal than the bonding metal, and the metal coating contacts the bonding metal to form a ground.

7. 7. The device of claim 6, wherein the interconnect material comprises at least one of InSn, PbSn, SnAgCu, InBiSn, InSnAg, SnAg, or InAg.

8. The device of claim 1 , wherein the plurality of qubits in the qubit chip layer are on an exposed surface.

9. forming a first chip layer having a first chip layer front surface and a first chip layer back surface; forming a set of bump bonds on the first chip layer front surface; forming a qubit chip layer having a qubit chip layer front surface operably coupled to the first chip layer front surface using the set of bump bonds, and a qubit chip layer back surface; forming a set of through silicon vias (TSVs) connected to at least one of the first chip layer backside or the qubit chip layer backside; forming a cap wafer metal bonded to at least one of the qubit chip layer backside or the first chip layer backside; and connecting a set of qubit chips in the qubit chip layer with a plurality of in-plane buses and a plurality of buried layer buses, wherein the plurality of in-plane buses are on a surface of the qubit chip layer and the plurality of buried layer buses are in a buried layer of the qubit chip layer; A method comprising:

10. 10. The method of claim 9, further comprising coupling the at least one of the qubit chip layer backside or the first chip layer backside to a filter.

11. 11. The method of claim 9 or 10, further comprising coupling the qubit chip layer backside or the first chip layer backside to a qubit feed line.

12. 12. The method of claim 9, further comprising coupling the qubit chip layer backside or the first chip layer backside to a resonator.

13. 13. The method of claim 9, further comprising coupling the qubit chip layer backside or the first chip layer backside to a coupler.

14. 14. The method of claim 9, further comprising forming the cap wafer metal having a plurality of cavities using a metal coating inside the cavities, the metal coating being the same or a different metal as the bonding metal, the metal coating contacting the bonding metal to form a ground.

15. 15. The method of any one of claims 9 to 14, further comprising forming a plurality of qubits on the exposed surface.

16. a first chip layer having a first chip layer front surface and a first chip layer back surface; a qubit chip layer having a qubit chip layer front surface operably coupled to the first chip layer front surface using a set of bump bonds, and a qubit chip layer back surface; a set of through silicon vias (TSVs) connected to at least one of the first chip layer backside or the qubit chip layer backside; and a cap wafer metal bonded to at least one of the qubit chip layer backside or the first chip layer backside, wherein the cap wafer metal has at least one cavity containing interconnect material; Equipped with the at least one of the qubit chip layer backside or the first chip layer backside is operably coupled to at least one of a filter, a qubit feed line, a resonator, or a coupler; and a set of qubits in the qubit chip layer on an exposed surface, the set of qubits connected by a plurality of in-plane buses and a plurality of buried layer buses, the plurality of in-plane buses being on a surface of the qubit chip layer and the plurality of buried layer buses being in a buried layer of the qubit chip layer; device.

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