Apparatus and method for reference read technique for threshold selection device memory - Patent Application 20070122997

Abstract

A device, system and method are provided that includes a memory cell that stores data using threshold voltage differences of value selection devices. The apparatus includes a memory array having a first memory cell including a first two-terminal element having a first threshold voltage and a second threshold voltage, a second memory cell including a second two-terminal element having a third threshold voltage and a fourth threshold voltage, and a control circuit coupled to the memory array, the control circuit causes the first two-terminal element to have a first threshold voltage and the second two-terminal element to have a third threshold voltage or a fourth threshold voltage, applies a third voltage signal that increases at a first ramp rate to the first memory cell and the second memory cell, determines when the first memory cell has switched from a non-conductive state to a conductive state, and reads the second memory cell using the third voltage signal after the first memory cell has switched from a non-conductive state to a conductive state.

Description

[Technical Field]

[0001] Memories are widely used in various electronic devices, such as mobile phones, digital cameras, personal digital assistants, medical electronic devices, mobile computing devices, non-mobile computing devices, and data servers. Memory can be non-volatile or volatile. Non-volatile memory allows information to be stored and retained even when the non-volatile memory is not connected to a power source (e.g., a battery).

[0002] One example of a non-volatile memory is a memory cell that includes a resistively switching memory element (e.g., a magnetic tunnel junction) coupled in series with a threshold selection device (e.g., an ovonic threshold switch including a chalcogenide material or other similar threshold selection device).

[0003] An alternative non-volatile memory technology omits the resistive switching memory element and uses a memory cell that includes a threshold selection device as both the memory element and the selection device, for example, the threshold selection device can be programmed to two different resistances (e.g., a high resistance state and a low resistance state) to store information.

[0004] Also, new memory technologies use memory cells that include threshold select devices as both memory elements and select devices, but use threshold voltage differences instead of resistance differences across the threshold select devices to store memory states.

[0005] For example, a memory cell including a threshold selection device, such as an ovonic threshold switch or other similar threshold selection device, can be programmed to two different threshold voltages (e.g., a high threshold voltage and a low threshold voltage) for storing information.

[0006] For simplicity, the remaining description will use the term "threshold selection memory cell" to describe a memory cell that includes a threshold selection device as both a memory element and a selection device, and that uses the threshold voltage difference of the threshold selection device to store data.

[0007] Although memory systems including threshold-selected memory cells show promise, many design and process challenges remain. [Brief explanation of the drawings]

[0008] [Figure 1A] 1 illustrates various embodiments of a memory system. [Figure 1B] 1 illustrates various embodiments of a memory system. [Figure 1C] 1 illustrates various embodiments of a memory system. [Figure 1D] 1 illustrates various embodiments of a memory system. [Figure 1E] 1 illustrates various embodiments of a memory system. [Figure 1F] 1 illustrates various embodiments of a memory system. [Figure 1G] 1 illustrates various embodiments of a memory system. [Figure 1H] 1 illustrates various embodiments of a memory system. [Figure 2A] 1 illustrates an embodiment of a portion of a three-dimensional memory array. [Figure 2B] 2B illustrates an embodiment of a memory cell of the three-dimensional memory array of FIG. 2A. [Figure 2C] 2C illustrates an exemplary current-voltage characteristic of the threshold selection device of FIG. 2B. [Figure 3A] 1 illustrates an embodiment of a cross-point memory array. [Figure 3B] 1 illustrates an embodiment of a cross-point memory array. [Figure 4A] 1 is a simplified diagram of threshold voltage versus time for a threshold selection device, as well as read and write voltages applied across a threshold selection memory cell. [Figure 4B] 10 shows threshold-select memory cell voltage versus time for the boundary read technique. [Figure 4C] FIG. 1 illustrates exemplary set and reset threshold voltage distributions and read voltage distributions for a population of threshold-selected memory cells. [Figure 4D]1 shows the original set threshold voltage distribution, the drifted set threshold voltage distribution, and the drift-free reset threshold voltage distribution of a threshold-selected memory cell. [Figure 5A] 1 is a flow diagram of an embodiment of a threshold voltage reference reading technique in accordance with the present technology. [Figure 5B] 10A-10C illustrate an exemplary reference memory cell set threshold voltage distribution, an exemplary data memory cell set threshold voltage distribution, and an exemplary data memory cell reset threshold voltage distribution. [Figure 5C] 5C illustrates the exemplary threshold voltage distribution of FIG. 5B with two different ramp read voltages. [Figure 6A] 1 is a simplified diagram of an embodiment of a threshold voltage reference reading system. [Figure 6B] 6B illustrates exemplary signals in the exemplary threshold voltage reference reading system of FIG. 6A. [Figure 6C] 1 is a simplified diagram of another embodiment of a threshold voltage reference reading system. [Figure 6D1] 6D are simplified diagrams of threshold voltage distributions and read voltage distributions for fast and slow read processes, respectively, of the exemplary threshold voltage reference read system of FIG. 6C. [Figure 6D2] 6D are simplified diagrams of threshold voltage distributions and read voltage distributions for fast and slow read processes, respectively, of the exemplary threshold voltage reference read system of FIG. 6C. [Figure 7] 1 is a flow diagram of an embodiment of a threshold voltage reference reading technique in accordance with the present technology. DETAILED DESCRIPTION OF THE INVENTION

[0009] A fundamental material property of threshold selectable devices, such as Ovonic threshold switches, is that the threshold voltage of such devices drifts over time after being written. As a result, the memory read window of threshold selectable memory cells is limited by this drift characteristic. As a result, highly reliable and low latency memory devices using threshold selectable memory cells are very challenging.

[0010] Techniques are described for reading threshold-selected memory cells by using a reference memory cell to track and mitigate threshold voltage drift in a corresponding data memory cell. In an embodiment, the reference memory cell and the corresponding data memory cell each include a threshold-selected device having a first threshold voltage and a second threshold voltage.

[0011] In an embodiment, a predetermined value is written to a reference memory cell each time data is written to the corresponding data memory cell. After the write operation, the threshold voltages of the reference memory cell and the corresponding data memory cell drift over time. In an embodiment, the drifted threshold voltage of the reference memory cell is detected and used to offset the drift component of the corresponding data memory cell.

[0012] 1A illustrates one embodiment of a memory system 100 and a host 102. Memory system 100 may include a non-volatile storage system that interfaces with host 102 (e.g., a mobile computing device or a server). In some cases, memory system 100 may be embedded within host 102. By way of example, memory system 100 may be a memory card, a solid-state drive (SSD) such as a high-density MLC SSD (e.g., 2 bits / cell or 3 bits / cell) or a high-performance SLC SSD, or a hybrid HDD / SSD drive.

[0013] As shown, memory system 100 includes a memory chip controller 104 and a memory chip 106. Memory chip 106 may include volatile and / or non-volatile memory. Although a single memory chip is shown, memory system 100 may include one or more memory chips. Memory chip controller 104 may receive data and commands from host 102 and provide memory chip data to host 102.

[0014] The memory chip controller 104 may include one or more of a control circuit, a state machine, a page register, an SRAM, a decoder, a sense amplifier, a read / write circuit, and / or a controller, or any combination thereof, to control the operation of the memory chip 106. One or more of the control circuit, the state machine, the page register, the SRAM, the decoder, the sense amplifier, the read / write circuit, and / or the controller for controlling the operation of the memory chip may be referred to as a managing circuit or control circuit. The managing circuit or control circuit may facilitate one or more memory array operations, including a forming operation, an erasing operation, a programming operation, or a reading operation.

[0015] In some embodiments, management circuitry or control circuitry (or portions of management circuitry or control circuitry) for facilitating one or more memory array operations may be integrated within memory chip 106. Memory chip controller 104 and memory chip 106 may be located on a single integrated circuit or may be located on a single die. In other embodiments, memory chip controller 104 and memory chip 106 may be located on different integrated circuits. In some cases, memory chip controller 104 and memory chip 106 may be integrated onto a system board, circuit logic board, or PCB.

[0016] Memory chip 106 includes memory core control circuitry 108 and memory core 110. Memory core control circuitry 108 controls the selection of memory blocks (or arrays) within memory core 110, controls the generation of voltage references for biasing particular memory arrays into read or write states, and may include logic for generating row and column addresses.

[0017] Memory core 110 may include one or more two-dimensional arrays of memory cells and / or one or more three-dimensional arrays of memory cells. In embodiments, memory core may include re-writeable memory cells, one-time programmable memory cells, and / or multiple-time programmable memory cells, or any combination thereof.

[0018] In some embodiments, memory core control circuitry 108 and memory core 110 may be located on a single integrated circuit. In other embodiments, memory core control circuitry 108 (or a portion of memory core control circuitry 108) and memory core 110 may be located on different integrated circuits.

[0019] A memory operation may be initiated when host 102 sends a command to memory chip controller 104 indicating that host 102 wishes to read data from or write data to memory system 100. In the case of a write (or programming) operation, host 102 may send both a write command and the data to be written to memory chip controller 104.

[0020] Memory chip controller 104 can buffer data to be written and can generate error correcting code (ECC) data corresponding to the written data. The ECC data, which allows for detection and / or correction of data errors that occur during transmission or storage, can be written to memory core 110 or stored in non-volatile memory within memory chip controller 104. In an embodiment, circuitry within memory chip controller 104 generates the ECC data and corrects data errors.

[0021] The memory chip controller 104 may control the operation of the memory chip 106. In one example, before issuing a write operation to the memory chip 106, the memory chip controller 104 may check a status register to verify that the memory chip 106 can accept the data to be written.

[0022] In another example, before issuing a read operation to the memory chip 106, the memory chip controller 104 may pre-read overhead information associated with the data to be read. The overhead information may include ECC data associated with the data to be read or a redirection pointer to a new memory location within the memory chip 106 from which to read the requested data.

[0023] When the memory chip controller 104 initiates a read or write operation, the memory core control circuitry 108 can generate the appropriate bias voltages and / or currents for the word lines and bit lines in the memory core 110, as well as generate the appropriate memory block, row, and column addresses.

[0024] 1B shows an embodiment of memory core control circuitry 108. In an embodiment, memory core control circuitry 108 includes an address decoder 120, a voltage generator 122 for selected control lines, and a voltage generator 124 for unselected control lines. The control lines may include word lines, bit lines, or a combination of word lines and bit lines. The selected control lines may include selected word lines or selected bit lines, which are used to place memory cells in a selected state. The unselected control lines may include unselected word lines or unselected bit lines, which are used to place memory cells in an unselected state.

[0025] The selected control line voltage generator (or voltage regulator) 122 may include one or more voltage generators for generating selected control line voltages. The unselected control line voltage generator 124 may include one or more voltage generators for generating unselected control line voltages. The address decoder 120 may generate memory block addresses, as well as row and column addresses for particular memory blocks.

[0026] 1C-1F illustrate one embodiment of a memory core organization including a memory core 110 having multiple memory bays, each memory bay having multiple memory blocks. Although a memory core organization is disclosed in which the memory bays contain memory blocks, and the memory blocks contain groups of memory cells, other organizations or groupings can also be used with the techniques described herein.

[0027] 1C illustrates an embodiment of memory core 110 of FIG. 1A. As shown, memory core 110 includes memory bay 130 and memory bay 132. In some embodiments, the number of memory buses per memory core may vary for different implementations. For example, a memory core may include only a single memory bay or multiple memory bays (e.g., 16 memory bays, 256 memory bays, etc.).

[0028] FIG. 1D illustrates one embodiment of memory bay 130 of FIG. 1C. As shown, memory bay 130 includes memory blocks 140-144 and read / write circuitry 150. In some embodiments, the number of memory blocks per memory bay may vary for different implementations. For example, a memory bay may include one or more memory blocks (e.g., 32 memory blocks per memory bay).

[0029] Read / write circuitry 150 includes circuitry for reading and writing memory cells in memory blocks 140-144. As shown, read / write circuitry 150 may be shared across multiple memory blocks in a memory bay. This reduces chip area because a single group of read / write circuits 150 can be used to support multiple memory blocks. However, in some embodiments, only a single memory block may be electrically coupled to read / write circuitry 150 at a particular time to avoid signal contention.

[0030] In some embodiments, read / write circuit 150 may be used to write one or more pages of data to memory blocks 140-144 (or to a subset of memory blocks). Memory cells within memory blocks 140-144 may allow for direct overwrite of a page (i.e., data representing a page or portion of a page may be written to memory blocks 140-144 without having to perform an erase or reset operation on the memory cells before writing the data).

[0031] 1E illustrates one embodiment of memory block 140 of FIG. 1D. As shown, memory block 140 includes memory array 160, row decoder 162, and column decoder 164. Memory array 160 may include a contiguous group of memory cells with contiguous word lines and bit lines. Memory array 160 may include one or more layers of memory cells and may include a two-dimensional memory array and / or a three-dimensional memory array.

[0032] Row decoder 162 decodes row addresses and, when appropriate (e.g., when reading or writing memory cells in memory array 160), selects particular word lines in memory array 160. Column decoder 164 decodes column addresses and selects particular groups of bit lines in memory array 160 to be electrically coupled to read / write circuits, such as read / write circuit 150 of FIG. 1D . In an embodiment, the number of word lines is 4K per memory layer, the number of bit lines is 1K per memory layer, and the number of memory layers is four, providing memory array 160 with 16M memory cells. Other numbers of word lines per layer, bit lines per layer, and number of layers may also be used.

[0033] FIG. 1F illustrates an embodiment of memory bay 170. Memory bay 170 is an example of an alternative implementation of memory bay 130 of FIG. 1D. In some embodiments, the row decoders, column decoders, and read / write circuits may be divided or shared between memory arrays. As shown, row decoder 172 is shared between memory arrays 174 and 176 because row decoder 172 controls the word lines in both memory arrays 174 and 176 (i.e., the word lines driven by row decoder 172 are shared).

[0034] Row decoders 178 and 172 may be divided so that even word lines in memory array 174 are driven by row decoder 178 and odd word lines in memory array 174 are driven by row decoder 172. Column decoders 180 and 182 may be divided so that even bit lines in memory array 174 are controlled by column decoder 182 and odd bit lines in memory array 174 are driven by column decoder 180.

[0035] Selected bit lines controlled by column decoder 180 may be electrically coupled to read / write circuits 184. Selected bit lines controlled by column decoder 182 may be electrically coupled to read / write circuits 186. Splitting the read / write circuits into read / write circuits 184 and 186 when the column decoder is split may allow for a more efficient layout of the memory bay.

[0036] Row decoders 188 and 172 may be divided so that the even word lines in memory array 176 are driven by row decoder 188 and the odd word lines in memory array 176 are driven by row decoder 172. Column decoders 190 and 192 may be divided so that the even bit lines in memory array 176 are controlled by column decoder 192 and the odd bit lines in memory array 176 are driven by column decoder 190.

[0037] Selected bit lines controlled by column decoder 190 may be electrically coupled to read / write circuits 184. Selected bit lines controlled by column decoder 192 may be electrically coupled to read / write circuits 186. Splitting the read / write circuits into read / write circuits 184 and 186 when the column decoder is split may allow for a more efficient layout of the memory bay.

[0038] Figure 1G shows an embodiment of a schematic diagram (including word lines and bit lines) corresponding to memory bay 170 of Figure 1F. As shown, word lines WL1, WL3, and WL5 are shared between memory arrays 174 and 176 and are controlled by row decoder 172 of Figure 1F. Word lines WL0, WL2, WL4, and WL6 are driven from the left side of memory array 174 and are controlled by row decoder 178 of Figure 1F. Word lines WL14, WL16, WL18, and WL20 are driven from the right side of memory array 176 and are controlled by row decoder 188 of Figure 1F.

[0039] Bit lines BL0, BL2, BL4, and BL6 are driven from the bottom of memory array 174 and are controlled by column decoder 182 of Figure 1F. Bit lines BL1, BL3, and BL5 are driven from the top of memory array 174 and are controlled by column decoder 180 of Figure 1F. Bit lines BL7, BL9, BL11, and BL13 are driven from the bottom of memory array 176 and are controlled by column decoder 192 of Figure 1F. Bit lines BL8, BL10, and BL12 are driven from the top of memory array 176 and are controlled by column decoder 190 of Figure 1F.

[0040] In an embodiment, memory arrays 174 and 176 may include memory layers oriented in a plane horizontal to the support substrate. In another embodiment, memory arrays 174 and 176 may include memory layers oriented in a plane vertical to the support substrate (i.e., the vertical plane is substantially perpendicular to the support substrate). In this case, the bit lines of the memory arrays may include substantially vertical bit lines.

[0041] 1H shows one embodiment of a schematic diagram (including word and bit lines) corresponding to a memory bay configuration in which word and bit lines are shared across memory blocks and both row and column decoders are split. Sharing word and / or bit lines helps reduce layout area because a single row and / or column decoder can be used to support two memory arrays.

[0042] As shown, word lines WL1, WL3, and WL5 are shared between memory arrays 200 and 202. Bit lines BL1, BL3, and BL5 are shared between memory arrays 200 and 204. Word lines WL8, WL10, and WL12 are shared between memory arrays 204 and 206. Bit lines BL8, BL10, and BL12 are shared between memory arrays 202 and 206.

[0043] The row decoder is divided so that word lines WL0, WL2, WL4, and WL6 are driven from the left side of memory array 200, and word lines WL1, WL3, and WL5 are driven from the right side of memory array 200. Similarly, word lines WL7, WL9, WL11, and WL13 are driven from the left side of memory array 204, and word lines WL8, WL10, and WL12 are driven from the right side of memory array 204.

[0044] The column decoder is split so that bit lines BL0, BL2, BL4, and BL6 are driven from the bottom of memory array 200, and bit lines BL1, BL3, and BL5 are driven from the top of memory array 200. Similarly, bit lines BL7, BL9, BL11, and BL13 are driven from the bottom of memory array 202, and bit lines BL8, BL10, and BL12 are driven from the top of memory array 202. Splitting the row and / or column decoders also helps to relax layout constraints (e.g., the column decoder pitch can be relaxed by a factor of two because the split column decoder only needs to drive every other bit line instead of every bit line).

[0045] FIG. 2A illustrates an embodiment of a portion of a monolithic three-dimensional memory array 210 including a first memory level 212 and a second memory level 214 disposed above the first memory level 212. Memory array 210 is an example of an implementation of memory array 160 of FIG. 1E. Word lines 216, 218 are disposed in a first direction, and bit lines 220 are disposed in a second direction orthogonal to the first direction. As illustrated, the top conductors of first memory level 212 can be used as bottom conductors of second memory level 214. In memory arrays with additional layers of memory cells, there are corresponding additional layers of bit lines and word lines.

[0046] The memory array 210 includes memory cells 222. In embodiments, the memory cells 222 may include re-writeable memory cells, one-time programmable memory cells, and multiple-time programmable memory cells. In embodiments, each of the memory cells 222 is vertically oriented. The memory cells 222 may include non-volatile memory cells or volatile memory cells. For the first memory level 212, a first portion of the memory cells 222 are between and connected to the word lines 216 and the bit lines 220. For the second memory level 214, a second portion of the memory cells 222 are between and connected to the word lines 218 and the bit lines 220.

[0047] In an embodiment, each memory cell 222 includes a threshold selection device, and each memory cell 222 represents one bit of data. Figure 2B is a simplified schematic diagram of memory cell 222a, which is one exemplary implementation of memory cell 222 of Figure 2A. In an embodiment, memory cell 222a includes a selection element S coupled between first terminal T1 and second terminal T2. x In an embodiment, memory cells 222a are vertically oriented.

[0048] In an embodiment, the memory cell 222a is a threshold selection memory cell, and the threshold selection device (selection element S x) as both a memory element and a selection device, and stores data using the threshold voltage difference of the threshold selection device. x 2B operates as a threshold-selection memory cell that can be configured to have either of two different threshold voltages (e.g., a first threshold voltage and a second threshold voltage) for storing information. For simplicity, the remaining description will refer to memory cell 222a of FIG. 2B as threshold-selection memory cell 222a.

[0049] In the embodiment, the selection element S x The select element S comprises a selection material that provides bidirectional current flow when the current or voltage exceeds a threshold. x will be referred to as the "threshold selection device S" in the remaining description. x Therefore, the threshold selection device S x is a bidirectional device that allows bidirectional current flow when the current or voltage exceeds a threshold value and prevents current flow when the current or voltage is below the threshold value.

[0050] In an embodiment, a threshold selection device S x The ovonic threshold switch material includes an ovonic threshold switch material that allows current flow only when a voltage difference across it exceeds a threshold voltage value. In embodiments, the ovonic threshold switch material can include a chalcogenide material. The chalcogenide material can include one or more of a GeSeAs alloy, a GeSeAsTe alloy, a GeTeAs alloy, a GeSeTe alloy, a GeSe alloy, a SeAs alloy, an AsTe alloy, a GeTe alloy, a SiTe alloy, a SiAsTe alloy, and a SiAsSe alloy. The chalcogenide material can be undoped or doped with at least one of N, O, C, P, Ge, As, Te, Se, In, or Si.

[0051] However, the threshold selection device S x(It may also include one or more conductive and / or barrier layers, such as tungsten, tungsten nitride, tantalum, tantalum nitride, carbon-nitrogen layers, etc.) The conductive and / or barrier layers may be disposed above and / or below the Ovonic threshold switch material.

[0052] FIG. 2C shows the threshold selection device S x 1 shows an exemplary current-voltage (IV) characteristic of each threshold selection device S x is initially in a high resistance (off) state. x To operate as a threshold switch, a threshold selection device S x However, an initial formation operation may be necessary to operate in the current range where switching can occur.

[0053] For example, the forming operations are each performed at a forming voltage V FORM one or more voltage pulses having a magnitude equal to or greater than a threshold selection device S x Following the forming operation, a threshold selection device S x can be switched on and off and can be used as either a unipolar or bipolar threshold selector. Thus, the threshold selector S x may be referred to as a bipolar threshold selector.

[0054] In the exemplary I-V characteristic of FIG. 2C, for a positive applied voltage, the threshold selection device S x is the voltage across the device that exceeds the first threshold voltage V TP The threshold selector S remains in the high resistance state (HRS) (e.g., off) until it meets or exceeds (i.e., is more positive) x switches to a low resistance state (LRS) (e.g., ON). x is the voltage across the device that is equal to the first holding voltage, V HP It remains on until it drops below x will be turned off.

[0055] For negative applied voltages, the threshold selection device S xis the voltage across the device that exceeds a second threshold voltage, V TN The HRS remains (e.g., off) until the threshold selector S x switches to LRS (e.g., ON). Threshold selection device S x is the voltage across the device that is equal to a second holding voltage, V HN It remains turned on until the threshold voltage increases to or exceeds (i.e., is less negative than) x will be turned off.

[0056] For simplicity, the remainder of the description will be focused on the threshold selection device S x Those skilled in the art will appreciate that the techniques described below are well suited to the threshold selection device S x It will be appreciated that this also applies to negative threshold voltages.

[0057] 3A-3B are simplified schematic diagrams of an exemplary cross-point memory array 300 including a first memory level 300a and a second memory level 300b disposed above the first memory level 300a. The cross-point memory array 300 is an example of an implementation of the memory array 160 of FIG. 1E. The cross-point memory array 300 may include two or more memory levels.

[0058] The cross-point memory array 300 includes word lines WL1a, WL2a, WL3a, WL1b, WL2b, and WL3b and bit lines BL1, BL2, and BL3. The first memory level 300a includes memory cells 302 coupled to word lines WL1a, WL2a, WL3a and bit lines BL1, BL2, and BL3. 11a , 302 12a , ..., 302 33a a second memory level 300b includes memory cells 302 coupled to word lines WL1b, WL2b, WL3b and bit lines BL1, BL2, and BL3; 11b , 302 12b , ..., 302 33b In an embodiment, memory cell 30211a , 302 12a , ..., 302 33a Each of the memory cells 302 is vertically oriented. 11b , 302 12b , ..., 302 33b Each of the is vertically oriented.

[0059] First memory level 300a is an example of an implementation of first memory level 212 of monolithic three dimensional memory array 210 of FIG. 2A, and second memory level 300b is an example of an implementation of second memory level 214 of monolithic three dimensional memory array 210 of FIG. 2A. In an embodiment, memory cells 302 11a , 302 12a , ..., 302 33a , 302 11b , 302 12b , ..., 302 33b Each of the threshold select memory cells 222a in FIG. 2B.

[0060] Those skilled in the art will appreciate that the cross-point memory array 300 may have more or less than six word lines, more or less than three bit lines, and more or less than eighteen memory cells 302. 11a , 302 12a , ..., 302 33a , 302 11b , 302 12b , ..., 302 33b It will be appreciated that in some embodiments, cross point memory array 300 may include 1000 x 1000 memory cells, although other array sizes may be used.

[0061] Each memory cell 302 11a , 302 12a , ..., 302 33a , 302 11b , 302 12b , ..., 302 33b is coupled to one of the word lines and one of the bit lines, and a corresponding select element S 11a , S12a, ..., S 33a , S11b , S 12b , ..., S 33b In an embodiment, each memory cell 302 11a , 302 12a , ..., 302 33a , 302 11b , 302 12b , ..., 302 33b is the threshold selection memory cell 222a, and the selection element S 11a , S 12a , S 33a , S 11b , S 12b , ..., S 33b can each be programmed to two different threshold voltages (eg, a high threshold voltage and a low threshold voltage) to store information.

[0062] Each memory cell 302 11a , 302 12a , ..., 302 33a Each memory cell 302 has a first terminal coupled to one of bit lines BL1, BL2, and BL3 and a second terminal coupled to one of word lines WL1a, WL2a, and WL3a. 11b , 302 12b , ..., 302 33b has a first terminal coupled to one of bit lines BL1, BL2, and BL3 and a second terminal coupled to one of word lines WL1b, WL2b, and WL3b. 13a is the selection element S 13a , and includes a first terminal connected to bit line BL3 and a second terminal connected to word line WL1a.

[0063] Similarly, memory cell 302 22b is the selection element S 22b , a first terminal connected to bit line BL2 and a second terminal connected to word line WL2b. 33a is the selection element S 33a , and includes a first terminal connected to bit line BL3 and a second terminal connected to word line WL3a.

[0064] Referring again to FIG. 2B, the threshold selection memory cell 222a includes a threshold selection device S x (e.g., a threshold selection device including an Ovonic threshold switch material), and a threshold selection device S x The threshold voltage of the threshold selection device S x The polarity of the applied voltage previously used to write to the

[0065] In an embodiment, a threshold selection device S x is the first (e.g., set) threshold voltage (referred to herein as the “set threshold voltage V TS "), and a second (e.g., reset) threshold voltage (referred to herein as the "reset threshold voltage V TR Therefore, two threshold voltages may be used to represent stored data, and the "memory" has a reset threshold voltage V TR and set threshold voltage V TS It is the difference between

[0066] In an embodiment, a threshold selection device S x Set threshold voltage V TS (e.g., 3V) represents a first memory state (e.g., set or "0") of the threshold selection memory cell 222a, and the threshold selection device S x Reset threshold voltage V TR (eg, 4V) represents a second memory state (eg, reset or "1") for the threshold selection memory cell 222a.

[0067] FIG. 4A shows the threshold selection device S x 1 depicts a simplified diagram of threshold voltage versus time for a threshold selection device S x 1 also depicts the read and write voltages applied across the threshold selection memory cell 222a, including the threshold selection device S. For simplicity, the following description assumes that at time t0, the threshold selection memory cell 222a is in the second memory state (reset) and the threshold selection device S x is the reset threshold voltage V TR(4V) In an embodiment, the sense amplifier determines the state of threshold select memory cell 222a after allowing sufficient time for stabilization following the initial current spike.

[0068] At time t1, the read voltage V RD (e.g., 3.5V) is applied across the threshold select memory cell 222a. RD is the reset threshold voltage V TR (4V), and therefore the threshold selection device S x does not switch and conduct current, indicating that the threshold selection memory cell 222a is in the second memory state (reset).

[0069] At time t2, a positive write voltage +V W (e.g., +4.5V) is applied. In an embodiment, a positive write voltage +V W is the read voltage V RD , and thus the threshold selection device S x The threshold voltage of the set threshold voltage V TS (3V).

[0070] At time t3, the read voltage V RD (3.5V) is applied across the threshold select memory cell 222a. RD is the set threshold voltage V TS (3V), and therefore the threshold selection device S x and conduction current indicates that the threshold selected memory cell 222a is in the first memory state (set).

[0071] At time t4, a negative write voltage -V W (e.g., −4.5V) is applied to the threshold selection memory cell 222a. In an embodiment, a negative write voltage −V W is the read voltage V RD and the threshold voltage threshold selection device S x is the reset threshold voltage V TR (4V).

[0072] At time t5, the read voltage V RD (3.5V) is applied across the threshold select memory cell 222a. RD is the reset threshold voltage V TR (4V), and therefore the threshold selection device S x does not switch and conduct current, indicating that the threshold selection memory cell 222a is in the second memory state (reset).

[0073] Therefore, as described above and shown in FIG. 4A, the threshold selection device S of the threshold selection memory cell 222a x have different threshold voltages based on the polarity of the voltage applied when writing to the memory cell. This exemplary read technique is sometimes referred to as a "boundary read," and Figure 4B shows the voltage versus time of a threshold-selected memory cell 222a for such a boundary read.

[0074] The examples of FIGS. 4A and 4B show the reset threshold voltage V TR and set threshold voltage V TS The threshold selection device S x A memory array (such as memory array 160 of FIG. 1E) typically includes a plurality of threshold selection devices, each of which has a corresponding threshold selection device S x 2. The memory cell 222 includes a number of threshold selection memory cells 222a, including:

[0075] Ideally, a threshold selection device S x is the same reset threshold voltage V TR and set threshold voltage V TS However, in practice, the threshold selection device S x The population of sets the threshold voltage V TS The first distribution of values ​​and the reset threshold voltage V TR has a second distribution of values.

[0076] Therefore, the first selection device S x1 has a first (set) threshold voltage and a second (reset) threshold voltage, and a second selection device S x2has a third (set) threshold voltage and a fourth (reset) threshold voltage. The set threshold voltage V TS The first distribution of values ​​includes a first (set) threshold voltage and a third (set) threshold voltage, and a reset threshold voltage V TR The second distribution of values ​​includes a second (reset) threshold voltage and a fourth (reset) threshold voltage.

[0077] FIG. 4C shows the threshold selection device S x For a population of threshold-selected memory cells 222a including TS Distribution, exemplary reset threshold voltage V TR distribution, and an example read voltage V RD FIG.

[0078] In an embodiment, each distribution has a lower tail and an upper tail. TS The upper tail of the distribution and the reset threshold voltage V TR The difference between the lower tail of the distribution is referred to herein as the read window margin (RWM) and the read voltage V RD (Read voltage V RD distribution) are ideally chosen within the reading window margin.

[0079] In the embodiment, the read voltage V RD is applied across the threshold selection memory cell 222a in the first memory state (set), while the threshold selection device S x does not switch and conduct current, or the read voltage V RD is applied across the threshold selection memory cell 222a in the second memory state (reset), while the threshold selection device S x If V switches and conducts current, a read error occurs. The required read reliability set by the read bit error rate (BER) specification determines the read window margin requirement for a memory array of threshold-selected memory cells 222a.

[0080] Threshold selection device S comprising ovonic threshold switch material xOne phenomenon of threshold selection devices such as TS and reset threshold voltage V TR The threshold voltage V TS and reset threshold voltage V TR may differ in terms of

[0081] For boundary reads, set threshold voltage V TS The drift is maximum and the reset threshold voltage V TR Assuming zero drift, the read window margin must be reduced because it is difficult to track how much the threshold voltage of the threshold-selected memory cell 222a may have drifted. The maximum drift can be limited by "refreshing" the threshold-selected memory cell 222a at defined time intervals determined based on performance impact. A refresh involves a read followed by a write of the threshold-selected memory cell 222a.

[0082] Taking threshold voltage drift into account significantly reduces the read window margin. Figure 4D shows the effect of threshold voltage drift on the read window available for reading at the target product read BER. In particular, this figure shows the effect of threshold voltage drift on the read window available for reading at the target product read BER. TS Distribution of drifted set threshold voltage V after time T TS Distribution and drift-free reset threshold voltage V TR The distribution is shown.

[0083] 4C and 4D, the shrinking read window margin as a result of threshold voltage drift makes border reading very difficult. One approach to addressing threshold voltage drift is to have a large nominal read window margin, low drift, and a very narrow V RD The goal is to find materials with distributed circuit designs, but these techniques are expensive and may still be insufficient to achieve the required product read BER.

[0084] A technique is described for reading a threshold-selected memory cell (such as threshold-selected memory cell 222a in FIG. 2B) using a "reference memory cell" to track and mitigate threshold voltage drift of the "data memory cell." In an embodiment, the data memory cell and the reference memory cell are each threshold-selected memory cells 222a that have the same physical structure and are substantially identical within the limits of semiconductor fabrication technology.

[0085] As used herein, a data memory cell is defined as a memory cell having a reset threshold voltage V TR (V TRD ) and set threshold voltage V TS (V TSD ) with a threshold selection device S x , which are threshold-selection memory cells (such as threshold-selection memory cell 222a in FIG. 2B) used to store data bits.

[0086] As used herein, a reference memory cell has a set threshold voltage V TS (V TSR ) and reset threshold voltage V TR (V TRR ) with a threshold selection device S x In an embodiment, the reference memory cell is used to store a reference bit (e.g., either a "0" (set) or a "1" (reset)).

[0087] In an embodiment, one reference memory cell is used to track the threshold voltage drift of N corresponding data memory cells, where N=1, 2, 3, .... In an embodiment, N=128, although other values ​​of N may be used. For simplicity, the following description will assume N=128.

[0088] In an embodiment, each time data is written to a data memory cell, a predetermined value (e.g., 0 or 1) is written to the corresponding reference memory cell. For simplicity, the following description assumes that the predetermined value is 0 (i.e., each time data is written to a data memory cell, the corresponding reference memory cell is written to a set memory state).

[0089] In an embodiment, the set threshold voltage V TSR The reference memory cell having the set threshold voltage V TSD and reset threshold voltage V TRD In an embodiment, the reference memory cell set threshold voltage V TSR The drift rate of the data memory cell set threshold voltage V TSD and the data memory cell reset threshold voltage V TRD is assumed to be substantially the same as the drift rate of

[0090] In an embodiment, the reference memory cell set threshold voltage V TSR is detected, and when reading the data memory cell, the data memory cell set threshold voltage V TSD and the data memory cell reset threshold voltage V TRD is used to offset the drift component of the threshold voltage reference read technique. In such an embodiment, the cost and power impact of a single reference memory cell for every N data memory cells is minimal. Such a technique is referred to herein as a threshold voltage reference read technique.

[0091] 5A is a flow diagram of an embodiment of a threshold voltage reference read technique in accordance with the present technology. In an embodiment, a threshold voltage reference read process 500 is used to read N data memory cells 222a, such as the threshold-selected memory cells of FIG. 2B. In an exemplary embodiment, process 500 is performed by one or more of the memory chip controller 104 and the memory core control circuitry 106 of FIG. 1A.

[0092] In an embodiment, each time data is written to N data memory cells, the corresponding reference memory cells are written to a first memory state (e.g., 0 or set). Thus, in step 502, a write signal writes a "0" to the reference memory cells, and a programming signal writes data to the N data memory cells. For simplicity, the remaining description of process 500 will refer to "data memory cells."

[0093] A determination is made whether a data memory cell should be read in step 504. If not, process 500 loops back to step 504 and continues to wait for a request to read a data memory cell to be received.

[0094] In an embodiment, the read request may be received any time after the data memory cells and the reference memory cells are written in step 502. During that time interval, the reference memory cells set threshold voltage V TSR Distribution of data memory cell set threshold voltage V TSD distribution, and data memory cell reset threshold voltage V TRD The distribution continues to drift.

[0095] In an embodiment, the reference memory cell set threshold voltage V TSR The drift rate of the distribution is the data memory cell set threshold voltage V TSD Distribution and data memory cell reset threshold voltage V TRD It is assumed to be substantially the same as the drift rate of the distribution.

[0096] Eventually, at some point after the data memory cell has been written in step 502, a request to read data from the data memory cell is received. Thus, in step 504, a determination is made that the data memory cell should be read, and process 500 proceeds to step 506, where a ramp read voltage V RD is applied to the word lines of the reference and data memory cells.

[0097] In step 508, it is determined whether the reference memory cell has been triggered. In particular, the ramp read voltage V RD is the reference memory cell set threshold voltage V TSR When the threshold value of the cell is satisfied or exceeded, the cell threshold selection device S x triggers and conducts current. Thus, step 508 sets the reference memory cell to a set threshold voltage V TSR The lamp reading voltage V is equal to RD Determine the value of

[0098] As mentioned above, the reference memory cell set threshold voltage V TSR The distribution is the data memory cell set threshold voltage V TSD Distribution and data memory cell reset threshold voltage V TRD The threshold voltages V of the reference memory cells determined in step 508 are assumed to drift at approximately the same rate as the threshold voltages V of the reference memory cells. TSR The value of is the data memory cell set threshold voltage V TSD Distribution and data memory cell reset threshold voltage V TRD It is assumed to be a measure of the amount of drift in the distribution.

[0099] If, in step 508, it is determined that the reference memory cell has not yet been triggered, the process returns to step 506 and the ramp read voltage V RD However, if a determination is made in step 508 that the reference memory cell has been triggered, then in step 510, the process 500 continues with a delay time ΔT D Just wait.

[0100] In particular, FIG. 5B illustrates an exemplary reference memory cell set threshold voltage V TSR , as well as the distribution of the exemplary data memory cell set threshold voltage V at the moment the reference memory cell is triggered. TSD Distribution and data memory cell reset threshold voltage V TRD 5B essentially shows the drifted reference memory cell set threshold voltage V TSR Distribution and drift of data memory cell set threshold voltage VTSD Distribution and reset threshold voltage V of data memory cells TRD It is a "snapshot" of the distribution.

[0101] the second threshold voltage V of the reference memory cell TSR The distribution is such that there are more data memory cells than reference memory cells, so the threshold voltage V TSD The set threshold voltage V of any particular reference memory cell is drawn smaller than the distribution of TSR is the reference memory cell set threshold voltage V TSR The exact location of any particular reference memory cell is unknown, although it will be somewhere within the distribution.

[0102] Therefore, in Figure 5B, the read voltage V RD In the example shown, the ramp read voltage V RD is the time t L The reference memory cell set threshold voltage V TSR crosses the lower tail of the distribution and at time t U The data memory cell set threshold voltage V TSD Intersects the upper tail of the distribution. In an embodiment, the data sample delay time ΔT D is the time difference t U -t L is set equal to

[0103] That is, the first predetermined delay time ΔT D is the lamp reading voltage V RD is the reference memory cell set threshold voltage V TSR The data memory cell set threshold voltage V of the corresponding reference memory cell that has a set threshold voltage in the lower tail of the distribution TSD The first predetermined delay time ΔT is selected to allow the upper tail of the distribution to be exceeded. D It will be appreciated that other criteria may be used to specify .

[0104] Referring again to FIG. 5A, the first predetermined delay time ΔT DAfter waiting for the read voltage V RD The lamp is stopped (for example, at value V RDF ), read voltage V RD V RDF is fixed at

[0105] In step 514, the N data memory cells are read at a read voltage V RD =V RDF Without being bound by any particular theory, the exemplary threshold voltage reference read process 500 of FIG. 5A is performed by reading the reset threshold voltage V of the data memory cell used to store the data bit. TRD and the data memory cell threshold voltage set V TSD A threshold selection device S x It is believed that this can mitigate the effect of threshold voltage drift on the read window margin of data memory cells (threshold selection memory cells 222a in FIG. 2B) each including

[0106] A simple example can be used to illustrate an exemplary operation of the threshold voltage reference read technique 500 of FIG. 5A. In this example, a first memory cell (reference memory cell) includes a first two-terminal device (e.g., a first threshold selection device S) having a first threshold voltage (set) and a second threshold voltage (reset). x) The second memory cell (data memory cell) includes a second two-terminal element (e.g., a second threshold selection device S) having a third threshold voltage (set) and a fourth threshold voltage (reset). x ) is included.

[0107] In an embodiment, a first voltage signal (e.g., a write signal) is applied to a first memory cell such that a first two-terminal element has a first threshold voltage (set), and a second voltage signal (e.g., a programming signal) is applied to a second memory cell such that a second two-terminal element has either a third threshold voltage (set) or a fourth threshold voltage (reset) (step 502).

[0108] A third voltage signal (e.g., a read voltage V RD) is applied to the first memory cell and the second memory cell, the third voltage signal increases at the first ramp rate (step 506).

[0109] A determination is made that the first memory cell switches from a non-conductive state to a conductive state when the third voltage signal meets or exceeds the first threshold voltage (step 508).

[0110] After the first memory cell switches from a non-conductive state to a conductive state, a first predetermined delay time (e.g., a first predetermined delay time ΔT D ), the second memory cell is read using a third voltage signal (steps 510 and 514).

[0111] In the exemplary threshold voltage reference read process 500 of FIG. 5A, the same ramp read voltage V RD is applied to the word lines of both the reference memory cells and the data memory cells. In another embodiment, a first ramp read voltage V RD1 is applied to the word line of the reference memory cell, and a second ramp read voltage V RD2 is applied to the word lines of the data memory cells.

[0112] For example, FIG. 5C illustrates a first ramp read voltage V applied to the word line of a reference memory cell. RD1 and a second ramp read voltage V applied to the word line of the data memory cell. RD2 5B having a first ramp read voltage V RD1 and the second lamp reading voltage V RD2 has the same ramp rate but a second ramp reading voltage V RD2 is the voltage offset V OFF Only the first lamp reading voltage V RD1 Offset from (lower than).

[0113] In the example of FIG. 5C, the set threshold voltage V of a particular reference memory cell TSR is the set threshold voltage V shown in FIG. TSRAs a result, the same lamp reading voltage V RD1 is applied to the word lines of both the reference memory cell and the data memory cell, and the data memory cell receives a delay time ΔT D After time t U The read may disturb some data memory cells, and the reset threshold voltage V TRD The reset threshold voltage V in the distribution of TRD (shown as a circle with a dashed line in FIG. 5C).

[0114] Instead, the first lamp read voltage V RD1 A second lamp reading voltage V offset (lower) from RD2 is applied to the data memory cell, and the data memory cell receives a delay time ΔT D After time t U When the data memory cell is read, the read does not disturb the data memory cell and the reset threshold voltage V TRD The reset threshold voltage V in the distribution of TRD (shown as solid circles in FIG. 5C). Without wishing to be bound by any particular theory, this technique is based on the idea that the minimum time ΔT D It is believed that it may be useful if the time is shorter than (due to the finite time required to feed back the reference bit information to the data bits).

[0115] 6A is a simplified diagram of an embodiment of a threshold voltage reference read system 600a that may be used to implement a threshold voltage reference read process, such as threshold voltage reference read process 500 of FIG. 5A. In an embodiment, threshold voltage reference read system 600a may be implemented on example memory chip 106 of FIG. 1A.

[0116] In an embodiment, the threshold voltage reference reading system 600a includes N data modules 6020, 6021, 6022, 602 N-1 , and the corresponding reference module 602 SData modules 6020, 6021, 6022, and 602 N-1 and the corresponding reference module 602 S are coupled to a corresponding word line decoder WL DEC and a corresponding bit line decoder BL DEC.

[0117] Data modules 6020, 6021, 6022, and 602 N-1 and the corresponding reference module 602 S includes an array of threshold-selected memory cells 222a, where the particular threshold-selected memory cell being accessed is selected using a word line address WL ADD and a bit line address BL ADD, respectively (referred to herein as the "selected threshold-selected memory cell").

[0118] Data modules 6020, 6021, 6022, and 602 N-1 and the corresponding reference module 602 S are connected to the sense amplifier circuits 6040, 6041, 6042, 6044 through the corresponding bit line decoders BL DEC. N-1 and 604 S Sense amplifier circuits 6040, 6041, 6042, 604 N-1 Using data modules 6020, 6021, 6022, 602 N-1 and determines the memory state of the selected data memory cells, and provides data outputs D0, D1, D2, and D N-1 are generated, respectively.

[0119] In an embodiment, the sense amplifier circuit 604 S is a first reference output signal C coupled to a first input terminal of the voltage ramp control circuit 606. S In an embodiment, the first reference output signal C S is the voltage ramp control circuit 606 generates a word line voltage (WL voltage) reference module 602 S the reference memory cell set threshold voltage V of the selected reference memory cell TSR has a first value (e.g., LOW) when the WL voltage is less than the reference module 602S the reference memory cell set threshold voltage V of the selected reference memory cell TSR When it is equal to or greater than 1, it has a second value (eg, HIGH).

[0120] In the embodiment, the first reference output signal C S are configured to control a voltage ramp control circuit 606, which is configured to generate a ramp WL voltage applied to the word line of the selected threshold selected memory cell. In an embodiment, the WL voltage is generated by the data modules 6020, 6021, 6022, 6023. N-1 and the corresponding reference module 602 S The selected threshold voltage is used to drive the selected memory cell.

[0121] 6B illustrates exemplary signals in the exemplary threshold voltage reference reading system 600a of FIG. 6A. In an embodiment, the WL voltage ramps are generated by the reference data modules 6020, 6021, 6022, 6023, 6024, 6025, 6026, 6027, 6028, 6029, 6030, 6031, 6032, 6033, 6034, 6035, 6036, 6037, 6038, 6039, 6040, 6041, 6042, 6043, 6044, 6045, 6046, 6047, 6048, 6049, 6050, 6051, 6052, 6053, 6054, 6 N-1 and the corresponding reference module 602 as shown in FIG. 6B S In particular, FIG. 6B shows the data memory cell set threshold voltage V TSD The distribution boundary of the data memory cell reset threshold voltage V TRD and the lower tail of the distribution.

[0122] In an embodiment, the read window margin is the reset threshold voltage V TRD The lower tail of the distribution and the data memory cell set threshold voltage V TSD In addition, FIG. 6B shows the difference between the threshold voltages of the reference cell set, V TSR The distribution range of

[0123] In the exemplary threshold voltage reference reading system 600a of FIG. 6A, N data bits are divided into N data modules 6020, 6021, 6022, 6023, 6024, 6025, 6026, 6027, 6028, 6029, 6030, 6031, 6032, 6033, 6034, 6035, 6 N-1 , each of which has an array of data memory cells from which one is selected for each access.S provides the corresponding reference bit for each access.

[0124] In an embodiment, access is performed by N data modules 6020, 6021, 6022, 602 N-1 , and the criteria module 602 S 6A, a controller (e.g., memory chip controller 104 of FIG. 1A) may select and read one data memory cell from each of N data modules 6020, 6021, 6022, 6023, 6024, 6025, 6026, 6027, 6028, 6029, 6030, 6031, 6032, 6033, 6034, 6035, 6036, 6037, 6038, 6039, 6040, 6041, 6042, 6043, 6044, 6045, 6046, 6047, 6048, 6049, 6050, 6051, 6052, 6053, 6054, 6055 N-1 The bank coordinates activity across a number of nodes, hereafter collectively referred to as the "bank."

[0125] Furthermore, any one set of N data bits and corresponding reference bits is referred to herein as a “line.” In embodiments, any line is assumed to be first written before it can be read.

[0126] In embodiments, a write operation to a line updates the data memory cells based on user data, but always sets the corresponding reference memory cells to a set memory state. Without wishing to be bound by any particular theory, it is believed that the write operation resets the threshold voltage drift of all bits in the line (e.g., no drift).

[0127] In an embodiment, the read operation begins with a fast ramping WL voltage for the data memory cells and the corresponding reference memory cells, which is shown as "Fast Ramp" in FIG. 6B. In an embodiment, a second predetermined delay time ΔT SR After this, the WL voltage transitions to a slower ramp, shown as "slow ramp" in FIG. 6B. In an embodiment, a second predetermined delay time ΔT SR is the fast ramp to the reference memory cell set threshold voltage V TSR is the estimated time to cross the lower tail of in Figure 6B (designated as "initial reference cell").

[0128] In an embodiment, the WL voltage transitions from a fast ramp to a slow ramp to ensure that any data memory cell reaches the data memory cell reset threshold voltage V TRD It prevents hitting the lower tail of the distribution and disturbing those data memory cells.

[0129] In an embodiment, when the reference data cell triggers (e.g., when the WL voltage ramp exceeds the reference memory cell set threshold voltage V TSR , the reference data cell sends a signal (shown as "Reference Trigger Signal" in FIG. 6B) to the controller. In an embodiment, after the controller receives the Ref trigger signal, the controller first waits a predetermined delay time ΔT D (Step 510 of FIG. 5A) and then stop the WL voltage ramp and sense the data memory cells.

[0130] In the embodiment, the first predetermined delay time ΔT D is selected so that the read of the data memory cell is properly positioned within the read window to achieve the target BER. In an embodiment, this delay is determined by the fast and slow ramp rates of the WL voltage. In an embodiment, the controller stops the WL voltage ramp and senses the data memory cell to determine the data memory cell reset threshold voltage V TRD Prevents continuous ramping of the WL voltage beyond the lower tail of the distribution.

[0131] Without wishing to be bound by any particular theory, the exemplary threshold voltage reference read system 600a of FIG. 6A may be configured to read a reset threshold voltage V TRD and the data memory cell threshold voltage set V TSD A threshold selection device S x It is believed that the effect of threshold voltage drift on the read window margin of data memory cells (such as threshold-selected memory cell 222a of FIG. 2B) each including the threshold voltage drift can be reduced.

[0132] The exemplary threshold voltage reference reading system 600a includes N data modules 6020, 6021, 6022, 602 N-1 a single corresponding reference module 602 S 6C is an embodiment of an alternative exemplary threshold voltage reference reading system 600b that may be used to implement the threshold voltage reference reading process. In an embodiment, the threshold voltage reference reading system 600b is similar to the threshold voltage reference reading system 600a of FIG. 6A, but includes an additional corresponding reference module 602. F (Fast Reference Module 602 F ) and additional sense amplifier circuitry 604 F The threshold voltage reference reading system 600b also includes a reference module 602. S (The slow reference module 602 S (also called

[0133] In an embodiment, the sense amplifier circuit 604 F is a second reference output signal C coupled to a second input terminal of the voltage ramp control circuit 606. F In an embodiment, the second reference output signal C F The WL voltage is F the reference memory cell set threshold voltage V of the selected reference memory cell TSR has a first value (e.g., LOW) when the WL voltage is less than F the reference memory cell set threshold voltage V of the selected reference memory cell TSR When it is equal to or greater than 1, it has a second value (eg, HIGH).

[0134] In an embodiment, the slow reference module 602 S A first reference output signal C generated from S are referred to herein as "slow read reference bits" and are read by the fast reference module 602 F A second reference output signal C generated from F is referred to herein as the "fast read reference bit." In an embodiment, the first reference output signal CS and the second reference output signal C F are data modules 6020, 6021, 6022, and 602 N-1 , and the reference module 602 S and 602 F The memory cell 600 is configured to control a voltage ramp control circuit 606 configured to generate a ramped WL voltage applied to the word line of a selected threshold selected memory cell in the memory cell 600 .

[0135] In an embodiment, a write operation to a line updates the data memory cells based on user data, but the slow reference module 602 S and high-speed reference module 602 F always sets the corresponding reference memory cells of the threshold voltage reference read system 600a to the set memory state. In contrast to the read operation of the threshold voltage reference read system 600a, in an embodiment, the threshold voltage reference read system 600b includes two different read operations, referred to herein as a "fast read" and a "slow read." In an embodiment, the slow read is invoked only if the fast read has an uncorrectable error (e.g., after applying ECC). In an embodiment, if the error rate of the fast read after ECC is below a predetermined threshold (e.g., 1% or some other value), only the fast read is performed.

[0136] In embodiments, high-speed reads can have a much higher BER relative to the desired BER specification, while low-speed reads must meet the desired BER specification. In embodiments, the result of a higher BER for high-speed reads is that the read window margin is increased enough to allow for more aggressive sample timing for the data bits. However, in embodiments, high-speed reads are performed such that the read disturb error rate does not increase. That is, to maintain a specified BER target, the data memory cell reset threshold voltage V TRD Maintain the necessary distance from the data level.

[0137] In an embodiment, when a read is performed, the fast reference module 602F Only the high-speed read reference memory cells in the data modules 6020, 6021, 6022, 602 N-1 and the slow reference module 602 S The slow read reference memory cells in are not triggered.

[0138] In an embodiment, data modules 6020, 6021, 6022, 602 N-1 The data bits from the fast read utilize a slow ramp rate that is much faster than the slow read slow ramp rate (e.g., the slow ramp shown in FIG. 6B). Additionally, in an embodiment, the fast read utilizes a first predetermined delay time ΔT that is shorter than that used in the slow read. D Without wishing to be bound by any particular theory, it is believed that this allows for low latency, high speed reads, but at a high BER.

[0139] In an embodiment, during a slow read, the fast reference module 602 F the high-speed read reference memory cell and the low-speed reference module 602 S Both the slow-read reference memory cells in the line are triggered. The fast-read reference memory cells can no longer be used to cancel the drift of any set bits that did not trigger during the previous fast read. This is because triggering the fast-read reference memory cell during the fast read resets the drift to 0. Because the slow-read reference memory cell was not triggered during the fast read, the slow-read reference memory cell continues to drift along with the remaining untriggered set bits in the line. Therefore, the slow-read reference memory cell can be used as a way to cancel the drift component for reading these data bits.

[0140] However, to accurately read these remaining data bits, in an embodiment, the slow read slow ramp rate is set to the read voltage V RDcan be accurately positioned to achieve a specified read BER. Without being bound by theory, it is believed that a slow read has a latency that is approximately twice the latency of a fast read. However, because slow reads occur infrequently (e.g., less than 1% of the time), the impact of a longer slow read latency on an average read operation is small.

[0141] 6D1-6D2 show threshold voltages and read voltages V for the high-speed read process and the low-speed read process, respectively, of the exemplary threshold voltage reference read system 600b of FIG. 6C. RD A simplified diagram of the distribution. The two diagrams show the tradeoff between speed and BER.

[0142] Without wishing to be bound by any particular theory, it is believed that the threshold voltage reference read technique described above may provide reliable, high speed read operations for OTS memory cells and consume less power than existing boundary read techniques.

[0143] FIG. 7 illustrates a flow diagram of an embodiment of a method 700 of a threshold voltage reference reading technique in accordance with the present technique.

[0144] In step 702, a reference memory cell is written to a first memory state and data is written to a plurality of data memory cells, each of the reference memory cell and the data memory cell comprising an ovonic threshold switch, the ovonic threshold switch comprising a first threshold voltage distribution and a second threshold voltage distribution.

[0145] In step 704, a ramp voltage is applied to the word lines coupled to the reference memory cells and the data memory cells.

[0146] In step 706, it is determined that the reference memory cell has switched from a non-conductive state to a conductive state.

[0147] In step 708, the ramp voltage is terminated a first predetermined delay time after the reference memory cell switches from a non-conductive state to a conductive state.

[0148] In step 710, a plurality of data memory cells are read with the ramp voltage stopped.

[0149] One embodiment of the disclosed technology includes an apparatus including a memory array having a first memory cell including a first two-terminal element having a first threshold voltage and a second threshold voltage, and a second memory cell including a second two-terminal element having a third threshold voltage and a fourth threshold voltage, and a control circuit coupled to the memory array, wherein the control circuit is configured to apply a first voltage signal to the first memory cell causing the first two-terminal element to have the first threshold voltage, apply a second voltage signal to the second memory cell causing the second two-terminal element to have either the third threshold voltage or the fourth threshold voltage, apply a third voltage signal to the first memory cell and the second memory cell, the third voltage signal increasing at a first ramp rate, determine that the first memory cell has switched from a non-conductive state to a conductive state, and read the second memory cell using the third voltage signal a first predetermined delay time after the first memory cell has switched from the non-conductive state to the conductive state.

[0150] One embodiment of the disclosed technology includes a system including a plurality of data modules, each data module including a plurality of data memory cells, each data memory cell including an ovonic threshold switch, the ovonic threshold switch including a first threshold voltage distribution and a second threshold voltage distribution; a first reference module including a first plurality of first reference memory cells, each first reference memory cell including an ovonic threshold switch including the first reference threshold voltage distribution; a plurality of word lines coupled to the plurality of data memory cells and the first plurality of first reference memory cells; a voltage ramp control circuit coupled to the plurality of data modules and the first reference module and configured to generate a ramp output voltage; and a control circuit coupled to the plurality of data modules, the first reference module, and the voltage ramp control circuit. The control circuit is configured to couple the ramp output voltage to a selected data memory cell from each of the plurality of data modules and to a selected first reference memory cell from the first reference module, determine that the selected first reference memory cell has switched from a non-conductive state to a conductive state, and initially read each of the selected data memory cells using the ramp output voltage a first predetermined delay time after the selected first reference memory cell has switched from the non-conductive state to the conductive state.

[0151] One embodiment of the disclosed technology includes a method including: writing a reference memory cell to a first memory state; writing data to a plurality of data memory cells, the reference memory cell and the data memory cell each including an ovonic threshold switch, the ovonic threshold switch including a first threshold voltage distribution and a second threshold voltage distribution; applying a ramp voltage to a word line coupled to the reference memory cell and the data memory cell; determining that the reference memory cell has switched from a non-conductive state to a conductive state; stopping the ramp voltage a first predetermined delay time after the reference memory cell has switched from the non-conductive state to the conductive state; and reading the plurality of data memory cells with the stopped ramp voltage.

[0152] For purposes of this document, a first layer may be over or above a second layer if zero, one or more intervening layers are between the first and second layers.

[0153] It should be noted that for the purposes of this document, the dimensions of the various features shown in the drawings have not necessarily been drawn to scale.

[0154] For purposes of this specification, references to "an embodiment," "one embodiment," "some embodiments," or "another embodiment" in the specification may be used to describe different embodiments and may not necessarily refer to the same embodiment.

[0155] For purposes of this specification, a connection may be a direct connection or an indirect connection (e.g., through another part). In some cases, when an element is referred to as being connected or coupled to another element, the element may be directly connected to the other element, or indirectly connected to the other element through intervening elements. When an element is referred to as being directly connected to another element, there are no intervening elements between the element and the other element.

[0156] For purposes of this specification, the term "based on" may be read as "based at least in part on."

[0157] For purposes of this specification, the use of numerical terms such as "first," "second," and "third" objects without additional context does not imply an ordering of the objects, but instead may be used for identification purposes to distinguish between different objects.

[0158] For purposes of this specification, the term "set" of objects may refer to one or more "sets" of objects.

[0159] Although the subject matter has been described in language specific to structural features and / or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing the claims.

Claims

1. 1. An apparatus comprising: a memory array comprising a first memory cell having a first two-terminal element with a first threshold voltage and a second threshold voltage, and a second memory cell having a second two-terminal element with a third threshold voltage and a fourth threshold voltage; a control circuit coupled to the memory array, the control circuit comprising: applying a first voltage signal to the first memory cell to cause the first two-terminal element to have the first threshold voltage; applying a second voltage signal to the second memory cell such that the second two-terminal element has either the third threshold voltage or the fourth threshold voltage; applying a third voltage signal to the first memory cell and the second memory cell, the third voltage signal increasing at a first ramp rate; determining that the first memory cell switches from a non-conductive state to a conductive state; and a control circuit configured to read the second memory cell using the third voltage signal at a first predetermined delay time after the first memory cell switches from the non-conductive state to the conductive state.

2. 2. The apparatus of claim 1, wherein the control circuitry is further configured to change the third voltage signal to a second ramp rate lower than the first ramp rate when the first memory cell switches from the non-conductive state to the conductive state.

3. 2. The apparatus of claim 1, wherein the control circuitry is further configured to stop increasing the third voltage signal at the first predetermined delay time after the first memory cell switches from the non-conductive state to the conductive state.

4. the first memory cell is configured to be read using a read voltage having a first polarity; 2. The apparatus of claim 1, wherein the first two-terminal element has the first threshold voltage when the first memory cell was previously written with a write signal including the first polarity, and the first two-terminal element has the second threshold voltage when the first memory cell was previously written with a write signal including a second polarity opposite the first polarity.

5. the second memory cell is configured to be read using a read voltage comprising the first polarity; 5. The apparatus of claim 4, wherein the second two-terminal element has the third threshold voltage when the second memory cell was previously written with a write signal including the first polarity, and the second two-terminal element has the fourth threshold voltage when the second memory cell was previously written with a write signal including the second polarity.

6. the first threshold voltage and the third threshold voltage comprise a first threshold voltage distribution; The apparatus of claim 1 , wherein the second threshold voltage and the fourth threshold voltage comprise a second threshold voltage distribution.

7. the first threshold voltage is lower than the second threshold voltage; The apparatus of claim 1 , wherein the third threshold voltage is lower than the fourth threshold voltage.

8. after the first memory cell is written, the first threshold voltage and the second threshold voltage drift; 2. The device of claim 1, wherein the third threshold voltage and the fourth threshold voltage drift after the second memory cell is written.

9. 9. The apparatus of claim 8, wherein the first threshold voltage, the second threshold voltage, the third threshold voltage, and the fourth threshold voltage drift at substantially the same rate.

10. 10. The device of claim 1, wherein the first two-terminal element and the second two-terminal element each comprise a selected material that provides bidirectional current flow when the current or voltage exceeds a threshold value.

11. The device of claim 1 , wherein the first two-terminal element and the second two-terminal element each comprise a chalcogenide material.

12. 2. The device of claim 1, wherein the first two-terminal element and the second two-terminal element each comprise one or more of a GeSeAs alloy, a GeSeAsTe alloy, a GeTeAs alloy, a GeSeTe alloy, a GeSe alloy, a SeAs alloy, an AsTe alloy, a GeTe alloy, a SiTe alloy, a SiAsTe alloy, and a SiAsSe alloy.

13. 10. The apparatus of claim 1, wherein the first two-terminal element and the second two-terminal element each comprise an Ovonic threshold switch.

14. 1. A system comprising: a plurality of data modules, each data module including a plurality of data memory cells, each data memory cell including an ovonic threshold switch, the ovonic threshold switch including a first threshold voltage distribution and a second threshold voltage distribution; a first reference module including a first plurality of first reference memory cells, each first reference memory cell including an ovonic threshold switch having a first reference threshold voltage distribution; a plurality of word lines coupled to the plurality of data memory cells and the first plurality of first reference memory cells; a voltage ramp control circuit coupled to the plurality of data modules and the first reference module, the voltage ramp control circuit configured to generate a ramp output voltage; a control circuit coupled to the plurality of data modules, the first reference module, and the voltage ramp control circuit, the control circuit comprising: coupling the ramp output voltage to a selected data memory cell from each of the plurality of data modules and to a selected first reference memory cell from the first reference module; determining that the selected first reference memory cell switches from a non-conductive state to a conductive state; and control circuitry configured to first read each of the selected data memory cells using the ramp output voltage at a first predetermined delay time after the selected first reference memory cell switches from the non-conductive state to the conductive state.

15. a second reference module including a second plurality of second reference memory cells, each second reference memory cell including an ovonic threshold switch including a second reference threshold voltage distribution; The control circuit coupling the ramp output voltage to a selected second reference memory cell from the second reference module; determining that the selected first reference memory cell switches from a non-conductive state to a conductive state; 15. The system of claim 14, further configured to second read each of the selected data memory cells using the ramp output voltage a first predetermined delay time after the selected second reference memory cell switches from the non-conductive state to the conductive state.

16. The system of claim 15 , wherein the second reading occurs before the first reading.

17. 16. The system of claim 15, wherein the first reading comprises a first error rate and the second reading comprises a second error rate that is higher than the first error rate.

18. 15. The system of claim 14, wherein each ovonic threshold switch comprises a chalcogenide material.

19. 15. The system of claim 14, wherein each Ovonic threshold switch comprises one or more of a GeSeAs alloy, a GeSeAsTe alloy, a GeTeAs alloy, a GeSeTe alloy, a GeSe alloy, a SeAs alloy, an AsTe alloy, a GeTe alloy, a SiTe alloy, a SiAsTe alloy, and a SiAsSe alloy.

20. 1. A method comprising: writing reference memory cells to a first memory state and writing data to a plurality of data memory cells, the reference memory cells and the data memory cells each comprising an ovonic threshold switch having a first threshold voltage distribution and a second threshold voltage distribution; applying a ramp voltage to a word line coupled to the reference memory cell and the data memory cell; determining that the reference memory cell has switched from a non-conductive state to a conductive state; Terminating the ramp voltage a first predetermined delay time after the reference memory cell switches from the non-conductive state to the conductive state; and reading the plurality of data memory cells with the stopped ramp voltage.

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