Semiconductor element drive circuit

Abstract

Drive circuits (50a-50d) respectively comprise control units (4a-4d) that individually control one of four semiconductor elements (5a-5d) connected in series to form a power conversion circuit unit for one phase of a three-level power converter and apply a gate voltage to the semiconductor elements (5a-5d) to drive the semiconductor elements (5a-5d). The drive circuits (50a-50d) detect an arm short circuit in the power conversion circuit unit on the basis of the main terminal voltages of the semiconductor elements (5a-5d). Each of the control units (4a, 4d) that controls the drive of the upper potential-side outer element (5a) or the low potential-side outer element (5d) out of the four semiconductor elements (5a-5d) applies a gate voltage lower than a prescribed voltage to the semiconductor element (5a or 5d) when the semiconductor element (5a or 5d) is turned on.

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor element drive circuit and drive device that drive four series-connected semiconductor elements that constitute a power conversion circuit section for one phase of a three-level power converter. [Background technology]

[0002] In a power conversion circuit section for one phase in a three-level power converter, there is a risk of an arm short circuit occurring. An arm short circuit is a phenomenon in which three adjacent semiconductor elements out of four semiconductor elements connected in series are accidentally turned on simultaneously. When an arm short circuit occurs, due to the nature of the circuit, if the inner semiconductor element is turned off first, the semiconductor element may be damaged by an excessive surge voltage caused by parasitic inductance. Patent Document 1 listed below discloses a technology that provides a logic circuit that controls the order in which semiconductor elements are turned off in order to suppress overcurrent caused by this type of excessive surge voltage. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 10-66348 Summary of the Invention [Problem to be solved by the invention]

[0004] However, the above-mentioned prior art does not disclose a specific configuration of the logic circuit. Furthermore, the technique using the logic circuit poses a problem of signal delay. If a signal delay occurs, the order of control in the logic circuit may be out of order, which makes it difficult to ensure reliable implementation of short-circuit protection.

[0005] The present invention has been made in view of the above, and an object of the present invention is to provide a semiconductor element drive circuit that can ensure reliable implementation of short-circuit protection operation. [Means for solving the problem]

[0006] To solve the above-mentioned problems and achieve the object, a semiconductor device drive circuit according to the present disclosure includes a control unit that individually controls one of four series-connected semiconductor devices that constitute one phase of a power conversion circuit unit of a three-level power converter, and applies a gate voltage to the semiconductor device to drive the semiconductor device. The semiconductor device drive circuit detects an arm short circuit in the power conversion circuit unit based on the main terminal voltage of the semiconductor device. Each control unit controls the drive of the higher potential side outer device and the lower potential side outer device of the four semiconductor devices, and applies a gate voltage lower than a specified voltage to the semiconductor device when turning on the semiconductor device. [Effects of the Invention]

[0007] The semiconductor element drive circuit according to the present disclosure has the effect of ensuring reliable implementation of short-circuit protection operation. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a schematic circuit diagram illustrating the connection relationship between a semiconductor element drive circuit (hereinafter abbreviated as "drive circuit" where appropriate) and a semiconductor element to be driven according to a first embodiment. [Figure 2] FIG. 1 is a diagram showing an example of a short-circuit detection circuit provided in a drive circuit according to the first embodiment; [Figure 3] FIG. 10 is a diagram illustrating control that becomes a problem in dealing with arm short-circuits in the drive circuit according to the first embodiment. [Figure 4] FIG. 1 is a first diagram illustrating a control method in a drive circuit according to a first embodiment. [Figure 5] FIG. 2 is a second diagram illustrating a control method in the drive circuit according to the first embodiment. [Figure 6] 1 is a schematic circuit diagram illustrating the connection relationship between a semiconductor element driving device (hereinafter abbreviated as "driving device" where appropriate) according to a second embodiment and a semiconductor element to be driven. [Figure 7] FIG. 10 is a diagram illustrating a first example of a control method in a drive device according to a second embodiment. [Figure 8] FIG. 10 is a diagram illustrating a second example of a control method in the drive device according to the second embodiment. [Figure 9] FIG. 10 is a diagram illustrating a third example of a control method in the drive device according to the second embodiment. [Figure 10] FIG. 10 is a table showing the main points of first to third examples of the control method in the drive device according to the second embodiment. [Figure 11] FIG. 10 is a diagram showing an example of a hardware configuration that realizes the functions of a control unit according to the first embodiment and a general control unit according to the second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, a semiconductor device drive circuit and a drive device according to an embodiment of the present disclosure will be described in detail with reference to the accompanying drawings. In the following description, multiple components of the same type will be denoted by subscripted symbols, but the subscripts will be omitted as appropriate when there is no need to distinguish between the individual components.

[0010] Embodiment 1 1 is a schematic circuit diagram illustrating the connection relationship between a drive circuit according to the first embodiment and a semiconductor element to be driven. A drive circuit 50 according to the first embodiment individually drives one of four semiconductor elements 5a to 5d connected in series. The four semiconductor elements 5a to 5d connected in series are connected across capacitors 1a and 1b that are connected in series and act as DC power sources, and operate to open and close the flow of DC power supplied from capacitors 1a and 1b, i.e., to switch between supplying and cutting off power.

[0011] The circuit section consisting of capacitors 1a and 1b connected in series is called the DC link section. The DC link section has DC terminal P1 drawn from the higher potential side of capacitor 1a, DC terminal N1 drawn from the lower potential side of capacitor 1b, and intermediate potential terminal C1 drawn from the connection point of capacitors 1a and 1b. In this paper, the side where DC terminal P1 exists is called the "higher potential side," and the side where DC terminal N1 exists is called the "lower potential side."

[0012] The collector of semiconductor element 5a is connected to DC terminal P1, and the junction between the emitter of semiconductor element 5a and the collector of semiconductor element 5b is connected to the cathode of clamp diode 6a. The anode of clamp diode 6a is connected to intermediate potential terminal C1, which is also connected to the cathode of clamp diode 6b. The emitter of semiconductor element 5b is connected to the collector of semiconductor element 5c, and this junction is drawn out to form AC terminal AC1. The junction between the emitter of semiconductor element 5c and the collector of semiconductor element 5d is connected to the anode of clamp diode 6b. The emitter of semiconductor element 5d is connected to DC terminal N1.

[0013] The four semiconductor elements 5a-5d and clamp diodes 6a and 6b connected as described above constitute a power conversion circuit for one phase in a three-level power converter. The power conversion circuit for one phase selects one of three potentials defined by the DC terminal P1, the intermediate potential terminal C1, and the DC terminal N1 through the switching operation of the semiconductor elements 5a-5d, and outputs the selected potential to the AC terminal AC1. In this paper, the semiconductor elements 5a-5d may be referred to as the "upper potential side outer element," the "upper potential side inner element," the "lower potential side inner element," and the "lower potential side outer element," respectively, depending on their placement in the circuit. The upper potential side outer element and the lower potential side outer element may be collectively referred to as the "outer element," and the upper potential side inner element and the lower potential side inner element may be collectively referred to as the "inner element."

[0014] Each drive circuit 50 is connected to the collector (C), gate (G), and emitter (E) of the semiconductor element 5. Drive circuit 50a drives semiconductor element 5a, drive circuit 50b drives semiconductor element 5b, drive circuit 50c drives semiconductor element 5c, and drive circuit 50d drives semiconductor element 5d. FIG. 1 illustrates a case where the semiconductor elements 5a to 5d are IGBTs (Insulated Gate Bipolar Transistors), but semiconductor elements other than IGBTs may also be used. Another example of the semiconductor elements 5a to 5d is MOSFETs (Metal Oxide Semiconductor Field Effect Transistors). Furthermore, FIG. 1 illustrates the semiconductor elements 5a to 5d as single elements, but each of the semiconductor elements 5a to 5d may be configured by connecting multiple elements in parallel.

[0015] The drive circuit 50a includes a gate drive circuit 2a, a short-circuit detection circuit 3a, and a control unit 4a; the drive circuit 50b includes a gate drive circuit 2b, a short-circuit detection circuit 3b, and a control unit 4b; the drive circuit 50c includes a gate drive circuit 2c, a short-circuit detection circuit 3c, and a control unit 4c; and the drive circuit 50d includes a gate drive circuit 2d, a short-circuit detection circuit 3d, and a control unit 4d.

[0016] The gate drive circuit 2 applies a drive voltage between the gate and emitter of the semiconductor element 5 to drive the semiconductor element 5. The control unit 4 controls the driving of the semiconductor element 5. In this paper, the drive voltage applied between the gate and emitter will be referred to as the "gate voltage" where appropriate.

[0017] The short-circuit detection circuit 3 detects an arm short circuit in the power conversion circuit unit based on the collector-emitter voltage of the semiconductor element 5. An arm short circuit in the power conversion circuit unit here refers to three adjacent semiconductor elements, 5a-5c or 5b-5d, of the four series-connected semiconductor elements 5a-5d being accidentally turned on simultaneously. In this paper, the collector-emitter voltage is referred to as the "main terminal voltage" where appropriate. When the short-circuit detection circuit 3 detects an arm short circuit in the power conversion circuit unit, the control unit 4 controls the semiconductor element 5 to be controlled to turn off.

[0018] The drive circuit 50 according to the first embodiment detects an arm short circuit in the power conversion circuit unit using a collector voltage detection method. The collector voltage detection method is a method for detecting an arm short circuit in the power conversion circuit unit based on the collector-emitter voltage, which is the main terminal voltage of the semiconductor element 5. In the following description, for simplicity, the collector-emitter voltage will be simply referred to as the "collector voltage."

[0019] FIG. 2 is a diagram showing an example of a short-circuit detection circuit provided in the drive circuit according to the first embodiment, illustrating a circuit example using a collector voltage detection method. The short-circuit detection circuit 3 mainly comprises a comparator 11, a detection capacitor 12, a diode 13, and a resistance circuit 15. The resistance circuit 15 includes at least one resistor 16. A capacitor 17 is connected across the resistor 16. If the resistance circuit 15 does not include a physical capacitor, the capacitor 17 refers to the parasitic capacitance of the resistance circuit 15. The collector voltage of the semiconductor element 5, not shown in FIG. 2, is applied to the negative terminal of the comparator 11 via the resistance circuit 15 and the like. A reference voltage Vref is applied to the positive terminal of the comparator 11.

[0020] Next, the operation of the short-circuit detection circuit 3 will be described. First, when the semiconductor element 5 is in the gate-off state, the cathode potential of the diode 13 is set to the GND potential. As a result, the potential on the side connected to the negative terminal of the capacitor 12 is also approximately the GND potential, and the capacitor 12 is not charged. In the short-circuit detection circuit 3, the GND potential is generally set to the emitter potential or negative bias potential of the drive circuit 50. On the other hand, when the semiconductor element 5 is in the gate-on state, the capacitor 12 is charged as the collector voltage increases. The voltage generated across the capacitor 12 is applied to the negative terminal of the comparator 11 as the detection voltage Vsig by the short-circuit detection circuit 3. The detection voltage Vsig increases according to a time constant determined by the resistance values ​​of the resistive elements, including the resistor 16, in the charging path of the capacitor 12 and the capacitance values ​​of the capacitive elements, including the capacitor 17, in the charging path of the capacitor 12.

[0021] The short circuit detection circuit 3 outputs a detection signal when the detection voltage Vsig exceeds the reference voltage Vref. When the detection signal is output from the short circuit detection circuit 3, the control unit 4 can determine that an arm short circuit has occurred in the power conversion circuit unit.

[0022] FIG. 3 is a diagram illustrating control problems that may occur when the drive circuit according to the first embodiment deals with an arm short circuit. FIG. 3 shows the path of a short-circuit current that may flow when the semiconductor elements 5a to 5c are simultaneously turned on. As shown in the figure, when the semiconductor elements 5a to 5c are simultaneously turned on, the short-circuit current flows through the following path: capacitor 1a → semiconductor element 5a → semiconductor element 5b → semiconductor element 5c → clamp diode 6b → capacitor 1a. In this case, if the inner semiconductor element 5b or semiconductor element 5c is turned off first, an excessive surge voltage (Ls × di / dt) may be generated due to the parasitic inductance Ls, potentially damaging the semiconductor element 5a. di / dt is the rate of change of current when the short-circuit current is interrupted. On the other hand, when the outer semiconductor element 5a is turned off first, this surge voltage is smaller than when the inner semiconductor element 5b or semiconductor element 5c is turned off first, significantly reducing the possibility of damage to the semiconductor element 5a. The same applies when the semiconductor elements 5b to 5d are simultaneously turned on, and it is a preferred embodiment to turn off the semiconductor element 5d, which is the outer element, first.

[0023] To address the above-mentioned issues, Patent Document 1 proposes a solution that provides a logic circuit that controls the order of tripping. Other possible solutions include increasing gate resistance to reduce di / dt during tripping, or providing a dedicated circuit to reduce di / dt during tripping only when an arm is short-circuited. However, these solutions create other issues, such as increased circuit complexity, increased loss, larger circuit size, and reduced reliability due to an increased number of circuit components. Therefore, in the first embodiment, the following method is proposed. In the description of Figures 4, 5, and 7-9, semiconductor elements 5a and 5d are referred to as "outer elements 5a and 5d," and semiconductor elements 5b and 5c are referred to as "inner elements 5b and 5c."

[0024] FIG. 4 is a first diagram illustrating a control technique in the drive circuit according to the first embodiment. The left side of FIG. 4 illustrates a situation in which, in a power conversion circuit section for one phase, the outer element 5a is turned on when the inner elements 5b and 5c are in the on state. The right side of FIG. 4 illustrates the operating waveforms of the gate voltage Vge and the collector voltage Vce in this situation. The horizontal axis represents time. The subscripts a, b, and c correspond to the subscripts of the semiconductor elements 5; for example, "Vge_a" represents the gate voltage Vge of the outer element 5a, and "Vce_b" represents the collector voltage Vce of the inner element 5b. The solid lines represent the operating waveforms according to a comparative example, and the dashed lines represent the operating waveforms according to the control technique of the first embodiment.

[0025] In the control technique of the first embodiment, when turning on the outer element 5a, the gate voltage Vge_a applied to the outer element 5a is controlled to be lower than the gate voltages Vge_b and Vge_c applied to the inner elements 5b and 5c. In contrast, in the comparative example, the outer element 5a and the inner elements 5b and 5c are not distinguished from each other, and a predetermined gate voltage that is a gate voltage during steady-state on-state is applied when turning on the semiconductor element 5. That is, in the comparative example, a uniform predetermined voltage is applied when turning on the semiconductor element 5, whereas in the first embodiment, a gate voltage Vge_a lower than the predetermined voltage is applied to the outer element 5a when turning on the outer element 5a.

[0026] In the comparative example, when the outer element 5a and the inner elements 5b and 5c are turned on, the collector voltage Vce_a of the outer element 5a and the collector voltages Vce_b and Vce_c of the inner elements 5b and 5c are divided by the on-resistance of each element. This phenomenon is referred to as "voltage sharing" in this paper. In the comparative example, as shown by the solid line waveform on the right, voltage is divided almost equally between each element. This makes it unclear which element's short-circuit detection circuit 3 will operate, and it is uncertain which element will be turned off. As mentioned above, if the inner elements 5b and 5c turn off first, an excessive surge voltage may occur.

[0027] In contrast, in the control method of the first embodiment, as shown by the dashed waveform on the right, voltage sharing is performed so that a larger divided voltage is generated in the outer element 5a to which a relatively low gate voltage Vge_a is applied. This voltage sharing results from the characteristics of the semiconductor element 5, in that when a certain amount of current flows through the semiconductor element 5, the collector voltage Vce fluctuates greatly with changes in the gate voltage Vge, and the lower the gate voltage Vge, the larger the collector voltage Vce. As a result, the short-circuit detection circuit 3 connected to the outer element 5a detects an arm short circuit in the power conversion circuit, and the outer element 5a can be turned off first. Therefore, by using the control method of the first embodiment, it is possible to ensure reliable implementation of short-circuit protection operation while suppressing the generation of excessive surge voltages.

[0028] The above-mentioned specified voltage does not need to be a constant fixed voltage, but may be a variable voltage from which several set voltages can be selected. Therefore, when gate voltages Vge_b and Vge_c applied when turning on inner elements 5b and 5c are defined as a first voltage, control unit 4a, which controls the driving of outer element 5a, applies a second voltage lower than the first voltage when turning on outer element 5a.

[0029] Furthermore, the voltage difference between the gate voltage Vge_b (=Vge_c) when the inner elements 5b and 5c are turned on and the gate voltage Vge_a when the outer element 5a is turned on may be such that a significant difference occurs in the voltage distribution of the collector voltage Vce between the semiconductor elements 5, and can be determined according to the characteristics of the semiconductor elements 5.

[0030] Furthermore, although the illustration of the operating waveforms is omitted, when the inner elements 5b and 5c are in the on state and the outer element 5d is turned on, control is performed to lower the gate voltage Vge_d applied to the outer element 5d below the gate voltages Vge_b and Vge_c applied to the inner elements 5b and 5c. This control allows the short-circuit detection circuit 3 connected to the outer element 5d to detect an arm short circuit in the power conversion circuit unit, making it possible to ensure reliable implementation of short-circuit protection operation while suppressing the generation of excessive surge voltage.

[0031] Fig. 5 is a second diagram illustrating a control technique in the drive circuit according to embodiment 1. Fig. 4 illustrates the operation when outer element 5a is turned on, while Fig. 5 illustrates the operation when inner element 5c is turned on. Note that the notation of symbols, distinctions between line types, and the meanings of comparative examples are the same as those in Fig. 4.

[0032] 5, outer element 5a in the ON state is driven by a gate voltage Vge_a that is lower than a specified voltage when turned on, and this gate voltage Vge_a is maintained even when in the ON state. Similarly, inner element 5b in the ON state is driven by a gate voltage Vge_b that is a specified voltage when turned on, and this gate voltage Vge_b is maintained even when in the ON state. Similarly, inner element 5c that is turned on is driven by a gate voltage Vge_c that is a specified voltage.

[0033] In the comparative example, similar to the example in Figure 4, the collector voltage Vce_a of the outer element 5a and the collector voltages Vce_b and Vce_c of the inner elements 5b and 5c are divided by the on-resistance of each element. Therefore, similar to the example in Figure 4, voltage division is performed almost equally between the elements, so it is unclear which element's short-circuit detection circuit 3 will operate. This creates an uncertainty as to which element will perform the turn-off operation, and if the inner elements 5b and 5c turn off first, an excessive surge voltage may occur.

[0034] In contrast, in the control method of embodiment 1, voltage sharing is performed so that a larger divided voltage is generated in outer element 5a to which a relatively low gate voltage Vge_a is applied, as in the example of Fig. 4. As a result, short-circuit detection circuit 3 connected to outer element 5a detects an arm short circuit in the power conversion circuit unit, so that outer element 5a can be turned off first, and it is possible to ensure reliable implementation of short-circuit protection operation while suppressing the occurrence of excessive surge voltage, as in the example of Fig. 4.

[0035] As described above, the semiconductor device drive circuit according to the first embodiment includes a control unit that individually controls one of four series-connected semiconductor devices constituting one phase of a power conversion circuit unit of a three-level power converter, applying a gate voltage to the semiconductor device to drive the semiconductor device. The semiconductor device drive circuit detects an arm short circuit in the power conversion circuit unit based on the main terminal voltage of the semiconductor device. In this drive circuit, each control unit that controls the drive of the higher potential side outer device and the lower potential side outer device of the four semiconductor devices applies a gate voltage lower than a specified voltage to the semiconductor device when turning on the semiconductor device. This control allows the short-circuit detection circuit connected to the outer device to detect an arm short circuit in the power conversion circuit unit, allowing the outer device to be turned off first. This allows a drive circuit that can ensure reliable implementation of short-circuit protection while suppressing the generation of excessive surge voltages.

[0036] In the above control, the specified voltage does not need to be a constant fixed voltage, but may be a variable voltage from which several set voltages can be selected. Therefore, in the semiconductor element drive circuit according to the first embodiment, each control unit that controls the drive of the upper potential side inner element and the lower potential side inner element may apply a first voltage as a gate voltage when turning on the semiconductor element, and each control unit that controls the drive of the upper potential side outer element and the lower potential side outer element may apply a second voltage lower than the first voltage as a gate voltage when turning on the semiconductor element. Even with this control, it is possible to ensure reliable implementation of short-circuit protection operation while suppressing the occurrence of excessive surge voltage.

[0037] Embodiment 2 FIG. 6 is a schematic circuit diagram illustrating the connection relationship between a drive device according to the second embodiment and a semiconductor element to be driven. The drive device 100 according to the second embodiment includes an integrated control unit 8 and four drive circuits 50a1, 50b1, 50c1, and 50d1. The drive circuit 50a1 drives the semiconductor element 5a, the drive circuit 50b1 drives the semiconductor element 5b, the drive circuit 50c1 drives the semiconductor element 5c, and the drive circuit 50d1 drives the semiconductor element 5d. Each drive circuit 50 includes a gate drive circuit 2 and a short-circuit detection circuit 3, as in the first embodiment. In the first embodiment, the control unit 4 included in each drive circuit 50 is configured to control one semiconductor element 5 to be controlled, but in the second embodiment, the integrated control unit 8 is configured to collectively control the four semiconductor elements 5a to 5d. The other configurations are the same as or equivalent to those of the first embodiment shown in FIG. 1, and the same or equivalent components are designated by the same reference numerals and redundant explanations will be omitted.

[0038] FIG. 7 is a diagram illustrating a first example of a control method in a drive device according to embodiment 2. The left side of FIG. 7 shows a situation in which, in a power conversion circuit section for one phase, the inner element 5c is turned on when the outer element 5a and the inner element 5b are in the on state. The right side of FIG. 7 shows the operating waveforms of the gate voltage Vge and the collector voltage Vce in this situation. Note that the notation of symbols, distinctions of line types, and meanings of comparative examples are the same as those in FIG. 5.

[0039] In Fig. 7, the operating waveforms in the comparative example are the same as or equivalent to those shown in Fig. 5. That is, as in the example of Fig. 5, voltage is divided almost equally between the elements, and it is unclear which element's short circuit detection circuit 3 will operate. Therefore, it is uncertain which element will perform the turn-off operation, and if inner elements 5b and 5c turn off first, an excessive surge voltage may be generated.

[0040] In contrast, in a first example of the control method of the second embodiment shown in FIG. 7, when the inner element 5c is turned on, the gate voltage Vge_a of the outer element 5a, which is in the on state, is temporarily lowered to a gate voltage Vge_a1 that is lower than the specified voltage. In this document, this control is appropriately referred to as the "first control." The gate voltage Vge_a of the outer element 5a is returned to its original voltage, i.e., the specified voltage Vge_0, after a specified time has elapsed. The specified time can be determined according to the characteristics of the semiconductor element 5. For example, the specified time can be determined by setting an appropriate margin based on the time from when a turn-on command is issued to the inner element 5c to immediately after the gate voltage Vge_c of the inner element 5c exceeds the mirror voltage.

[0041] In the first example of the control method of the second embodiment, voltage sharing is performed so that a larger divided voltage is generated in the outer element 5a to which a relatively low gate voltage Vge_a is applied, similar to the examples of Figures 4 and 5. As a result, the short-circuit detection circuit 3 connected to the outer element 5a detects an arm short circuit in the power conversion circuit unit, so that the outer element 5a can be turned off first, and it is possible to ensure reliable implementation of short-circuit protection operation while suppressing the occurrence of excessive surge voltage, similar to the examples of Figures 4 and 5.

[0042] 7 illustrates an example in which the first control is implemented when the inner element 5c is turned on while the outer element 5a and the inner element 5b are on. However, the first control is also implemented when the outer element 5a is turned on while the inner elements 5b and 5c are on. That is, when the outer element 5a is turned on while the inner elements 5b and 5c are on, the first control is implemented to temporarily lower the gate voltage applied to the outer element 5a to a voltage lower than the specified voltage. Even in this case, the short-circuit detection circuit 3 connected to the outer element 5a detects an arm short circuit in the power conversion circuit unit, so the outer element 5a can be turned off first. This makes it possible to ensure reliable implementation of short-circuit protection operation while suppressing the generation of excessive surge voltage.

[0043] FIG. 8 is a diagram illustrating a second example of a control method in the drive device according to the second embodiment. The left side of FIG. 8 shows a situation in which, in a power conversion circuit section for one phase, the inner element 5b is turned on when the inner element 5c and the outer element 5d are in the on state. The right side of FIG. 8 shows the operating waveforms of the gate voltage Vge and the collector voltage Vce in this situation. Note that the notation of symbols, distinctions between line types, and the meanings of the comparative example are the same as those in FIG. 7.

[0044] In Fig. 8, the operating waveforms in the comparative example are equivalent to those shown in Fig. 7. That is, as in the example of Fig. 7, voltage is divided almost equally between the elements, and it is unclear which element's short circuit detection circuit 3 will operate. Therefore, it is uncertain which element will perform the turn-off operation, and if inner elements 5b and 5c turn off first, an excessive surge voltage may occur.

[0045] In contrast, in a second example of the control method of the second embodiment shown in FIG. 8, when the inner element 5b is turned on, the gate voltage Vge_d of the outer element 5d, which is in the on state, is temporarily lowered to a gate voltage Vge_d1 that is lower than the specified voltage. In this document, this control is appropriately referred to as the "second control." Note that the gate voltage Vge_d of the outer element 5d is returned to its original voltage, i.e., the specified voltage Vge_0, after a specified time has elapsed. Note that the specified time can be determined according to the characteristics of the semiconductor element 5, as described in the example of FIG. 7.

[0046] In a second example of the control method of the second embodiment, voltage sharing is performed so that a larger divided voltage is generated in the outer element 5d to which a relatively low gate voltage Vge_d is applied. As a result, the short-circuit detection circuit 3 connected to the outer element 5d detects an arm short circuit in the power conversion circuit unit, and the outer element 5d can be turned off first. As in the example of Fig. 7, it is possible to ensure reliable implementation of short-circuit protection operation while suppressing the occurrence of excessive surge voltage.

[0047] 8 illustrates an example in which the second control is performed when the inner element 5b is turned on while the inner element 5c and the outer element 5d are on. However, the second control is also performed when the outer element 5d is turned on while the inner elements 5b and 5c are on. That is, when the outer element 5d is turned on while the inner elements 5b and 5c are on, the second control is performed to temporarily lower the gate voltage applied to the outer element 5d to a voltage lower than the specified voltage. Even in this case, the short-circuit detection circuit 3 connected to the outer element 5d detects an arm short circuit in the power conversion circuit, so the outer element 5d can be turned off first. This makes it possible to ensure reliable implementation of short-circuit protection operation while suppressing the generation of excessive surge voltage.

[0048] 9 is a diagram illustrating a third example of a control method in the drive device according to the second embodiment. The left side of FIG. 9 illustrates a situation in which, in a power conversion circuit section for one phase, the inner element 5c is turned on when the outer element 5a and the inner element 5b are in the on state. The right side of FIG. 9 illustrates the operating waveforms of the gate voltage Vge and the collector voltage Vce in this situation. The symbol notation, the distinction of the line types, and the meanings of the comparative example are the same as those in FIG. 7.

[0049] In Figure 9, the operating waveforms in the comparative example are equivalent to those shown in Figure 7. That is, as in the example of Figure 7, voltage is divided almost equally between the elements, and it is unclear which element's short circuit detection circuit 3 will operate. Therefore, it is uncertain which element will perform the turn-off operation, and if inner elements 5b and 5c turn off first, an excessive surge voltage may occur.

[0050] In contrast, in a third example of the control method of the second embodiment shown in FIG. 9 , when turning on the inner element 5c, the gate voltage Vge_b of the inner element 5b, which is in the ON state, is temporarily increased to a gate voltage Vge_b1 higher than the specified voltage, and the gate voltage Vge_c of the inner element 5c to be turned on is temporarily increased to a gate voltage Vge_c1 higher than the specified voltage. In this document, this control is appropriately referred to as the “third control.” The gate voltages Vge_b1 and Vge_c1 may be the same voltage. Furthermore, the gate voltages Vge_b of the inner element 5b and the gate voltages Vge_c of the inner element 5c are returned to their original voltages, i.e., the specified voltage Vge_0, after a specified time has elapsed. The specified time can be determined according to the characteristics of the semiconductor element 5, as described in the examples of FIGS. 7 and 8 .

[0051] In a third example of the control method of the second embodiment, voltage sharing is performed so that a larger divided voltage is generated in the outer element 5a to which a relatively low gate voltage Vge_a is applied. As a result, the short-circuit detection circuit 3 connected to the outer element 5a detects an arm short circuit in the power conversion circuit unit, so that the outer element 5a can be turned off first, and it is possible to ensure reliable implementation of short-circuit protection operation while suppressing the occurrence of excessive surge voltage, similar to the examples of FIGS. 7 and 8.

[0052] 9 illustrates an example in which the third control is implemented when the inner element 5c is turned on while the outer element 5a and the inner element 5b are on. However, the third control is also implemented when the outer element 5a is turned on while the inner elements 5b and 5c are on. That is, when the outer element 5a is turned on while the inner elements 5b and 5c are on, the third control is implemented to temporarily increase the gate voltage applied to the inner elements 5b and 5c to a voltage higher than the specified voltage. Even in this case, the short-circuit detection circuit 3 connected to the outer element 5a detects an arm short circuit in the power conversion circuit, so the outer element 5a can be turned off first. This makes it possible to ensure reliable implementation of short-circuit protection operation while suppressing the generation of excessive surge voltage.

[0053] Although not shown, the third control is also performed when the inner element 5b is turned on while the inner element 5c and the outer element 5d are on. That is, when the inner element 5b is turned on while the inner element 5c and the outer element 5d are on, the third control is performed to temporarily increase the gate voltage applied to the inner elements 5b and 5c to a voltage higher than the specified voltage. Even in this case, the short-circuit detection circuit 3 connected to the outer element 5d detects an arm short circuit in the power conversion circuit, so the outer element 5d can be turned off first, making it possible to ensure reliable implementation of short-circuit protection operation while suppressing the generation of excessive surge voltage.

[0054] Although not shown, the third control is also performed when the outer element 5d is turned on while the inner elements 5b and 5c are on. That is, when the outer element 5d is turned on while the inner elements 5b and 5c are on, the third control is performed to temporarily increase the gate voltage applied to the inner elements 5b and 5c to a voltage higher than the specified voltage. Even in this case, the short-circuit detection circuit 3 connected to the outer element 5d detects an arm short circuit in the power conversion circuit, so the outer element 5d can be turned off first, making it possible to ensure reliable implementation of short-circuit protection operation while suppressing the generation of excessive surge voltage.

[0055] Fig. 10 is a diagram showing, in tabular form, the main points of first to third examples of the control method in the drive device according to embodiment 2. The upper side of Fig. 10 shows the elements that are in the ON state, the elements that are turned on, and the elements that lower the gate voltage when lowering the gate voltage Vge_a of outer element 5a and the gate voltage Vge_d of outer element 5d shown in Figs. 7 and 8. The first row from the top of Fig. 10 corresponds to Fig. 7, and the fourth row from the top of Fig. 10 corresponds to Fig. 8. Furthermore, the fourth row from the bottom of Fig. 10 corresponds to Fig. 9.

[0056] As described above, the semiconductor device driver according to the second embodiment includes a centralized control unit that controls the operation of four gate drive circuits that individually drive one of four semiconductor devices, each of which consists of an upper potential side outer device, an upper potential side inner device, a lower potential side inner device, and a lower potential side outer device connected in series and constituting one phase of a power conversion circuit device of a three-level power converter. The semiconductor device driver detects an arm short circuit in the power conversion circuit device based on the main terminal voltage of the semiconductor device. In this driver, when the centralized control unit turns on the upper potential side outer device and the lower potential side inner device of the four semiconductor devices, it performs a first control to temporarily reduce the gate voltage applied to the upper potential side outer device to a voltage lower than a specified voltage. Furthermore, when the centralized control unit turns on the lower potential side outer device and the upper potential side inner device of the four semiconductor devices, it performs a second control to temporarily reduce the gate voltage applied to the lower potential side outer device to a voltage lower than the specified voltage. This control allows the short-circuit detection circuit connected to the outer device to detect an arm short circuit in the power conversion circuit device, so that the outer device can be turned off first. This makes it possible to obtain a drive device that can ensure reliable implementation of short-circuit protection operation while suppressing the occurrence of excessive surge voltage.

[0057] In the above control, the first control may be performed when the lower potential side inner element is turned on when both the upper potential side outer element and the upper potential side inner element are on. Alternatively, the first control may be performed when the upper potential side outer element is turned on when both the upper potential side inner element and the lower potential side inner element are on. By such a control operation, an arm short circuit in the power conversion circuit unit is detected by the short circuit detection circuit connected to the outer element.

[0058] In the above control, the second control may be performed when the lower potential side outer element is turned on when both the upper potential side inner element and the lower potential side inner element are on. Alternatively, the second control may be performed when the upper potential side inner element is turned on when both the lower potential side inner element and the lower potential side outer element are on. By such a control operation, an arm short circuit in the power conversion circuit unit is detected by the short circuit detection circuit connected to the outer element.

[0059] A semiconductor device driver according to a second embodiment includes a centralized control unit that controls the operation of four gate drive circuits, each of which individually drives one of four semiconductor devices, each of which consists of a series-connected upper potential side outer device, an upper potential side inner device, a lower potential side inner device, and a lower potential side outer device, constituting one phase of a power conversion circuit of a three-level power converter. The semiconductor device driver detects an arm short circuit in the power conversion circuit based on the main terminal voltage of the semiconductor device. In this driver, when one of the four semiconductor devices is turned on, the centralized control unit performs a third control that temporarily increases the gate voltages applied to the upper potential side inner device and the lower potential side inner device to a voltage higher than a specified voltage. This control allows a short-circuit detection circuit connected to the outer device to detect an arm short circuit in the power conversion circuit, allowing the outer device to be turned off first. This results in a driver that can ensure reliable implementation of short-circuit protection while suppressing the generation of excessive surge voltages.

[0060] In the above control, the third control may be performed when the lower potential side inner element is turned on when the upper potential side outer element and the upper potential side inner element are both on. Alternatively, the third control may be performed when the upper potential side outer element or the lower potential side outer element is turned on when the upper potential side inner element and the lower potential side inner element are both on. Alternatively, the third control may be performed when the upper potential side inner element is turned on when the lower potential side inner element and the lower potential side outer element are both on. By such control operations, an arm short circuit in the power conversion circuit unit is detected by the short circuit detection circuit connected to the outer element.

[0061] Finally, a description will be given of a hardware configuration for realizing the functions of the control unit 4 and the overall control unit 8. Fig. 11 is a diagram showing an example of a hardware configuration for realizing the functions of the control unit 4 according to the first embodiment and the overall control unit 8 according to the second embodiment. The functions of the control unit 4 and the overall control unit 8 are realized by a processor 200 and a memory 202.

[0062] The processor 200 is a CPU (Central Processing Unit, also referred to as a central processing unit, processing unit, arithmetic unit, microprocessor, microcomputer, processor, or DSP (Digital Signal Processor)) or a system LSI (Large Scale Integration). The memory 202 can be exemplified by non-volatile or volatile semiconductor memories such as RAM (Random Access Memory), ROM (Read Only Memory), flash memory, EPROM (Erasable Programmable Read Only Memory), and EEPROM (registered trademark) (Electrically Erasable Programmable Read Only Memory).

[0063] The memory 202 stores a program that executes the functions of the control unit 4 according to the first embodiment or the overall control unit 8 according to the second embodiment. The processor 200 reads the program stored in the memory 202, runs the program, and refers to the data stored in the memory 202, thereby executing the above-mentioned processing.

[0064] The configurations shown in the above embodiments are merely examples, and may be combined with other known technologies, or different embodiments may be combined with each other. It is also possible to omit or modify parts of the configurations as long as they do not deviate from the gist of the invention.

[0065] For example, in the first embodiment, an individual control unit 4 is provided for each drive circuit 50, but the present invention is not limited to this configuration. A configuration may also be adopted in which an overall control unit 8 similar to that of the second embodiment is provided, and the overall control unit 8 is connected to each of the gate drive circuits 2a to 2d and each of the short-circuit detection circuits 3a to 3d, and the overall control unit 8 controls the operations of the four semiconductor elements 5a to 5d. [Explanation of symbols]

[0066] 1a, 1b, 12, 17 capacitors, 2, 2a to 2d gate drive circuits, 3, 3a to 3d short circuit detection circuits, 4, 4a to 4d control units, 5a to 5d semiconductor elements, 6a, 6b clamp diodes, 8 general control unit, 11 comparator, 13 diodes, 15 resistor circuits, 16 resistors, 50, 50a to 50d, 50a1 to 50d1 drive circuits, 100 drive device, 200 processor, 202 memory, AC1 AC terminal, C1 intermediate potential terminal, N1, P1 DC terminals.

Claims

1. A semiconductor element drive circuit includes a control unit that configures a power conversion circuit unit for one phase of a three-level power converter, and that individually controls one of four semiconductor elements connected in series in the order of a first semiconductor element, a second semiconductor element, a third semiconductor element, and a fourth semiconductor element, and applies a gate voltage to the semiconductor element to drive the semiconductor element, and that detects an arm short circuit of the power conversion circuit unit based on a main terminal voltage of the semiconductor element, the semiconductor element is an IGBT or a MOSFET, each of the control units that controls driving of the first semiconductor element and the fourth semiconductor element applies a gate voltage that is lower than a specified voltage to the first semiconductor element and the fourth semiconductor element when turning on the first semiconductor element and the fourth semiconductor element; The control units that control the driving of the second semiconductor element and the third semiconductor element apply gate voltages of specified voltages to the second semiconductor element and the third semiconductor element when turning on the second semiconductor element and the third semiconductor element. A semiconductor element drive circuit comprising:

2. The control unit on the side to which a gate voltage lower than the specified voltage is applied detects an arm short circuit in the power conversion circuit unit based on the main terminal voltage.

2. The semiconductor device drive circuit according to claim 1.

3. A semiconductor element drive circuit includes a control unit that configures a power conversion circuit unit for one phase of a three-level power converter, and that individually controls one of four semiconductor elements connected in series in the order of a first semiconductor element, a second semiconductor element, a third semiconductor element, and a fourth semiconductor element, and applies a gate voltage to the semiconductor element to drive the semiconductor element, and that detects an arm short circuit of the power conversion circuit unit based on a main terminal voltage of the semiconductor element, the semiconductor element is an IGBT or a MOSFET, the control unit that controls driving of the second semiconductor element and the third semiconductor element applies a first voltage as the gate voltage when turning on the second semiconductor element and the third semiconductor element; The control units that control the driving of the first semiconductor element and the fourth semiconductor element each apply a second voltage that is lower than the first voltage as the gate voltage when turning on the first semiconductor element and the fourth semiconductor element. A semiconductor element drive circuit comprising:

4. The control unit on the side to which the second voltage is being applied or the side to which the second voltage was applied detects an arm short circuit in the power conversion circuit unit based on the main terminal voltage.

4. The semiconductor device drive circuit according to claim 3.

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