ETHERNET INTERFACE AND RELATED SYSTEMS, METHODS, AND DEVICES - Patent application

Abstract

The disclosed embodiments relate generally to improved data reception processing at the physical layer (PHY). Some embodiments relate to a line end system including a legacy medium access control (MAC) and PHY that implements the improved data reception processing disclosed herein. The improved data reception processing improves the operation of the line end system, and more specifically the MAC, to comply, in some cases, with a medium access tuning protocol implemented at the physical layer.

Description

[Technical Field]

[0001] (Priority Claim) This application claims the benefit of the filing date of Chinese Patent Application No. 201910785140.7, filed August 23, 2019, entitled "Ethernet Interface and Related Systems, Methods and Devices," and of the pending U.S. Patent Application No. 16 / 684,428, filed November 14, 2019, entitled "Ethernet Interface and Related Systems, Methods and Devices," the disclosure of each of which is incorporated herein by reference in its entirety.

[0002] (Technical field) The disclosed embodiments relate generally to Ethernet, and more particularly, some embodiments relate to Ethernet interfaces. [Background technology]

[0003] Interconnects are widely used to facilitate communication between devices in a network. Generally speaking, electrical signals are transmitted over a physical medium (e.g., a bus, coaxial cable, or twisted pair—generally referred to simply as a “line”) by devices coupled to that physical medium.

[0004] According to the Open Systems Interconnection model (OSI model), Ethernet-based computer networking technology uses baseband transmission (i.e., electrical signals are discrete electrical pulses) to transport data packets and ultimately messages communicated between network devices. According to the OSI model, specialized circuitry called a physical layer (PHY) device or controller is used to interface between the analog domain of the line and the digital domain of the data link layer (also referred to herein simply as the "link layer"), which operates according to packet signaling. While the data link layer may include one or more sublayers, in Ethernet-based computer networking, the data link layer typically includes at least a media access control (MAC) layer, which provides control abstraction of the physical layer. As an example, when transmitting data to another device on the network, the MAC controller may prepare a frame for the physical medium, add error correction elements, and perform collision avoidance. Additionally, when receiving data from another device, the MAC controller may ensure the integrity of the received data and prepare a frame for a higher layer.

[0005] There are various network topologies that implement the physical layer and link layer (and may include, without limitation, other layers). The Peripheral Component Interconnect (PCI) standard and the Parallel Advanced Technology Attachment (Parallel ATA), which have been around since the early 1990s, may implement a multi-drop bus topology. Since the early 2000s, the trend has been to use a point-to-point bus topology; for example, the PCI Express standard and the Serial ATA (SATA) standard implement a point-to-point topology.

[0006] A typical point-to-point bus topology may implement a line between each device (e.g., dedicated point-to-point) or a line between a device and a switch (e.g., without limitation, switched point-to-point). In a multi-drop topology, the physical medium is a shared bus, and each network device is coupled to the shared bus via a circuit selected based on, for example, the type of physical medium (e.g., without limitation, coaxial or twisted pair).

[0007] Point-to-point bus topologies, such as dedicated point-to-point topologies or switched point-to-point topologies, require more wires and more expensive materials than multi-drop topologies, due in part to the larger number of links between devices. In certain applications, such as automobiles, physical constraints may exist that make it difficult to directly connect devices; therefore, topologies that do not require direct connections within a network or sub-network, or that do not require as many direct connections as a point-to-point bus topology (e.g., without limitation, a multi-drop topology), may be less susceptible to such constraints.

[0008] Devices in a baseband network (for example, but not limited to, a multi-drop network) share the same physical transmission medium and typically use the entire bandwidth of that medium for transmission (i.e., the digital signals used in baseband transmission occupy the entire bandwidth of the medium). As a result, only one device on the baseband network can transmit at a given moment. Therefore, medium access control methods are used to handle contention for the shared transmission medium. To easily identify the discussion of any particular element or function, one or more of the most significant digits of a reference number will refer to the figure number in which that element is first introduced. [Brief explanation of the drawings]

[0009] [Figure 1]1 illustrates a network segment in accordance with one or more embodiments. [Figure 2] FIG. 1 illustrates a block diagram of a system that implements common clock interfacing in accordance with one or more embodiments. [Figure 3] 3 shows a block diagram of an embodiment of a system for implementing a common clock interfacing system such as the system shown in FIG. 2. [Figure 4] 1 illustrates a flowchart of a process in accordance with one or more embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0010] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and which show, by way of illustration, specific exemplary embodiments in which the present disclosure may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the disclosure. However, other embodiments may be used, and changes in structure, materials, and processes may be made without departing from the scope of the present disclosure.

[0011] The figures presented herein are not intended to be actual illustrations of any particular method, system, device, or structure, but merely idealized representations used to describe embodiments of the present disclosure. The figures presented herein are not necessarily drawn to scale. Similar structures or components in various figures may retain the same or similar numbering for the convenience of the reader. However, similarity in numbering does not necessarily mean that the structures or components are identical in size, composition, configuration, or any other characteristic.

[0012] It will be readily understood that the components of the embodiments, as generally described and illustrated in the Figures herein, could be arranged and designed in a wide variety of different configurations. Thus, the following description of various embodiments is not intended to limit the scope of the present disclosure, but is merely representative of various embodiments.

[0013] The following description may include examples to assist those skilled in the art in practicing the disclosed embodiments. The use of the terms "exemplary," "example," and "for example" means that the associated description is explanatory, and the scope of the present disclosure is intended to encompass examples and legal equivalents. The use of such terms is not intended to limit the embodiments or the scope of the present disclosure to specific components, steps, features, functions, etc.

[0014] Furthermore, the specific implementations shown and described are merely examples and should not be construed as the only way to implement the present disclosure, unless otherwise specified herein. Elements, circuits, and functions may be shown in block diagram form so as not to obscure the present disclosure in unnecessary detail. Conversely, the specific implementations shown and described are merely exemplary and should not be construed as the only way to implement the present disclosure, unless otherwise specified herein. Furthermore, the block definitions and partitioning of logic among various blocks are exemplary specific implementations. It will be readily apparent to one skilled in the art that the present disclosure can be implemented with numerous other partitioning solutions. For the most part, details regarding timing considerations and the like have been omitted; such details are not necessary to obtain a complete understanding of the present disclosure and are within the capabilities of those skilled in the art.

[0015] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, and symbols that may be referenced throughout this specification may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some figures may illustrate signals as a single signal for clarity of presentation and explanation. Those skilled in the art will understand that a signal may represent a bus of signals, which may have various bit widths, and that the present disclosure may be implemented with any number of data signals, including a single data signal.

[0016] As used herein, the terms "substantially" and "about" when referring to a given parameter, characteristic, or condition mean and include the extent to which one of ordinary skill in the art would understand that the given parameter, characteristic, or condition satisfies some degree of variation, such as within acceptable manufacturing tolerances. For example, a parameter that is substantially at or about a particular value may be at least about 90% of the particular value, at least about 95% of the particular value, at least about 99% of the particular value, or even at least about 99.9% of the particular value.

[0017] Any reference to elements herein using designations such as "first," "second," etc., should be understood not to limit the quantity or order of those elements unless such limitation is expressly stated. Rather, these designations are used herein as a convenient method of distinguishing between two or more elements or instances of an element. Thus, reference to a first element and a second element does not imply that only two elements may be used or that the first element must precede the second element in any way. Also, unless otherwise specified, a set of elements may include one or more elements. Similarly, sometimes an element referred to in the singular may also include one or more instances of the element.

[0018] The various illustrative logic blocks, modules, and circuits described in connection with the embodiments disclosed herein may be implemented or performed using a general-purpose processor, a special-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor (which may also be referred to herein as a host processor or simply a host) may be a microprocessor, although the processor may alternatively be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in combination with a DSP core, or any other such configuration. A general-purpose computer including a processor is considered a special-purpose computer, and a general-purpose computer is configured to execute computing instructions (e.g., software code) related to the embodiments of the present disclosure.

[0019] Also, it should be noted that the embodiments may be described in terms of a process that is depicted as a flowchart, a flow diagram, a structure diagram, or a block diagram. While a flowchart may describe operational acts as a sequential process, many of these acts may be performed in a different order, in parallel, or substantially simultaneously. Additionally, the order of acts may be rearranged. A process may correspond to, but is not limited to, a method, a thread, a function, a procedure, a subroutine, or a subprogram. Further, the methods disclosed herein may be implemented in hardware, software, or both. If implemented in software, the functions may be stored on or transmitted as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media, such as any medium that facilitates transfer of a computer program from one place to another.

[0020] In the disclosed embodiments, unless otherwise specified, a collision should be understood to refer to a logical collision (i.e., an actual collision is predicted, but two or more nodes do not actually transmit signals simultaneously on a shared transmission medium).

[0021] Protocols may be implemented at the physical layer for medium access tuning. For example, 10SPE (i.e., 10Mbps Single Pair Ethernet) is a networking technology specification currently under development by the Institute of Electrical and Electronics Engineers (IEEE) as IEEE 802.3cg™. The 10SPE specification includes an optional physical layer collision avoidance (PLCA) coordination sublayer, which could theoretically be used to avoid collisions on multi-drop buses.

[0022] Other medium access tuning protocols may be implemented in the PHY, including time-aware protocols and traffic shaping protocols. Generally speaking, a time-aware protocol is one in which medium access is granted or withheld for a period of time according to a schedule, or by a scheduler using a schedule. Generally speaking, a traffic shaping protocol is one in which medium access is granted or withheld based at least in part on a performance level, quality of service, or return on investment (as an alternative or addition to collision avoidance and / or time-aware protocols). Traffic shaping may include, by way of non-limiting example, prioritization of types of traffic or types of traffic streams (e.g., but not limited to, time-sensitive data, best-effort data, and low or no priority data).

[0023] Generally speaking, an interface between a PHY and a MAC (e.g., but not limited to, a Media Independent Interface (MII) or a Reduced Media Independent Interface (RMII)) specifies particular signals that are transmitted between the devices. To comply with these specifications, devices that implement a PHY or MAC (e.g., but not limited to, microchips and microcontrollers) typically include pins that are assigned to the specified signals. For example, an MII PHY may include, among other pins, pins for receive data (RXD) and transmit data (TXD) data lines, as well as pins for signaling valid receive data (RXDV), carrier activity (CRS), valid transmit data (TX_EN), receive reference clock (RX_CLK), transmit reference clock (TX_CLK), and management data (MDIO). Depending on the implementation, each input and output pin of the PHY and MAC may be assigned to signal one of these signals exclusively or to signal two or more of these signals non-exclusively.

[0024] The inventors of this disclosure understand the need for signaling between a MAC and a PHY, between a controller and a PHY, or simply between other devices in a network protocol stack and a PHY. While more pins can be added to a chip, costs (e.g., but not limited to, in terms of one or more of money, time, and physical space) increase proportionally with the number of pins and / or interconnections between devices, and it is desirable to limit costs. Signaling can also be varied, but such changes should be performed carefully because adhering to interface specifications is an important way to promote interoperability and predictability of Ethernet devices, including PHY devices and link layer devices.

[0025] In a typical PHY for interfacing a link layer and a shared bus, the receive data path (circuitry for moving receive data from the shared bus to the link layer) typically operates in a different clock domain than the transmit data path (circuitry for moving transmit data from the link layer to the link layer on the shared bus) and the interface operatively coupling the PHY and link layer. As a non-limiting example, in the case of a 10SPE PHY, the receive data path is in the remote clock domain, i.e., the clock domain of the remote clock of the remote device that sent the receive data. The remote clock is recovered from the receive data and provided to the MAC via the interface with the receive data. The receive data is not synchronized to a new clock domain until it is sent via the interface to the link layer, where it is synchronized to the MAC's clock domain. Meanwhile, the transmit data path and interface operate in the local clock domain, i.e., the clock domain of the PHY's local clock.

[0026] As described above, to implement different clock domains for the transmit and receive data paths, the PHY provides two reference clocks: a receive reference clock (e.g., RX_CLK) for the receive data path clock domain, and a transmit reference clock (e.g., TX_CLK) for the transmit data path clock domain. The MAC may, for example, use the receive reference clock to synchronize received data frames to its clock domain and the transmit reference clock to synchronize transmit data frames to the PHY's local clock domain.

[0027] Before it was desirable to implement medium access tuning in the PHY, the drawbacks, if any, of having receive and transmit data paths operating in different clock domains typically did not outweigh the drawbacks of adding circuitry for domain crossing to the receive path (e.g., but not limited to, design issues involving cost, power, and timing). However, the inventors of the present disclosure recognize that having a common clock domain for the PHY-side receive data path and the PHY-side transmit data path would free up one or more pins for signaling, including, but not limited to, medium access tuning or additional control data paths.

[0028] One or more embodiments generally relate to operating a PHY-side receive data path and a PHY-side transmit data path in the same clock domain. In one embodiment, the PHY-side receive data path can include synchronization circuitry, which can be configured to enable domain crossing in the receive data path from a second clock domain (e.g., a remote clock domain) to a first clock domain (e.g., a local clock domain). The transmit data path and interface operatively coupling the PHY to the link layer can also operate in the same clock domain (e.g., the first clock domain).

[0029] One or more embodiments generally relate to a network protocol stack of a node of a multi-drop network segment that implements a control data path between devices and / or functions of the network protocol stack and a PHY. In one embodiment, the PHY may include one or more pins for transmitting and / or receiving control data via the control data path. In one embodiment, the control data may be for implementing aspects of medium access tuning in the PHY. In another embodiment, the control data may be for filtering types of Ethernet packets (e.g., using, but not limited to, information in the type field of a standard Ethernet packet).

[0030] 1 is a functional block diagram of a network segment 100 including a link layer device, MAC 104, and a physical layer (PHY) device, PHY 102. By way of non-limiting example, network segment 100 may be a segment of a multi-drop network, a segment of a multi-drop subnetwork, a multi-drop bus that is a segment of a mixed-media network, or a combination or sub-combination thereof. By way of non-limiting example, network segment 100 may be, be part of, or include one or more of, without limitation, a microcontroller-type embedded system, a user-type computer, a computer server, a notebook computer, a tablet, a handheld device, a mobile device, a wireless earphone or headphone device, a wired earphone or headphone device, an appliance subsystem, a lighting subsystem, an audio subsystem, a building management system, a home monitoring system (e.g., without limitation, for security or utility use), an elevator system or subsystem, a public transportation control system (e.g., without limitation, for an overground train, subway, trolley, or bus), an automobile system or automobile subsystem, or an industrial control system.

[0031] PHY 102 is generally configured to interface with MAC 104. As a non-limiting example, PHY 102 and / or MAC 104 may be chip packages that include memory and / or logic configured to perform all or a portion of the embodiments described herein. As a non-limiting example, PHY 102 and MAC 104 may each be implemented as separate chip packages or circuits (e.g., integrated circuits) within a single chip package (e.g., a system-in-a-package (SIP)).

[0032] PHY 102 is generally configured to interface with a shared transmission medium 108, e.g., the physical medium that is the communication path of nodes that are part of network segment 100, or with a network of which network segment 100 is a part, including nodes that each include PHY 102 and MAC 104. As a non-limiting example, shared transmission medium 108 may be a single twisted pair, such as used in single-pair Ethernet.

[0033] In one or more embodiments, PHY 102 is configured to perform medium access tuning. In one or more embodiments, MAC 104 is configured to be traffic-aware, and more specifically, to implement a collision detection and / or avoidance protocol. In one embodiment, MAC 104 is configured to perform carrier sense multiple access (CSMA). More specifically, MAC 104 is configured to check for a carrier on shared transmission medium 108, and if it detects a carrier, it waits until the carrier is no longer detected (i.e., the channel is idle) before initiating data transmission.

[0034] 1, network segment 100 also includes one or more other functions 106. Other functions 106 may be, by way of non-limiting example, a function at the link layer or other layer of a network protocol stack, a device that implements one or more layers of a network protocol stack, or a device that is part of a subsystem.

[0035] 2 is a block diagram of a system 200 that implements a common clock for receive and transmit data paths in accordance with one or more embodiments. System 200 may include a receive data path 210 and a transmit data path 212.

[0036] 2, system 200 includes at least two clock domains: a first clock domain 220 and a second clock domain 218. First clock domain 220 corresponds to the clock rate of a local clock 224, e.g., generated by PHY 102 of FIG. 1. Second clock domain 218 corresponds to the clock rate of a remote clock 228, e.g., the clock rate of a node other than the node that includes system 200.

[0037] In receive data path 210, PHY-side second portion 232 of data path 202 and PHY-side data path 206 are in the same clock domain, here clock first clock domain 220. First interface 214 operably couples the PHY side of data path 202 to link layer side data path 204, and second interface 216 operably couples link layer side data path 208 to PHY-side data path 206. First interface 214 and second interface 216 are also in first clock domain 220.

[0038] A first portion 230 on the PHY side of data path 202 is in second clock domain 218. In the embodiment of Figure 2, second clock domain 218 may be a remote clock domain associated with remote clock 228. As a non-limiting example, remote clock 228 represents the clock used at a remote PHY of a remote node that receives data on receive data path 210. As discussed herein, remote clock 228 is not necessarily recovered in system 200 or system 300.

[0039] A clock domain transition 234 exists between the first portion 230 and the second portion 232 on the PHY side of the data path 202, crossing a clock domain on the PHY side of the data path 202 from the second clock domain 218 to the first clock domain 220.

[0040] In various embodiments, link layer side data path 204 and link layer side data path 208 may be in the same or a different clock domain than first clock domain 220 .

[0041] As noted above, in one or more embodiments, system 200 may include clock generator 222. In one embodiment, clock generator 222 is configured to provide a local clock 224 to first clock domain 220, and more specifically to data path 202 and the PHY side of PHY-side data path 206.

[0042] In one or more embodiments, system 200 may include a third data path, here a control data path 226, which may operate in first clock domain 220 or another clock domain not shown. Control data path 226 may be configured to move control data to and from the physical layer, for example, between PHY 102 and other functions 106 of FIG. 1. In one embodiment, control data path 226 may be used when executing one or more control cycles in system 200.

[0043] In contemplated use cases of the disclosed embodiments, the clock rates of the first clock domain 220 and the second clock domain 218 may be the same or different clock rates.

[0044] FIG. 3 illustrates a block diagram of an embodiment of a system 300 for implementing receive and transmit data paths within the same clock domain, for example, in system 200 of FIG.

[0045] In one or more embodiments, system 300 may include a PHY 302 and a link layer 308. PHY 302 and link layer 308 are operatively coupled by a receive interface 336 and a transmit interface 338. In one embodiment, receive interface 336 and transmit interface 338 may include pins, interconnects, and respective circuitry of PHY 302 and link layer 308 to implement some or all of a particular interface.

[0046] In one embodiment, the designated interface may specify exclusive collision avoidance signaling from PHY 302 to link layer 308 (e.g., without limitation, an MII interface). Exclusive signaling is signaling used for one special purpose (e.g., without limitation, to indicate a particular condition), whereas exclusive collision avoidance signaling is signaling used for the special purpose of indicating a collision detected in a shared transmission medium operably coupled to interface circuit 328. In this embodiment, the PHY and MAC sides of receive interface 336 may each include a respective pin (output for PHY, input for MAC) assigned to exclusive collision avoidance signaling. PHY 302 may further include circuitry configured for exclusive collision avoidance signaling, and link layer 308 may include circuitry for performing collision avoidance using exclusive collision avoidance signaling. In the embodiment of FIG. 3, the PHY includes an output 360 for exclusive signaling of the collision avoidance signal. More specifically, PHY 302 may be configured to generate an exclusive collision avoidance signal and provide the signal to link layer 308 via output 360 and collision signaling line 362 .

[0047] In one or more embodiments, PHY 302 may include a receive data path 304, a transmit data path 306, a reference clock generator 334, and an interface circuit 328. Interface circuit 328 is configured to operably couple PHY 302 to a shared transmission medium (e.g., shared transmission medium 108), and more specifically, to operably couple each of receive data path 304 and transmit data path 306 to the shared transmission medium. As a non-limiting example, interface circuit 328 may be a medium dependent interface (MDI) configured to operably couple to a single-pair Ethernet-type cable.

[0048] The receive data path 304 may generally be configured to move receive data from the shared transmission medium to the link layer and may include circuitry at the PHY 302 for moving receive data toward the link layer 308. The transmit data path 306 may generally be configured to move transmit data from the link layer to the shared transmission medium and may include circuitry at the PHY 302 for moving transmit data away from the link layer 308.

[0049] In one or more embodiments, the receive data path 304 may include a receiver 310, oversampling 314, a digital clock and data recovery (DCDR) with synchronization (sync) (i.e., DCDR with sync 316), alignment and decoding 318, and a receive buffer 320.

[0050] For data reception, an analog input data stream is received at receiver 310 and then oversampled by oversampling 314. The sampling rate of oversampling 314 may be based at least in part on local reference clock 342 (for example, but not by way of limitation, using a quadrature component generated in response to local reference clock 342). In most cases, the approximate rate of the input data stream will be known, so in some embodiments, the frequency of oscillator 344 may be selected to be a multiple (i.e., an even or odd multiple) of the frequency of the input data stream.

[0051] The oversampled data is provided to DCDR with synchronization 316, which performs digital clock and data recovery and synchronizes the recovered data (i.e., received data) with local clock 340. Local clock 340 is generated by clock divider 330, which is configured to receive local reference clock 342 and generate a divided clock in response to local reference clock 342. Thus, the frequency of local reference clock 342 is an integer multiple (even or odd) of the frequency of local clock 340. Thus, when the oversampled data is received at DCDR with synchronization 316, it is immediately synchronized with local clock 340 (indeed, it can be considered to be synchronized by a sampling rate synchronized with local reference clock 342 and local clock 340), and local clock 340 can be used as a recovered clock for received data recovered from the oversampled data by the DCDR of DCDR with synchronization 316. The unaligned received data is provided to alignment and decode 318, which is configured to provide recovered data by performing symbol alignment on the unaligned received data provided by DCDR with synchronization 316. The recovered data (i.e., received data) is stored in receive buffer 320 to await transmission to link layer 308 via receive interface 336.

[0052] In one or more embodiments, reference clock generator 334 is configured to generate local reference clock 342 based on a crystal oscillator, here crystal oscillator 344. In one embodiment, the frequency of crystal oscillator 344 may be selected to be a multiple (even or odd) of the expected frequency associated with the shared transmission medium coupled to interface circuit 328. As a non-limiting example, for a twisted single pair cable used in 10SPE Ethernet, the transmission frequency may be 12.5 megahertz, the frequency of crystal oscillator 344 may be 25 megahertz, the frequency of local reference clock 342 may be 5 megahertz, and the frequency of local clock 340 may be 2.5 megahertz.

[0053] A local reference clock 342 is provided to oversampling 314, which is configured to oversample a signal including received data coming from a shared transmission medium using local reference clock 342. In the embodiment shown in Figure 3, local reference clock 342 is optionally provided to transmit data path 306 for sending transmit data to the shared transmission medium.

[0054] As described above, clock divider 330 is configured to generate local clock 340 in response to local reference clock 342. In one embodiment, clock divider 330 is configured to divide local reference clock 342 in response to one or more control bits (not shown). In one embodiment, the control bits may be one or more bits that set an integer divider that defines the relationship between local reference clock 342 and local clock 340. In one embodiment, the control bits may be set by a user (e.g., programmed using, but not limited to, a design interface) and / or the control bits may be set by a controller, i.e., a microcontroller that implements one or more portions of a network protocol stack, such as, but not limited to, a link layer.

[0055] In one or more embodiments, receive interface 336 may include, among other lines, output 350, receive reference clock line 322, receive data line 312, and receive clock input 354. Additionally, transmit interface 338 may include transmit reference clock line 326, and Biden The local clock 340 may include a transmit clock input 356. The local clock 340 is provided to the receive reference clock line 322 and the transmit reference clock line 326 by the reference clock line 324 and an output 350 of the receive interface 336. The local clock 340 is further provided to the receive clock input 354 and the transmit clock input 356 (respective inputs of the link layer 308) at the receive interface 336 and the transmit interface 338, respectively. By way of non-limiting example, in various embodiments, the reference clock line 324 may include one or more bond wires or integral conductors.

[0056] In particular, the bit rate of data at the receiving interface 336 and the bit rate at the transmitting interface 338 may be the same. Furthermore, the respective bit rates of the receiving interface 336 and the transmitting interface 338 may be different from each other. 8 It may be the same as or later than that specified in the interface definition implemented by

[0057] In a contemplated use case, the interfaces implemented by receive interface 336 and transmit interface 338 may specify that PHY 302 should provide a clock for each of the transmit and receive data paths. In the disclosed embodiment, receive interface 336 and transmit interface 338 operate from a common clock, namely, local clock 340, so that receive reference clock line 322 and transmit reference clock line 326 may be driven by the same line, namely, reference clock line 324. In this example, such an arrangement frees up inputs on PHY 302, here 348 and input 358.

[0058] In some embodiments, input 348 may be used to implement a control data path (e.g., for control signaling) between PHY 302 and functions (e.g., other functions 106 of FIG. 1 ) that are localized somewhere other than link layer 308 (e.g., implemented in a device and / or sub-layer, without limitation). Characterized in another way, input 348 may be used to implement a control data path that is separate from receive interface 336 and transmit interface 338. In one embodiment, a control data path may be implemented between PHY 302 and functions that are localized anywhere in a network protocol stack, including but not limited to the link layer. In one embodiment, a control data path may be implemented between PHY 302 and functions and devices that are not part of a network protocol stack and that are specific to a certain type of application (e.g., without limitation, an automotive network, a building network, a transportation control network, a lighting network), as a non-limiting example.

[0059] In the embodiment of Figure 3, input 348 is operatively coupled to time synchronization 332, which together form part of a control data path 352 that can be used for control cycles related to medium access tuning. Another control data path is formed, in part, by input 358 and time synchronization 332. In Figure 3, input 358 can be part of transmit interface 338 or receive interface 336.

[0060] In this case, the time synchronization 332 is configured to generate a control signal 346 usable for time synchronization of medium access tuning. As a non-limiting example, the control signal 346 may include an event related to a time-aware protocol, such as an event indicating the start of a scheduled transmission opportunity. As another non-limiting example, the control signal 346 may include an event related to a traffic shaping protocol, such as the start of a transmission opportunity for time-sensitive data (regular traffic (e.g., but not limited to, audio frames, sensor polls) where deterministic latency is important), or best-effort data (non-regular data (e.g., but not limited to, firmware updates, audio control signals) where latency is not important but starvation should be avoided). In this manner, the control signal 346 may be or be related to one or more control cycles of the PHY 302, including, but not limited to, control cycles for a time-aware protocol, a traffic shaping protocol, and physical layer collision avoidance.

[0061] Those skilled in the art will recognize many advantages and benefits of the embodiments disclosed herein. By way of non-limiting example, a control data path may be added to a PHY architecture suitable for a specified interface without adding additional inputs and / or outputs. By way of non-limiting example, the control path may be used for communication between the PHY and the link layer, communication between the PHY and elsewhere in the network protocol stack other than the link layer, and communication between the PHY and other devices in a system or subsystem.

[0062] FIG. 4 shows a flowchart of a data reception process 400 according to one or more embodiments. At operation 402, process 400 begins receiving data from a shared transmission medium. The data reception may be performed at a physical layer device, such as PHY 102 or PHY 302. In one embodiment, the shared transmission medium is a twisted single-pair Ethernet cable, and the physical layer device is configured for 10 megabits per second communication over the shared transmission medium. At operation 404, process 400 moves the received data toward an interface configured to operably couple the physical layer device to a link layer device. In one embodiment, the interface uses exclusive collision avoidance signaling. In one embodiment, the link layer device is a medium access control device. While moving the received data at operation 404, at operation 406, process 400 traverses from a remote clock domain to a local clock domain of the physical layer device. In one embodiment, the received data traverses to the local clock domain after it is recovered. In another embodiment, the received data traverses to the local clock domain while it is being recovered. In operation 408, the process 400 provides the received data, now in the local clock domain, to an interface for transmission to the link layer.

[0063] In this disclosure, characterizations of something as "typical," "conventional," or "known" do not necessarily mean that it is disclosed in the prior art or that the discussed aspect is recognized in the prior art, or that it is widely known, well understood, or routinely used in the relevant field.

[0064] The terms used in this disclosure, and particularly in the appended claims (e.g., the body of the appended claims), are generally intended as "open" terms (e.g., the term "including" should be interpreted as "including, but not limited to," the term "having" should be interpreted as "having at least," the term "including" should be interpreted as "including, but not limited to," etc.).

[0065] Additionally, if a specific number of introduced claim recitations is intended, such intent will be explicitly recited in the claim; absent such recitation, no such intent exists. For example, as an aid to understanding, the following appended claims may include the use of the introductory phrases "at least one" and "one or more" to introduce claim recitations. However, the use of such phrases should not be construed as introducing a claim recitation with the indefinite article "a" or "an" limiting any particular claim including such introduced claim recitations to embodiments including only one of such recitations (e.g., "a" and / or "an" should be construed to mean "at least one" or "one or more"). The same applies to the use of definite articles used to introduce claim recitations, even if the same claim includes the introductory phrases "one or more" or "at least one" and an indefinite article such as "a" or "an."

[0066] Additionally, even when a particular number of introduced claim recitations is explicitly recited, those skilled in the art will recognize that such recitation should be interpreted to mean at least the recited number (e.g., the explicit recitation of "two recitations" without other modifiers means at least two recitations or more than two recitations). Furthermore, when conventions similar to "at least one of A, B, and C, etc." or "one or more of A, B, and C, etc." are used, it is generally intended that such structures include A only, B only, C only, A and B together, A and C together, B and C together, or A, B, and C together.

[0067] Furthermore, any disjunction or phrase presenting two or more alternative terms, whether in the description, claims, or drawings, should be understood to contemplate the possibility of including one of the terms, either of the terms, or both terms. For example, the phrase "A or B" should be understood to include the possibilities of "A" or "B" or "A and B."

[0068] Further non-limiting embodiments of the present disclosure are as follows.

[0069] Embodiment 1: A system comprising: a physical layer side receive data path configured to move receive data toward a link layer side receive data path; and a physical layer side transmit data path configured to move transmit data toward a shared transmission medium, wherein the receive data path and the transmit data path are in a first clock domain.

[0070] Embodiment 2: The system of embodiment 1, further comprising a control data path.

[0071] Embodiment 3: A system as described in any of embodiments 1 and 2, wherein the control data path is configured to move control data to and from the physical layer of the system.

[0072] Embodiment 4: A system according to any one of embodiments 1 to 3, wherein the control data path is configured to move control data between a physical layer of the system and an application layer of a network protocol stack.

[0073] Embodiment 5: A system described in any of embodiments 1 to 4, wherein the control data path is configured to move control data between a physical layer of the system and a device that is separate from the network protocol stack.

[0074] Embodiment 6: A system described in any of embodiments 1 to 5, wherein the control data path can be used for one or more control cycles that involve moving control data to or from the physical layer.

[0075] Embodiment 7: A system described in any of embodiments 1 to 6, wherein one of the one or more control cycles is associated with one of a time-aware protocol, a traffic shaping protocol, and a physical layer collision avoidance protocol.

[0076] Embodiment 8: A system described in any of embodiments 1 to 7, wherein the physical layer side receive data path comprises a first portion in a second clock domain, a second portion in a first clock domain, and a transition boundary across which receive data moved by the physical layer side receive data path crosses from the second clock domain to the first clock domain.

[0077] Embodiment 9: A circuit of a physical layer device comprising: a local clock generator configured to generate a local clock; a receive circuit and a transmit circuit, each of which is operably coupled to an output of the local clock generator and configured for clocking by the local clock; and one or more outputs, the one or more outputs including a first output operably coupled to the clock generator and configured to propagate the local clock.

[0078] Embodiment 10: The circuit of embodiment 9, wherein the local reference clock generator is operably coupled to the output of the local clock generator and configured to generate the local reference clock in response to the local clock. Further, the local clock generator is operably coupled to the output of the local reference clock generator and configured to generate the local clock in response to the local reference clock.

[0079] Embodiment 11: A circuit described in any of embodiments 9 and 10, further comprising an interconnect, the interconnect configured to operably couple the first output to a receive clock input of the link layer device and to operably couple the first output to a transmit clock input of the link layer device.

[0080] Embodiment 12: A circuit according to any one of embodiments 9 to 11, wherein the one or more outputs include a second output, and the second output is assigned to a signal for exclusive collision signaling.

[0081] Embodiment 13: A circuit described in any of embodiments 9 to 12, further comprising one or more inputs, the one or more inputs including a first input operably coupled to a transmission circuit, the first input being assigned to a signal for control signaling.

[0082] Embodiment 14: The circuit described in any of embodiments 9 to 13, further comprising an interconnect, the interconnect configured to operably couple the first input to one or more devices above the link layer of the network protocol stack.

[0083] Embodiment 15: The circuit of any one of embodiments 9 to 14, further comprising an interface circuit for operably coupling to a shared transmission medium.

[0084] Embodiment 16: The circuit of any one of embodiments 9 to 15, wherein one of the one or more devices is a time synchronization circuit.

[0085] Embodiment 17: A circuit described in any of embodiments 9 to 16, wherein at least one output of the one or more outputs is configured for exclusive collision signaling.

[0086] Embodiment 18: Further comprising an interconnection, the interconnection having at least one for exclusive collision signaling. output to an input of a link layer device for exclusive collision signaling.

[0087] Embodiment 19: The circuit of any one of embodiments 9 to 18, further comprising a second clock generator configured to generate a local reference clock.

[0088] Embodiment 20: The circuit of any one of embodiments 9 to 19, wherein the local clock generator is configured to generate the local clock in response to a local reference clock.

[0089] Embodiment 21: A circuit described in any of embodiments 9 to 20, wherein the receiving circuit comprises an oversampling circuit configured to receive a local reference clock and a synchronization circuit configured to receive a local clock.

[0090] Embodiment 22: A method, comprising: initiating data reception from a shared transmission medium; and moving the received data toward an interface for operatively coupling to a link layer, wherein moving the received data includes crossing the received data from a remote clock domain to a local clock domain of a physical layer device.

[0091] Embodiment 23: The method of embodiment 22, wherein the step of shifting the received data further includes the step of oversampling the data received from the shared transmission medium.

[0092] Embodiment 24: The method of any of embodiments 22 and 23, wherein the step of shifting the received data further includes a step of performing digital clock and data recovery using the oversampled data.

[0093] Embodiment 25: The method of any one of embodiments 22 to 24, further comprising providing the received data to an interface for transmission to the link layer.

[0094] While the present disclosure has been described herein with reference to certain illustrated embodiments, those skilled in the art will recognize and appreciate that the present invention is not so limited. Rather, numerous additions, deletions, and modifications can be made to the illustrated and described embodiments without departing from the scope of the invention as claimed below, along with their legal equivalents. In addition, features of one embodiment can be combined, as contemplated by the inventor, with features of other disclosed embodiments and still fall within the scope of the present disclosure.

Claims

1. 1. A system comprising: a physical layer receive data path configured to move received data toward a link layer receive data path; a physical layer transmission data path configured to move transmission data toward a shared transmission medium; a clock generator operably coupled to the physical layer receive data path and the physical layer transmit data path, the clock generator configured to generate a local clock defining a first clock domain; a second portion of the receive data path and the transmit data path are in the first clock domain, and the first portion of the receive data path is in a second clock domain, the second clock domain being different from the first clock domain, and the second clock domain being defined by a remote clock.

2. The system of claim 1 further comprising a control data path.

3. The system of claim 2 , wherein the control data path is configured to move control data to and from the physical layer of the system.

4. The system of claim 3 , wherein the control data path is configured to move the control data between the physical layer of the system and an application layer of a network protocol stack.

5. The system of claim 3 , wherein the control data path is configured to move the control data between the physical layer of the system and a device that is separate from a network protocol stack.

6. The system of claim 3 , wherein the control data path can be used for one or more control cycles involving moving control data to or from the physical layer.

7. The system of claim 6 , wherein one of the one or more control cycles is associated with one of a time-aware protocol, a traffic shaping protocol, and a physical layer collision avoidance protocol.

8. The physical layer side receiving data path is a first portion in a second clock domain; a second portion in the first clock domain; 2. The system of claim 1, wherein receive data moved by the physical layer side receive data path comprises a transition boundary crossing from the second clock domain to the first clock domain.

9. A circuit for a physical layer device, comprising: a local clock generator configured to generate a local clock; a receive circuit and a transmit circuit, each of the receive circuit and the transmit circuit operatively coupled to an output of the local clock generator and configured for clocking by the local clock; one or more outputs, the one or more outputs including a first output operatively coupled to the clock generator and configured to propagate the local clock; an interconnect configured to operably couple the first output to a receive clock input of a link layer device and to operably couple the first output to a transmit clock input of the link layer device.

10. 10. The circuit of claim 9, wherein the one or more outputs include a second output, the second output being assigned to a signal for exclusive collision signaling.

11. 10. The circuit of claim 9, further comprising one or more inputs, the one or more inputs including a first input operably coupled to the transmission circuit, the first input assigned to a signal for control signaling.

12. 12. The circuit of claim 11, further comprising an interconnect configured to operatively couple the first input to one or more devices above a link layer of a network protocol stack.

13. The circuit of claim 12 further comprising an interface circuit for operably coupling to a shared transmission medium.

14. The circuit of claim 13 , wherein one of the one or more devices is a time synchronization circuit.

15. 10. The circuit of claim 9, wherein at least one output of the one or more outputs is configured for exclusive collision signaling.

16. 16. The circuit of claim 15, further comprising an interconnect configured to operatively couple the at least one output for exclusive collision signaling to an input of a link layer device for exclusive collision signaling.

17. The circuit of claim 9 , further comprising a reference clock generator configured to generate a local reference clock.

18. 18. The circuit of claim 17, wherein the local clock generator is configured to generate the local clock in response to the local reference clock.

19. The receiving circuit 18. The circuit of claim 17, comprising: an oversampling circuit configured to receive the local reference clock; and a synchronization circuit configured to receive the local clock.

20. 1. A method comprising: initiating data reception from a shared transmission medium; moving the received data towards an interface for operatively coupling to a link layer, said moving the received data comprising traversing the received data from a remote clock domain to a local clock domain of a physical layer device; the local clock domain includes a first portion of a receive data path of the physical layer device; The method, wherein the remote clock domain includes a second portion of the receive data path of the physical layer device.

21. The step of moving the received data includes:

21. The method of claim 20, further comprising oversampling data received from the shared transmission medium.

22. The step of moving the received data includes:

22. The method of claim 21, further comprising performing digital clock and data recovery using the oversampled data.

23. 23. The method of claim 22, further comprising providing the received data to the interface for transmission to the link layer.

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