Receiver circuit performing adaptive equalization and system comprising the same

Abstract

A receiver circuit includes an equalizer configured to generate an equalized signal by equalizing an input data signal transmitted through a communication channel based on an equalization coefficient, a clock data recovery circuit configured to generate a data clock signal and an edge clock signal based on the equalized signal, generate a data sample signal including a plurality of data bits by sampling the equalized signal in synchronization with the data clock signal, and generate an edge sample signal including a plurality of edge bits by sampling the equalized signal in synchronization with the edge clock signal, and an equalization control circuit configured to control the equalization coefficient by comparing the plurality of data bits and the plurality of edge bits.

Description

[0001] Cross-references of related applications

[0002] Korean Patent Application No. 10-2020-0103524, filed on August 18, 2020 with the Korean Intellectual Property Office and entitled “Receiver Circuit for Performing Adaptive Equalization and System Including the Receiver Circuit”, is incorporated herein by reference in its entirety. Technical Field

[0003] The embodiments generally relate to semiconductor integrated circuits, and more specifically to receiver circuitry that performs adaptive equalization and systems including such receiver circuitry. Background Technology

[0004] Electronic devices perform functions based on the operation of various electronic circuits included within them. Electronic devices can operate independently or in communication with other electronic devices. With the increasing amount of data exchanged between electronic devices, communication circuits capable of high-speed signal transmission and reception are being adopted. Electronic devices are interconnected via communication channels, which transmit signals for transmission and reception between them. The bandwidth of communication channels may be limited, and signals on these channels may be distorted due to various factors such as the skin effect and dielectric loss. Therefore, the quality of signals transmitted at high speeds may degrade. Summary of the Invention

[0005] The embodiment relates to a receiver circuit, comprising: an equalizer configured to generate an equalized signal by equalizing an input data signal transmitted through a communication channel based on an equalization coefficient; a clock data recovery circuit configured to generate a data clock signal and an edge clock signal based on the equalized signal, generate a data sample signal including multiple data bits by sampling the equalized signal synchronously with the data clock signal, and generate an edge sample signal including multiple edge bits by sampling the equalized signal synchronously with the edge clock signal; and an equalization control circuit configured to control the equalization coefficient by comparing the multiple data bits and the multiple edge bits.

[0006] Embodiments also relate to an electronic system comprising a communication channel, a first device configured to output a transmission data signal to the communication channel based on transmission data, and a second device comprising a receiver circuit connected to the communication channel. The receiver circuit can comprise an equalizer configured to generate an equalized signal by equalizing an input data signal transmitted through the communication channel based on equalization coefficients, a clock data recovery circuit configured to generate a data clock signal and an edge clock signal based on the equalized signal, generate a data sample signal comprising a plurality of data bits by sampling the equalized signal in synchronization with the data clock signal, and generate an edge sample signal comprising a plurality of edge bits by sampling the equalized signal in synchronization with the edge clock signal, and an equalization control circuit configured to control the equalization coefficients by comparing the plurality of data bits and the plurality of edge bits.

[0007] Embodiments also relate to a receiver circuit comprising an equalizer configured to generate an equalized signal by equalizing an input data signal transmitted through a communication channel based on equalization coefficients, a data sampler configured to generate a data sample signal comprising a plurality of data bits by sampling the equalized signal in synchronization with a data clock signal, an edge sampler configured to generate an edge sample signal comprising a plurality of edge bits by sampling the equalized signal in synchronization with an edge clock signal, a clock recovery circuit configured to generate the data clock signal and the edge clock signal based on the data sample signal and the edge sample signal, a state monitor configured to generate a plurality of equalization state values by bit-wise comparing the plurality of data bits and the plurality of edge bits, an accumulator configured to generate a state accumulated value by accumulating the plurality of equalization state values during an accumulation time interval, and control logic configured to control the equalization coefficients based on the state accumulated value. BRIEF DESCRIPTION OF DRAWINGS

[0008] Features will become apparent to those of ordinary skill in the art upon examination of the following detailed description of example embodiments in conjunction with the accompanying drawings, in which:

[0009] Figure 1 is a block diagram illustrating a system comprising a receiver circuit according to an example embodiment.

[0010] Figure 2 is a block diagram illustrating an example embodiment of a clock data recovery circuit comprised in a receiver circuit according to an example embodiment.

[0011] Figure 3 is a flowchart illustrating an equalization control method according to an example embodiment.

[0012] Figure 4 is a block diagram illustrating an example embodiment of an equalization control circuit comprised in a receiver circuit according to an example embodiment.

[0013] Figure 5 is a circuit diagram illustrating an example embodiment of an equalizer included in a receiver circuit according to an example embodiment.

[0014] Figure 6 is a graph illustrating a frequency response according to an equalization state of an equalizer.

[0015] Figure 7 is a graph for describing inter-symbol interference (ISI) of a signal transmitted through a communication channel.

[0016] Figure 8A and Figure 8B is a graph for describing a relationship between sampled bits in an under-equalization state.

[0017] Figure 9A and Figure 9B is a graph for describing a relationship between sampled bits in an over-equalization state.

[0018] Figure 10 is a timing chart illustrating an equalized signal in a good equalization state.

[0019] Figure 11 is a graph illustrating an example embodiment of an equalization control circuit included in a receiver circuit according to an example embodiment.

[0020] Figure 12 and Figure 13 is a timing chart illustrating an operation of the equalization control circuit of Figure 11

[0021] Figure 14 is a graph illustrating an example of an equalization coefficient and a state accumulation value.

[0022] Figure 15A and Figure 15B is a graph illustrating an example embodiment of adjusting an equalization coefficient based on a state accumulation value.

[0023] Figure 16 is a graph illustrating an example embodiment of an equalization control circuit included in a receiver circuit according to an example embodiment.

[0024] Figure 17 is a timing chart illustrating an example embodiment of a deserializing operation of a clock data recovery circuit included in a receiver circuit according to an example embodiment.

[0025] Figure 18 is a graph illustrating an example embodiment of a state monitor included in a receiver circuit according to an example embodiment.

[0026] Figure 19 ​is a block diagram illustrating a system including a receiver circuit according to an example embodiment.

[0027] Figure 20 is a diagram illustrating an example operation of a transmission equalizer included in Figure 19 the system of

[0028] Figure 21 is a block diagram illustrating a system including a receiver circuit according to an example embodiment.

[0029] Figure 22 is a diagram illustrating Figure 21 an operation mode of the system of

[0030] Figure 23 is a block diagram illustrating a system including a receiver circuit according to an example embodiment.

[0031] Figure 24 is a block diagram illustrating an example embodiment of an interface employable in a computing system according to an example embodiment. DETAILED DESCRIPTION

[0032] Figure 1 is a block diagram illustrating a system including a receiver circuit according to an example embodiment.

[0033] Referring to Figure 1 , the system 1000 includes a transmitter circuit 1100, a receiver circuit 1200, and a communication channel 10 connecting the transmitter circuit 1100 and the receiver circuit 1200.

[0034] The transmitter circuit 1100 can include a transmission driver DR outputting a transmission data signal STD to the communication channel 10 based on transmission data TDT.

[0035] The receiver circuit 1200 can include a reception buffer BF, an equalizer EQZ 100, a clock data recovery circuit CDR 200, and an equalization control circuit EQCON 300.

[0036] The reception buffer BF can buffer and output an input data signal SRD transmitted through the communication channel 10. The equalizer 100 can generate an equalized signal SEQ by equalizing the input data signal SRD based on an equalization coefficient CEQ. According to an example embodiment, the reception buffer BF can be omitted, and the equalizer 100 can directly receive the input data signal SRD from the communication channel 10. Reference will be made to Figure 5 and Figure 6 Example embodiments of the equalizer 100 are described below.

[0037] By using the equalized signal SEQ, the clock data recovery circuit 200 can internally generate a data clock signal (DCK, see Figure 2) and an edge clock signal (ECK, see Figure 2 The clock data recovery circuit 200 can generate a data sample signal RDT including a plurality of data bits by sampling the equalized signal SEQ in synchronization with the data clock signal DCK. Further, the clock data recovery circuit 200 can generate an edge sample signal EDT including a plurality of edge bits by sampling the equalized signal SEQ in synchronization with the edge clock signal ECK. Example embodiments of the clock data recovery circuit 200 will be described below with reference to Figure 2

[0038] The equalization control circuit 300 can control the equalization coefficient CEQ by comparing the plurality of data bits in the data sample signal RDT and the plurality of edge bits in the edge sample signal EDT.

[0039] As will be described below with reference to Figures 3-18 The equalization control circuit 300 can generate a plurality of equalization state values by bit-by-bit comparing the plurality of data bits and the plurality of edge bits, and can generate a state accumulated value by accumulating the equalization state values during an accumulated time interval.

[0040] The receiver circuit 1200 according to an example embodiment can reduce jitter of the equalized signal SEQ with high precision by digitally performing adaptive equalization based on data bits and edge bits, and thus can enhance the performance of the receiver circuit 1200 and the system 1000 including the receiver circuit 1200.

[0041] Figure 2 is a block diagram illustrating an example embodiment of a clock data recovery circuit included in a receiver circuit according to an example embodiment.

[0042] Referring to Figure 2 , the clock data recovery circuit 200 can include a data sampler DSMP 210, an edge sampler ESMP 220, a clock recovery circuit CRCV 230, a first deserializer DDES 250, and a second deserializer EDES 260. According to an example embodiment, the first deserializer 250 and the second deserializer 260 can be omitted or arranged outside the receiver circuit 1200. In an example embodiment, the first deserializer 250 and the second deserializer 260 can be included in the data sampler 210 and the edge sampler 220, respectively.

[0043] The data sampler 210 can generate a data sample signal RDT including a plurality of data bits by sampling the equalized signal SEQ in synchronization with the data clock signal DCK. The edge sampler 220 can generate an edge sample signal EDT including a plurality of edge bits by sampling the equalized signal SEQ in synchronization with the edge clock signal ECK.

[0044] ​The clock recovery circuit 230 can generate a data clock signal DCK and an edge clock signal ECK based on the data sample signal RDT and the edge sample signal EDT. The data clock signal DCK and the edge clock signal ECK can have a phase difference of about 180 degrees.

[0045] The first deserializer 250 can generate a plurality of parallel data sample signals RDT1 to RDTn by deserializing the data sample signal RDT. The second deserializer 260 can generate a plurality of parallel edge sample signals EDT1 to EDTn by deserializing the edge sample signal EDT.

[0046] The clock recovery circuit 230 can include a feedback loop (such as a phase-locked loop (PLL), a delay-locked loop (DLL), etc.) to search and fix the phase and frequency of the output clock signal. The data sampler 210, the edge sampler 220, the first deserializer 250, and the second deserializer 260 can include flip-flops, clock dividers, multiplexers, etc. that latch input signals in synchronization with the clock signal.

[0047] In an example embodiment, the equalization control circuit 300 can control the equalization coefficient CEQ based on the data sample signal RDT and the edge sample signal EDT. In an example embodiment, the equalization control circuit 300 can control the equalization coefficient CEQ based on at least one of the parallel data sample signals RDT1 to RDTn and at least one of the parallel edge sample signals EDT1 to EDTn.

[0048] Figure 3 is a flowchart illustrating an equalization control method according to an example embodiment, Figure 4 is a block diagram illustrating an example embodiment of an equalization control circuit included in a receiver circuit according to an example embodiment.

[0049] Referring to Figure 3 and Figure 4 The equalization control circuit 300 can include a state monitor SMON 400, an accumulator ACC 500, and a control logic CLOG 600.

[0050] The state monitor 400 can generate a plurality of equalization state values by bit-by-bit comparing a plurality of data bits included in the data sample signal RDT and a plurality of edge bits included in the edge sample signal EDT (S100). The plurality of equalization state values can be included in a state monitor signal STT output from the state monitor 400. The state monitor 400 can include at least one XOR gate configured to perform an XOR logical operation bit-by-bit on the plurality of data bits and the plurality of edge bits to output the plurality of equalization state values, as will be described below with reference to Figure 11 and Figure 16

[0051] ​The accumulator 500 can generate a state accumulated value AVL by accumulating the equalization state value during an accumulation time interval (S200), and the control logic 600 can control the equalization coefficient CEQ based on the state accumulated value AVL (S300). The state accumulated value AVL can be included in an accumulator output signal SAC provided from the accumulator 500 to the control logic 600. The control logic 600 can generate a reset signal RST and an accumulation enable signal CEN to be provided to the accumulator 500. The accumulator 500 can be initialized in response to the reset signal RST, and the accumulation time interval can be defined by an activation time interval of the accumulation enable signal CEN, as will be described below with reference to Figure 13 The accumulator output signal SAC can maintain the state accumulated value AVL after the accumulation time interval until the accumulator 500 is again reset in response to the reset signal RST.

[0052] Figure 5 is a circuit diagram illustrating an example embodiment of an equalizer included in a receiver circuit according to an example embodiment, Figure 6 is a graph illustrating a frequency response according to an equalization state of the equalizer.

[0053] Figure 5 A circuit of the equalizer 101 according to an example embodiment is conceptually illustrated. The equalizer 101 can equalize an input data signal SRD and generate an equalization signal SEQ.

[0054] The equalizer 101 can be implemented with at least one frequency-dependent source degeneration amplifier as illustrated in Figure 5 The structure of the equalizer 101 can be well suited for one-dimensional control of equalization strength.

[0055] Referring to Figure 5 , the equalizer 101 can include a resistor R D , a pair of transistors M1 and M2, a variable resistor array Rs, a variable capacitor array Cs, and current sources CS1 and CS2. The resistor R D may be connected between a power supply voltage VDD and nodes N1 and N2. The current sources CS1 and CS2 can be connected between nodes N3 and N4 and a ground voltage VSS. The pair of transistors M1 and M2 can be connected to the power supply voltage VDD through the resistor R D and to the ground voltage VSS through the current sources CS1 and CS2, respectively. The transistors M1 and M2 can be coupled through the variable resistor array Rs and the variable capacitor array Cs, which are coupled to each other in parallel between the nodes N3 and N4.

[0056] In an example embodiment, the variable resistor array Rs can include a plurality of resistors, which can be coupled in parallel to each other by a switch, respectively, such that each switch is coupled in series to each resistor. The opening and closing of the switches can be controlled by the numerical value of the equalization coefficient CEQ.

[0057] In an example embodiment, the variable capacitor array Cs can include a plurality of capacitors, which can be coupled in parallel by a switch, respectively, such that each switch is coupled in series to each capacitor. The opening and closing of the switches can be controlled by the numerical value of the equalization coefficient CEQ.

[0058] Resistor R D And the resistance value of the variable resistor array Rs and the capacitance of the variable capacitor array Cs can determine the DC gain, the pole position, and the zero position of the equalizer 101.

[0059] Figure 6 It is shown how the gain of the equalizer 101 adaptively changes according to the equalization state which can be determined according to an example embodiment. In Figure 6 , the horizontal axis represents the frequency of the input data signal SRD, and the vertical axis represents the DC gain of the equalizer 101.

[0060] Referring to Figure 6 , the equalizer 101 can have a characteristic defined by the following equation:

[0061] A0 = R D / Rs

[0062] fz = 1 / (Cs x Rs)

[0063] f1 = gm / Cs

[0064] f2 = 1 / (Cs x R D )

[0065] In the above equations, A0 is the DC gain of the equalizer 101, fz is the zero position of the equalizer 101, f1 and f2 are the pole positions of the equalizer 101, and gm is the transconductance of the transistors M1 and M2. In addition, R D is the resistance of the resistor R D , Rs is the resistance of the variable resistor array Rs, and Cs is the capacitance of the variable capacitor array Cs.

[0066] The zero position fz determines the frequency band to be boosted by the equalizer 101, and the DC gain A0 controls the equalization strength. Once the data rate of the input data signal SRD is determined, the zero position fz can be set by manual control or an automatic band selection circuit. Then, Figure 1 The equalization control circuit 300 in the above equation can adjust the equalization coefficient CEQ to change the DC gain A0 and obtain the maximum eye opening in a non-return-to-zero (NRZ) data pattern.

[0067] Generally, since the DC gain A0 depends on the resistances R D and Rs, the DC gain A0 of the equalizer 101 can be controlled by adjusting the value of the resistance Rs using the equalization coefficient CEQ. In the present example embodiment, the switches in the array of variable resistors Rs are configured such that an increase in the equalization coefficient CEQ results in an increase in the resistance Rs, and thus a decrease in the DC gain A0. The decrease in the DC gain A0 effectively results in a relative increase in the high frequency gain for the high frequency pattern. Thus, an increase in the equalization coefficient CEQ results in a relative increase in the high frequency gain for the high frequency pattern relative to the low frequency gain for the low frequency pattern. On the other hand, a decrease in the equalization coefficient CEQ results in a decrease in the resistance Rs and the DC gain A0, and thus a relative decrease in the high frequency gain for the high frequency pattern relative to the low frequency gain for the low frequency pattern.

[0068] Figure 7 is a diagram for describing inter-symbol interference (ISI) of a signal transmitted through a communication channel.

[0069] In Figure 7 , the unit interval UI represents a time interval between two adjacent data bits of the input data signal SRD. The unit interval UI can correspond to a cycle period of the data clock signal DCK and the edge clock signal ECK. The unit interval UI can be maintained after the clock recovery circuit 230 in Figure 2 fixes the data clock signal DCK and the edge clock signal ECK.

[0070] In Figure 7 , tdn-3, tdn-2, and tdn-1 represent data sampling time points, and ten represents an edge sampling time point. Thus, the data sampling time points tdn-3, tdn-2, and tdn-1 correspond to edges of the data clock signal DCK, and the edge sampling time point ten corresponds to an edge of the edge clock signal ECK.

[0071] The levels of the data symbols or data bits DBn-3, DBn-2, and DBn-1 at 3.5UI, 2.5UI, and 1.5UI before the edge sampling time point ten can affect the edge EG1 at the edge sampling time point ten due to inter-symbol interference (ISI).

[0072] In an under-equalized state of the equalizer, when the preceding data bit is 0, the original edge EG1 can move to the delayed edge EG2, and when the preceding data bit is 1, the original edge EG1 can move to the preceding edge EG3.

[0073] On the contrary, in the over-equalization state of the equalizer, when the preceding data bit is 1, the original edge EG1 can move to the delayed edge EG2, and when the preceding data bit is 0, the original edge EG1 can move to the preceding edge EG3.

[0074] Among the preceding data bits DBn-3, DBn-2 and DBn-1, the data bit DBn-1 one and a half UI before causes the most significant ISI to the original edge EG1 at the edge sampling time point ten. According to the example embodiment, the equalization state or the equalization signal SEQ of the equalizer can be determined by comparing the edge bit and the data bit that most significantly affects the edge bit. Thus, the equalization state of the equalizer can be determined by comparing each data bit with the corresponding one edge bit that is sampled one and a half unit intervals (i.e., 1.5 UI) after the data bit is sampled.

[0075] Figure 8A and Figure 8B is a diagram for describing the relationship between the sampling bits in the under-equalization state. Figure 9A and Figure 9B is a diagram for describing the relationship between the sampling bits in the over-equalization state. The under-equalization state and the over-equalization state are described in turn below.

[0076] Under-equalization state

[0077] Figure 8A The equalization signal SEQ1 of the low frequency pattern and the equalization signal SEQ2 of the high frequency pattern in the under-equalization state are shown. In Figure 8A , td1 to td5 denote data sampling times, and te1 to te4 denote edge sampling times.

[0078] will be described below with reference to Figure 7 , Figure 8A and Figure 8B . Note that, in Figure 8A , the data sampling point td3 is 1.5 UI before the edge sampling point te4. It should also be noted that, as described above in connection with Figure 7 , for the under-equalization state, when the preceding data bit is 0, the original edge EG1 can be delayed to the delayed edge EG2, and when the preceding data bit is 1, the original edge EG1 can be advanced to the preceding edge EG3.

[0079] Referring to Figure 8A , in the under-equalization state, in the equalization signal SEQ1 of the low frequency pattern, the edge corresponding to the edge sampling point te4 has a data bit value of 0 (logic low (L)) at the data sampling point td3, and thus it is delayed.

[0080] Referring to Figure 8AIn the underbalanced state, in the equalization signal SEQ2 of the high-frequency mode, the edge corresponding to the edge sampling point te4 has a data bit value of 1 (logic high level (H)) at the data sampling point td3, so it is advanced.

[0081] Figure 8B The above combination is shown. Figure 8A The results of the ISI are described.

[0082] Figure 8B Show Figure 8A The sampling results are obtained by comparing the reference voltage VREF with signal level V3 (at data sampling time point td3) and signal levels V1 and V2 (at edge sampling time point te4).

[0083] like Figure 8B As shown, whether it is the low-frequency mode equalization signal SEQ1 or the high-frequency mode equalization signal SEQ2, the data bits at data sampling time point td3 and the edge bits at edge sampling time point te4 can have the same logic level, that is, the same bit value, in the underbalanced state. In this case, the state accumulation value AVL can be increased by one (+1).

[0084] Over-equilibrium state

[0085] Figure 9A The equalization signal SEQ1 in the low-frequency mode and the equalization signal SEQ2 in the high-frequency mode are shown in the over-equalization state.

[0086] The following will refer to Figure 7 , Figure 9A and Figure 9B Describe it. Note that in Figure 9A In the data sample point td3, the edge sample point te4 is 1.5 UI ahead. It should also be noted that, as mentioned above... Figure 7 Specifically, for the over-balanced state, when the preceding data bit is 1, the original edge EG1 can be delayed to the delayed edge EG2, and when the preceding data bit is 0, the original edge EG1 can be advanced to the preceding edge EG3.

[0087] Reference Figure 9A In the over-equalized state, in the equalized signal SEQ1 of the low-frequency mode, the edge corresponding to the sampling time point te4 has a data bit value of 0 (logic low level (L)), so it is advanced.

[0088] Reference Figure 9A In the over-equalized state, in the equalized signal SEQ2 of the high-frequency mode, the edge corresponding to the sampling time point te4 has a data bit value of 1 (logic high level (H)), so it is delayed.

[0089] Figure 9BThe above combination is shown. Figure 9A The results of the ISI are described.

[0090] Figure 9B Show Figure 9A The sampling results are obtained by comparing the reference voltage VREF with the signal level V3 (at the data sampling time point td3) and the signal levels V1 and V2 (at the edge sampling time point te4).

[0091] like Figure 9B As shown, whether it is the low-frequency mode equalization signal SEQ1 or the high-frequency mode equalization signal SEQ2, the data bits at data sampling time point td3 and the edge bits at edge sampling time point te4 can have different logic levels, that is, different bit values, in the over-equalization state. In this case, the state accumulation value AVL can be reduced by -1.

[0092] Good equilibrium state

[0093] Figure 10 This is a timing diagram showing the equalization signal under good equalization conditions.

[0094] like Figure 10 As shown, in a well-balanced state, data sampling time points td1 to td5 can be located very close to the center of the corresponding data bit, and edge sampling time points te1 to te4 can be located very close to the edge of the data bit. Furthermore, the signal levels of the equalization signals SEQ1 and SEQ2 at edge sampling time points te1 to te4 can be substantially the same as the reference voltage VREF, and therefore the data bit at data sampling time point td3 and the data bit at edge sampling time point te4 can have the same bit value as in the underbalanced state or different bit values ​​as in the overbalanced state. Therefore, in a well-balanced state, the probability of being identified as an underbalanced state and the probability of being identified as an overbalanced state can be substantially the same.

[0095] According to the example embodiment, an equilibrium state value can be generated by comparing a data bit with the edge bit corresponding to that data bit, and the equilibrium state can be accurately determined by accumulating the equilibrium state value during the accumulation time interval.

[0096] Figure 11 This is a diagram illustrating an example embodiment of an equalization control circuit included in a receiver circuit according to an example embodiment.

[0097] Reference Figure 11 The equalization control circuit 301 may include a status monitor 401 and an accumulator 501. Figure 11 References are omitted in the text. Figure 4 The control logic is described, and may be omitted from the description. Figure 4Duplicate description.

[0098] The state monitor 401 can generate the state monitoring signal STT including a plurality of equalization state values by comparing a plurality of data bits included in the data sampling signal RDT with a plurality of edge bits included in the edge sampling signal EDT on a bit-by-bit basis.

[0099] The accumulator 501 can generate the state accumulation value AVL by accumulating the equalization state values during an accumulation time interval. The state accumulation value AVL can be included in an accumulator output signal SAC provided from the accumulator 501 to the control logic. The accumulator 501 can be initialized in response to the reset signal RST, and the accumulation time interval can be defined by an activation time interval of the accumulation enable signal CEN. The accumulator output signal SAC can maintain the state accumulation value AVL after the accumulation time interval until the accumulator 501 is again reset in response to the reset signal RST.

[0100] The state monitor 401 can include a delay circuit DEL 411, an XOR gate 412, and a flip-flop FF 413.

[0101] The delay circuit 411 can generate the delayed data sampling signal DRDT by delaying the data sampling signal RDT. In an example embodiment, the delay circuit 411 can delay the data sampling signal RDT by 1.5 UI to generate the delayed data sampling signal DRDT, as described above with reference to FIG. 3. Figures 8A-10

[0102] The XOR gate 412 can perform an XOR logical operation on the delayed data sampling signal DRDT and the edge sampling signal EDT. The XOR gate 412 can output a value 1 (i.e., a logical high level H) when two input bit values are equal, and output a value 0 (i.e., a logical low level L) when the two input bit values are not equal.

[0103] The flip-flop 413 can generate the state monitoring signal STT including a plurality of equalization state values by latching an output of the XOR gate 412. In an example embodiment, the flip-flop 413 can perform a latching operation in synchronization with the data clock signal DCK.

[0104] The accumulator 501 can include a counter, e.g., an up-down counter UDCNT, configured to generate the state accumulation value AVL based on the state monitoring signal STT. The up-down counter UDCNT can increase a stored value in the up-down counter UDCNT when the equalization state value in the state monitoring signal STT is 1, and decrease the stored value when the equalization state value is 0.

[0105] Figure 12 and Figure 13 are timing diagrams illustrating operations of the equalization control circuit of Figure 11 . In​Figure 12 In the equation, tdi (i is a natural number) denotes each data sampling time point, and tei denotes each edge sampling point. In the equation, tdi (i is a natural number) denotes each data sampling time point, and tei denotes each edge sampling point. Figure 13 In the equation, tdi (i is a natural number) denotes each data sampling time point, and tei denotes each edge sampling point. In the equation, tdi (i is a natural number) denotes each data sampling time point, and tei denotes each edge sampling point.

[0106] In the present example embodiment, the data sampling time points can correspond to rising edges of the data clock signal DCK, and the edge sampling time points can correspond to rising edges of the edge clock signal ECK.

[0107] Referring to Figure 2 , Figure 11 and Figure 12 , the data sampler 210 can generate a data sample signal RDT including a plurality of data bits DBn-2 to DBn+2 by sampling the equalization signal SEQ in synchronization with the data clock signal DCK. The edge sampler 220 can generate an edge sample signal EDT including a plurality of edge bits EBn-1 to EBn+3 by sampling the equalization signal SEQ in synchronization with the edge clock signal ECK. As shown in Figure 12 , the data clock signal DCK and the edge clock signal ECK can have a phase difference of about 180 degrees.

[0108] The delay circuit 411 can generate a delayed data sample signal DRDT by delaying the data sample signal RDT by 1.5UI. In this way, the delayed data sample signal DRDT and the edge sample signal EDT can be synchronized such that each edge bit and each data bit 1.5UI before can be aligned with a rising edge of the data clock signal DCK.

[0109] Figure 13 An example of bit values of the delayed data sample signal DRDT and the edge sample signal EDT is shown.

[0110] Referring to Figure 11 and Figure 13 , the XOR gate 412 can perform an XOR logical operation on the delayed data sample signal DRDT and the edge sample signal EDT. The XOR gate 412 can output a value of 1 when two corresponding bit values of the delayed data sample signal DRDT and the edge sample signal EDT are equal, and a value of 0 when the two corresponding bit values are different.

[0111] The flip-flop 413 can generate a state monitor signal STT including a plurality of equalization state values by latching an output of the XOR gate in synchronization with the data clock signal DCK.

[0112] As a result, the state monitor 401 of the equalization control circuit 301 can generate an equalization state value of 1 when the compared data bit and edge bit have equal values, and an equalization state value of 0 when the compared data bit and edge bit have different values.

[0113] The up-down counter UDCNT of the accumulator 501 can reset the stored value in the up-down counter UDCNT to the value 0 in response to the reset signal RST. The activation time interval TA of the accumulation enable signal CEN can correspond to the accumulation time interval described above. The up-down counter UDCNT can generate the state accumulation value AVL by accumulating the equalization state values included in the state monitoring signal STT during the accumulation time interval TA. The accumulator output signal SAC can maintain the state accumulation value AVL after the accumulation time interval TA until the accumulator 501 is reset again in response to the reset signal RST.

[0114] As a result, the equalization control circuit 301 can increase the state accumulation value AVL by one when the compared data bit and the edge bit have equal values, and can decrease the state accumulation value AVL by one when the compared data bit and the edge bit have different values.

[0115] Figure 14 is a graph showing examples of the equalization coefficient and the state accumulation value.

[0116] In Figure 14 , the horizontal axis represents time, and the vertical axis represents the value of the accumulator output signal SAC. Also, ta denotes the accumulation start time point, i.e., the activation time point of the accumulation enable signal CEN, and tb denotes the accumulation end time point, i.e., the deactivation time point of the accumulation enable signal CEN.

[0117] In an example embodiment, as Figure 14 shown, the first equalization coefficient value CEQ1 and the second equalization coefficient value CEQ2 of the equalization coefficient CEQ can correspond to the under-equalization state, the third equalization coefficient value CEQ3 of the equalization coefficient CEQ can correspond to the good equalization state, and the fourth equalization coefficient value CEQ4 and the fifth equalization coefficient value CEQ5 of the equalization coefficient CEQ can correspond to the over-equalization state.

[0118] When the state accumulation value AVL is greater than the first reference value NTH, Figure 4 The control logic 600 of the equalization control circuit 300 in may determine that the equalizer or the equalization signal SEQ is in the under-equalization state, and can increase the equalization coefficient CEQ to increase the equalization strength of the equalizer. In an example embodiment, when the first state accumulation value AVL1 corresponding to the first equalization coefficient value CEQ1 and the second state accumulation value AVL2 corresponding to the second equalization coefficient value CEQ2 are greater than the first reference value NTH, the control logic 600 can increase the equalization coefficient CEQ in the case of the under-equalization state.

[0119] In contrast, when the state accumulation value AVL is less than a second reference value NTL lower than the first reference value NTH, the control logic 600 can determine that the equalizer or the equalized signal SEQ is in an over-equalization state, and can decrease the equalization coefficient CEQ to reduce the equalization strength of the equalizer. In an example embodiment, when a fourth state accumulation value AVL4 corresponding to a fourth equalization coefficient value CEQ4 and a fifth state accumulation value AVL5 corresponding to a fifth equalization coefficient value CEQ5 are less than the second reference value NTL, the control logic 600 can decrease the equalization coefficient CEQ in the case of the over-equalization state.

[0120] When the state accumulation value AVL is between the first reference value NTH and the second reference value NTL, the control logic 600 can maintain the equalization coefficient CEQ without adjustment. In an example embodiment, when a third state accumulation value AVL3 corresponding to a third equalization coefficient value CEQ3 is between the first reference value NTH and the second reference value NTL, the control logic 600 can maintain the equalization coefficient CEQ in the case of the good equalization state.

[0121] Figure 15A and Figure 15B are diagrams illustrating example embodiments of adjusting the equalization coefficient based on the state accumulation value.

[0122] Referring to Figure 15A and Figure 15B , Figure 4 The control logic 600 in the equalizer 600 can adjust the equalization coefficient CEQ at each accumulation time interval (i.e., at the time points TA to 6TA).

[0123] In an example embodiment, as shown in Figure 15A , the control logic 600 can sequentially increase or decrease the equalization coefficient CEQ by comparing the state accumulation value AVL with the reference values NTH and NTL. In an example embodiment, when the initial equalization coefficient CEQ is an eleventh equalization coefficient CEQ11, the control logic 600 can sequentially decrease the equalization coefficient CEQ so that the equalization coefficient CEQ converges to a predetermined value, i.e., a fifth equalization coefficient value CEQ5 corresponding to the good equalization state, at the time point 6TA. As another example, when the initial equalization coefficient CEQ is a first equalization coefficient CEQ1, the control logic 600 can sequentially increase the equalization coefficient CEQ so that the equalization coefficient CEQ converges to the fifth equalization coefficient value CEQ5 corresponding to the good equalization state at the time point 4TA.

[0124] In an example embodiment, as shown in Figure 15BAs shown, the control logic 600 can adjust the equalization coefficient CEQ using a binary search method by comparing the state accumulation value AVL to the reference values NTH and NTL. In an example embodiment, the control logic 600 can increase the equalization coefficient CEQ from the eleventh equalization coefficient value CEQ11 to the third equalization coefficient value CEQ3 at the time point TA with a relatively large change width, decrease the equalization coefficient CEQ from the third equalization coefficient value CEQ3 to the seventh equalization coefficient value CEQ7 at the time point 2TA with a reduced change width, and so on. Through such a binary search method, the equalization coefficient CEQ can quickly converge to the fifth equalization coefficient value CEQ5 corresponding to a good equalization state at the time point 4TA.

[0125] Figure 16 FIG. 4 is a diagram illustrating an example embodiment of an equalization control circuit included in a receiver circuit according to an example embodiment.

[0126] Referring to Figure 16 , the equalization control circuit 302 can include a state monitor 402 and an accumulator 502. In Figure 16 , the control logic described with reference to Figure 4 is omitted, and descriptions duplicated with Figure 4 may be omitted.

[0127] The state monitor 402 can generate a state monitor signal STT including a plurality of equalization state values by comparing a plurality of data bits included in the data sample signal RDT and a plurality of edge bits included in the edge sample signal EDT on a bit-by-bit basis.

[0128] The accumulator 502 can generate a state accumulation value AVL by accumulating the equalization state values during an accumulation time interval. The state accumulation value AVL can be included in an accumulator output signal SAC provided from the accumulator 502 to the control logic. The accumulator 501 can be initialized in response to a reset signal RST, and the accumulation time interval can be defined by an activation time interval of an accumulation enable signal CEN. The accumulator output signal SAC can maintain the state accumulation value AVL after the accumulation time interval until the accumulator 501 is again reset in response to the reset signal RST.

[0129] The state monitor 402 can include a delay circuit DEL 421, an XOR gate 422, an XNOR gate 423, a first flip-flop FF1 424, and a second flip-flop FF2 425.

[0130] The delay circuit 421 can generate a delayed data sample signal DRDT by delaying the data sample signal RDT. In an example embodiment, the delay circuit 421 can delay the data sample signal RDT by 1.5 UI to generate the delayed data sample signal DRDT as described above with reference to Figures 8A-10 .

[0131] The XOR gate 422 can perform an XOR logical operation on the delayed data sample signal DRDT and the edge sample signal EDT. The XOR gate 422 can output a value of 1 (i.e., a logical high H) when the two input bit values are equal, and output a value of 0 (i.e., a logical low L) when the two input bit values are not equal.

[0132] The XNOR gate 423 can perform an XNOR logical operation on the delayed data sample signal DRDT and the edge sample signal EDT. The XNOR gate 423 can output a value of 0 when the two input bit values are equal, and output a value of 1 when the two input bit values are not equal.

[0133] The first flip-flop 424 can generate a first state monitor signal STT1 by latching the output of the XOR gate 422. The second flip-flop 425 can generate a second state monitor signal STT2 by latching the output of the XNOR gate 423. In an example embodiment, the first flip-flop 424 and the second flip-flop 425 can perform the latching operation in synchronization with the data clock signal DCK.

[0134] The accumulator 501 can include a first counter CNT1 521, a second counter CNT2 522, and a subtracter 523.

[0135] When the bit value in the first state monitor signal STT1 is 1, the first counter 521 can increase a first stored value in the first counter 521. When the bit value in the second state monitor signal STT2 is 0, the second counter 522 can increase a second stored value in the second counter 522. The subtracter 523 can generate a state accumulation value AVL by subtracting the output of the second counter 522 from the output of the first counter 521.

[0136] As a result, the equalization control circuit 302 can increase the state accumulation value AVL by one when the compared data bit and the edge bit have equal values, and can decrease the state accumulation AVL by one when the compared data bit and the edge bit have different values.

[0137] Figure 17 is a timing diagram illustrating an example embodiment of a deskewing operation of a clock data recovery circuit included in a receiver circuit according to an example embodiment, and Figure 18 is a diagram illustrating an example embodiment of a state monitor included in a receiver circuit according to an example embodiment.

[0138] Figure 17 and Figure 18 illustrates Figure 2Each of the first de-serializer 250 and the second de-serializer 260 in the example embodiment de-serializes the data sample signal RDT into four parallel signals, but the specific number of parallel signals can vary.

[0139] Referring to Figure 2 and Figure 17 , the first de-serializer 250 can generate first to fourth parallel data sample signals RDT1 to RDT4 by de-serializing the data sample signal RDT including the data bits DB1 to DB16. The second de-serializer 260 can generate first to fourth parallel edge sample signals EDT1 to EDT4 by de-serializing the edge sample signal EDT. In this case, each edge bit can be aligned to a corresponding data bit without delaying the data sample signal RDT by 1.5 UI, as described above with reference to Figure 11 and Figure 12 .

[0140] Figure 18 An example embodiment of a state monitor that generates state monitor signals without delaying the data sample signal RDT is illustrated.

[0141] Referring to Figure 18 , the state monitor 403 can include first to fourth XOR gates 431 to 434 and first to fourth flip-flops FF1 435 to FF4 438. In an example embodiment, the first to fourth flip-flops 435 to 438 can perform a latching operation in synchronization with the data clock signal DCK.

[0142] Referring to Figure 17 and Figure 18 , the first XOR gate 431 can perform an XOR logical operation on the first data sample signal RDT1 and the second edge sample signal EDT2, and the first flip-flop 435 can generate a first state monitor signal STT1 by latching an output of the first XOR gate 431 in synchronization with the first clock signal CLK1.

[0143] The second XOR gate 432 can perform an XOR logical operation on the second data sample signal RDT2 and the third edge sample signal EDT3, and the second flip-flop 436 can generate a second state monitor signal STT2 by latching an output of the second XOR gate 432 in synchronization with the second clock signal CLK2.

[0144] The third XOR gate 433 can perform an XOR logical operation on the third data sample signal RDT3 and the fourth edge sample signal EDT4, and the third flip-flop 437 can generate a third state monitor signal STT3 by latching an output of the third XOR gate 433 in synchronization with the third clock signal CLK3.

[0145] The fourth XOR gate 434 can perform an XOR logical operation on the fourth data sample signal RDT4 and the first edge sample signal EDT1, and the fourth flip-flop 438 can generate a fourth state monitor signal STT4 by latching an output of the fourth XOR gate 434 in synchronization with a fourth clock signal CLK4.

[0146] As a result, the first to fourth state monitor signals STT1 to STT4 can respectively include a portion of the division of the above-described equalization state value. The above-described accumulator can generate a state accumulation value AVL based on at least one of the first to fourth state monitor signals STT1 to STT4.

[0147] Thus, the equalization control circuit of the state monitor 403 including Figure 18 may control an equalization coefficient by comparing a data bit of an nth parallel data sample signal of a plurality of parallel data sample signals with an edge bit of an (n+1)th parallel edge sample signal of a plurality of parallel edge sample signals, where n is a natural number.

[0148] Figure 19 is a block diagram illustrating a system including a receiver circuit according to an example embodiment.

[0149] Referring to Figure 19 , the system 1001 includes a transmitter circuit 1101, a receiver circuit 1201, and a communication channel 10 connecting the transmitter circuit 1101 and the receiver circuit 1201.

[0150] The transmitter circuit 1101 can include a transmission equalizer TEQZ and a transmission driver DR. The transmission equalizer TEQZ can perform a transmission equalization operation for transmission data TDT as will be described below with reference to Figure 20 , and the transmission driver DR can output a transmission data signal STD to the communication channel 10 based on an output of the transmission equalizer TEQZ.

[0151] The receiver circuit 1201 can include a reception buffer BF, an equalizer EQZ 100, a clock data recovery circuit CDR 200, and an equalization control circuit EQCON 301.

[0152] The reception buffer BF can buffer and output an input data signal SRD transmitted through the communication channel. The equalizer 100 can generate an equalized signal SEQ by equalizing the input data signal SRD based on an equalization coefficient CEQ. According to an example embodiment, the reception buffer BF can be omitted, and the equalizer 100 can directly receive the input data signal SRD from the communication channel 10. Example embodiments of the equalizer 100 are the same as described with reference to Figure 5 and Figure 6 .

[0153] ​The clock data recovery circuit 200 can internally generate a data clock signal and an edge clock signal based on the equalized signal. The clock data recovery circuit 200 can generate a data sample signal RDT including a plurality of data bits by sampling the equalized signal SEQ in synchronization with the data clock signal. In addition, the clock data recovery circuit 200 can generate an edge sample signal EDT including a plurality of edge bits by sampling the equalized signal SEQ in synchronization with the edge clock signal. An example embodiment of the clock data recovery circuit 200 can be the same as described with reference to Figure 2 .

[0154] The equalization control circuit 301 can control the equalization coefficient CEQ by comparing the plurality of data bits in the data sample signal RDT and the plurality of edge bits in the edge sample signal EDT. As described with reference to Figures 3-18 , the equalization control circuit 301 can generate a plurality of equalization state values by bit-by-bit comparing the plurality of data bits and the plurality of edge bits, and generate a state accumulated value by accumulating the equalization state values during an accumulation time interval.

[0155] In addition, the equalization control circuit 301 can provide the equalization state information OPT to the transmitter circuit 1101 through the auxiliary communication channel 11. The transmit equalizer TEQZ of the transmitter circuit 1101 can perform a transmit equalization operation, such as pre-emphasis, based on the equalization state information OPT.

[0156] In this way, the receiver circuit 1201 according to an example embodiment can reduce jitter of the equalized signal SEQ with high precision by digitally performing adaptive equalization based on data bits and edge bits, and thus can enhance the performance of the receiver circuit 1201 and the system 1001 including the receiver circuit 1201. In addition, the receiver circuit 1201 according to an example embodiment can further enhance the performance of the system 1001 including the transmitter circuit 1101 and the receiver circuit 1201 by performing a transmit equalization operation based on the equalization state information OPT.

[0157] Figure 20 is a diagram illustrating an example operation of a transmit equalizer included in the system of Figure 19 .

[0158] Referring to Figure 19 and Figure 20 , the transmit data TDT can include data bits as illustrated in Figure 20 , and the transmit equalizer TEQZ can perform a transmit equalization operation, for example, pre-emphasis of the transmit data TDT.

[0159] The pre-emphasis indicates an operation of a transmission equalizer TEQZ that exerts an influence on a signal in advance before the signal is output to the communication channel 10 so that the influence can offset characteristics of the communication channel 10. Through the exerted influence, a waveform of the signal can be changed to a desired waveform while the signal is transmitted through the communication channel 10.

[0160] In Figure 20 , SDT indicates a transmission data signal when pre-emphasis is not performed, and STD' indicates a transmission data signal when pre-emphasis is performed. The transmission equalizer TEQZ can adjust the strength of the pre-emphasis based on equalization state information OPT provided from the receiver circuit 1201.

[0161] Figure 21 is a block diagram illustrating a system 2000 including a display driving circuit. The above-described method and circuit of controlling equalization can be applied to Figure 21 the system 2000. For convenience of description, a display panel 2300 is illustrated in Figure 21 .

[0162] Referring to Figure 21 , the display driving circuit can include a timing controller TCON 2200, a plurality of source drivers SD1 to SDm, a data transmission lane 30, and a shared backward lane 40.

[0163] The timing controller 2200 can transmit data to the plurality of source drivers SD1 to SDm. The data transmitted to the plurality of source drivers SD1 to SDm can be packet data including display data. Each of the plurality of source drivers SD1 to SDm can drive one or more data lines of the display panel 2300 based on the received data.

[0164] The timing controller 2200 can transmit and receive data with the plurality of source drivers SD1 to SDm through the data transmission lane 30. An interface scheme between the timing controller 2200 and the plurality of source drivers SD1 to SDm can be referred to as an intra-panel interface.

[0165] In addition, the timing controller 2200 can transmit and receive data with the host device 2100 through the communication channel 20. An interface scheme between the timing controller 2200 and the host device 2100 can be referred to as an inter-panel interface.

[0166] Hereinafter, an operation of a display driving integrated circuit through a high-speed interface scheme will be described.

[0167] The timing controller 2200 can be connected to the plurality of source drivers SD1 to SDm in a point-to-point manner, and can transmit data to each of the plurality of source drivers SD1 to SDm through different data transmission channels 30. Distances between the timing controller 2200 and the plurality of source drivers SD1 to SDm can be different from each other. Accordingly, lengths of the data transmission channels 30 can be different from each other, and parasitic resistances Rp1 to Rpm of the data transmission channels 30 and parasitic capacitances Cp1 to Cpm of the data transmission channels 30 can be different from each other. Accordingly, impedances and frequency characteristics of the data transmission channels 30 can be different from each other, and thus the plurality of source drivers SD1 to SDm can perform training for optimizing a reception operation according to the impedances and frequency characteristics of the transmission channels corresponding thereto.

[0168] In more detail, each of the plurality of source drivers SD1 to SDm can optimize a reception operation of the receiver circuit RX1 to RXm through training. The plurality of source drivers SD1 to SDm determine parameter values OPT1 to OPTm of the receiver circuits RX1 to RXm, respectively, by optimizing the reception operation, and transmit the parameter values OPT1 to OPTm to the timing controller 2200. In an example embodiment, the plurality of source drivers SD1 to SDm can transmit the parameter values OPT1 to OPTm to the timing controller 2200, respectively, in response to (i.e., based on) a read command received from the timing controller 2200.

[0169] The plurality of source drivers SD1 to SDm can be connected to the timing controller 2200 in a multi-point manner through the shared backward channel 40. In an example embodiment, the shared backward channel 40 can be configured as one signal line. The plurality of source drivers SD1 to SDm can sequentially transmit the parameter values OPT1 to OPTm to the timing controller 2200 through the shared backward channel 40. At least one of the plurality of source drivers SD1 to SDm can transmit an indication of an abnormal state related to the reception operation (i.e., when the reception abnormal state occurs) to the timing controller 2200 through the shared backward channel 40.

[0170] As described above, a system according to an example embodiment can include a first device including a transmitter circuit and a second device including a receiver circuit.

[0171] In an example embodiment, the first device can correspond to a host device 2100 configured to output display data to the communication channel 20, and the second device can correspond to a display device configured to display an image based on the received display data. In this case, the receiver circuit according to an example embodiment can be included in a timing controller 2200 of the display device.

[0172] In an example embodiment, the first device can correspond to the timing controller 2200 and the host device 2100, and the second device can correspond to each of the plurality of source drivers SD1 to SDm. In this case, the receiver circuit according to an example embodiment can be included in each of the plurality of source drivers SD1 to SDm.

[0173] Figure 22 is a diagram showing an operation mode of a system of Figure 21 .

[0174] Referring to Figure 21 and Figure 22 , the operation mode of the display driving circuit can include an initialization mode S20, a display data mode S30, and a vertical blanking mode S40. A period in which the display driving circuit operates in the initialization mode S20 can be referred to as an initialization period. A period in which the display driving circuit operates in the display data mode S30 or the vertical blanking mode S40 can be referred to as a display period.

[0175] When the display driving circuit operates in the initialization mode S20, the display driving circuit can perform a first initialization or a second initialization. When the display driving circuit performs the first initialization, the plurality of source drivers SD1 to SDm can perform a full initialization and optimization of the reception unit. When the display driving circuit performs the second initialization, the plurality of source drivers SD1 to SDm can perform a partial initialization of the reception unit. In an example embodiment, when the display driving circuit performs the first initialization, the plurality of source drivers SD1 to SDm can perform DC training and AC training based on a training pattern provided from the timing controller 2200. The DC training can optimize reception characteristics of the reception unit independently of an external factor (e.g., a signal received from the timing controller 2200), and can include, for example, impedance matching, offset calibration, etc. The AC training can optimize the reception characteristics based on the training pattern received from the timing controller 2200, and can include, for example, system clock recovery, equalization parameter determination, etc.

[0176] The plurality of source drivers SD1 to SDm can initialize and optimize the reception unit through the first initialization, and can determine parameter values of the reception unit. When the display driving circuit performs the second initialization, the plurality of source drivers SD1 to SDm can perform the partial initialization during the AC training. In an example embodiment, the plurality of source drivers SD1 to SDm can recover a system clock by performing clock recovery training.

[0177] In an example embodiment, the first initialization can be performed during a first initialization period after power is supplied to the display driving circuit. In an example embodiment, the first initialization can be periodically performed in a preset time unit or interval or according to a preset condition.

[0178] If the display driving circuit (e.g., the timing controller 2200 and the plurality of source drivers SD1 to SDm) is powered on (S10), the display driving circuit can perform first initialization. Each of the plurality of source drivers SD1 to SDm can optimize a reception unit through training (e.g., DC training and AC training), and can store a parameter value of the reception unit in a register set internally.

[0179] Thereafter, the display driving circuit operates in a display data mode S30. The timing controller 2200 can inform of the start of the display data mode S30 by transmitting data packets including a line start field SOL to the plurality of source drivers SD1 to SDm for a display time period. The timing controller 2200 can transmit display data corresponding to each of the lines of an image frame to each of the plurality of source drivers SD1 to SDm. In this regard, the timing controller 2200 can sequentially transmit the display data and a read command for requesting reading of a parameter value to the plurality of source drivers SD1 to SDm. The source driver that receives the read command can transmit the parameter value stored in the register to the timing controller 2200. The timing controller 2200 can store the received parameter value.

[0180] When the display data corresponding to one image frame is transmitted, the display driving circuit operates in a vertical blanking mode (S40). The timing controller 2200 can inform of the end of the display data mode S30 by transmitting display data including a frame sync signal FSYNC to the plurality of source drivers SD1 to SDm.

[0181] In an example embodiment, the display driving circuit can perform second initialization during the vertical blanking mode S40. The timing controller 2200 can transmit a training pattern to each of the plurality of source drivers SD1 to SDm. Each of the plurality of source drivers SD1 to SDm can perform system clock recovery training based on the training pattern.

[0182] The display data mode S30 and the vertical blanking mode S40 can be repeatedly performed for each image frame. The display data mode S30 and the vertical blanking mode S40 can be repeatedly performed until the display driving circuit is powered off or a soft failure (SOFT FAIL) occurs in one of the plurality of source drivers SD1 to SDm.

[0183] When the operation mode of the display driving circuit is changed from the vertical blanking mode S40 to the display data mode S30, the timing controller 2200 can transmit packet data including the line start field SOL to the plurality of source drivers SD1 to SDm. When the operation mode of the display driving circuit is changed from the display data mode S30 to the vertical blanking mode S40, the timing controller 2200 can transmit packet data including the frame sync signal FSYNC to the plurality of source drivers SD1 to SDm.

[0184] When a soft failure occurs in at least one of the plurality of source drivers SD1 to SDm during a display period, the display driving circuit can perform initialization. For example, when an error system clock is output due to a clock recovery circuit included in the reception unit being in an unlocked state, or when an internal setting value of the reception unit is changed due to ESD, a soft failure can occur.

[0185] In this regard, the plurality of source drivers SD1 to SDm can restore the system clock by performing the second initialization, and can optimize the reception operation of the reception unit based on the parameter values received from the timing controller 2200. Each of the plurality of source drivers SD1 to SDm can restore the system clock based on the training pattern received from the timing controller 2200. The timing controller 2200 can transmit the parameter values stored in the display data pattern S30 to the plurality of source drivers SD1 to SDm. The timing controller 2200 can provide the parameter values corresponding to each of the plurality of source drivers SD1 to SDm. Each of the plurality of source drivers SD1 to SDm can rapidly optimize the reception operation of the reception unit based on the received parameter values. Thereafter, the display driving circuit can operate in the display data pattern S30.

[0186] Figure 23 is a block diagram illustrating a system including a receiver circuit according to an example embodiment.

[0187] Figure 23 An electronic system 3000 performing bidirectional communication is illustrated. Referring to Figure 23 , the electronic system 3000 can include an electronic device 3100 and an electronic device 3200. In an example embodiment, each of the electronic device 3100 and the electronic device 3200 can be implemented as one of various electronic devices, such as a desktop computer, a laptop computer, a tablet computer, a smart phone, a wearable device, a video game console, a home appliance, a medical device, etc. In another example embodiment, the electronic system 3000 can be implemented as a single electronic device. Each of the electronic device 3100 and the electronic device 3200 can be a component or intellectual property (IP) that can be included in a single electronic device, and can be implemented as a circuit, a module, a chip, and / or a package level entity. The terms "system" and "device" are provided for better understanding, not to limit the example embodiments.

[0188] The electronic device 3100 and the electronic device 3200 can exchange data / signals through a communication channel 50 and a communication channel 60 while communicating with each other. Each of the communication channel 50 and the communication channel 60 can include a conductive material to transmit data / signals. In an example embodiment, each of the communication channel 50 and the communication channel 60 can be implemented as a trace pattern on a printed circuit board (PCB), a wire, a cable, a metal pin / pad of a connector, etc.Figure 23 An example embodiment showing two unidirectional communication channels 50 and 60, which can be combined into one bidirectional communication channel in an example embodiment.

[0189] The electronic device 3100 can include a functional circuit INT1, a serializer / deserializer SEDES1, a transmitter circuit TX1, and a receiver circuit RX1. The electronic device 3200 can include a functional circuit INT2, a serializer / deserializer SEDES2, a transmitter circuit TX2, and a receiver circuit RX2.

[0190] The functional circuit INT1 and the functional circuit INT2 can be configured to perform functions of the electronic device 3100 and the electronic device 3200, respectively. In an example embodiment, the functional circuit INT1 and the functional circuit INT2 can constitute various components or IPs, such as at least one processor (e.g., a central processing unit (CPU), an application processor (AP), etc.), a memory, an image sensor, a display device, etc.

[0191] The electronic device 3100 and the electronic device 3200 can be implemented as separate components, IPs, or devices. In an example embodiment, the electronic device 3100 can be an external device of the electronic device 3200, and the electronic device 3200 can be an external device of the electronic device 3100.

[0192] The serializer / deserializer SEDES1 can be configured to serialize data generated according to an operation of the functional circuit INT1. The serializer / deserializer SEDES1 can provide the serialized data to the transmitter circuit TX1. The transmitter circuit TX1 can transmit the serialized signal to the electronic device 3200 through the communication channel 50. The receiver circuit RX2 can equalize a signal received through the communication channel 50, and recover a clock and data based on the equalized signal. The serializer / deserializer SEDES2 can deserialize the signal from the receiver circuit RX2 to provide deserialized data to the functional circuit INT2.

[0193] The serializer / deserializer SEDES2 can be configured to serialize data generated according to an operation of the functional circuit INT2. The serializer / deserializer SEDES2 can provide the serialized data to the transmitter circuit TX2. The transmitter circuit TX2 can transmit the serialized signal to the electronic device 3100 through the communication channel 60. The receiver circuit RX1 can equalize a signal received through the communication channel 60, and recover a clock and data based on the equalized signal. The serializer / deserializer SEDES1 can deserialize the signal from the receiver circuit RX1 to provide deserialized data to the functional circuit INT1.

[0194] In this way, the electronic device 3100 and the electronic device 3200 can exchange data / signals with each other through the communication channel 50 and the communication channel 60, and when the communication speed between the electronic device 3100 and the electronic device 3200 increases (for example, when communication is performed at a higher frequency or with a larger bandwidth), the electronic device 3100 and the electronic device 3200 can exchange a larger amount of data with respect to time.

[0195] However, due to various reasons such as skin effect, dielectric loss, etc., each of the communication channel 1210 and the communication channel 1250 can exhibit a low-pass frequency response characteristic. Therefore, in high-speed operation, the bandwidth of the communication channel 1210 and the communication channel 1250 can be limited, and can become smaller than the bandwidth of the signal. This can weaken the high-frequency components of the signal transmitted through the communication channel 1210 and the communication channel 1250, and can cause inter-symbol interference in the time domain. As a result, as the signal transmission speed increases, the distortion of the signal can become more serious, and the quality of the signal can become deteriorated.

[0196] According to an example embodiment, at least one of the receiver circuit RX1 and the receiver circuit RX2 can include an equalizer, a clock and data recovery circuit, and an equalization control circuit to perform adaptive equalization digitally based on data bits and edge bits, as described above.

[0197] To compensate for the unintended distortion of the signal, the equalizer in the receiver circuit RX1 and RX2 can perform equalization on the signal, and the equalizer in the transmitter circuit TX1 and the transmitter circuit TX2 can perform pre-equalization on the signal. The equalizer included in the transmitter circuit TX1 and the transmitter circuit TX2 can be referred to as a transmission equalizer, and the equalizer included in the receiver circuit RX1 and the receiver circuit RX2 can be referred to as a reception equalizer.

[0198] Figure 24 is a block diagram illustrating an example embodiment of an interface employable in a computing system, according to an example embodiment.

[0199] Referring to Figure 21The computing system 4100 can be implemented by a data processing apparatus using or supporting a Mobile Industry Processor Interface (MIPI) interface. The computing system 4100 can include an application processor 4110, a three-dimensional image sensor 4140, a display apparatus 4150, etc. A CSI host 4112 of the application processor 4110 can perform serial communication with a CSI device 4141 of the three-dimensional image sensor 4140 via a Camera Serial Interface (CSI). In an example embodiment, the CSI host 4112 can include a deserializer (DES) and the CSI device 4141 can include a serializer (SER). A DSI host 4111 of the application processor 4110 can perform serial communication with a DSI device 4151 of the display apparatus 4150 via a Display Serial Interface (DSI).

[0200] In an example embodiment, the DSI host 4111 can include a serializer (SER) and the DSI device 1151 can include a deserializer (DES). The computing system 4100 can further include a Radio Frequency (RF) chip 4160 performing communication with the application processor 4110. A physical layer (PHY) 4113 of the computing system 4100 and a physical layer (PHY) 4161 of the RF chip 4160 can perform data communication based on MIPI DigRF. The application processor 4110 can further include a DigRF MASTER 4114 controlling data communication of the PHY 4161.

[0201] The computing system 4100 can further include a Global Positioning System (GPS) 4120, a memory 4170, a MIC 4180, a DRAM device 4185, and a speaker 4190. In addition, the computing system 4100 can perform communication using Ultra Wide Band (UWB) 4120, Wireless Local Area Network (WLAN) 4220, Worldwide Interoperability for Microwave Access (WIMAX) 4130, etc.

[0202] As described above, the receiver circuit according to an example embodiment can reduce jitter of an equalized signal with high accuracy by performing adaptive equalization digitally based on data bits and edge bits, and thus can enhance performance of the receiver circuit and a system including the receiver circuit. An example embodiment can provide a receiver circuit and a system including the same, which can efficiently perform adaptive equalization of a signal received through a communication channel.

[0203] Embodiments can be applied to any electronic devices and systems operating at high speed data communication. In example embodiments, embodiments can be applied to systems such as a memory card, a solid state drive (SSD), an embedded Multi-Media Card (eMMC), a Universal Flash Storage (UFS), a mobile phone, a smart phone, a Personal Digital Assistant (PDA), a Portable Multimedia Player (PMP), a digital camera, a camcorder, a Personal Computer (PC), a server computer, a workstation, a laptop computer, a digital TV, a set-top box, a portable game console, a navigation system, a wearable device, an Internet of Things (IoT) device, an Internet of Everything (IoE) device, an electronic book, a Virtual Reality (VR) device, an Augmented Reality (AR) device, etc.

[0204] Example embodiments have been disclosed herein and, although a particular terminology is employed, it is understood that the terms are used in a generic and descriptive sense only and are not intended to be limiting. In some instances, features, attributes and / or elements described in conjunction with a particular embodiment are likewise applicable to other embodiments, except where clearly incompatible. In some instances, features, attributes and / or elements described in conjunction with a particular embodiment are not necessarily applicable to other embodiments, except where clearly incompatible. In some instances, features, attributes and / or elements described in conjunction with a particular embodiment can be used, either alone or in combination, with or without other features, attributes and / or elements described in conjunction with other embodiments, except where clearly incompatible. Thus, the skilled artisan will appreciate that various adaptations and modifications of the embodiments described can be accomplished without departing from the scope of the disclosure as set forth in the appended claims.

Claims

1. A receiver circuit comprising: an equalizer configured to generate an equalized signal by equalizing an input data signal transmitted through a communication channel based on an equalization coefficient; a clock data recovery circuit configured to generate a data clock signal and an edge clock signal based on the equalized signal, generate a data sample signal including a plurality of data bits by sampling the equalized signal in synchronization with the data clock signal, and generate an edge sample signal including a plurality of edge bits by sampling the equalized signal in synchronization with the edge clock signal; and an equalization control circuit configured to control the equalization coefficient by comparing the plurality of data bits and the plurality of edge bits, wherein the equalization control circuit generates a plurality of equalization state values by comparing the plurality of data bits and the plurality of edge bits bit by bit, and generates a state accumulated value by accumulating the plurality of equalization state values during an accumulation time interval, wherein the equalization control circuit increases the state accumulated value when compared data bits and edge bits have equal values, and decreases the state accumulated value when compared data bits and edge bits have different values.

2. The receiver circuit of claim 1, wherein, The equalization control circuit determines an equalization state of the equalizer by comparing each data bit of the plurality of data bits with a corresponding one of the plurality of edge bits, each edge bit being sampled later than the corresponding one data bit.

3. The receiver circuit of claim 2, wherein, The equalization control circuit determines an equalization state of the equalizer by comparing each data bit of the plurality of data bits with a corresponding one of the plurality of edge bits, each edge bit being sampled one and a half unit intervals later than the corresponding one data bit, the unit interval indicating a time interval between two adjacent data bits of the input data signal.

4. The receiver circuit of claim 1, wherein, The equalization control circuit generates an equalization state value 1 when compared data bits and edge bits have equal values, and generates an equalization state value 0 when compared data bits and edge bits have different values.

5. The receiver circuit of claim 1, wherein, The equalization control circuit includes at least one XOR gate configured to perform an XOR logical operation on the plurality of data bits and the plurality of edge bits bit by bit to output the plurality of equalization state values.

6. The receiver circuit of claim 1, wherein, The equalization control circuit determines that the equalizer is in an under-equalized state when the state accumulated value is greater than a first reference value, and determines that the equalizer is in an over-equalized state when the state accumulated value is less than a second reference value.

7. The receiver circuit of claim 6, wherein, The equalization control circuit increases the equalization coefficient to increase an equalization strength of the equalizer when it is determined that the equalizer is in the under-equalized state, and decreases the equalization coefficient to decrease the equalization strength of the equalizer when it is determined that the equalizer is in the over-equalized state.

8. The receiver circuit of claim 1, wherein, The equalization control circuit generates a plurality of state accumulated values corresponding to a plurality of accumulated time intervals, and controls the equalization coefficients based on the plurality of state accumulated values until the equalization coefficients converge to predetermined values.

9. The receiver circuit of claim 1, wherein: The clock data recovery circuit generates a plurality of parallel data sample signals by de-serializing the data sample signal, and generates a plurality of parallel edge sample signals by de-serializing the edge sample signal, and The equalization control circuit controls an equalization coefficient by comparing a data bit of an n-th parallel data sample signal of the plurality of parallel data sample signals and an edge bit of an (n+1)-th parallel edge sample signal of the plurality of parallel edge sample signals, where n is a natural number.

10. The receiver circuit of claim 1, wherein, The clock data recovery circuit includes: a data sampler configured to generate the data sample signal including the plurality of data bits by sampling the equalization signal in synchronization with the data clock signal; an edge sampler configured to generate the edge sample signal including the plurality of edge bits by sampling the equalization signal in synchronization with the edge clock signal; and a clock recovery circuit configured to generate the data clock signal and the edge clock signal based on the data sample signal and the edge sample signal.

11. The receiver circuit of claim 10, wherein, The clock data recovery circuit further includes: a first deserializer configured to generate a plurality of parallel data sample signals by de-serializing the data sample signal; and a second deserializer configured to generate a plurality of parallel edge sample signals by de-serializing the edge sample signal.

12. The receiver circuit of claim 1, wherein, The equalization control circuit includes: a state monitor configured to generate a plurality of equalization state values by bit-by-bit comparing the plurality of data bits and the plurality of edge bits; an accumulator configured to generate a state accumulated value by accumulating the plurality of equalization state values during an accumulated time interval; and control logic configured to control the equalization coefficients based on the state accumulated value.

13. The receiver circuit of claim 12, wherein: The state monitor includes: a delay circuit configured to generate a delayed data sample signal by delaying the data sample signal; an XOR gate configured to perform an XOR logical operation on the delayed data sample signal and the edge sample signal; and a flip-flop configured to generate a state monitor signal including the plurality of equalization state values by latching an output of the XOR gate, and The accumulator includes a counter configured to generate the state accumulated value by increasing a stored value in the counter when each equalization state value is 1, and decreasing the stored value in the counter when each equalization state value is 0.

14. The receiver circuit of claim 12, wherein: The state monitor includes: a delay circuit configured to generate a delayed data sample signal by delaying the data sample signal; an XOR gate configured to perform an XOR logical operation on the delayed data sample signal and the edge sample signal; and a flip-flop configured to generate a state monitor signal including the plurality of equalization state values by latching an output of the XOR gate, and a counter configured to generate the state accumulated value by increasing a stored value in the counter when each equalization state value is 1, and decreasing the stored value in the counter when each equalization state value is 0. an XNOR gate configured to perform an XNOR logical operation on the delayed data sample signal and the edge sample signal; a first flip-flop configured to generate a first state monitoring signal by latching an output of the XOR gate; and a second flip-flop configured to generate a second state monitoring signal by latching an output of the XNOR gate, and the accumulator includes: a first counter configured to increase a first stored value in the first counter when a bit value in the first state monitoring signal is 1; a second counter configured to increase a second stored value in the second counter when a bit value in the second state monitoring signal is 0; and a subtracter configured to generate the state accumulation value by subtracting an output of the second counter from an output of the first counter.

15. An electronic system comprising: a communication channel; a first device configured to output a transmission data signal to the communication channel based on transmission data; and a second device including a receiver circuit connected to the communication channel, the receiver circuit including: an equalizer configured to generate an equalized signal by equalizing an input data signal transmitted through the communication channel based on an equalization coefficient; a clock data recovery circuit configured to generate a data clock signal and an edge clock signal based on the equalized signal, to generate a data sample signal including a plurality of data bits by sampling the equalized signal in synchronization with the data clock signal, and to generate an edge sample signal including a plurality of edge bits by sampling the equalized signal in synchronization with the edge clock signal; and an equalization control circuit configured to control the equalization coefficient by comparing the plurality of data bits and the plurality of edge bits, wherein the equalization control circuit generates a plurality of equalization state values by comparing the plurality of data bits and the plurality of edge bits bit by bit, and generates a state accumulation value by accumulating the plurality of equalization state values during an accumulation time interval, wherein the equalization control circuit increases the state accumulation value when compared data bits and edge bits have equal values, and decreases the state accumulation value when compared data bits and edge bits have different values.

16. The system of claim 15, wherein, the first device is a host device that provides display data as the transmission data to the second device through the communication channel, the second device is a display device that displays an image based on the display data, and the receiver circuit is included in a timing controller of the display device.

17. The system of claim 15, wherein, the first device is a timing controller of a display device, the second device is a source driver of the display device, and the receiver circuit is included in the source driver.

18. A receiver circuit comprising: an equalizer configured to generate an equalized signal by equalizing an input data signal transmitted through a communication channel based on an equalization coefficient; a data sampler configured to generate a data sample signal comprising a plurality of data bits by sampling the equalized signal in synchronization with a data clock signal; an edge sampler configured to generate an edge sample signal comprising a plurality of edge bits by sampling the equalized signal in synchronization with an edge clock signal; a clock recovery circuit configured to generate the data clock signal and the edge clock signal based on the data sample signal and the edge sample signal; a state monitor configured to generate a plurality of equalization state values by bit-wise comparing the plurality of data bits and the plurality of edge bits; an accumulator configured to generate a state accumulated value by accumulating the plurality of equalization state values during an accumulation time interval; and control logic configured to control the equalization coefficient based on the state accumulated value, wherein the accumulator increases the state accumulated value when compared data bits and edge bits have equal values, and decreases the state accumulated value when compared data bits and edge bits have different values. ​

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