Fluxgate Current Converter

Abstract

A fluxgate current converter (2) comprising a control circuit (3) and a fluxgate measurement device (7) including a fluxgate magnetic field detector (4), the fluxgate magnetic field detector including a saturable soft magnetic core surrounded by an excitation coil, the control circuit including an excitation coil drive circuit (14) connected to the excitation coil and a controller (18) connected to the excitation coil drive circuit configured to generate an alternating excitation current Ifx to alternately saturate the soft magnetic core, the controller being in the form of an FPGA (Field Programmable Gate Array) including at least one input including a 1-bit sigma-delta analog-to-digital converter (ADC) (21) connected to the excitation coil for receiving a measurement signal (19) output by the excitation coil.

Description

[Technical Field]

[0001] The present invention relates to a current converter with a fluxgate detector, and in particular to a closed-loop current converter with a fluxgate detector. [Background technology]

[0002] Fluxgate current transducers are well known and used in many current sensing applications. They typically include a magnetic field detector with a saturable soft magnetic core 4 surrounded by an excitation coil 6. In many fluxgate transducers, a primary conductor carrying the current to be measured extends through a central passageway of the magnetic field detector. In closed-loop transducers, a compensation coil is magnetically coupled to the magnetic field detector and connected in a feedback loop to signal processing circuitry. The compensation coil attempts to cancel the magnetic field generated by the primary conductor. Such arrangements are well known. It is also possible to use fluxgates in an open-loop configuration without a compensation coil, with only a primary conductor carrying the current to be measured. However, given the high sensitivity of fluxgate magnetic field detectors, they are primarily used in closed-loop configurations.

[0003] A closed-loop current transducer with a fluxgate detector is described in U.S. Pat. No. 10,126,332. Current transducers with fluxgate detectors, such as those described in the aforementioned patent, advantageously provide highly accurate measurements of current or differential current flowing in one or more primary conductors extending through a central region of the transducer surrounded by a magnetic circuit core. Fluxgate detectors have high sensitivity and low offset compared to the widely used Hall-effect detectors. The electronics required to drive the excitation current to saturate the magnetic core of the fluxgate detector, as well as the compensation current and ripple compensation current, make such current transducers more expensive and less compact than conventional open-loop current transducers with Hall-effect detectors.

[0004] Typically, to ensure sufficiently high performance, the aforementioned fluxgate-type current converters generally require a microcontroller (digital signal processor DSP) with two cores: one core is used to continuously excite the fluxgate and acquire fluxgate current information in real time, and the other core is used to manage, communicate, and perform calculations. The microcontroller also typically has a 16-bit differential analog-to-digital ADC converter and generates a high-resolution pulse-width modulated (PWM) signal operating at, for example, 10 megahertz. However, the cost of such DSPs is quite high and they typically need to be implemented on a circuit board of a size beyond that strictly required for the signal processing functions required by the current converter with a fluxgate detector. Summary of the Invention [Problem to be solved by the invention]

[0005] SUMMARY OF THE INVENTION It is an object of the present invention to provide a current transducer with a fluxgate detector that is highly accurate and cost-effective to manufacture and implement.

[0006] It would be advantageous to provide a current converter with a fluxgate detector that can be easily adjusted or calibrated according to the needs of the user.

[0007] It would be advantageous to provide a current transducer that is highly accurate, has low offset, is easy to implement, and can be easily configured for different current measurement ranges in a cost-effective and reliable manner.

[0008] It would be advantageous to provide a fluxgate current converter that is easy to install and operate. [Means for solving the problem]

[0009] The object of the present invention has been achieved by providing a fluxgate current converter as claimed in claim 1 and a method for operating a fluxgate current converter as claimed in claim 7.

[0010] Disclosed herein is a fluxgate current converter comprising a control circuit and a fluxgate measurement device including a fluxgate magnetic field detector, the fluxgate magnetic field detector including a saturable soft magnetic core surrounded by an excitation coil, the control circuit including an excitation coil drive circuit connected to the excitation coil and a controller connected to the excitation coil drive circuit configured to generate an alternating excitation current Ifx to alternately saturate the soft magnetic core, the controller being in the form of an FPGA (Field Programmable Gate Array) including at least one input including a 1-bit sigma-delta analog-to-digital converter (ADC) connected to the excitation coil to receive a measurement signal output by the excitation coil.

[0011] The at least one input comprises an LVDS (Low Voltage Differential Signaling) input or a comparator input of an FPGA. Note that an LVDS input can also act as a comparator, and input circuits designated as comparators can also be used in the sigma-delta (ΣΔ) modulator circuit of the present invention.

[0012] The FPGA includes multiple inputs, each containing a 1-bit sigma-delta analog-to-digital converter (ADC), and the bitstream output signals of the multiple 1-bit sigma-delta analog-to-digital converters are added before being fed into a digital filter.

[0013] In an advantageous embodiment, a 1-bit sigma-delta analog-to-digital converter (ADC) includes a first resistor (R1) connected in series with a first input of an LVDS, a first capacitor (C1) connected between a reference potential and the first input, and a feedback loop from the output of the LVDS and the first input, the feedback loop including a 1-bit DAC and a second resistor (R2).

[0014] In an advantageous embodiment, the FPGA includes a 1-bit sigma-delta digital-to-analog (DAC) output connected through an RC filter to the excitation coil to provide a voltage control signal, which is provided to an amplifier in the excitation coil driver circuit to provide an AC excitation current to the excitation coil of the flux-gate detector.

[0015] In an advantageous embodiment, the converter further includes a compensation coil, the control circuit includes a compensation coil driver circuit that supplies a compensation current Is to the compensation coil of the flux-gate measurement device that attempts to cancel the magnetic field of the primary current Ip, and the FPGA includes a 1-bit sigma-delta digital-to-analog (DAC) output connected to the compensation current coil via an RC filter for providing a voltage control signal to the compensation coil driver circuit.

[0016] In an advantageous embodiment, the current converter further includes a ripple cancellation coil, the control circuit includes a ripple cancellation coil drive circuit that supplies a compensation current Is to a compensation coil of the flux-gate measurement device that attempts to cancel the magnetic field of the primary current Ip, and the FPGA includes a 1-bit sigma-delta digital-to-analog (DAC) output connected to the ripple current cancellation coil via an RC filter for providing a voltage control signal to the ripple cancellation coil drive circuit.

[0017] In an advantageous embodiment, the FPGA includes an excitation voltage control circuit portion configured to generate an excitation voltage control signal Ve for the excitation coil having a trapezoidal waveform with rounded corners.

[0018] In an advantageous embodiment, the FPGA includes multiple inputs, each containing a 1-bit sigma-delta analog-to-digital converter (ADC), with the 1-bit stream of each ADC being added before being input to a digital filter.

[0019] In an advantageous embodiment, the claim is characterized in that the method comprises generating an excitation signal for an excitation coil of a fluxgate magnetic field detector as a trapezoidal waveform with rounded corners. The excitation signal can also be viewed as a substantially square wave with softened rising and falling edges to reduce noise. The method of softening the edges can include replacing the edges with a reduced harmonic waveform, such as the rising part of a sine wave.

[0020] In an advantageous embodiment, the trapezoidal waveform is generated using a fluxgate excitation lookup table stored in the memory of the FPGA.

[0021] Further objects and advantageous features of the present invention will become apparent from the appended claims, detailed description and accompanying drawings. [Brief explanation of the drawings]

[0022] [Figure 1] FIG. 1 is a schematic block diagram of a current converter with a fluxgate detector according to an embodiment of the present invention. [Figure 2a] FIG. 2 is a schematic circuit diagram of a portion of the input circuitry to a field programmable gate array (FPGA) of a converter control circuit according to one embodiment of the present invention. [Figure 2b] FIG. 2B is a view similar to FIG. 2a of a modified example. [Figure 2c] FIG. 2c is a view similar to FIG. 2b of yet another variant; [Figure 3a] 1 is a schematic graphical representation of a plot of a sinusoidal excitation voltage and associated excitation current of an excitation coil driver according to the prior art; [Figure 3b] 1 is a schematic graphical representation of a plot of a square excitation voltage and associated excitation current of an excitation coil driver according to the prior art; [Figure 4] 1 is a schematic graphical representation of a plot of a hybrid excitation voltage and associated excitation current signal in accordance with an embodiment of the present invention; DETAILED DESCRIPTION OF THE INVENTION

[0023] Referring to Figure 1, the primary current I flowing through the primary conductor 1 P The current transducer 2 for measuring the current comprises a fluxgate measuring device 7 and a control circuit 3.

[0024] The fluxgate measurement device includes a fluxgate magnetic field detector 4 and a secondary coil 6 .

[0025] As is known per se in the art, the secondary coil is connected to the fluxgate detector 4 in a feedback loop 12 to receive a current I S This compensation coil acts as a compensation coil supplied with the measured current I P The primary conductor 1 carries a magnetic field which attempts to cancel the magnetic field generated by the primary conductor 1, which extends through a central passage 10 of the transducer.

[0026] The fluxgate magnetic field detector 4 includes a saturable soft magnetic core surrounded by an excitation coil connected to an excitation coil drive circuit 14, which supplies an alternating excitation current I configured to alternately saturate the soft magnetic core. fx occurs.

[0027] The current converter may further comprise a ripple compensation circuit 28 connected to the ripple compensation coil 26 for performing a ripple compensation function, as known per se, for example from WO2016 / 016038.

[0028] The ripple compensation circuit 28 reduces the excitation current I of the fluxgate detector 4. fx A ripple compensation current I tries to cancel the ripple signal caused by R is configured to generate

[0029] Excitation voltage signal I for the excitation coil of the fluxgate magnetic field detector 4 fxis generated by a controller 18 connected to the control circuit 3, in particular the excitation coil drive circuit 14, which includes an amplifier 20 that amplifies the excitation coil control signal 17 output by the controller 18.

[0030] According to a first aspect of the invention, the controller 18 is in the form of an FPGA (Field Programmable Gate Array) that includes at least one LVDS (Low Voltage Differential Signaling) input connected to the excitation coil.

[0031] The LVDS input forms part of a 1-bit sigma-delta analog-to-digital converter (ADC) 21 connected to the excitation coil for receiving the measurement signal 19 output by the excitation coil.

[0032] 1, there are two LVDS inputs that form part of two 1-bit sigma-delta analog-to-digital converters (ADCs) 21 connected to the excitation coils, but the FPGA may include only one or more than two LVDS inputs connected to the excitation coils within the scope of the present invention. Preferably, the FPGA includes more than two LVDS inputs connected to the excitation coils, for example six, eight, or more LVDS inputs.

[0033] The 1-bit sigma-delta analog-to-digital converter (ADC) 21 includes a first resistor R1 connected in series with the LVDS first input 23, a first capacitor C1 connected between a reference potential (e.g., ground) and the first input 23, and a feedback loop from the LVDS output 29 and the first input 23, the feedback loop including the 1-bit DAC 27d and a second resistor R2. The LVDS second input is connected to a reference voltage, which can be, for example, the midpoint of the FPGA LVDS bank.

[0034] On the LVDS input line, the R1-C1 circuit components form the integrator of the sigma-delta converter, and amplifier 15 serves to regulate the voltage to the LVDS input and act as a low impedance output, allowing the sigma-delta converter to function properly.

[0035] Essentially, the ADC 21 includes an oversampling modulator followed by a digital / decimation filter, which together produce a high-resolution data stream output. The R1-C1 and Rx-Cx circuit components act as integrators, and the LVDS input acts as a comparator. The system clock frequency (e.g., greater than 100 MHz) then generates one bit stream for each ADC 21, which is added before the digital filter 32. Adding multiple 1-bit sigma-delta converters 21 improves the resolution and reduces noise in the bit stream.

[0036] Advantageously, a 1-bit sigma-delta analog-to-digital converter (ADC) 21 configured using an FPGA's LVDS input is very cost-effective to implement and allows for high accuracy due to the high frequency operating capability of the FPGA LVDS, typically above 100 MHz, and subsequent digital signal processing of the measurement signal output by the LVDS. Furthermore, a 1-bit sigma-delta analog-to-digital converter (ADC) 21 configured using an FPGA's LVDS input 29 exhibits little or no drift and stable measurement accuracy over the typical operating temperature range of a flux-gate current converter.

[0037] Another key advantage of FPGAs is that they start up very quickly, typically in less than 500 milliseconds compared to about 8 seconds for DSPs.

[0038] The FPGA may advantageously further include a 1-bit sigma-delta digital-to-analog (DAC) output 27a connected to the excitation coil via a low-pass RC filter 31a to provide a voltage control signal which is supplied to the amplifier 20 of the excitation coil drive circuit 14 to provide an AC excitation current to the excitation coil of the flux-gate detector. The FPGA advantageously enables a high frequency 1-bit DAC that can be filtered using only a first order low-pass filter with simple RC circuit components, thereby eliminating the need for an active filter.

[0039] The fluxgate excitation LUT (look up table) defines a table of N points that are read at a dedicated frequency to generate the fluxgate excitation signal. Each output value of this table can be dynamically adjusted by the gain circuit 31, and other parameters such as temperature or magnetic material variations can be compensated for by the excitation adjustment circuit portion 30.

[0040] In a variant (not shown), the FPGA may include two 1-bit sigma-delta digital-to-analog (DAC) outputs 27a to generate a differential output DAC to the excitation coil via a low-pass RC filter 31a to provide a voltage control signal, which is provided to the amplifier 20 of the excitation coil driver circuit 14 to provide an AC excitation current to the excitation coil of the flux-gate detector.

[0041] The FPGA may advantageously further include a 1-bit sigma-delta digital-to-analog (DAC) output 27b connected via a low-pass RC filter to the compensation current coil to provide a voltage control signal which is supplied to amplifier 20b of compensation coil driver circuit 13 to supply a compensation current Is to the compensation coil of converter device 7 which attempts to cancel the magnetic field of the primary current Ip. The ADC input is supplied to digital filter 32 which digitizes the fluxgate current by means of a CIC filter (Cascaded-Integrator-Comb-Filter) and a decimation filter. The digitized fluxgate current is then processed to estimate by simple calculations the even-order harmonics of the fluxgate current which must be compensated for to perform regulation.

[0042] In a variant (not shown), the FPGA may include two 1-bit sigma-delta digital-to-analog (DAC) outputs 27b to generate a differential output DAC connected via a low-pass RC filter to the compensation current coil to provide a voltage control signal, which is supplied to amplifier 20b of the compensation coil drive circuit 13.

[0043] The FPGA may advantageously further include a 1-bit sigma-delta digital-to-analog (DAC) output 27c connected to the ripple current cancellation coil 26 via a low-pass RC filter 31c to provide a voltage control signal, which is provided to an amplifier 20c of the ripple coil drive circuit 28 to provide a ripple coil cancellation current Ir to the ripple current cancellation coil 26 of the converter device 7.

[0044] In a variant (not shown), the FPGA may include two 1-bit sigma-delta digital-to-analog (DAC) outputs 27c to generate a differential output DAC connected to the ripple current cancellation coil 26 via a low-pass RC filter 31c to provide a voltage control signal, which is supplied to an amplifier 20c of the ripple coil driver circuit 28.

[0045] The generation of the ripple signal uses similar blocks as described for the generation of the excitation signal. There is a look-up table that is read at a specific frequency by the FPGA. The output is dynamically adjusted in gain circuit section 39 and can be temperature compensated by temperature adjustment circuit section 37. To be able to compensate for converter noise, a small delay is added to this ripple compensation by delay circuit section 38 to properly compensate for the noise.

[0046] 2a and 2b show another embodiment of the present invention using a 1-bit sigma-delta ADC in pseudo-differential mode to improve resolution and noise. In Fig. 2b, LVDS input 21b is shifted to obtain the inverse bit stream of LVDS input 21a. In Fig. 2a, an inverting amplifier 33 is used to avoid inverting the LVDS input to create the pseudo-differential mode.

[0047] FIG. 2C uses a differential amplifier 35 that includes two outputs that are used to generate the pseudo-differential mode.

[0048] According to a second aspect of the present invention, the excitation voltage signal for the excitation coil of a fluxgate magnetic field detector is provided as a trapezoidal waveform Ve with rounded corners (FIG. 4). The purpose is to reduce the high-frequency components of the excitation current signal Ie compared to a square-wave voltage signal (FIG. 3a) and to increase the average value of the signal half-cycle compared to a sinusoidal signal with the same peak value (FIG. 3b). This allows the fluxgate core to be saturated using a lower peak voltage than would be required when using a sinusoidal signal, but eliminates the drawback of using a square voltage that generates high-frequency noise that adversely affects the output measurement signal. The FPGA includes an excitation voltage control circuit portion 22 configured to generate an excitation voltage control signal for the excitation coil having a trapezoidal waveform with rounded corners. The trapezoidal waveform may be generated using a fluxgate excitation lookup table 29 stored in the FPGA's memory or externally using an EPROM or flash memory.

[0049] [List of features] Primary conductor 1 Current Transducer 2 Fluxgate Measuring Device 7 Fluxgate Magnetic Field Detector 4 Saturable soft magnetic core Excitation coil Secondary coil 6 Ripple compensation coil 26 Control circuit 3 Feedback Loop 12 Compensation current drive circuit 13 Excitation coil drive circuit 14 Amplifier 20 Ripple compensation circuit 28 FPGA Controller 18 1-bit Sigma-Delta Analog-to-Digital Converter (ADC)21 LVDS input 29a 1-bit Sigma-Delta Digital-to-Analog (DAC) outputs 27a, 27b, 27c, and 27d RC filters 31a, 31b, and 31c Primary current I P Secondary current I S AC excitation current I fx Ripple cancellation current I R

[0050] [Embodiment] (1) A flux-gate current converter (2), a control circuit (3); a fluxgate measurement device (7) including a fluxgate magnetic field detector (4); Including, the fluxgate magnetic field detector includes a saturable soft magnetic core surrounded by an excitation coil; The control circuit includes an excitation coil drive circuit (14) connected to the excitation coil, and an AC excitation current I fxa controller (18) connected to the excitation coil drive circuit configured to generate the controller is in the form of an FPGA (Field Programmable Gate Array) including a plurality of input circuit portions, each including a 1-bit sigma-delta analog-to-digital converter (ADC) (21) connected to the excitation coil for receiving a measurement signal (19) output by the excitation coil, each input circuit portion including an LVDS (Low Voltage Differential Signaling) comparator input of the FPGA, and the bitstream output signals of the 1-bit sigma-delta analog-to-digital converters (21) being summed before being supplied to a digital filter (32). (2) The current converter of embodiment 1, wherein the 1-bit sigma-delta analog-to-digital converter (ADC) includes a first resistor (R1) connected in series with a first input (23) of the LVDS, a first capacitor (C1) connected between a reference potential and the first input, and a feedback loop from the output (25) of the LVDS and the first input, the feedback loop including a 1-bit DAC (27d) and a second resistor (R2). (3) The current converter of claim 1, wherein the FPGA includes a 1-bit sigma-delta digital-to-analog (DAC) output (27a) connected to the excitation coil via an RC filter (31a) to provide a voltage control signal, and the voltage control signal is provided to an amplifier (20) of the excitation coil drive circuit to provide an AC excitation current to the excitation coil of the flux-gate detector. (4) The current converter of embodiment 1 further includes a compensation coil, wherein the control circuit includes a compensation coil drive circuit (13) that supplies a compensation current Is to the compensation coil of the flux-gate measurement device to cancel the magnetic field of the primary current Ip, and the FPGA includes a 1-bit sigma-delta digital-to-analog (DAC) output (27b) connected to the compensation current coil via an RC filter (31b) to supply a voltage control signal to the compensation coil drive circuit. (5) The current converter of embodiment 1, further comprising a ripple cancellation coil (26), wherein the control circuit includes a ripple cancellation coil drive circuit (28) that supplies a compensation current Is to the compensation coil of the flux-gate measurement device to cancel the magnetic field of the primary current Ip, and wherein the FPGA includes a 1-bit sigma-delta digital-to-analog (DAC) output (27c) connected to the ripple current cancellation coil via an RC filter (31c) to supply a voltage control signal to the ripple cancellation coil drive circuit.

[0051] (6) The current converter of embodiment 1, wherein the FPGA includes an excitation voltage control circuit portion (22) configured to generate an excitation voltage control signal Ve for the excitation coil having a trapezoidal waveform with rounded corners. (7) A method of operating the flux-gate current converter (2) according to any one of the first to sixth embodiments, comprising: 10. A method comprising generating an excitation signal for the excitation coil of the fluxgate magnetic field detector as a trapezoidal waveform with rounded corners. (8) The method of claim 7, wherein the trapezoidal waveform is generated using a flux-gate excitation lookup table (29) stored in a memory of the FPGA.

Claims

1. A flux-gate current converter (2), comprising: A control circuit (3); a fluxgate measurement device (7) including a fluxgate magnetic field detector (4); Including, The fluxgate magnetic field detector includes an excitation coil, an annular saturable soft magnetic core surrounded by the excitation coil, a compensation coil (6) arranged coaxially with the excitation coil and surrounding the annular saturable soft magnetic core, and a feedback loop (12) connected to the compensation coil (6); The feedback loop (12) is configured to cancel a magnetic field generated by a primary conductor (1) extending through a central passage (10) of the flux-gate magnetic field detector by a compensation current Is flowing through the compensation coil (6); The control circuit includes an excitation coil drive circuit (14) connected to the excitation coil and including an amplifier (20), and an AC excitation current I for alternately saturating the annular saturable soft magnetic core in a forward direction and a reverse direction. ｆｘ a controller (18) connected to the amplifier (20) of the excitation coil drive circuit configured to generate the controller is in the form of an FPGA (Field Programmable Gate Array) including a plurality of input circuit portions, each including a 1-bit sigma-delta analog-to-digital converter (ADC) (21) connected to the excitation coil separately from the excitation coil driver circuit (14) to receive a measurement signal (19) induced based on a change in the magnetic properties of the annular sigma-delta core in response to an AC excitation current I fx flowing through the excitation coil, each input circuit portion including an LVDS (Low Voltage Differential Signaling) comparator of the FPGA, the LVDS comparator forming part of the 1-bit sigma-delta ADC (21), and a bitstream output signal of the plurality of 1-bit sigma-delta ADCs (21) arranged in parallel is input to a digital filter (32) for processing.

2. 2. The current converter of claim 1, wherein the 1-bit sigma-delta ADC (21) includes a first resistor (R1) connected in series with a first input terminal (23) of the LVDS comparator, a first capacitor (C1) connected between a reference potential and the first input terminal (23), and a feedback loop from an output terminal (25) of the LVDS comparator and the first input terminal (23), the feedback loop including a 1-bit DAC (27d) and a second resistor (R2).

3. 2. The current converter of claim 1, wherein the FPGA includes a 1-bit sigma-delta digital-to-analog (DAC) output (27a) connected to the excitation coil through an RC filter (31a) to provide a voltage control signal, the voltage control signal being provided to an amplifier (20) of the excitation coil driver circuit to provide an alternating excitation current to the excitation coil of the flux-gate magnetic field detector.

4. A current converter as described in claim 1, wherein the control circuit includes a compensation coil drive circuit (13) that supplies the compensation current Is, and the FPGA includes a 1-bit sigma-delta digital-to-analog (DAC) output (27b) connected to the compensation coil via an RC filter (31b) to supply a voltage control signal to the compensation coil drive circuit.

5. 2. The current converter of claim 1, further comprising a ripple cancellation coil (26), wherein the control circuit includes a ripple cancellation coil drive circuit (28) that supplies a compensation current Is to the compensation coil of the flux-gate measurement device, the compensation current Is tending to cancel the magnetic field of the primary current Ip, and wherein the FPGA includes a 1-bit sigma-delta digital-to-analog (DAC) output (27c) connected to the ripple cancellation coil through an RC filter (31c) to provide a voltage control signal to the ripple cancellation coil drive circuit.

6. 2. The current converter of claim 1, wherein the FPGA includes an excitation voltage control circuit portion (22) configured to generate an excitation voltage control signal Ve for the excitation coil having a trapezoidal waveform with rounded corners.

7. A method of operating a flux-gate current converter (2) according to any one of claims 1 to 6, comprising the steps of:

10. A method comprising generating an excitation signal for the excitation coil of the fluxgate magnetic field detector as a trapezoidal waveform with rounded corners.

8. 8. The method of claim 7, wherein the trapezoidal waveform is generated using a fluxgate excitation lookup table (29) stored in memory of the FPGA.

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