Detection device

Abstract

This detection device has: a plurality of photodiodes provided on a substrate; a plurality of light emission parts arranged opposite to the plurality of photodiodes; and a collimating lens that is arranged between the plurality of photodiodes and the light emission parts and that enables emission of parallel light toward the plurality of photodiodes. Among the plurality of light emission parts, at least one light emission part is set to a lighting state, and the other light emission parts are set to a non-lighting state. The emission angle of parallel light from the collimating lens differs according to the position of the light emission part in the lighting state.

Description

[Technical Field]

[0001] The present invention relates to a detection device. [Background technology]

[0002] Patent Document 1 describes a display device with optical sensors that has an active matrix substrate having a plurality of pixels and optical sensors provided in the pixel region. In the display device with optical sensors in Patent Document 1, the plurality of pixels and the plurality of optical sensors are provided on the same substrate.

[0003] Patent Document 2 describes an implementation device that performs super-resolution processing to generate an image with a higher resolution than a captured image. Non-Patent Documents 1 and 2 each describe super-resolution processing techniques for acquiring high-resolution data that is higher than the resolution of the sensor. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] International Publication No. 2012 / 060303 [Patent Document 2] International Publication No. 2018 / 203373 [Non-patent literature]

[0005] [Non-Patent Document 1] Yuji Nakazawa, Takashi Komatsu & Takahiro Saito: "Sub-pixel registration for super high resolution image acquisition based on temporal integration", ICIAP 1995: Image Analysis and Processing pp 387-392 [Non-patent document 2] Shin Aoki:"Super Resolution Processing by Plural Number of Lower Resolution Images", Ricoh Technical Report No.24, NOVEMBER, 1998 Summary of the Invention [Problem to be solved by the invention]

[0006] In the display device with optical sensors in Patent Document 1, the arrangement pitch of the multiple optical sensors is larger than the arrangement pitch of the multiple pixels, so the resolution of the optical sensors is low compared to the resolution of the pixels. Detection devices equipped with such optical sensors are required to have higher detection resolution. Patent Document 2 and Non-Patent Documents 1 and 2 do not describe a specific configuration for applying super-resolution processing to a detection device equipped with optical sensors.

[0007] An object of the present invention is to provide a detection device that includes an optical sensor and is capable of acquiring an image having a resolution that exceeds the sensor resolution. [Means for solving the problem]

[0008] A detection device according to one embodiment of the present invention comprises a plurality of photodiodes provided on a substrate, a plurality of light-emitting sections arranged opposite the plurality of photodiodes, and a collimating lens arranged between the plurality of photodiodes and the light-emitting sections and emitting parallel light toward the plurality of photodiodes, wherein at least one of the plurality of light-emitting sections is in a lit state and the other light-emitting sections are in a non-lit state, and the collimating lens varies the angle at which the parallel light is emitted depending on the position of the light-emitting section in the lit state. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a cross-sectional view schematically showing a detection device according to a first embodiment. [Figure 2]FIG. 2 is a cross-sectional view schematically showing the detection device in a detection period different from that in FIG. [Figure 3] FIG. 3 is a block diagram showing an example of the configuration of the detection device according to the first embodiment. [Figure 4] FIG. 4 is a block diagram showing an example of the configuration of the detection control circuit according to the first embodiment. [Figure 5] FIG. 5 is a circuit diagram showing a sensor pixel. [Figure 6] FIG. 6 is a plan view schematically showing a sensor pixel according to the first embodiment. [Figure 7] FIG. 7 is a cross-sectional view taken along line VII-VII' in FIG. [Figure 8] FIG. 8 is an explanatory diagram schematically showing the lighting patterns of a plurality of light-emitting elements for each detection period of the light source according to the first embodiment. [Figure 9] FIG. 9 is an explanatory diagram for explaining a method for generating a super-resolution image in the detection device according to the first embodiment. [Figure 10] FIG. 10 is a plan view schematically showing a stage of the detection device according to the first embodiment. [Figure 11] FIG. 11 is a plan view showing a reference marker of the detection device according to the first embodiment. [Figure 12] FIG. 12 is an explanatory diagram for explaining the relationship between the amount of light transmitted through the reference marker and the sensor values ​​of the multiple photodiodes. [Figure 13] FIG. 13 is an explanatory diagram for explaining the relationship between the amount of light transmitted through the reference marker and the sensor values ​​of a plurality of photodiodes in a detection period different from that in FIG. [Figure 14] FIG. 14 is a plan view showing a modified example of the fiducial marker. [Figure 15] FIG. 15 is a flowchart illustrating an example of the detection operation of the detection device according to the first embodiment. [Figure 16] FIG. 16 is a cross-sectional view schematically showing a detection device according to the second embodiment. [Figure 17] FIG. 17 is a cross-sectional view schematically showing the detection device in a detection period different from that in FIG. [Figure 18] FIG. 18 is a cross-sectional view schematically showing a liquid crystal panel according to the second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] Modes (embodiments) for carrying out the present invention will be described in detail with reference to the drawings. The present disclosure is not limited to the contents described in the following embodiments. Furthermore, the components described below include those that can be easily imagined by a person skilled in the art and those that are substantially identical. Furthermore, the components described below can be combined as appropriate. Note that the disclosure is merely an example, and any appropriate modifications that a person skilled in the art can easily make while maintaining the gist of the present disclosure are naturally included within the scope of the present disclosure. Furthermore, for clarity of explanation, the drawings may schematically depict the width, thickness, shape, etc. of each part compared to the actual embodiment. However, these are merely examples and are not intended to limit the interpretation of the present disclosure. Furthermore, in this disclosure and each figure, elements similar to those previously described with reference to the preceding figures may be designated by the same reference numerals, and detailed descriptions may be omitted as appropriate.

[0011] In this specification and claims, when expressing an aspect of placing another structure on top of a certain structure, the term "on top" is used, unless otherwise specified, to include both a case in which another structure is placed directly on top of a certain structure so as to be in contact with the certain structure, and a case in which another structure is placed above a certain structure via yet another structure.

[0012] (First embodiment) Fig. 1 is a cross-sectional view schematically showing a detection device according to a first embodiment. As shown in Fig. 1, the detection device 1 includes an optical sensor 10, a stage 101, and a parallel light generating unit 80. The stage 101 and the parallel light generating unit 80 are arranged in this order above the optical sensor 10. A detection target 100 to be detected is placed on the stage 101 and is arranged between the optical sensor 10 and the parallel light generating unit 80.

[0013] The collimated light generating unit 80 has a light source 81, a light distribution lens 82, and a collimating lens 83. The light source 81 is disposed opposite the multiple photodiodes 30 (see FIG. 3) of the optical sensor 10, and has multiple light-emitting elements 85 (light emitting units). The light source 81 may have any configuration, but the multiple light-emitting elements 85 are each formed of, for example, a light-emitting diode (LED: Light Emitting Diode).

[0014] The collimating lens 83 is disposed between the light source 81 and the plurality of photodiodes 30 (see FIG. 3) of the optical sensor 10, and emits collimated light L toward the plurality of photodiodes 30. The collimating lens 83 is, for example, a Fresnel lens. However, the collimating lens 83 is not limited to this, and any lens other than a Fresnel lens, such as an aspherical lens, may be used as long as the collimating lens 83 is configured to be able to emit collimated light L. Furthermore, the collimating lens 83 is not limited to a single lens, and may be a combination of multiple lenses.

[0015] The light distributing lens 82 is provided between the light source 81 and the collimating lens 83. The light distributing lens 82 is an optical element that appropriately adjusts the light from the light emitting element 85 and outputs it toward the collimating lens 83. The light distributing lens 82 adjusts, for example, the directivity (spread angle) and distribution of the light amount of the light incident from the light emitting element 85. The number of light distributing lenses 82 is not limited to one, and multiple light distributing lenses 82 may be provided corresponding to the multiple light emitting elements 85, respectively. Alternatively, the light distributing lens 82 may be omitted.

[0016] The object to be detected 100 is a minute object such as a cell. The detection device 1 can be applied to the detection of minute objects such as cells. However, the object to be detected 100 is not limited to this, and may be a living body such as a finger, palm, or wrist. For example, the optical sensor 10 may be configured as a fingerprint detection device that detects fingerprints or a vein detection device that detects blood vessel patterns such as veins.

[0017] The stage 101 is provided between the multiple photodiodes 30 (see FIG. 3) of the optical sensor 10 and the collimating lens 83 of the collimated light generating unit 80 in a direction perpendicular to the substrate 21 (see FIG. 3) of the optical sensor 10. The object to be detected 100 is placed on the stage 101. The upper surface of the stage 101 is formed of a light-transmitting plate-like member such as glass, and is configured so that the collimated light L emitted from the collimating lens 83 passes through and reaches the optical sensor 10.

[0018] Fig. 2 is a cross-sectional view schematically showing the detection device during a detection period different from that shown in Fig. 1. As shown in Figs. 1 and 2, the light source 81 turns on at least one of the plurality of light-emitting elements 85 and turns off the other light-emitting elements 85. The light source 81 turns on the plurality of light-emitting elements 85 sequentially for each detection period.

[0019] 1, the light source 81 turns on the light-emitting element 85-2 located in the center and turns off the light-emitting elements 85-1 and 85-3 located on the left and right. The light emitted from the light-emitting element 85-2 passes through the light distribution lens 82 and the collimating lens 83, and is irradiated as parallel light L toward the multiple photodiodes 30 of the optical sensor 10. In FIG. 1, the parallel light L travels in a direction substantially perpendicular to the optical sensor 10. A portion of the parallel light L passes through the object to be detected 100 and enters the multiple photodiodes 30 of the optical sensor 10.

[0020] 2, the light source 81 turns on the light-emitting element 85-3 located on the right side and turns off the light-emitting elements 85-1 and 85-2. The light emitted from the light-emitting element 85-3 passes through the light distribution lens 82 and the collimating lens 83, and is irradiated as parallel light L toward the multiple photodiodes 30 of the optical sensor 10. In FIG. 2, the parallel light L travels in a direction inclined relative to the optical sensor 10. A portion of the parallel light L passes through the object to be detected 100 and enters the multiple photodiodes 30 of the optical sensor 10.

[0021] 1 and 2, the collimating lens 83 emits light at different angles depending on the position of the light-emitting element 85 in the lit state. Because the traveling direction of the collimated light L shown in FIG. 2 differs from the traveling direction of the collimated light L shown in FIG. 1, a deviation occurs in the projection position of the collimated light L that has passed through the detectable object 100 onto the optical sensor 10. For this reason, a positional deviation occurs between the image of the detectable object 100 captured by the optical sensor 10 in FIG. 1 and the image of the detectable object 100 captured by the optical sensor 10 in FIG. 2.

[0022] In the following description, the "positional shift" of the image refers to the positional shift of the object 100 in multiple captured images, which is caused by the shift in the projection position of the parallel light L depending on the position of the light-emitting element 85 in the lit state, even if the relative positional relationship between the optical sensor 10 and the object 100 is the same when viewed in a plane.

[0023] The detection device 1 of this embodiment acquires multiple images with misalignment by having the light source 81 sequentially scan the light-emitting elements 85 that are turned on for each detection period. The detection device 1 then combines these multiple images and performs super-resolution processing to generate a super-resolution image with a resolution higher than the resolution of the multiple photodiodes 30 of the optical sensor 10. The method of acquiring the multiple images and the generation of the super-resolution image will be described in detail below.

[0024] 3 is a block diagram showing an example of the configuration of the detection device according to the first embodiment. As shown in Fig. 3, the detection device 1 further includes a host IC 70 that controls the optical sensor 10 and the light source 81. The optical sensor 10 includes an array substrate 2, a plurality of sensor pixels 3 (photodiodes 30) formed on the array substrate 2, gate line drive circuits 15A and 15B, a signal line drive circuit 16A, and a detection control circuit 11.

[0025] The array substrate 2 is formed using a substrate 21 as a base. Each of the sensor pixels 3 includes a photodiode 30, a plurality of transistors, and various wirings. The array substrate 2 on which the photodiodes 30 are formed is a drive circuit substrate that drives the sensors for each predetermined detection area, and is also called a backplane or active matrix substrate.

[0026] The substrate 21 has a detection area AA and a peripheral area GA. The detection area AA is an area where a plurality of sensor pixels 3 (a plurality of photodiodes 30) are provided. The peripheral area GA is an area between the periphery of the detection area AA and the outer edge of the substrate 21, and is an area where a plurality of sensor pixels 3 are not provided. The gate line driving circuits 15A and 15B, the signal line driving circuit 16A, and the detection control circuit 11 are provided in the peripheral area GA.

[0027] Each of the plurality of sensor pixels 3 is an optical sensor having a photodiode 30 as a sensor element. The photodiode 30 outputs an electrical signal according to the light irradiated thereon. More specifically, the photodiode 30 is a PIN (Positive Intrinsic Negative) photodiode or an OPD (Organic Photodiode) using an organic semiconductor. The plurality of sensor pixels 3 (the plurality of photodiodes 30) are arranged in a matrix in the detection area AA.

[0028] The detection control circuit 11 is a circuit that supplies control signals Sa, Sb, and Sc to the gate line drive circuits 15A, 15B and the signal line drive circuit 16A, respectively, and controls their operations. Specifically, the gate line drive circuits 15A and 15B output gate drive signals to the sensor gate lines GLS (see FIG. 5) based on the control signals Sa and Sb. The signal line drive circuit 16A electrically connects the sensor signal line SLS selected based on the control signal Sc to the detection control circuit 11. The detection control circuit 11 also includes a signal processing circuit that processes the detection signals Vdet from the multiple photodiodes 30.

[0029] The photodiodes 30 included in the multiple sensor pixels 3 perform detection in accordance with gate drive signals supplied from the gate line drive circuits 15A and 15B. The multiple photodiodes 30 output electrical signals corresponding to the light irradiated thereon as detection signals Vdet to the signal line drive circuit 16A. The detection control circuit 11 processes the detection signals Vdet from the multiple photodiodes 30 and outputs a sensor value So based on the detection signals Vdet to the host IC 70. In this way, the detection device 1 detects information related to the object 100 to be detected.

[0030] Fig. 4 is a block diagram showing an example of the configuration of the detection control circuit according to the first embodiment. As shown in Fig. 4, the detection control circuit 11 has a detection signal amplitude adjustment circuit 41, an A / D conversion circuit 42, a signal processing circuit 43, and a detection timing control circuit 44. The detection timing control circuit 44 controls the detection signal amplitude adjustment circuit 41, the A / D conversion circuit 42, and the signal processing circuit 43 to operate synchronously based on a control signal supplied from the host IC 70 (see Fig. 3).

[0031] The detection signal amplitude adjustment circuit 41 is a circuit that adjusts the amplitude of the detection signal Vdet output from the photodiode 30, and is configured to include, for example, an amplifier. The A / D conversion circuit 42 converts the analog signal output from the detection signal amplitude adjustment circuit 41 into a digital signal. The signal processing circuit 43 is a circuit that processes the digital signal from the A / D conversion circuit 42 and transmits the sensor value So to the host IC 70.

[0032] Returning to FIG. 3, the light source 81 includes an array substrate 84, a plurality of light-emitting elements 85 formed on the array substrate 84, gate line driving circuits 15C and 15D, a signal line driving circuit 16B, and a light-emitting element control circuit 12.

[0033] The plurality of light-emitting elements 85 are arranged in a matrix in an area overlapping with the detection area AA of the array substrate 84. The array substrate 84 is a drive circuit board that drives each of the plurality of light-emitting elements 85 by switching them between on (lighted state) and off (non-lighted state).

[0034] The light-emitting element control circuit 12 is a circuit that supplies control signals Sd, Se, and Sf to the gate line driving circuits 15C, 15D and the signal line driving circuit 16B, respectively, and controls their operations. Specifically, the gate line driving circuits 15C and 15D output drive signals to gate lines (not shown) based on the control signals Sd and Se, thereby selecting light-emitting elements 85 in a predetermined row. The signal line driving circuit 16B supplies a light-emitting element control signal to a signal line (not shown) selected based on the control signal Sf. This allows the light source 81 to switch each of the multiple light-emitting elements 85 between a lit state and a non-lit state.

[0035] The array substrate 84 of the light source 81 is a so-called active matrix substrate, but is not limited to this. The on / off control of the plurality of light-emitting elements 85 may be performed by any method. For example, the light-emitting element control circuit 12 may control each of the plurality of light-emitting elements 85 individually.

[0036] The host IC 70 has, as control circuits on the optical sensor 10 side, a sensor value storage circuit 71, a reference marker storage circuit 72, a correction value generation circuit 73, and a correction value storage circuit 79. The sensor value storage circuit 71 is a circuit that stores the sensor value So output from the detection control circuit 11 of the optical sensor 10. The reference marker storage circuit 72 is a circuit that stores in advance a correlation equation that indicates the relationship between the sensor value So of the photodiode 30 at a position overlapping with the reference marker 90 (see FIG. 10) and the position of the light-emitting element 85 in an lit state.

[0037] The correction value generation circuit 73 is a circuit that calculates correction values ​​for misalignment of multiple images that occurs due to on / off switching of multiple light-emitting elements 85. The correction value generation circuit 73 may calculate the correction values ​​for misalignment of multiple images based on the correlation equation of the reference marker storage circuit 72, or may calculate the correction values ​​based on information about the position of each light-emitting element 85 in the detection device 1 and the design of the optical system. The correction value storage circuit 79 is a circuit that stores correction values ​​for misalignment of multiple images for each position of a light-emitting element 85 that is turned on. The reference marker storage circuit 72, the correction value generation circuit 73, and the correction value storage circuit 79 will be described later with reference to FIG. 10 and subsequent figures.

[0038] The host IC 70 has a lighting pattern generation circuit 74 and a lighting pattern storage circuit 75 as control circuits on the light source 81 side. The lighting pattern storage circuit 75 is a circuit that stores information on an arrangement pattern of on (lighted state) and off (non-lighted state) of a plurality of light-emitting elements 85 for each detection period F (see FIG. 8). The lighting pattern generation circuit 74 is a circuit that generates various control signals based on the arrangement pattern information in the lighting pattern storage circuit 75. The lighting pattern generation circuit 74 outputs a light-emitting element control signal including information on the arrangement pattern of the plurality of light-emitting elements 85 to the light-emitting element control circuit 12 for each detection period F.

[0039] The host IC 70 further includes an image generation circuit 76 and an image processing circuit 77. The image generation circuit 76 is a circuit that generates a plurality of images for each of a plurality of detection periods F (i.e., for each position of the light-emitting element 85 that is in an lit state) based on the sensor value So from the sensor value storage circuit 71. The image processing circuit 77 is a circuit that combines the multiple images acquired for each of the detection periods F and performs super-resolution processing to generate a single super-resolution image having a resolution higher than the resolution of the optical sensor 10. Detailed examples of the operation of the image generation circuit 76 and the image processing circuit 77 will be described later with reference to FIGS. 8 and 9.

[0040] Although not shown, the host IC 70 has a control circuit that synchronously controls the detection control circuit 11 and the light-emitting element control circuit 12. That is, based on a control signal from the host IC 70, the on / off switching of the arrangement pattern of the plurality of light-emitting elements 85 on the light source 81 side and the detection of the plurality of photodiodes 30 on the optical sensor 10 side are synchronously controlled. Note that the optical sensor 10 has two gate line drive circuits 15A and 15B, but may have one gate line drive circuit. The light source 81 has two gate line drive circuits 15C and 15D, but may have one gate line drive circuit.

[0041] Next, a configuration example of the optical sensor 10 will be described. FIG. 5 is a circuit diagram showing a sensor pixel. As shown in FIG. 5, the sensor pixel 3 includes a photodiode 30, a capacitance element Ca, and a first transistor TrS. The first transistor TrS is provided corresponding to the photodiode 30. The first transistor TrS is configured by a thin film transistor, and in this example, is configured by an n-channel MOS (Metal Oxide Semiconductor) TFT (Thin Film Transistor). The gate of the first transistor TrS is connected to a sensor gate line GLS. The source of the first transistor TrS is connected to a sensor signal line SLS. The drain of the first transistor TrS is connected to the anode of the photodiode 30 and the capacitance element Ca.

[0042] A power supply potential SVS is supplied to the cathode of the photodiode 30 from the detection control circuit 11. Furthermore, a reference potential VR1, which is the initial potential of the capacitance element Ca, is supplied from the detection control circuit 11 to the capacitance element Ca.

[0043] When light is irradiated onto the sensor pixel 3, a current corresponding to the amount of light flows through the photodiode 30, causing charge to accumulate in the capacitance element Ca. When the first transistor TrS is turned on, a current corresponding to the charge accumulated in the capacitance element Ca flows through the sensor signal line SLS. The sensor signal line SLS is connected to the detection control circuit 11 via the signal line drive circuit 16A. This allows the optical sensor 10 of the detection device 1 to detect a signal corresponding to the amount of light irradiated onto the photodiode 30 for each sensor pixel 3.

[0044] The first transistor TrS is not limited to an n-type TFT, and may be a p-type TFT. The pixel circuit of the sensor pixel 3 shown in FIG. 5 is merely an example, and the sensor pixel 3 may be provided with multiple transistors corresponding to one photodiode 30.

[0045] Next, a detailed description will be given of the configuration of the optical sensor 10. Fig. 6 is a plan view schematically showing a sensor pixel according to the first embodiment.

[0046] In the following description, the first direction Dx is a direction in a plane parallel to the substrate 21 (see FIG. 7). The second direction Dy is a direction in a plane parallel to the substrate 21, and is a direction perpendicular to the first direction Dx. The second direction Dy may intersect with the first direction Dx without being perpendicular thereto. The third direction Dz is a direction perpendicular to the first direction Dx and the second direction Dy, and is a normal direction to the main surface of the substrate 21. Furthermore, "planar view" refers to the positional relationship when viewed from a direction perpendicular to the substrate 21.

[0047] As shown in FIG. 6, the sensor pixel 3 is an area surrounded by the sensor gate line GLS and the sensor signal line SLS. In this embodiment, the sensor gate line GLS includes a first sensor gate line GLA and a second sensor gate line GLB. The first sensor gate line GLA is provided to overlap the second sensor gate line GLB. The first sensor gate line GLA and the second sensor gate line GLB are provided in different layers with insulating layers 22c and 22d (see FIG. 7) interposed therebetween. The first sensor gate line GLA and the second sensor gate line GLB are electrically connected at an arbitrary location and are supplied with a gate drive signal having the same potential. At least one of the first sensor gate line GLA and the second sensor gate line GLB is connected to the gate line drive circuits 15A and 15B. Although the first sensor gate line GLA and the second sensor gate line GLB have different widths in FIG. 6, they may have the same width.

[0048] The photodiodes 30 are provided in an area surrounded by the sensor gate lines GLS and the sensor signal lines SLS. An upper electrode 34 and a lower electrode 35 are provided corresponding to each photodiode 30. The photodiodes 30 are, for example, PIN photodiodes. The lower electrode 35 is, for example, an anode electrode of the photodiode 30. The upper electrode 34 is, for example, a cathode electrode of the photodiode 30.

[0049] The upper electrode 34 is connected to the power supply signal line Lvs via a connection wiring 36. The power supply signal line Lvs is a wiring that supplies a power supply potential SVS to the photodiode 30. In this embodiment, the power supply signal line Lvs overlaps with the sensor signal line SLS and extends in the second direction Dy. A plurality of sensor pixels 3 arranged in the second direction Dy are connected to a common power supply signal line Lvs. This configuration allows the aperture of the sensor pixel 3 to be large. The lower electrode 35, the photodiode 30, and the upper electrode 34 are each substantially rectangular in plan view. However, this is not limited thereto, and the shapes of the lower electrode 35, the photodiode 30, and the upper electrode 34 can be changed as appropriate.

[0050] The first transistor TrS is provided near the intersection of the sensor gate line GLS and the sensor signal line SLS, and includes a semiconductor layer 61, a source electrode 62, a drain electrode 63, a first gate electrode 64A, and a second gate electrode 64B.

[0051] The semiconductor layer 61 is an oxide semiconductor. More preferably, the semiconductor layer 61 is a transparent amorphous oxide semiconductor (TAOS) among oxide semiconductors. By using an oxide semiconductor for the first transistor TrS, the leakage current of the first transistor TrS can be suppressed. That is, the first transistor TrS can reduce the leakage current from the unselected sensor pixels 3. This allows the optical sensor 10 to improve the S / N ratio. However, the semiconductor layer 61 is not limited to this, and may be a microcrystalline oxide semiconductor, an amorphous oxide semiconductor, polysilicon, low temperature polycrystalline silicon (LTPS), etc.

[0052] The semiconductor layer 61 is provided along the first direction Dx and intersects with the first gate electrode 64A and the second gate electrode 64B in a plan view. The first gate electrode 64A and the second gate electrode 64B are provided branching off from the first sensor gate line GLA and the second sensor gate line GLB, respectively. In other words, portions of the first sensor gate line GLA and the second sensor gate line GLB that overlap with the semiconductor layer 61 function as the first gate electrode 64A and the second gate electrode 64B. The first gate electrode 64A and the second gate electrode 64B are made of aluminum (Al), copper (Cu), silver (Ag), molybdenum (Mo), or an alloy thereof. In addition, a channel region is formed in the portion of the semiconductor layer 61 that overlaps with the first gate electrode 64A and the second gate electrode 64B.

[0053] One end of the semiconductor layer 61 is connected to the source electrode 62 via a contact hole H1. The other end of the semiconductor layer 61 is connected to the drain electrode 63 via a contact hole H2. The portion of the sensor signal line SLS that overlaps with the semiconductor layer 61 serves as the source electrode 62. The portion of the third conductive layer 67 that overlaps with the semiconductor layer 61 functions as the drain electrode 63. The third conductive layer 67 is connected to the lower electrode 35 via a contact hole H3. With this configuration, the first transistor TrS can switch between connecting and disconnecting the photodiode 30 and the sensor signal line SLS.

[0054] Next, a description will be given of the layer structure of the optical sensor 10. Fig. 7 is a cross-sectional view taken along line VII-VII' in Fig. 6.

[0055] In the description of the detection device 1 including the optical sensor 10, the direction from the substrate 21 toward the photodiode 30 in the direction perpendicular to the surface of the substrate 21 (third direction Dz) will be referred to as the "upper side" or "top." The direction from the photodiode 30 toward the substrate 21 will be referred to as the "lower side" or "bottom."

[0056] 7, the substrate 21 is an insulating substrate, and may be, for example, a glass substrate such as quartz or alkali-free glass. The first transistor TrS, various wirings (sensor gate line GLS and sensor signal line SLS), and an insulating layer are provided on one surface of the substrate 21 to form the array substrate 2. A plurality of photodiodes 30 are arranged on the array substrate 2, i.e., on one surface of the substrate 21. The substrate 21 may be a resin substrate or a resin film made of a resin such as polyimide.

[0057] The insulating layers 22a and 22b are provided on the substrate 21. The insulating layers 22a, 22b, 22c, 22d, 22e, 22f, and 22g are inorganic insulating films, such as silicon oxide (SiO2), silicon nitride (SiN), etc. Furthermore, each inorganic insulating layer is not limited to a single layer and may be a multilayer film.

[0058] The first gate electrode 64A is provided on the insulating layer 22b. The insulating layer 22c is provided on the insulating layer 22b, covering the first gate electrode 64A. The semiconductor layer 61, the first conductive layer 65, and the second conductive layer 66 are provided on the insulating layer 22c. The first conductive layer 65 is provided to cover the end of the semiconductor layer 61 that is connected to the source electrode 62. The second conductive layer 66 is provided to cover the end of the semiconductor layer 61 that is connected to the drain electrode 63.

[0059] The insulating layer 22d is provided on the insulating layer 22c, covering the semiconductor layer 61, the first conductive layer 65, and the second conductive layer 66. The second gate electrode 64B is provided on the insulating layer 22d. The semiconductor layer 61 is provided between the first gate electrode 64A and the second gate electrode 64B in the direction perpendicular to the substrate 21. In other words, the first transistor TrS has a so-called dual-gate structure. However, the first transistor TrS may have a bottom-gate structure in which the first gate electrode 64A is provided but the second gate electrode 64B is not provided, or a top-gate structure in which the first gate electrode 64A is not provided but only the second gate electrode 64B is provided.

[0060] The insulating layer 22e is provided on the insulating layer 22d, covering the second gate electrode 64B. The source electrode 62 (sensor signal line SLS) and the drain electrode 63 (third conductive layer 67) are provided on the insulating layer 22e. In this embodiment, the drain electrode 63 is the third conductive layer 67 provided on the semiconductor layer 61 via the insulating layers 22d and 22e. The source electrode 62 is electrically connected to the semiconductor layer 61 via a contact hole H1 and a first conductive layer 65. The drain electrode 63 is electrically connected to the semiconductor layer 61 via a contact hole H2 and a second conductive layer 66.

[0061] The third conductive layer 67 is provided in a region overlapping with the photodiode 30 in plan view. The third conductive layer 67 is also provided above the semiconductor layer 61, the first gate electrode 64A, and the second gate electrode 64B. That is, the third conductive layer 67 is provided between the second gate electrode 64B and the lower electrode 35 in the direction perpendicular to the substrate 21. As a result, the third conductive layer 67 functions as a protective layer that protects the first transistor TrS.

[0062] The second conductive layer 66 extends opposite the third conductive layer 67 in a region not overlapping with the semiconductor layer 61. Furthermore, a fourth conductive layer 68 is provided on the insulating layer 22d in a region not overlapping with the semiconductor layer 61. The fourth conductive layer 68 is provided between the second conductive layer 66 and the third conductive layer 67. As a result, a capacitance is formed between the second conductive layer 66 and the fourth conductive layer 68, and a capacitance is formed between the third conductive layer 67 and the fourth conductive layer 68. The capacitance formed by the second conductive layer 66, the third conductive layer 67, and the fourth conductive layer 68 is the capacitance of the capacitive element Ca shown in FIG. 5 .

[0063] The first organic insulating layer 23a is provided on the insulating layer 22e, covering the source electrode 62 (sensor signal line SLS) and the drain electrode 63 (third conductive layer 67). The first organic insulating layer 23a is a planarizing layer that flattens unevenness formed by the first transistor TrS and various conductive layers.

[0064] Next, a description will be given of the cross-sectional structure of the photodiode 30. The photodiode 30 is formed by stacking a lower electrode 35, the photodiode 30, and an upper electrode 34 on the first organic insulating layer 23a of the array substrate 2 in this order.

[0065] The lower electrode 35 is provided on the first organic insulating layer 23a and is electrically connected to the third conductive layer 67 through a contact hole H3. The lower electrode 35 is the anode of the photodiode 30 and is an electrode for reading out the detection signal Vdet. The lower electrode 35 is made of a metal material such as molybdenum (Mo) or aluminum (Al). Alternatively, the lower electrode 35 may be a laminated film in which a plurality of these metal materials are laminated. The lower electrode 35 may also be made of a light-transmitting conductive material such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide).

[0066] The photodiode 30 includes semiconductor layers such as an i-type semiconductor layer 31, an n-type semiconductor layer 32, and a p-type semiconductor layer 33. The i-type semiconductor layer 31, the n-type semiconductor layer 32, and the p-type semiconductor layer 33 are formed of, for example, amorphous silicon (a-Si). In FIG. 7, the p-type semiconductor layer 33, the i-type semiconductor layer 31, and the n-type semiconductor layer 32 are stacked in this order in the direction perpendicular to the surface of the substrate 21. However, the opposite configuration, that is, the n-type semiconductor layer 32, the i-type semiconductor layer 31, and the p-type semiconductor layer 33 may also be used. Each semiconductor layer may be a photoelectric conversion element made of an organic semiconductor.

[0067] The n-type semiconductor layer 32 is formed by doping impurities into a-Si to form an n+ region. The p-type semiconductor layer 33 is formed by doping impurities into a-Si to form a p+ region. The i-type semiconductor layer 31 is, for example, an undoped intrinsic semiconductor and has lower conductivity than the n-type semiconductor layer 32 and the p-type semiconductor layer 33.

[0068] The upper electrode 34 is a cathode of the photodiode 30 and is an electrode for supplying the power supply potential SVS to the photoelectric conversion layer. The upper electrode 34 is a light-transmitting conductive layer made of, for example, ITO, and a plurality of upper electrodes 34 are provided for each photodiode 30.

[0069] Insulating layers 22f and 22g are provided on the first organic insulating layer 23a. Insulating layer 22f covers the periphery of the upper electrode 34, and an opening is provided in the insulating layer 22f at a position where it overlaps with the upper electrode 34. The connecting wiring 36 is connected to the upper electrode 34 at a portion of the upper electrode 34 where insulating layer 22f is not provided. Insulating layer 22g is provided on insulating layer 22f, covering the upper electrode 34 and the connecting wiring 36. A second organic insulating layer 23b, which is a planarizing layer, is provided on insulating layer 22g. In the case of an organic semiconductor photodiode 30, an insulating layer 22h may be further provided thereon.

[0070] Next, an example of a detection method of the detection device 1 of this embodiment will be described. Fig. 8 is an explanatory diagram schematically showing the lighting patterns of multiple light-emitting elements for each detection period of the light source according to the first embodiment. In Fig. 8, of the multiple light-emitting elements 85, light-emitting elements 85 in a lit state are shown in white, and light-emitting elements 85 in a non-lit state are shown with hatching.

[0071] As shown in Fig. 8, the plurality of light-emitting elements 85 of the light source 81 are arranged in a matrix in plan view. In the example shown in Fig. 8, the plurality of light-emitting elements 85-1, 85-2, ..., 85-9 are arranged in three rows and three columns. In the following description, when there is no need to distinguish between the light-emitting elements 85-1, 85-2, ..., 85-9, they will be simply referred to as light-emitting elements 85.

[0072] As shown in FIG. 8 , the light source 81 sequentially lights up the multiple light-emitting elements 85 for each detection period F. During the detection period F1, the light source 81 lights up the light-emitting element 85-1 of the multiple light-emitting elements 85 and turns off the other light-emitting elements 85-2 to 85-9. During the next detection period F2, the light source 81 lights up the light-emitting element 85-2 of the multiple light-emitting elements 85 and turns off the other light-emitting elements 85-1 and 85-3 to 85-9. Similarly, the light source 81 switches the position of the light-emitting elements 85 that are in the light-up state for each detection period F. During the final detection period F9, the light-emitting element 85-9 of the multiple light-emitting elements 85 is turned on and the other light-emitting elements 85-1 to 85-8 are turned off.

[0073] However, Figure 8 is merely an example, and the number of the plurality of light-emitting elements 85 may be eight or less, or ten or more. Furthermore, the arrangement of the plurality of light-emitting elements 85 is not limited to a matrix, and other arrangement patterns such as a triangular lattice may be used. In Figure 8, one light-emitting element 85 is turned on in each detection period F, but the light source 81 may switch between a turned-on state and a turned-off state for each light-emitting element group including adjacent plurality of light-emitting elements 85, depending on the size and light intensity of the light-emitting element 85.

[0074] The photodiode 30 of the optical sensor 10 sequentially outputs a detection signal Vdet (sensor value So) corresponding to the position of the lit light-emitting element 85 for each detection period F1, F2, ..., F9. Specifically, since the lit light-emitting elements 85 are scanned sequentially in each detection period F, the emission angle of the collimated light L emitted from the collimating lens 83 differs for each detection period F (i.e., for each position of the lit light-emitting element 85), similar to the examples shown in Figures 1 and 2.

[0075] Although the relative positional relationship between the optical sensor 10 and the object to be detected 100 is constant during each detection period F, the projection position of the parallel light L on the optical sensor 10 also differs because the emission angle of the parallel light L differs. During each detection period F, the multiple photodiodes 30 output detection signals Vdet (sensor values ​​So) according to the projection position of the parallel light L.

[0076] 9 is an explanatory diagram for explaining a method for generating a super-resolution image in the detection device according to the first embodiment. As shown in Fig. 9, the image generation circuit 76 (see Fig. 3) generates a plurality of images A1, A2, ..., A9 for each of a plurality of detection periods F based on the sensor value So from the sensor value storage circuit 71. The images A1, A2, ..., A9 correspond to, for example, images acquired during the detection periods F1, F2, ..., F9 shown in Fig. 8.

[0077] As described above, the relative positional relationship between the optical sensor 10 and the object to be detected 100 is constant for the multiple images A1, A2, ..., A9, but the projection position of the parallel light L on the optical sensor 10 is different for each detection period F. As a result, there is a positional shift of the object to be detected 100 captured in the multiple images A1, A2, ..., A9. As described above, information regarding correction values ​​for the positional shift of the multiple images A1, A2, ..., A9 is calculated in advance based on the position of each light-emitting element 85 of the detection device 1 (the position of the light-emitting element 85 in the lit state) and the design of the optical system, and is stored in the correction value storage circuit 79 (see FIG. 3) as a correction value for the image positional shift. The correction value for the image positional shift is calculated, for example, for each position of the light-emitting element 85 in the lit state, and stored in the correction value storage circuit 79 in association with the position of the light-emitting element 85 in the lit state.

[0078] Furthermore, pixel pitches P1 and P2 (resolution) of each of the multiple images A1, A2, ..., A9 are determined corresponding to the arrangement pitches PS1 and PS2 (see FIG. 3) of the photodiodes 30. The pixel pitches P1 and P2 match the arrangement pitches PS1 and PS2 of the photodiodes 30. The arrangement pitch PS1 of the photodiodes 30 in the first direction Dx is determined by the arrangement pitch of the sensor signal lines SLS (see FIG. 6) in the first direction Dx. The arrangement pitch PS2 of the photodiodes 30 in the second direction Dy is determined by the arrangement pitch of the sensor gate lines GLS (see FIG. 6) in the second direction Dy.

[0079] The image processing circuit 77 (see FIG. 3) performs super-resolution processing based on a plurality of images A1, A2, ..., A9 acquired by the image generation circuit 76 for each of a plurality of detection periods F and a correction value for image positional deviation acquired from the correction value storage circuit 79. For example, the image processing circuit 77 superimposes and combines the plurality of images A1, A2, ..., A9 based on the correction value for image positional deviation so that the position of the object 100 coincides, thereby generating a super-resolution image AX. The image processing circuit 77 can employ, for example, the methods described in Non-Patent Document 1 and Non-Patent Document 2 as specific examples of super-resolution processing.

[0080] Here, the amount of shift between the multiple images A1, A2, ..., A9 for each detection period F in plan view (specifically, the magnitude of the positional shift of the object to be detected 100) is a non-integer multiple of the arrangement pitches PS1, PS2 of the multiple photodiodes 30. In other words, the design of the optical system including the multiple light-emitting elements 85 and the collimating lens 83, etc., and the arrangement pattern of the light-emitting elements 85 in the lit state, etc. are determined so that the amount of shift between the multiple images A1, A2, ..., A9 becomes a non-integer multiple of the arrangement pitches PS1, PS2 of the multiple photodiodes 30.

[0081] 9, the resolution of the super-resolution image AX is improved compared to the resolution of the original plurality of images A1, A2, ..., A9, and the contour of the detectable object 100 in the super-resolution image AX is reproduced more clearly than the contour of the detectable object 100 in each of the plurality of images A1, A2, ..., A9. In other words, the pixel pitches PX1, PX2 of the super-resolution image AX are smaller than the pixel pitches P1, P2 of the original plurality of images A1, A2, ..., A9, respectively.

[0082] As described above, the detection device 1 can generate a super-resolution image AX having a resolution exceeding the sensor resolution of the optical sensor 10 by having the image processing circuit 77 perform super-resolution processing based on the multiple images A1, A2, ..., A9. Furthermore, the detection device 1 of this embodiment can capture multiple images A1, A2, ..., A9 with misalignment by switching on and off the multiple light-emitting elements 85 of the light source 81 while maintaining a constant relative positional relationship between the object to be detected 100 and the optical sensor 10. Therefore, a mechanism for the stage 101 for moving the object to be detected 100 and a configuration for moving the optical sensor 10 are not required, and the detection device 1 can capture multiple images A1, A2, ..., A9 with misalignment with a simple configuration.

[0083] Although the example has been described in which the correction value for image misalignment is calculated in advance and stored in the correction value storage circuit 79, the present invention is not limited to this. The image processing circuit 77 may also use a correction value acquired by the reference marker 90.

[0084] Next, a method for correcting image positional deviation using a reference marker 90 will be described. Fig. 10 is a plan view schematically showing a stage of the detection device according to the first embodiment. As shown in Fig. 10, the reference marker 90 is provided on a stage 101. In other words, the reference marker 90 is disposed between the multiple photodiodes 30 of the optical sensor 10 and the collimating lens 83 of the collimated light generating unit 80 (see Fig. 1).

[0085] The reference marker 90 is provided in a region that overlaps with the detection region AA of the stage 101 in a plan view, but does not overlap with the detection object 100. The reference marker 90 is disposed, for example, at a corner of the region that overlaps with the detection region AA of the stage 101.

[0086] Fig. 11 is a plan view showing a reference marker of the detection device according to the first embodiment. As shown in Fig. 11, a reference marker 90 has a first region 91 having high light transmittance and a second region 92 having lower light transmittance than the first region 91. In the example shown in Fig. 11, the first region 91 is a light-transmitting region made of a light-transmitting member, and the second region 92 is a light-shielding region made of a black member.

[0087] The first region 91 and the second region 92 of the reference marker 90 are arranged in a grid pattern. Specifically, the first region 91 and the second region 92 are arranged adjacent to each other in the first direction Dx. Furthermore, the first region 91 and the second region 92 are arranged adjacent to each other in the second direction Dy.

[0088] The width W1 of the second region 92 in the first direction Dx is equal to the width of the first region 91 in the first direction Dx. Furthermore, the width W2 of the second region 92 in the second direction Dy is equal to the width of the first region 91 in the second direction Dy. The widths W1 and W2 of the second region 92 are greater than twice the arrangement pitches PS1 and PS2 (see FIG. 3) of the photodiodes 30. More preferably, the widths W1 and W2 of the second region 92 are non-integer multiples of the arrangement pitches PS1 and PS2 of the photodiodes 30.

[0089] Fig. 12 is an explanatory diagram for explaining the relationship between the amount of light transmitted through the reference marker and the sensor values ​​of multiple photodiodes. Fig. 13 is an explanatory diagram for explaining the relationship between the amount of light transmitted through the reference marker and the sensor values ​​of multiple photodiodes during a detection period different from that shown in Fig. 12.

[0090] 12 and 13 schematically show detection results when the reference marker 90 is detected along line XII-XII′ shown in FIG. 11. Specifically, the upper graphs in FIGS. 12 and 13 each show the relationship between the position in the first direction Dx and the amount of light transmitted through the reference marker. The lower graphs in FIGS. 12 and 13 each show the relationship between the position in the first direction Dx and the sensor values ​​So of the multiple photodiodes 30. The lower graphs in FIGS. 12 and 13 show the sensor values ​​So for three photodiodes 30 adjacent to each other in the first direction Dx, corresponding to the arrangement pitch PS1 of the photodiodes 30. The positions of the light-emitting elements 85 in the lit state are different between the detection period Fa shown in FIG. 12 and the detection period Fb shown in FIG. 13.

[0091] 12, during detection period Fa, photodiodes 30 located at positions overlapping first region 91 of reference marker 90 output sensor value So-b. Photodiodes 30 located at positions overlapping second region 92 of reference marker 90 output sensor value So-a, which is smaller than sensor value So-b. Photodiodes 30 located at an area overlapping boundary EG between first region 91 and second region 92 of reference marker 90 output sensor value So-c.

[0092] In the photodiode 30 in the region overlapping the boundary EG, a portion of the region corresponding to the first region 91 is irradiated with the collimated light L that has passed through the first region 91. Furthermore, since the collimated light L is blocked by the second region 92, the other region of the photodiode 30 in the position overlapping the boundary EG that corresponds to the second region 92 is not irradiated with the collimated light L. Therefore, the sensor value So-c corresponding to the region straddling the boundary EG is greater than the sensor value So-a corresponding to the second region 92 and is smaller than the sensor value So-b corresponding to the first region 91.

[0093] As shown in Figure 13, during a detection period Fb different from Figure 12, the sensor value So-b of the photodiode 30 at a position overlapping the first region 91 of the reference marker 90 and the sensor value So-a of the photodiode 30 at a position overlapping the second region 92 are equivalent to those in Figure 12.

[0094] 13, the position of the light-emitting element 85 in the lit state is different from that in the detection period Fa shown in FIG. 12. Therefore, even if the relative positional relationship between the optical sensor 10 and the reference marker 90 remains the same, a deviation in the projection position of the collimated light L that has passed through the first region 91 occurs depending on the position of the light-emitting element 85 in the lit state. In the example shown in FIG. 13, the area of ​​the portion of the photodiode 30 that is positioned overlapping the boundary EG and that is irradiated with the collimated light L that has passed through the first region 91 is larger than in FIG. 12. Therefore, the sensor value So-d corresponding to the region overlapping the boundary EG is larger than the sensor value So-c corresponding to the region overlapping the boundary EG in FIG. 12.

[0095] As described above, there is a correlation between the sensor value So of the photodiode 30 at a position overlapping the boundary EG and the amount of positional deviation of the boundary EG in the captured image. The detection device 1 sequentially lights up the plurality of light-emitting elements 85 in advance and acquires the sensor value So of the photodiode 30 at a position overlapping the boundary EG for each of the light-emitting elements 85 that are lit. As a result, as described above, the reference marker storage circuit 72 (see FIG. 3) stores in advance a correlation equation that indicates the relationship between the sensor value So of the photodiode 30 at a position overlapping the reference marker 90 (see FIG. 10) and the position of the light-emitting element 85 that is lit. The correction value generation circuit 73 then calculates a correction value for positional deviation of the plurality of images for each of the light-emitting elements 85 that are lit, based on the correlation equation stored in the reference marker storage circuit 72.

[0096] In Figures 12 and 13, we have explained the correlation between the sensor value So of the photodiode 30 and the amount of positional deviation of the boundary EG of the captured image in the first direction Dx, but the reference marker memory circuit 72 (see Figure 3) also acquires the correlation between the sensor value So of the photodiode 30 and the amount of positional deviation of the boundary EG of the captured image in the second direction Dy.

[0097] Fig. 14 is a plan view showing a modified example of the reference marker. Fig. 11 shows a pattern in which the first region 91 and the second region 92 of the reference marker 90 are arranged in a grid pattern, but the present invention is not limited to this. The reference marker 90 may have any pattern as long as it has a boundary EG between the first region 91 and the second region 92 in each of the first direction Dx and the second direction Dy.

[0098] 14, a reference marker 90A according to a modified example has a first region 91 provided as a background and a second region 92 provided in a cross shape. The second region 92 is provided by intersecting a portion 92a extending in the second direction Dy with a portion 92b extending in the first direction Dx. In this modified example, there are two boundaries EG between the first region 91 and the second region 92 in the region along the line XV-XV' that intersects with the portion 92a of the second region 92. There are also two boundaries EG between the first region 91 and the second region 92 in the region that intersects with the portion 92b of the second region 92.

[0099] The width W1A of the portion 92a of the second region 92 and the width W2A of the portion 92b of the second region 92 are greater than twice the arrangement pitches PS1, PS2 (see FIG. 3) of the photodiodes 30. More preferably, the widths W1A, W2A are non-integer multiples of the arrangement pitches PS1, PS2 of the photodiodes 30.

[0100] Next, an example of the detection operation of the detection device will be described with reference to Fig. 3, Fig. 15, etc. Fig. 15 is a flowchart showing an example of the detection operation of the detection device according to the first embodiment. First, the lighting pattern generation circuit 74 of the host IC 70 sets the light-emitting element number n to n = 1 based on information from the lighting pattern storage circuit 75 (step ST1). Here, the light-emitting element number n is a natural number between 1 and N. That is, the light-emitting elements 85 are provided from light-emitting element 85-1 to light-emitting element 85-N.

[0101] The light source 81 lights up the nth (=1) light-emitting element 85-n (step ST2) based on the control signal from the lighting pattern generation circuit 74. In addition, the light source 81 keeps the other light-emitting elements 85 other than the light-emitting element 85-n in a non-lighted state.

[0102] The photodiodes 30 of the optical sensor 10 output a plurality of sensor values ​​So based on the parallel light L from the light-emitting elements 85-n in the lit state, and the sensor value storage circuit 71 stores the plurality of sensor values ​​So. The image generation circuit 76 generates an image based on the plurality of sensor values ​​So of the optical sensor 10 (step ST3). The image generation circuit 76 also generates an image of the reference marker 90 together with an image of the object 100.

[0103] The correction value generation circuit 73 calculates the amount of positional deviation of the image corresponding to the light-emitting element 85-n in the lit state by image analysis of the reference marker 90 generated in step ST3, and generates the calculated amount of positional deviation of the image as a correction value (step ST4). The correction value storage circuit 79 stores the correction value corresponding to the light-emitting element 85-n in the lit state.

[0104] The lighting pattern generation circuit 74 determines whether the light-emitting element number n is n=N (step ST5). If the light-emitting element number n is not n=N (step ST5, No), the lighting pattern generation circuit 74 updates the light-emitting element number n to n=n+1 (step ST6). Then, the detection device 1 changes the position of the light-emitting element 85 in the lit state and executes steps ST1 to ST4.

[0105] If the light-emitting element number n is n=N (step ST5, Yes), that is, if the light source 81 has completed scanning the lit light-emitting elements 85 from light-emitting element 85-1 to light-emitting element 85-N, the image processing circuit 77 performs a superposition process on the multiple images acquired by the image generation circuit 76 for each position of the lit light-emitting element 85 based on the correction value stored in the correction value memory circuit 79 calculated for each position of the lit light-emitting element 85 (step ST7).

[0106] As a result, the image processing circuit 77 performs super-resolution processing to generate a super-resolution image AX having a resolution exceeding the sensor resolution of the optical sensor 10 (step ST8).

[0107] It should be noted that the generation of the correction value in step ST4 does not necessarily have to be performed, and may be performed at predetermined intervals, for example, when starting up the detection device 1. Also, in step ST4, the generated correction value may be compared with the correlation equation held by the reference marker memory circuit 72, and if a difference occurs between these values, calibration may be performed to update the correlation equation.

[0108] (Second embodiment) 16 is a cross-sectional view schematically showing a detection device according to the second embodiment. In the following description, the same components as those described in the above-mentioned embodiments are denoted by the same reference numerals, and redundant description will be omitted.

[0109] 16 , the detection device 1A according to the second embodiment has a liquid crystal panel 50 and a light source 86 instead of the light source 81 and the light distribution lens 82 of the first embodiment described above. That is, the collimated light generation unit 80A according to the second embodiment has a liquid crystal panel 50, a light source 86, and a collimating lens 83. In the collimated light generation unit 80A, the collimating lens 83, the liquid crystal panel 50, and the light source 86 are arranged in this order in a direction perpendicular to the substrate 21 of the optical sensor 10.

[0110] The light source 86 is a backlight for the liquid crystal panel 50, and is provided on the rear surface of the liquid crystal panel 50 (the surface opposite to the optical sensor 10). The light source 86 has at least one light-emitting element 88, and emits light toward the liquid crystal panel 50. Specifically, the light source 86 includes a translucent light guide plate 87 and a light-emitting element 88 facing a side surface of the light guide plate 87. The light-emitting elements 88 are formed, for example, from LEDs, and a plurality of light-emitting elements 88 are arranged along the side surface of the light guide plate 87. The light guide plate 87 is disposed opposite the liquid crystal panel 50. The light emitted from the light-emitting element 88 propagates through the light guide plate 87 while being repeatedly reflected and scattered, and a portion of the light inside the light guide plate 87 is emitted to the liquid crystal panel 50.

[0111] The liquid crystal panel 50 is disposed opposite the multiple photodiodes 30 (see FIG. 3 ) of the optical sensor 10, and has multiple pixels Pix (light emitting portions). Although not shown, the multiple pixels Pix are arranged in a matrix in a planar view. The liquid crystal panel 50 functions as an optical filter layer that switches between a light transmitting state and a non-transmitting state for each of the multiple pixels Pix. The liquid crystal panel 50 emits light from the light source 86 that has passed through the pixels Pix in the transmitting state toward the collimating lens 83. Furthermore, the liquid crystal panel 50 blocks light from the light source 86 at the pixels Pix in the non-transmitting state, and does not emit the light toward the collimating lens 83.

[0112] The collimating lens 83 is disposed between the liquid crystal panel 50 and the plurality of photodiodes 30 (see FIG. 3) of the optical sensor 10, and emits collimated light L toward the plurality of photodiodes 30.

[0113] Fig. 17 is a cross-sectional view schematically showing the detection device during a detection period different from that shown in Fig. 16. As shown in Figs. 16 and 17, the liquid crystal panel 50 sets at least one pixel Pix of the multiple pixels Pix to a transmissive state and the other pixels Pix to a non-transmissive state. The liquid crystal panel 50 then sequentially scans the transmissive pixels Pix during each detection period. The multiple photodiodes 30 of the optical sensor 10 sequentially output detection signals Vdet (sensor values ​​So) corresponding to light transmitted through the transmissive pixels Pix during each detection period.

[0114] 16, the liquid crystal panel 50 has the pixel Pix-1 located in the center in a transmissive state and the other pixels Pix in a non-transmissive state. Light from the light source 86 passes through the transmissive pixel Pix-1 of the liquid crystal panel 50. The light emitted from the transmissive pixel Pix-1 of the liquid crystal panel 50 is converted into parallel light L by the collimating lens 83, and the parallel light L is irradiated toward the multiple photodiodes 30 of the optical sensor 10. In FIG. 16, the parallel light L travels in a direction substantially perpendicular to the optical sensor 10. A portion of the parallel light L passes through the object 100 to be detected and enters the multiple photodiodes 30 of the optical sensor 10.

[0115] In the example shown in FIG. 17, the liquid crystal panel 50 sets pixel Pix-2 adjacent to pixel Pix-1 in a transmissive state and sets the other pixels Pix in a non-transmissive state. Light from the light source 86 passes through the transmissive pixel Pix-2 of the liquid crystal panel 50. The light emitted from the transmissive pixel Pix-2 of the liquid crystal panel 50 is converted into parallel light L by the collimating lens 83, and the parallel light L is irradiated toward the multiple photodiodes 30 of the optical sensor 10. In FIG. 17, the parallel light L travels in a direction inclined with respect to the optical sensor 10. A portion of the parallel light L passes through the object 100 to be detected and enters the multiple photodiodes 30 of the optical sensor 10.

[0116] In this embodiment, the collimating lens 83 emits light at different angles depending on the position of the pixel Pix in the transmissive state. As a result, similar to the first embodiment, the traveling direction of the collimated light L shown in FIG. 17 differs from the traveling direction of the collimated light L shown in FIG. 16, causing a shift in the projection position of the collimated light L transmitted through the object 100 onto the optical sensor 10. Therefore, when the liquid crystal panel 50 sequentially scans the transmissive pixels Pix, a shift in position occurs between the multiple images of the object 100 captured by the optical sensor 10 for each position of the transmissive pixel Pix. As in the first embodiment described above, the detection device 1A can generate a super-resolution image AX by combining multiple images with a positional shift.

[0117] Fig. 18 is a cross-sectional view schematically showing a liquid crystal panel according to the second embodiment. As shown in Fig. 18, the liquid crystal panel 50 includes, for example, an array substrate SUB1, a counter substrate SUB2, and a liquid crystal layer LC. The counter substrate SUB2 is disposed opposite the array substrate SUB1. The liquid crystal layer LC is sealed between the array substrate SUB1 and the counter substrate SUB2.

[0118] The array substrate SUB1 has a first insulating substrate 51, a circuit formation layer 52, a common electrode 53, an insulating film 54, a pixel electrode 55, and a lower alignment film 56. The circuit formation layer 52, the common electrode 53, the insulating film 54, the pixel electrode 55, and the lower alignment film 56 are stacked in this order on the first insulating substrate 51 in the third direction Dz.

[0119] The first insulating substrate 51 is a light-transmitting glass substrate or film substrate. The circuit formation layer 52 is a layer on which pixel circuits including transistors of the pixels Pix and various wirings are formed. The common electrode 53 is an electrode to which a predetermined constant potential is applied. The insulating film 54 insulates the common electrode 53 from the pixel electrodes 55. The pixel electrodes 55 are provided for each pixel Pix, and the potential of each electrode is individually controlled. The lower alignment film 56 is provided to cover the pixel electrodes 55 and the insulating film 54.

[0120] The counter substrate SUB2 has a second insulating substrate 59 and an upper alignment film 58. The upper alignment film 58 is provided on the surface of the second insulating substrate 59 facing the first insulating substrate 51. The upper alignment film 58 forms the surface of the counter substrate SUB2 on the liquid crystal layer LC side. In this embodiment, no color filters are provided on the array substrate SUB1 or the counter substrate SUB2. That is, the liquid crystal panel 50 emits monochrome light toward the photodiode 30.

[0121] 18, optical elements including polarizing plates are provided on the outer surfaces of the first insulating substrate 51 and the second insulating substrate 59. The polarization axes of the pair of polarizing plates are in a crossed Nicol positional relationship in a plan view. Furthermore, the counter substrate SUB2 may be provided with a color filter or a light-shielding film as needed.

[0122] The liquid crystal layer LC modulates light passing therethrough according to the state of an electric field, and uses, for example, a liquid crystal in a transverse electric field mode such as IPS (In-Plane Switching) including FFS (Fringe Field Switching). In this embodiment, the liquid crystal layer LC is driven by a transverse electric field generated between the pixel electrodes 55 and the common electrode 53 provided on the array substrate, and the orientation of the liquid crystal molecules 57 of the liquid crystal layer LC is controlled.

[0123] However, the liquid crystal panel 50 is not limited to this configuration, and may be a vertical electric field type. In this case, the pixel electrodes are provided on the array substrate SUB1, and the common electrode is provided on the counter substrate SUB2. Vertical electric field type liquid crystal panels include TN (Twisted Nematic), VA (Vertical Alignment), and ECB (Electrically Controlled Birefringence), in which a so-called vertical electric field is applied to the liquid crystal layer.

[0124] Although preferred embodiments of the present invention have been described above, the present invention is not limited to such embodiments. The contents disclosed in the embodiments are merely examples, and various modifications are possible without departing from the spirit of the present invention. Appropriate modifications made without departing from the spirit of the present invention naturally fall within the technical scope of the present invention. At least one of various omissions, substitutions, and modifications of components can be made without departing from the spirit of each of the above-described embodiments and modifications. [Explanation of symbols]

[0125] 1. 1A detection device 2, 84 array board 3 sensor pixels 10 Optical Sensor 11 Detection control circuit 12 Light-emitting element control circuit 21 PCB 30 Photodiode 50 LCD panel 70 Host IC 71 Sensor value storage circuit 73 Correction value generation circuit 76 Image generation circuit 77 Image processing circuit 80, 80A parallel light generation section 81, 86 light source 82 Light distribution lens 83 Collimating Lens 85, 88 Light-emitting element 90, 90A reference marker 100 Object to be detected 101 Stages Pix, Pix-1, Pix-2 pixels

Claims

1. a plurality of photodiodes provided on a substrate; a plurality of light emitting units arranged opposite the plurality of photodiodes; a collimating lens disposed between the plurality of photodiodes and the light emitting unit, the collimating lens emitting collimated light toward the plurality of photodiodes; Among the plurality of light emitting portions, at least one of the light emitting portions is in a lighting state and the other light emitting portions are in a non-lighting state; The collimating lens has an output angle of the collimated light that varies depending on the position of the light output portion in a lit state. Detection device.

2. a stage provided between the plurality of photodiodes and the collimating lens in a direction perpendicular to the substrate; The object to be detected is placed on the stage. The detection device according to claim 1 .

3. the plurality of light emitting units are sequentially turned on for each detection period; The photodiode sequentially outputs a detection signal corresponding to the position of the light emitting portion in a turned-on state for each detection period. The detection device according to claim 1 .

4. an image processing circuit that generates a single image by combining a plurality of images for each detection period based on the plurality of detection signals output for each detection period and information on the lighting state of the light emitting portion for each detection period; The detection device according to claim 3 .

5. The amount of shift of the plurality of images for each detection period in plan view is a non-integer multiple of the arrangement pitch of the plurality of photodiodes. The detection device according to claim 3 .

6. a light distribution lens provided between the light emitting portion and the parallelizing lens; The detection device according to claim 1 .

7. A reference marker having a first region with high light transmittance and a second region with lower light transmittance than the first region is provided between the plurality of photodiodes and the collimating lens. The detection device according to claim 1 .

8. In a plan view, the first region and the second region of the reference marker are disposed adjacent to each other in a first direction and are disposed adjacent to each other in a second direction perpendicular to the first direction. The detection device according to claim 7.

9. Detecting the amount of image shift for each position of the light emitting portion in a lit state based on the detection signals of the plurality of photodiodes at positions overlapping the reference marker. The detection device according to claim 7.

10. a light source having a plurality of light-emitting elements and disposed opposite the plurality of photodiodes; The light emitting portion is the light emitting element. The detection device according to claim 1 .

11. a liquid crystal panel having a plurality of pixels and disposed opposite the plurality of photodiodes; The light emitting portion is the pixel. The detection device according to claim 1 .

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