Receiving circuit

Abstract

To provide a receiving circuit which is suppressed in deterioration in noise characteristics thereof within a range of small input current and furthermore can suppress an increase in offset of a differential signal.SOLUTION: A receiving circuit comprises: a transimpedance amplifier that converts into a voltage signal, a current signal input to an input node connected to an input terminal for receiving an input current; a reference voltage circuit that generates a reference voltage depending on a first feedback current; a differential amplifier circuit that generates a differential signal depending on a voltage difference between the voltage signal and the reference voltage; and an offset control circuit that generates the first feedback current and a second feedback current depending on an offset of the differential signal. The offset control circuit, when an average voltage value of the voltage signal is larger than the reference voltage, adjusts the first feedback current so that the offset of the differential signal falls within a predetermined range, and when the average voltage value of the voltage signal is smaller than the reference voltage, subtracts the second feedback current from the input current so that the offset of the differential signal falls within the predetermined range.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a receiving circuit. [Background technology]

[0002] A receiver circuit used in optical communications receives an input current signal converted from an optical signal by a photodiode or the like, and converts the received current signal into a voltage signal using a transimpedance amplifier. A receiver circuit that outputs a differential voltage signal may have an automatic offset control circuit that compensates for an offset that occurs in the differential voltage signal. The automatic offset control circuit compensates for the offset by withdrawing a portion of the input current. For example, the automatic offset control circuit controls the amount of current withdrawn from the input current so as to reduce the magnitude of the offset. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2020-5124 Summary of the Invention [Problem to be solved by the invention]

[0004] For example, if the input current is drawn even when it is close to zero in order to compensate for the offset in the receivable input current range, the noise characteristics of the receiving circuit may be degraded.Furthermore, if the draw from the input current is stopped in the range where the input current value is small in order to suppress the degradation of the noise characteristics, the offset may not be compensated.

[0005] Therefore, an object of the present disclosure is to provide a receiver circuit that can suppress an increase in offset of a differential signal while suppressing deterioration of noise characteristics in a range where the input current value is small. [Means for solving the problem]

[0006] A receiver circuit according to the present disclosure includes an input terminal for receiving an input current, a transimpedance amplifier having an input node and for converting a current signal input to the input node into a voltage signal, a reference voltage circuit for generating a reference voltage in accordance with a first feedback current, a differential amplifier circuit for generating a differential signal in accordance with a voltage difference between the voltage signal and the reference voltage, and an offset control circuit for generating the first feedback current and a second feedback current in accordance with an offset of the differential signal, wherein the input node is electrically connected to the input terminal, and the offset control circuit adjusts the first feedback current so that the offset of the differential signal falls within a predetermined range when an average voltage value of the voltage signal is greater than the reference voltage, and subtracts the second feedback current from the input current so that the offset of the differential signal falls within the predetermined range when the average voltage value of the voltage signal is smaller than the reference voltage. the transimpedance amplifier includes a first amplifier circuit that converts a current signal input to the input node into an intermediate voltage signal, and a first level shift circuit that includes a first resistor element and a first current source and that generates the voltage signal by level-shifting the intermediate voltage signal using a voltage drop caused when a first current supplied by the first current source flows through the first resistor element; the reference voltage circuit includes a second amplifier circuit that generates a reference voltage, and a second level shift circuit that includes a second resistor element and a second current source and that generates the reference voltage by level-shifting the reference voltage using a voltage drop caused when a second current supplied by the second current source flows through the second resistor element; the first feedback current flows through the second resistor element in the same direction as the direction in which the second current flows; the transimpedance amplifier generates the voltage signal such that the voltage signal becomes smaller as the current signal becomes larger; the differential signal has a pair of positive and negative phase signals, and an offset of the differential signal represents a difference between a DC component of the positive phase signal and a DC component of the negative phase signal. . [Effects of the Invention]

[0007] According to the present disclosure, it is possible to provide a receiver circuit that can suppress an increase in offset of a differential signal while suppressing deterioration of noise characteristics in a range where the input current value is small. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a block diagram illustrating an example of a receiving circuit according to the first embodiment. [Figure 2] FIG. 2 is a circuit diagram illustrating an example of the transimpedance amplifier stage of FIG. [Figure 3] FIG. 3 is a circuit diagram showing an example of the automatic offset control circuit of FIG. [Figure 4] FIG. 4 is a diagram showing the DC transfer characteristic of the automatic offset control circuit of FIG. [Figure 5] FIG. 5 is a diagram illustrating an example of the operating characteristics of the receiving circuit of FIG. [Figure 6] FIG. 6 is an enlarged view of the output voltage of FIG. [Figure 7]FIG. 7 is a circuit diagram illustrating an example of an automatic offset control circuit mounted on the receiver circuit according to the second embodiment. [Figure 8] FIG. 8 is a block diagram showing an example of another receiving circuit. [Figure 9] FIG. 9 is a diagram illustrating an example of the operating characteristics of the receiving circuit of FIG. [Figure 10] FIG. 10 is a diagram showing another example of the operating characteristics of the receiving circuit of FIG. [Figure 11] FIG. 11 is a block diagram illustrating an example of a receiving circuit according to the third embodiment. [Figure 12] FIG. 12 is a circuit diagram showing an example of the automatic offset control circuit of FIG. [Figure 13] FIG. 13 is a block diagram illustrating an example of a receiving circuit according to the fourth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] [Description of the embodiments of the present disclosure] First, embodiments of the present disclosure will be listed and described.

[0010] [1] A receiving circuit according to one aspect of the present disclosure includes an input terminal for receiving an input current, a transimpedance amplifier having an input node and converting a current signal input to the input node into a voltage signal, a reference voltage circuit for generating a reference voltage according to a first feedback current, a differential amplifier circuit for generating a differential signal according to a voltage difference between the voltage signal and the reference voltage, and an offset control circuit for generating the first feedback current and a second feedback current according to an offset of the differential signal, wherein the input node is electrically connected to the input terminal, and the offset control circuit adjusts the first feedback current so that the offset of the differential signal falls within a predetermined range when the average voltage value of the voltage signal is greater than the reference voltage, and subtracts the second feedback current from the input current so that the offset of the differential signal falls within the predetermined range when the average voltage value of the voltage signal is smaller than the reference voltage.

[0011] In this receiver circuit, when the average voltage value of the voltage signal is greater than the reference voltage, an increase in the offset of the differential signal can be suppressed by flowing a first feedback current through the reference voltage circuit so that the offset of the differential signal falls within a predetermined range. Because the increase in the offset of the differential signal can be suppressed without relying on the second feedback current, for example, the second feedback current can be set to zero in a range where the input current value is small, thereby suppressing noise degradation. In other words, the increase in the offset of the differential signal can be suppressed while suppressing noise degradation in a range where the input current value is small.

[0012] [2] In the above [1], the transimpedance amplifier may include a first amplifier circuit that converts a current signal input to the input node into an intermediate voltage signal, and a first level shift circuit that includes a first resistor and a first current source and that generates the voltage signal by level-shifting the intermediate voltage signal using a voltage drop caused by a first current supplied by the first current source flowing through the first resistor. By level-shifting the intermediate voltage signal from the first amplifier circuit and supplying it to the differential amplifier circuit, the voltage value of the voltage signal can be set within a voltage range that allows the differential amplifier circuit to operate appropriately. As a result, the differential amplifier circuit can generate an appropriate differential signal according to the input current.

[0013] [3] In the above [2], the reference voltage circuit may include a second amplifier circuit that generates a reference voltage, and a second level shift circuit that includes a second resistor element and a second current source and that generates the reference voltage by level-shifting the reference voltage using a voltage drop caused by a second current supplied by the second current source flowing through the second resistor element, and the first feedback current may flow through the second resistor element in the same direction as the second current. By causing the first feedback current from the offset control circuit to flow through the second resistor element in the same direction as the second current, the reference voltage provided to the differential amplifier circuit can be directly adjusted to suppress an increase in offset of the differential signal.

[0014] [4] In the above [2], the reference voltage circuit may include a second amplifier circuit that generates a reference voltage, and a second level shift circuit that includes a second resistor element and a second current source and that generates the reference voltage by level-shifting the reference voltage using a voltage drop caused by a second current supplied by the second current source flowing through the second resistor element, and the offset control circuit may draw the first feedback current from an input node of the second amplifier circuit. By drawing the first feedback current from the input node of the second amplifier circuit using the offset control circuit, the input voltage of the second amplifier circuit can be adjusted to adjust the reference voltage provided to the differential amplifier circuit, thereby suppressing an increase in offset of the differential signal.

[0015] [5] In the above [3] or [4], the second amplifier circuit may be configured with the same circuit elements as the first amplifier circuit. This allows for accurate adjustment of the offset between the voltage value of the voltage signal and the reference voltage. Furthermore, common design data can be used, simplifying the circuit design of the receiver circuit.

[0016] [6] In any one of the above [1] to [5], the offset control circuit may include a differential integrator that generates a control voltage according to the offset of the differential signal, and may invert the magnitude relationship between the magnitude of the first feedback current and the magnitude of the second feedback current according to the control voltage. This makes it possible to control the generation and switching of the first feedback current and the second feedback current based on the control voltage generated by the differential integrator according to the differential signal that changes depending on the input current.

[0017] [7] In any of the above [1] to [6], the value of the reference voltage when the first feedback current is zero may be set to be smaller than the average voltage value of the voltage signal when the current signal is zero. This allows the offset control circuit to perform automatic offset control that suppresses an increase in the offset of the differential signal by adjusting the first feedback current when the input signal is small and the average voltage value of the voltage signal is larger than the reference voltage, and adjusting the second feedback current when the input signal is large and the average voltage value of the voltage signal is smaller than the reference voltage.

[0018] [8] In any of the above [1] to [7], the transimpedance amplifier, the reference voltage circuit, the differential amplifier circuit, and the offset control circuit may be integrated into a single semiconductor integrated circuit chip. This reduces variations in electrical characteristics between multiple circuits formed using the same elements, and improves the accuracy of the offset adjustment of the differential signal by the offset control circuit.

[0019] [Details of the embodiments of the present disclosure] Specific examples of receiving circuits according to the present disclosure will be described below with reference to the drawings. In the following description, identical or corresponding elements will be designated by the same reference numerals, and descriptions of these elements may be omitted. Furthermore, the reference numerals for terminals, signal lines, and nodes are also used to indicate signals, voltages, or currents.

[0020] [First embodiment] [Circuit configuration of receiving circuit] Fig. 1 is a block diagram showing an example of the configuration of a receiving circuit according to the first embodiment. For example, the receiving circuit 100 shown in Fig. 1 is included in an optical receiver that receives an optical signal. The receiving circuit 100 has an input terminal In that receives an input current Iin from a light-receiving element (such as a photodiode) (not shown), and output terminals OutN / OutP that output voltage signals generated in accordance with the input current Iin as differential signals OutN / OutP.

[0021] The light receiving element generates an input current Iin in response to the received optical signal. The optical signal transmitted through the long-distance optical fiber becomes weak, and the input current Iin also becomes weak. The receiving circuit 100 amplifies the input current Iin and converts it into a voltage signal. The receiving circuit 100 outputs the voltage signal as a differential signal OutN / OutP. The differential signal OutN / OutP has a pair of output signals OutP and OutN. One of the pair of output signals, OutP, is also referred to as a positive-phase signal, and the other of the pair of output signals, OutN, is also referred to as a negative-phase signal. The positive-phase signal OutP and the negative-phase signal OutN are complementary to each other, and the positive-phase signal OutP has a phase that is 180° different from the phase of the negative-phase signal OutN.

[0022] For example, when the positive-phase signal OutP increases, the negative-phase signal OutN decreases, and when the positive-phase signal OutP decreases, the negative-phase signal OutN increases. For example, when the positive-phase signal OutP reaches its peak value, the negative-phase signal OutN reaches its bottom value, and when the positive-phase signal OutP reaches its bottom value, the negative-phase signal OutN reaches its peak value. For example, the negative-phase signal OutN has the same amplitude as the amplitude of the positive-phase signal OutP.

[0023] When the receiver circuit 100 does not compensate for the offset, for example, when the average value (DC component) of the input current Iin increases, the receiver circuit 100 increases the voltage value (DC component) of the output signal OutP and decreases the voltage value (DC component) of the output signal OutN. When the receiver circuit 100 does not compensate for the offset, when the average value (DC component) of the input current Iin decreases, the receiver circuit 100 decreases the voltage value (DC component) of the output signal OutP and increases the voltage value (DC component) of the output signal OutN.

[0024] The receiver circuit 100 reduces the difference between the voltage value (DC component) of the output signal OutP and the voltage value (DC component) of the output signal OutN by performing offset compensation. The offset represents the difference between the voltage value (DC component) of the output signal OutP and the voltage value (DC component) of the output signal OutN. In other words, offset compensation means bringing the offset closer to zero. The receiver circuit 100 amplifies the signal component (AC component) of the input current and converts it into a voltage signal, outputting it as the signal component (AC component) of the differential signal OutN / OutP. The amplitude of the signal component of the differential signal OutN / OutP is equal to the difference between the signal component of the positive-phase signal OutP and the signal component of the negative-phase signal OutN. For example, as the amplitude of the signal component of the input current Iin increases, the amplitude of the signal component of the differential signal OutN / OutP also increases. The differential signals OutN / OutP output from the output terminals OutN / OutP are output to a signal processing circuit, such as a DSP (Digital Signal Processor), for processing.

[0025] The receiver circuit 100 includes, for example, a transimpedance amplifier stage TIA, a level shift circuit LS1, a dummy transimpedance amplifier stage DTIA, a level shift circuit LS2, a buffer BUF, and an automatic offset control circuit AOC1.

[0026] For example, each circuit of the receiver circuit 100 is integrated on a single semiconductor integrated circuit chip. This reduces variations in electrical characteristics between multiple circuits formed using the same circuit elements. For example, by making the transimpedance amplifier stage TIA and the dummy transimpedance amplifier stage DTIA similar in circuit configuration to each other, the effects of variations in their respective electrical characteristics can be reduced. Furthermore, by making the level shift circuit LS1 and the level shift circuit LS2 similar in circuit configuration to each other, the effects of variations in their respective electrical characteristics can be reduced. As a result, the accuracy of the offset adjustment of the differential signals OutP / OutN by the automatic offset control circuit AOC1 can be improved.

[0027] The transimpedance amplifier stage TIA and the dummy transimpedance amplifier stage DTIA may have the same circuit configuration, so that the transimpedance amplifier stage TIA and the dummy transimpedance amplifier stage DTIA have the same electrical characteristics.Furthermore, the level shift circuit LS1 and the level shift circuit LS2 may have the same circuit configuration, so that the level shift circuit LS1 and the level shift circuit LS2 have the same electrical characteristics.

[0028] The transimpedance amplifier stage TIA and the level shift circuit LS1 are an example of a transimpedance amplifier. The transimpedance amplifier stage TIA is an example of a first amplifier circuit. The dummy transimpedance amplifier stage DTIA and the level shift circuit LS2 are an example of a reference voltage circuit. The dummy transimpedance amplifier stage DTIA is an example of a second amplifier circuit that generates a reference voltage. The buffer BUF is an example of a differential amplifier circuit. Hereinafter, the transimpedance amplifier stage TIA will also be simply referred to as the TIA stage, and the dummy transimpedance amplifier stage DTIA will also be simply referred to as the DTIA stage.

[0029] The TIA stage includes an inverter amplifier INV1 and a resistor R1. The input of the inverter amplifier INV1 is electrically connected to the input terminal In via an input node TIAin of the TIA stage. The output of the inverter amplifier INV1 is connected to the level shift circuit LS1 via an output node TIAout of the TIA stage. The resistor R1 is connected between the input node TIAin and the output node TIAout.

[0030] The TIA stage converts the input current Iin input to the input node TIAin into a voltage signal using the inverter amplifier INV1 and the resistor element R1, inverts and amplifies the voltage, and outputs the inverted and amplified voltage signal to the output node TIAout. The inverter amplifier INV1 is, for example, an inverting amplifier circuit. For example, as the input current Iin increases, the voltage output to the output node TIAout decreases, and as the input current Iin decreases, the voltage output to the output node TIAout increases. The gain of the TIA stage is expressed as impedance (resistance value). The gain of the TIA stage is mainly determined by the resistance value of the resistor element R1.

[0031] The level shift circuit LS1 includes, for example, a resistor RLS1, a capacitor CLS1, and a current source ILS1. The resistor RLS1 and the capacitor CLS1 are connected in parallel between an output node TIAout of the TIA stage and a node Vtia connected to one input of the buffer BUF. The current source ILS1 is connected between a power supply line VCC and the node Vtia. The power supply line VCC is a power supply wiring for supplying a power supply voltage VCC.

[0032] The level shift circuit LS1 generates a voltage signal Vtia by level-shifting the voltage signal TIAout output from the TIA stage to a higher potential side by using a voltage drop across the resistor element RLS1 caused by the current supplied by the current source ILS1 flowing through the resistor element RLS1. The voltage signal TIAout is an example of an intermediate voltage signal.

[0033] The capacitive element CLS1 transmits high-frequency components of the signal input to the level shift circuit LS1 to the output faster than the resistive element RLS1. For example, the capacitive element CLS1 suppresses degradation of the rising and falling edges of the pulse wave level-shifted by the level shift circuit LS1. The capacitive element CLS1 is a so-called speed-up capacitor. The current source ILS1 can be configured, for example, with a p-channel MOS (Metal Oxide Semiconductor) transistor. Note that, in order to adjust the amount of current supplied, the current source ILS1 may be configured with a current mirror circuit including a p-channel MOS transistor. Alternatively, the current source ILS1 may be configured using a resistive element instead of a p-channel MOS transistor.

[0034] This allows the average value of the output voltage of the level shift circuit LS1 to be greater than the average value of the input voltage to the level shift circuit LS1. The level shift circuit LS1 can then set the voltage value of the voltage signal Vtia input to the buffer BUF within a voltage range that allows the buffer BUF to operate appropriately. As a result, the buffer BUF can generate an appropriate differential signal according to the input current Iin. For example, the signal component of the voltage signal Vtia generated according to the signal component of the input current Iin is superimposed on the voltage value (average value) of the voltage signal Vtia and input to the buffer BUF. Note that while the current from the current source ILS1 flows into the TIA stage, the current flowing from the current source ILS1 into the TIA stage is offset by increasing the current amount of the current source (ITIA in Figure 2) inside the TIA stage.

[0035] Instead of increasing the current amount of the current source inside the TIA stage, a current source may be added between the input node of the level shift circuit LS1 connected to the output node TIAout and the ground line GND, and current from the current source ILS1 may be passed through the added current source. In this case, the added current source may be configured, for example, by an n-channel MOS transistor. In order to adjust the current amount, it may also be configured by a current mirror circuit including an n-channel MOS transistor. Alternatively, the added current source may be configured using a resistive element instead of an n-channel MOS transistor.

[0036] The DTIA stage has the same circuit configuration as, for example, the TIA stage, except that no input current is input to the input terminal. Configuring the DTIA stage using the same circuit elements as the TIA stage simplifies the circuit design of the receiver circuit 100. The DTIA stage includes an inverter amplifier INV2 and a resistor element R2 connected between the output and input of the inverter amplifier INV2. For example, the circuit configuration of the inverter amplifier INV2 may be the same as that of the inverter amplifier INV1, and the resistance value of the resistor element R2 may be the same as that of the resistor element R1. The DTIA stage generates a predetermined reference voltage and outputs the generated reference voltage to the level shift circuit LS2. For example, as described below, the voltage value of the DTIA stage reference voltage is set to be smaller than the voltage value of the voltage signal TIAout output from the TIA stage when the input current Iin is zero (note that no extraction is performed when the input current Iin is zero).

[0037] The level shift circuit LS2 includes, for example, a resistive element RLS2, a capacitive element CLS2, and a current source ILS2. The resistive element RLS2 is connected between the output of the DTIA stage and a reference voltage line Vref connected to the other input of the buffer BUF. The capacitive element CLS2 is connected between the reference voltage line Vref and a ground line GND. The current source ILS2 is connected between a power supply line VCC and the reference voltage line Vref.

[0038] The level shift circuit LS2 generates a reference voltage Vref on the reference voltage line Vref by level-shifting the reference voltage output from the DTIA stage to a higher potential side using a voltage drop across the resistor element RLS2 caused by the current supplied by the current source ILS2 flowing through the resistor element RLS2. Similar to the level shift circuit LS1, the level shift circuit LS2 can make the average value of the output voltage of the level shift circuit LS2 greater than the average value of the input voltage to the level shift circuit LS2.

[0039] The capacitance element CLS2 transfers noise generated on the reference voltage line Vref to the ground line GND, stabilizing the voltage of the reference voltage line Vref (reference voltage Vref). The capacitance element CLS1 is a so-called bypass capacitor. The current source ILS2 can be configured, for example, by a p-channel MOS transistor. Note that, in order to adjust the amount of current supplied, the current source ILS2 may be configured by a current mirror circuit including a p-channel MOS transistor. Alternatively, the current source ILS2 may be configured using a resistive element instead of a p-channel MOS transistor.

[0040] For example, if the current source ILS1 is configured with a p-channel MOS transistor, the current source ILS2 may also be configured with a p-channel MOS transistor. In this case, it is preferable that the p-channel MOS transistor configuring the current source ILS2 has the same electrical characteristics as the p-channel MOS transistor configuring the current source ILS1. While the current from the current source ILS2 flows into the DTIA stage, the current flowing from the current source ILS2 into the DTIA stage can be offset by increasing the current amount of the current source within the DTIA stage. Instead of increasing the current amount of the current source within the DTIA stage, a current source may be added between the input node of the level shift circuit LS2 connected to the output node of the DTIA stage and the ground line GND, and the current from the current source ILS2 may be passed through that current source.

[0041] As will be described later, the reference voltage Vref is set to a value smaller than the average value (DC component) of the voltage Vtia when the input current Iin is zero when the automatic offset control circuit AOC1 is not operating (feedback current Iaoc1=0). As the input current Iin increases, the voltage value (average value) of the voltage signal Vtia decreases. As the input current Iin continues to increase, it eventually becomes smaller than the reference voltage Vref. When the voltage value (average value) of the voltage signal Vtia is smaller than the reference voltage Vref, the feedback current Iaoc1 is extracted from the input current Iin input to the input terminal In, thereby reducing the current signal input to the input node TIAin and increasing the voltage of the voltage signal Vtia, bringing it closer to the reference voltage Vref. As a result, the offset control circuit AOC1 can perform automatic offset control that suppresses increases in the offset of the differential signals OutP / OutN.

[0042] The buffer BUF has a differential input and a differential output. The buffer BUF differentially amplifies the difference Vtia-Vref between the voltage of the voltage signal Vtia received at the differential input and a reference voltage Vref, and outputs the difference Vtia-Vref to the output terminals OutN / OutP as a differential signal OutN / OutP. By generating the reference voltage Vref in this way, the single-phase voltage signal Vtia generated from the single-phase input current Iin can be converted into a differential signal OutN / OutP. The buffer BUF may be composed of a single amplifier or may be composed of multiple amplifiers connected in cascade.

[0043] The buffer BUF performs inverting amplification. For example, the voltage signal Vtia is input to the non-inverting input terminal of the buffer BUF, and a reference voltage Vref is input to the inverting input terminal of the buffer BUF. The non-inverting output terminal of the buffer BUF is connected to the output terminal OutN, and the inverting output terminal of the buffer BUF is connected to the output terminal OutP. As a result, when the voltage signal Vtia increases, the positive-phase signal OutP decreases, and when the voltage signal Vtia decreases, the positive-phase signal OutP increases.

[0044] The automatic offset control circuit AOC1 has input terminals InP and InN connected to the output terminals OutP and OutN, respectively, a feedback current terminal Iaoc1 connected to the input terminal In, and a feedback current terminal Iaoc2 connected to a reference voltage line Vref. The automatic offset control circuit AOC1 subtracts the feedback current Iaoc1 from the input current Iin input to the input terminal In, or outputs the feedback current Iaoc2 to the reference voltage line Vref, depending on the voltage difference OutP-OutN between the differential signals OutP and OutN received at the input terminals InP and InN. That is, the automatic offset control circuit AOC1 subtracts the feedback current Iaoc1 from the input current Iin input to the input terminal In, or outputs the feedback current Iaoc2 to the reference voltage line Vref, depending on the magnitude relationship between the average voltage values ​​of the output signal OutP and the output signal OutN.

[0045] The automatic offset control circuit AOC1 controls switching of the change characteristics of the feedback currents Iaoc1 and Iaoc2 depending on whether the input current value Iin is smaller or larger than a predetermined value. For example, when the input current value Iin is smaller than a predetermined value, the automatic offset control circuit AOC1 controls not to flow the feedback current Iaoc1 but to flow a feedback current Iaoc2 that is added to the current supplied by the current source ILS2. Here, the current addition is achieved by flowing the feedback current Iaoc2, which has the same direction as the current supplied by the current source ILS2, through the resistor element RLS2. Furthermore, when the input current Iin is equal to or larger than a predetermined value, the automatic offset control circuit AOC1 controls to flow the feedback currents Iaoc1 and Iaoc2 in accordance with the input current Iin. The feedback current Iaoc2 is an example of a first feedback current, and the feedback current Iaoc1 is an example of a second feedback current.

[0046] The differential signals OutP / OutN vary depending on the input current Iin. For example, if no current flows through the feedback current terminal Iaoc1, when the input current Iin increases, the voltage signal Vtia decreases and the differential signals OutP / OutN increase. On the other hand, when the input current Iin decreases, the voltage signal Vtia increases and the differential signals OutP / OutN decrease. Therefore, the differential signals OutP / OutN are generated as non-inverted, amplified signals of the input current Iin.

[0047] Therefore, the automatic offset control circuit AOC1 can perform the above-mentioned automatic offset control by monitoring the voltage of the differential signals OutP / OutN. That is, the automatic offset control circuit AOC1 can control the feedback current Iaoc1 (0 mA or more) and the feedback current Iaoc2 (0 mA or more) so that the DC (Direct Current) offset of the differential signals OutP / OutN falls within an allowable range. As a result, the buffer BUF can be operated at an appropriate operating point regardless of the magnitude of the input current Iin, and good amplification characteristics with suppressed DC offset can be obtained. An example of the circuit configuration of the automatic offset control circuit AOC1 is shown in FIG. 3, and an example of the operation of the automatic offset control circuit AOC1 is shown in FIG. 4.

[0048] When the input current Iin is greater than a predetermined value, by flowing not only the feedback current Iaoc1 but also the feedback current Iaoc2 in response to the increase in the input current Iin, it is possible to increase the base-collector voltage Vcb of the first-stage cascode transistor (Q2 in Figure 2) of the TIA stage. More specifically, by flowing the feedback current Iaoc2, the reference voltage Vref gradually increases as the input current Iin increases, and the average value (DC component) of the voltage signal Vtia approaches the reference voltage Vref. As a result, the voltage value (average value) of the voltage signal Vtia becomes larger than when the feedback current Iaoc2 is not flowing. This increases the operating margin of the transimpedance amplifier (TIA stage + LS1) when the input current Iin is large.

[0049] The current value of the input current Iin that switches the change characteristics of the feedback currents Iaoc1 and Iaoc2 can be set by adjusting the reference voltage Vref when the feedback current Iaoc2=0 mA. For example, the reference voltage Vref when the feedback current Iaoc2=0 mA is set to be smaller than the voltage value (average value) of the voltage signal Vtia when the input current Iin=0 mA. The reference voltage Vref is adjusted by adjusting the current value of the current source ILS2 of the level shift circuit LS2. For example, the current value of the input current Iin that switches the change characteristics of the feedback currents Iaoc1 and Iaoc2 is set to Iswitch.

[0050] At this time, the current flowing through current source ILS2 is set so that the reference voltage Vref is equal to the "voltage value (average value) of the voltage signal Vtia when Iin = Iswitch." For example, assume that the transimpedance amplifier (TIA stage + LS1) and the reference voltage circuit (DTIA stage + LS2) have the same electrical characteristics and the resistance values ​​of the resistor elements RLS1 and RLS2 are equal. In this case, the current value of current source ILS1 is set to be greater than the current value of current source ILS2.

[0051] [Transimpedance amplifier stage circuit configuration] FIG. 2 is a circuit diagram showing an example of the transimpedance amplifier stage TIA of FIG. 1. The circuit configuration of the DTIA stage of FIG. 1 is the same as that of FIG. 2, except that no input current is input to the input terminal (the input terminal is open). The TIA stage has a load resistor RL connected in series between a power supply line VCC and a ground line GND, and cascode-connected transistors Q2 and Q1. The TIA stage also has a transistor Q3 and a current source ITIA connected in series between the power supply line VCC and the ground line GND. The TIA stage also has a feedback resistor RF connected between the input terminal TIAin and the output terminal TIAout. The feedback resistor RF corresponds to the resistor R1 of FIG. 1.

[0052] Transistor Q2 receives a bias voltage Vcas at its base and operates as a cascode transistor. Transistor Q1 has its base connected to the input terminal TIAin and receives an input current Iin. Transistor Q1's emitter is grounded to the ground line GND and its collector is connected to the emitter of transistor Q2, so it operates as an amplifying transistor. The collector voltage of transistor Q1 is maintained at a constant value corresponding to the bias voltage Vcas even when transistor Q1 is amplifying, thereby suppressing the mirror effect of the base-collector capacitance of transistor Q1. The collector current of transistor Q1 flows through resistor RL via transistor Q2, causing a voltage drop. The collector voltage of transistor Q2 is a voltage corresponding to the voltage drop across resistor RL, with power supply voltage Vcc as the reference potential.

[0053] The transistor Q3 has its base connected to the collector of the transistor Q2 and its emitter connected to the output terminal TIAout, and operates as an emitter follower. The TIA stage operates as an inverting amplifier that inverts and amplifies a voltage corresponding to the input current Iin received at the input terminal TIAin and outputs the amplified voltage from the output terminal TIAout. The current source ITIA can be configured, for example, with an n-channel MOS transistor. It may also be configured with a current mirror circuit including an n-channel MOS transistor to adjust the current amount. Alternatively, the current source ITIA may be configured using a resistive element instead of an n-channel MOS transistor.

[0054] Since the collector of transistor Q2 is connected to the base of emitter-follower transistor Q3, the collector voltage of transistor Q2 has the same polarity as the output voltage TIAout. Therefore, when the output voltage TIAout decreases, the collector voltage of transistor Q2 also decreases, and the base-collector voltage Vcb of transistor Q2 decreases. When the output voltage TIAout increases, the collector voltage of transistor Q2 also increases, and the base-collector voltage Vcb of transistor Q2 increases. When the base-collector voltage Vcb decreases, the operating margin of transistor Q2 decreases, so it is preferable to keep it above a specified value.

[0055] [Circuit configuration of automatic offset control circuit] Figure 3 is a circuit diagram showing an example of the automatic offset control circuit AOC1 of Figure 1. The automatic offset control circuit AOC1 has a differential integrator DI, p-channel MOS (Metal Oxide Semiconductor) transistors PM1, PM2, PM3, PM4, and PM5, and n-channel MOS transistors NM1, NM2, NM3, and NM4. The automatic offset control circuit AOC1 also has diodes D1 and D2 and current sources I1 and I2. Hereinafter, the p-channel MOS transistors PM1-PM5 and the n-channel MOS transistors NM1-NM4 will be referred to as transistors PM1-PM5 and transistors NM1-NM4, respectively.

[0056] The differential integrator DI has resistors R31 and R32, capacitors C31 and C32, and an operational amplifier OPA. One input (non-inverting input terminal) of the operational amplifier OPA is connected to an input terminal InP via the resistor R31, and the other input (inverting input terminal) of the operational amplifier OPA is connected to an input terminal InN via the resistor R32. The capacitor C31 is connected between one input of the operational amplifier OPA and the other output (inverting output terminal) of the operational amplifier OPA. The other output of the operational amplifier OPA is connected to a control terminal Vaoc1. The capacitor C32 is connected between the other input of the operational amplifier OPA and one output (non-inverting output terminal) of the operational amplifier OPA. One output of the operational amplifier OPA is connected to a control terminal Vaoc2.

[0057] The differential integrator DI generates control voltages Vaoc1 and Vaoc2 in response to input voltages VInP / VInN, which are the voltage values ​​of the differential signals OutP / OutN. Then, the automatic offset control circuit AOC1 inverts the magnitude relationship between the magnitude of the feedback current Iaoc2 and the magnitude of the feedback current Iaoc1 in response to the input voltages VInP / VInN, as shown in FIG.

[0058] The resistor R31 and the capacitor C31, and the resistor R32 and the capacitor C32, function as RC filters (low-pass filters), respectively. The differential integrator DI smoothes the input voltages InP and InN. The operational amplifier OPA operates as a differential integrator, differentially amplifying the voltage signals obtained by smoothing the input voltages InP and InN received via the resistors R31 and R32, respectively, and outputting them as control voltages Vaoc1 and Vaoc2.

[0059] For example, if the average value of the input voltage InP is greater than the average value of the input voltage InN, the control voltage value Vaoc1 will be smaller than the control voltage value Vaoc2. If the average value of the input voltage InP is smaller than the average value of the input voltage InN, the control voltage value Vaoc1 will be greater than the control voltage value Vaoc2.

[0060] That is, when the difference voltage VInP-VinN between the average value of the input voltage InP and the average value of the input voltage InN is positive, the control voltage value Vaoc2 generated by the non-inverting amplification operation of the operational amplifier OPA is greater than the control voltage value Vaoc1 generated by the inverting amplification operation of the operational amplifier OPA. Also, when the difference voltage VInP-VinN is negative, the control voltage value Vaoc2 generated by the non-inverting amplification operation of the operational amplifier OPA is smaller than the control voltage value Vaoc1 generated by the inverting amplification operation of the operational amplifier OPA.

[0061] The control terminal Vaoc1 is connected to the gate of the transistor NM4 and the current source I1 via the diode D1, so that a voltage obtained by subtracting the voltage drop caused by the diode D1 from the control voltage Vaoc1 is applied to the gate of the transistor NM4.

[0062] The control terminal Vaoc2 is connected to the gate of the transistor NM1 and the current source 12 via the diode D2, so that a voltage obtained by subtracting the voltage drop caused by the diode D2 from the control voltage Vaoc2 is applied to the gate of the transistor NM1.

[0063] The transistors PM1 and NM1 are connected in series between the power supply line VCC and the ground line GND. The transistors PM2 and NM2 are connected in series between the power supply line VCC and the ground line GND. The transistor PM3 is connected between the power supply line VCC and the feedback current terminal Iaoc2, and its gate is connected to the drain of the transistor NM1. The transistors PM4 and NM4 are connected in series between the power supply line VCC and the ground line GND.

[0064] More specifically, the source of transistor NM1 is connected to the ground line GND, the drain of transistor NM1 is connected to the drain of transistor PM1, and the source of transistor PM1 is connected to the power supply line VCC. Transistors PM2, NM2 and transistors PM4, NM4 are connected in the same manner as transistors PM1, NM1, so their explanation will be omitted.

[0065] The sources of the transistors PM1, PM2, and PM3 are commonly connected to the power supply line VCC, and the gates are commonly connected to the drain of the transistor NM1, and they operate as a current mirror circuit. The drain of the transistor PM3 is connected to the feedback current terminal Iaoc2.

[0066] The sources of transistors NM2 and NM3 are commonly connected to the ground line GND, and their gates are commonly connected to the drain of transistor PM2, so that they operate as a current mirror circuit. The drain of transistor NM3 is connected to the feedback current terminal Iaoc1. The sources of transistors PM4 and PM5 are commonly connected to the power supply line VCC, and their gates are commonly connected to the drain of transistor NM4, so that they also operate as a current mirror circuit. The drain of transistor PM5 is connected to the feedback current terminal Iaoc2.

[0067] The transistor NM1 turns on when the control voltage Vaoc2 is equal to or greater than a predetermined value, and turns off when the control voltage Vaoc2 is less than the predetermined value. Regarding the input of the differential integrator DI, when the difference voltage VInP-VinN between the average value of the input voltage InP and the average value of the input voltage InN exceeds a predetermined value, the transistor NM1 turns on, and when the difference voltage VInP-VinN is less than the predetermined value, the transistor NM1 turns off.

[0068] While transistor NM1 is on, current flows through the current mirror circuit (first current mirror circuit) formed by transistors PM1, PM2, and PM3, and current flows through the current mirror circuit (second current mirror circuit) formed by transistors NM2 and NM3. As a result, feedback current Iaoc2 is output from feedback current terminal Iaoc2, and feedback current Iaoc1 is drawn from input terminal In (Figure 1) via feedback current terminal Iaoc1.

[0069] Transistor NM4 turns on when control voltage Vaoc1 is equal to or greater than a predetermined value, and turns off when control voltage Vaoc1 is less than the predetermined value. Regarding the input of differential integrator DI, when the difference voltage VInP-VinN between the average value of input voltage InP and the average value of input voltage InN is less than a predetermined value, transistor NM4 turns on, and when the difference voltage VInP-VinN exceeds the predetermined value, transistor NM4 turns off. While transistor NM4 is on, a feedback current Iaoc1 is output from the current mirror circuit (third current mirror circuit) formed by transistors PM4 and PM5 to the reference voltage line Vref (Figure 1) via feedback current terminal Iaoc2.

[0070] The automatic offset control circuit AOC1 is configured such that, by adjusting the current amounts of the current sources I1 and I2, when the average value of the input voltage InP is greater than the average value of the input voltage InN, the transistor NM1 is turned on and the transistor NM4 is turned off. In this case, current flows through both the feedback current terminals Iaoc1 and Iaoc2. The automatic offset control circuit AOC1 is also configured such that, by adjusting the current amounts of the current sources I1 and I2, when the average value of the input voltage InP is less than the average value of the input voltage InN, the transistor NM1 is turned off and the transistor NM4 is turned on. In this case, current flows only through the feedback current terminal Iaoc2.

[0071] The input terminal InP is connected to the output terminal OutP of the receiver circuit 100 in Fig. 1. The input terminal InN is connected to the output terminal OutN of the receiver circuit 100. Therefore, when the input current value Iin is smaller than a predetermined value and the average value (DC component) of the output voltage value OutP is smaller than the average value (DC component) of the output voltage value OutN, a current flows only through the feedback current terminal Iaoc2. When the input current Iin is larger than a predetermined value and the average value (DC component) of the output voltage value OutP is larger than the average value (DC component) of the output voltage value OutN, a current flows through both the feedback current terminals Iaoc1 and Iaoc2.

[0072] In this way, the automatic offset control circuit AOC1 switches the circuit path that operates to generate feedback currents Iaoc1 and Iaoc2 depending on the polarity of the differential output (Vaoc1-Vaoc2) of the differential integrator DI. The differential integrator DI operates by receiving differential signals OutP / OutN, which change according to the input current Iin, at its input terminals InP / InN. That is, the differential integrator DI generates control voltages Vaoc1 / Vaoc2 according to the input current Iin.

[0073] Therefore, the automatic offset control circuit AOC1 can control the generation and switching of the feedback currents Iaoc1 and Iaoc2 in accordance with the control voltages Vaoc1 / Vaoc2 that the differential integrator DI generates in response to the input current Iin. In other words, the automatic offset control circuit AOC1 can invert the magnitude relationship between the magnitude of the feedback current Iaoc1 and the magnitude of the feedback current Iaoc2 in accordance with the control voltages Vaoc1 / Vaoc2.

[0074] Figure 4 is a diagram showing the DC transfer characteristics of the automatic offset control circuit AOC1 of Figure 3. Figure 4 shows simulation results, with the horizontal axis representing the differential input voltage VInP-VInN and the vertical axis representing the feedback currents Iaoc1 and Iaoc2. The symbols VInP and VInN represent the voltages at the input terminals InP and InN of the automatic offset control circuit AOC1, respectively. Note that the feedback currents Iaoc1 and Iaoc2 are positive in the direction of the arrows shown in Figure 1.

[0075] The automatic offset control circuit AOC1 reverses the magnitude relationship between the magnitude of the feedback current Iaoc2 and the magnitude of the feedback current Iaoc1 based on the control voltages Vaoc1 and Vaoc2 generated by the differential integrator DI in response to the differential input voltage VInP-VInN. For example, when the differential input voltage VInP-VInN is negative, that is, when the average value (DC component) of the output voltage OutP is smaller than the average value (DC component) of the output voltage OutN, the feedback current Iaoc1 does not flow (0 mA), and only the feedback current Iaoc2 flows. When the differential input voltage VInP-VInN is positive, that is, when the average value (DC component) of the output voltage OutP is greater than the average value (DC component) of the output voltage OutN, both the feedback currents Iaoc1 and Iaoc2 flow (Iaoc1 > Iaoc2).

[0076] Note that there is a region where both feedback currents Iaoc1 and Iaoc2 are zero when the differential input voltage VInP-VInN is near 0 mV. This region occurs when both control voltage Vaoc2 and control voltage Vaoc1 are below a predetermined value. By providing such a region where both feedback currents Iaoc1 and Iaoc2 are reliably zero, the generation and switching of feedback currents Iaoc1 and Iaoc2 can be performed stably.

[0077] In this way, the automatic offset control circuit AOC1 can control the generation and switching of the feedback currents Iaoc1 and Iaoc2 in response to the differential signals OutP / OutN, which vary depending on the input current Iin. As a result, the receiver circuit 100 can be configured with the operating characteristics shown in Fig. 5, and can suppress an increase in the DC offset of the differential signals OutP / OutN while suppressing noise in the range where the input current value Iin is small.

[0078] Furthermore, by continuing to flow the feedback current Iaoc2 even after the feedback current Iaoc1 starts to flow due to an increase in the input current Iin, the operating margin of the transimpedance amplifier (TIA stage+LS1) can be increased.

[0079] [Operating characteristics of the receiving circuit] FIG. 5 is a diagram showing an example of the operating characteristics (DC operating characteristics) of the receiver circuit 100 of FIG. 1. FIG. 6 is an enlarged view of the output voltages OutP and OutN of FIG. 5. FIGS. 5 and 6 show simulation results. The horizontal axes of FIGS. 5 and 6 represent the input current Iin. The vertical axes of FIG. 5 represent the output voltages OutP and OutN, the reference voltage Vref, the voltage Vtia, the base-collector voltage Vcb, and the feedback currents Iaoc1 and Iaoc2, respectively. The vertical axes of FIG. 6 represent the output voltages OutP and OutN. Note that all values ​​represent the average values ​​(DC components) of the respective voltages or currents.

[0080] 6, when the input current value Iin is smaller than 0.06 mA, the output voltage value OutP is smaller than the output voltage value OutN, and when the input current value Iin is larger than 0.06 mA, the output voltage value OutP is larger than the output voltage value OutN. In other words, the automatic offset control circuit AOC1 switches the control of the feedback currents Iaoc1 and Iaoc2 using the input current value Iin=0.06 mA as a threshold value.

[0081] The threshold value of the input current Iin can be set by making the voltage value of the reference voltage Vref slightly smaller than the voltage value of the voltage signal Vtia when the input current Iin is zero. That is, while the input current Iin is increasing from zero to a certain level, the voltage value of the voltage signal Vtia is larger than the voltage value of the reference voltage Vref, and the inverting amplification operation of the buffer BUF causes the output voltage OutP to be smaller than the output voltage OutN. Also, when the input current Iin increases beyond a certain level, the voltage value of the voltage signal Vtia becomes smaller than the voltage value of the reference voltage Vref, and the inverting amplification operation of the buffer BUF causes the output voltage OutP to be larger than the output voltage OutN.

[0082] The automatic offset control circuit AOC1 shown in Figure 3 sets the feedback current Iaoc1 to 0 mA when the input current value Iin is small, and instead of flowing the feedback current Iaoc1, flows a feedback current Iaoc2 to the reference voltage line Vref. For example, in Figure 5, when the input current Iin is approximately 0.06 mA or less, the feedback current Iaoc1 is 0 mA. As a result, as shown in Figure 5, the DC offset of the voltages Vtia and Vref can be reduced regardless of the input current Iin, and the DC offset of the output voltages OutP and OutN can be kept below the tolerance of the receiver circuit 100.

[0083] For example, as shown in FIG. 6, the DC offset of the output voltages OutP and OutN is suppressed to 9 μV or less in the range where the input current value Iin is less than 0.1 mA, and is suppressed to 21 μV or less in the range where the input current Iin is up to 1.0 mA.

[0084] Furthermore, by setting the feedback current Iaoc1 to 0 mA in the range where the input current value Iin is small, noise in the range where the input current value Iin is small can be reduced. For example, as shown in FIG. 5, the noise when the input current Iin is 0 mA is 9.4 pA / rtHz. Therefore, the receiver circuit 100 shown in FIG. 1 can suppress the deterioration of noise characteristics in the range where the input current value Iin is small while suppressing an increase in the DC offset of the output voltages OutP and OutN.

[0085] Furthermore, after the feedback current Iaoc2 decreases to 0 mA when the control of the automatic offset control circuit AOC1 switches, it increases together with the feedback current Iaoc1 in response to an increase in the input current Iin. This makes it possible to increase the base-collector voltage Vcb of transistor Q2 in Figure 2 in the region where the input current value Iin is large, thereby increasing the operating margin of the transimpedance amplifier (TIA stage + LS1).

[0086] More specifically, by flowing feedback current Iaoc2 into level shift circuit LS2, the voltage value of reference voltage Vref is increased, and the action of automatic offset control circuit AOC1 brings the voltage value (average value) of voltage signal Vtia closer to reference voltage Vref, so the voltage value (average value) of voltage signal TIAout increases and the base-collector voltage Vcb increases. Note that in order to increase the average value (DC component) of voltage signal TIAout, the feedback current Iaoc1 increases slightly compared to when feedback current Iaoc2 does not flow.

[0087] As described above, in this embodiment, the automatic offset control circuit AOC1 sets the feedback current Iaoc1 to 0 mA in the range where the input current Iin is small, and instead of flowing the feedback current Iaoc1, flows the feedback current Iaoc2 to the reference voltage line Vref. This suppresses noise in the range where the input current Iin is small, while also suppressing increases in the DC offset between the voltage Vtia and the reference voltage Vref and in the differential output voltages OutP / OutN. At this time, by flowing the feedback current Iaoc2 through the resistor element RLS2, the voltage value of the reference voltage Vref is increased, bringing it closer to the voltage value of the voltage Vtia, thereby suppressing increases in the DC offset.

[0088] The voltage signal TIAout output from the inverter amplifier INV1 is level-shifted by the level shift circuit LS1 and supplied to the buffer BUF, so that the voltage value of the voltage signal TIAout can be set within a voltage range that allows the buffer BUF to operate appropriately. As a result, the buffer BUF can generate appropriate differential signals OutP and OutN according to the input current Iin.

[0089] By adding the feedback current Iaoc2 from the automatic offset control circuit AOC1 to the current from the current source ILS2 and flowing the result through the resistance element RLS2, the reference voltage Vref can be directly adjusted to suppress an increase in the DC offset of the differential signals OutP / OutN.

[0090] By configuring the dummy transimpedance amplifier stage using the same circuit elements as the transimpedance amplifier stage TIA, the circuit design of the receiver circuit 100 can be simplified.

[0091] As shown in Fig. 4, the automatic offset control circuit AOC1 inverts the magnitude relationship between the magnitude of the feedback current Iaoc2 and the magnitude of the feedback current Iaoc1 in response to the control voltages Vaoc1 and Vaoc2. This makes it possible to configure the receiver circuit 100 having the operating characteristics shown in Fig. 5. That is, it is possible to suppress noise in the region where the input current value Iin is small while also suppressing an increase in the DC offset of the differential signals OutP / OutN.

[0092] When the input current Iin exceeds a predetermined threshold, the reference voltage Vref becomes larger than the voltage value (average value) of the voltage signal Vtia, so that the voltage Vtia can be made to approach the reference voltage Vref in response to the extraction of the feedback current Iaoc1. As a result, the automatic offset control circuit AOC1 can perform automatic offset control that suppresses an increase in the DC offset of the differential signals OutP / OutN.

[0093] Integrating the circuits of the receiver circuit 100 onto a single semiconductor integrated circuit chip can reduce variations in the electrical characteristics between the TIA stage and the DTIA stage, or can reduce variations in the electrical characteristics of the level shift circuits LS1 and LS2. For example, by configuring each stage using the same circuit elements, the power supply voltage dependence (or temperature dependence) of the electrical characteristics of the dummy transimpedance amplifier stage can be matched to the power supply voltage dependence (or temperature dependence) of the electrical characteristics of the transimpedance amplifier stage TIA, allowing the receiver circuit 100 to operate more stably against fluctuations in the power supply voltage (or temperature). As a result, the accuracy of adjustment of the DC offset of the differential signals OutP / OutN by the automatic offset control circuit AOC1 can be improved.

[0094] Second Embodiment [Circuit configuration of the automatic offset control circuit mounted on the receiving circuit] Fig. 7 is a circuit diagram showing an example of an automatic offset control circuit AOC2 mounted in a receiver circuit according to a second embodiment. The receiver circuit mounted with the automatic offset control circuit AOC2 of Fig. 7 is similar to the receiver circuit 100 shown in Fig. 1, except for the configuration of the automatic offset control circuit AOC2. That is, the receiver circuit of this embodiment is included in an optical receiver or the like, amplifies an input current Iin received from a photodiode, converts it into a voltage signal, and outputs differential signals OutP / OutN.

[0095] The automatic offset control circuit AOC2 in Figure 7 is configured by removing transistor PM3 from the automatic offset control circuit AOC1 in Figure 3. Without transistor PM3, when the average value of the input voltage InP is greater than the average value of the input voltage InN and the control voltage value Vaoc1 is smaller than the control voltage value Vaoc2, the automatic offset control circuit AOC2 does not flow feedback current Iaoc2 but only flows feedback current Iaoc1. Other operations of the automatic offset control circuit AOC2 are similar to those of the automatic offset control circuit AOC1 in Figure 3.

[0096] That is, the automatic offset control circuit AOC2 of this embodiment switches the circuit operation so that only the feedback current Iaoc2 flows when the input current value Iin is smaller than a predetermined value, and only the feedback current Iaoc1 flows when the input current Iin is larger than the predetermined value.

[0097] For example, if the transimpedance amplifier (TIA stage + LS1) has sufficient operating margin when the input current Iin is large, the automatic offset control circuit AOC2 can be configured by removing transistor PM3 from the automatic offset control circuit AOC1 in Figure 3. For example, as the input current Iin increases, the voltage value (average value) of the voltage signal TIAout output from the TIA stage decreases. However, if the TIA stage can perform a specified amplification operation in response to such a decrease in the voltage value (average value) of the voltage signal TIAout, it is possible to flow only the feedback current Iaoc1 when the input current Iin is greater than a specified value. In this case, the circuit size of the receiver circuit including the automatic offset control circuit AOC2 can be reduced.

[0098] As described above, this embodiment can also achieve the same effects as the above-described embodiments. For example, it is possible to suppress noise in the region where the input current value Iin is small, while suppressing increases in the DC offsets of the voltages Vtia and Vref and the DC offsets of the differential signals OutP and OutN.

[0099] Furthermore, in this embodiment, when there is a sufficient operating margin for the transimpedance amplifier (TIA stage+LS1) on the side where the input current value Iin is large, the automatic offset control circuit AOC2 can be simplified compared to the automatic offset control circuit AOC1 in Fig. 3. As a result, the circuit scale of the receiver circuit including the automatic offset control circuit AOC2 can be reduced.

[0100] [Circuit configuration of other receiving circuits] Fig. 8 is a block diagram showing another example of a receiver circuit. Elements similar to those in the receiver circuit 100 of Fig. 1 are designated by the same reference numerals, and detailed description thereof will be omitted. The receiver circuit 110 of Fig. 8 has an automatic offset control circuit AOC3 instead of the automatic offset control circuit AOC1 of the receiver circuit 100 of Fig. 1.

[0101] The other configuration of the receiver circuit 110 is the same as that of the receiver circuit 100 in Fig. 1, except that the automatic offset control circuit AOC3 does not have the function of outputting the feedback current Iaoc2 to the reference voltage line Vref. Like the automatic offset control circuit AOC1 in Fig. 1, the automatic offset control circuit AOC3 has the function of drawing out the feedback current Iaoc1 from the input terminal In in accordance with the voltage difference between the differential signals OutP / OutN.

[0102] FIG. 9 is a diagram showing an example of the operating characteristics (DC operating characteristics) of the receiver circuit 110 of FIG. 8. FIG. 9 shows simulation results. The horizontal axis of FIG. 9 represents the input current Iin. The vertical axis of FIG. 9 represents the voltages of the differential signals OutP and OutN, the reference voltage Vref, the voltage Vtia, the base-collector voltage Vcb, and the feedback current Iaoc1, respectively. Note that each value represents the average value (DC component) of the respective voltage or current. Furthermore, since the receiver circuit 110 does not pass the feedback current Iaoc2, the feedback current Iaoc2 (0 mA) is shown for reference.

[0103] As shown in Figure 9, the operation of the automatic offset control circuit AOC3 causes the feedback current Iaoc1 to increase as the input current Iin increases. Therefore, the DC offset of the differential signals OutP / OutN is kept small regardless of the input current Iin, similar to the operation of the receiver circuit 100 shown in Figure 5. This allows the amplifiers in each stage of the buffer circuit BUF to operate at an appropriate operating point, enabling good amplification characteristics to be obtained. However, in order for the automatic offset control by the automatic offset control circuit AOC3 to perform automatic offset control, the feedback current Iaoc1 must flow even when Iin = 0 mA, which can result in a problem of degraded noise characteristics.

[0104] In the example shown in FIG. 9, the feedback current Iaoc1 that flows when the input current Iin=0 mA is 15.3 μA, and the noise at this time is 14.1 pA / rtHz, which is larger than the noise (9.4 pA / rtHz) described in FIG.

[0105] Fig. 10 is a diagram showing another example of the operating characteristics of the receiver circuit 110 of Fig. 8. In the example shown in Fig. 10, in order to reduce noise by preventing the feedback current Iaoc1 from flowing in a region where the input current value Iin is small, the circuit characteristics of the receiver circuit 110 are set so that the reference voltage Vref is lower than the voltage Vtia when the input current Iin is 0 mA.

[0106] In this case, in the range where the input current Iin is small, the feedback current Iaoc1 is 0 mA, but a large DC offset occurs in the differential signals OutP / OutN, preventing good amplification characteristics. Until the automatic offset control circuit AOC3 starts operating and the feedback current Iaoc1 begins to flow, the reference voltage Vref is lower than the voltage Vtia. Because the reference voltage Vref is a constant value, even after the feedback current Iaoc1 begins to flow, the average value (DC component) of the voltage Vtia gradually decreases to a value smaller than the reference voltage Vref, reducing the base-collector voltage Vcb of the first-stage cascode transistor (Figure 2) in the transimpedance amplifier stage TIA. This results in a reduced operating margin in the range where the input current Iin is large compared to Figures 5 and 9.

[0107] Third Embodiment [Circuit configuration of receiving circuit] Fig. 11 is a block diagram showing an example of a receiver circuit according to the third embodiment. Elements similar to those in the receiver circuit 100 of Fig. 1 are assigned the same reference numerals, and detailed description thereof will be omitted. The receiver circuit 102 of Fig. 11 has the same configuration as the receiver circuit 100 of Fig. 1, except that it has an automatic offset control circuit AOC4 instead of the automatic offset control circuit AOC1. For example, the receiver circuit 102 is formed by integrating each circuit element on a single semiconductor integrated circuit chip.

[0108] In this embodiment, a feedback current terminal Iaoc2 of the automatic offset control circuit AOC4 is connected to the input of the inverter amplifier INV2 in the DTIA stage. The receiving circuit 102 is included in an optical receiver or the like, and amplifies an input current Iin received from a photodiode, converts it into a voltage signal, and outputs a differential signal OutP / OutN.

[0109] The automatic offset control circuit AOC4 differs from the automatic offset control circuit AOC1 in Fig. 1 in that it has the function of drawing a feedback current Iaoc2 from the input node of the DTIA stage. The other configuration of the receiver circuit 102 is the same as that of the receiver circuit 100 in Fig. 1, except that the feedback current terminal Iaoc2 of the automatic offset control circuit AOC4 is connected to the input of the inverter amplifier INV2 in the DTIA stage. Note that, as in Fig. 1, the arrows of the feedback currents Iaoc1 and Iaoc2 are positive.

[0110] FIG. 12 is a circuit diagram showing an example of the automatic offset control circuit AOC4 of FIG. 11. Elements similar to those of the automatic offset control circuit AOC1 of FIG. 3 are assigned the same reference numerals, and detailed description thereof will be omitted. The automatic offset control circuit AOC4 has a circuit modified from the automatic offset control circuit AOC1 of FIG. 3 in order to draw the feedback current Iaoc2 from the input of the inverter amplifier INV2. Specifically, the automatic offset control circuit AOC4 has transistor PM3 removed from the automatic offset control circuit AOC1 of FIG. 3 and transistors NM5, NM6, and NM7 added. The transistors NM5, NM6, and NM7 are n-channel MOS transistors.

[0111] The source of transistor NM5 is connected to the ground line GND, the drain is connected to the feedback current terminal Iaoc2, and the gate is connected to the drain of transistor PM2. The sources of transistors NM6 and NM7 are commonly connected to the ground line GND, and the gates are commonly connected to the drain of transistor PM5, and they operate as a current mirror circuit. The drain of transistor NM6 is connected to the drain of transistor PM5. The drain of transistor NM7 is connected to the feedback current terminal Iaoc2.

[0112] When the input voltage value InP is higher than the input voltage value InN, the automatic offset control circuit AOC4 turns on the transistor NM1 and turns off the transistor NM4, and adjusts the current sources I1 and I2 so that current flows to both the feedback current terminals Iaoc1 and Iaoc2. When the input voltage value InP is lower than the input voltage value InN, the automatic offset control circuit AOC4 turns off the transistor NM1 and turns on the transistor NM4, and adjusts the current sources I1 and I2 so that current flows only to the feedback current terminal Iaoc2.

[0113] The input terminal InP is connected to the output terminal OutP of the receiver circuit 100 in Fig. 1. The input terminal InN is connected to the output terminal OutN of the receiver circuit 100 in Fig. 1. Therefore, when the output voltage value OutP is greater than the output voltage value OutN, current flows through both feedback current terminals Iaoc1 and Iaoc2. When the output voltage value OutP is smaller than the output voltage value OutN, current flows only through the feedback current terminal Iaoc2.

[0114] For example, in the receiver circuit 100 of FIG. 1, the automatic offset control circuit AOC1 increases the reference voltage Vref by injecting a feedback current Iaoc2 into the level shift circuit LS2 via the reference voltage line Vref. In the receiver circuit 102 of FIG. 11, the automatic offset control circuit AOC4 increases the output voltage of the DTIA stage by drawing in the feedback current Iaoc2 from the input node of the DTIA stage (i.e., reducing the input current), thereby increasing the reference voltage Vref. Therefore, just as the automatic offset control circuit AOC1 outputs the feedback current Iaoc2 in response to the differential signals OutP / OutN, the automatic offset control circuit AOC4 can increase the reference voltage Vref by drawing in the feedback current Iaoc2 in response to the differential signals OutP / OutN.

[0115] The operating characteristics of the receiver circuit 102 shown in Fig. 11 are similar to those of the receiver circuit 100 shown in Fig. 5 and Fig. 6, except that the polarity of the feedback current Iaoc2 is reversed. That is, the receiver circuit 102 can suppress an increase in the DC offset of the differential signals OutP / OutN while suppressing deterioration of noise characteristics in a range where the input current value Iin is small.

[0116] As described above, this embodiment can also achieve the same effects as the above-described embodiments. For example, it is possible to suppress the deterioration of noise characteristics in the region where the input current value Iin is small, while suppressing an increase in the DC offset between the voltage Vtia and the reference voltage Vref and the DC offset of the differential signals OutP / OutN.

[0117] Furthermore, in this embodiment, the automatic offset control circuit AOC4 draws a feedback current Iaoc2 from the input node of the inverter amplifier INV2, thereby adjusting the reference voltage Vref applied to the buffer BUF by adjusting the input voltage of the inverter amplifier INV2, thereby suppressing an increase in the DC offset of the differential signals OutP / OutN.

[0118] The transistor NM5 may be removed from the automatic offset control circuit AOC4 shown in FIG. 12, and when the output voltage value OutP is greater than the output voltage value OutN, a current may flow only through the feedback current terminal Iaoc1.

[0119] [Fourth embodiment] [Circuit configuration of receiving circuit] Fig. 13 is a block diagram showing an example of a receiver circuit according to the fourth embodiment. Elements similar to those in the receiver circuit 100 of Fig. 1 are assigned the same reference numerals, and detailed description thereof will be omitted. In the receiver circuit 104 of Fig. 13, a buffer BUF2 is disposed between a buffer BUF and output terminals OutP / OutN, and an automatic offset control circuit AOC5 is connected to the output and input of the buffer BUF2. For example, the receiver circuit 104 is formed by integrating each circuit element on a single semiconductor integrated circuit chip.

[0120] In this embodiment, the input terminals InP and InN of the automatic offset control circuit AOC1 are connected to the nodes Vref and Vtia, respectively. That is, the automatic offset control circuit AOC1 subtracts a feedback current Iaoc1 from the input current Iin or outputs a feedback current Iaoc2 to the reference voltage line Vref, depending on the voltage difference between the nodes Vref and Vtia received at the input terminals InP and InN. The automatic offset control circuit AOC1 then performs automatic offset control to suppress an increase in the DC offset between the voltage Vtia and the reference voltage Vref.

[0121] The automatic offset control circuit AOC5 adjusts the voltage value of the differential signal supplied to the differential input of the buffer BUF2 in accordance with the differential signals OutP / OutN to suppress an increase in the DC offset of the differential signals OutP / OutN. For example, in a region where the automatic offset control circuit AOC1 is not operating, a DC offset occurs between the voltage Vtia and the reference voltage Vref. However, the automatic offset control circuit AOC5 can cancel the DC offset of the differential signals OutP / OutN caused by the DC offset between the voltage Vtia and the reference voltage Vref, thereby suppressing an increase in the DC offset of the differential signals OutP / OutN. As a result, good amplification characteristics can be obtained.

[0122] As described above, this embodiment can also achieve the same effects as the above-described embodiments. For example, in this embodiment, the input terminals InP and InN of the automatic offset control circuit AOC1 operate by receiving the voltages of the nodes Vref and Vtia. In this case, the receiver circuit 104 can also suppress increases in the DC offset between the voltage Vtia and the reference voltage Vref and the DC offset of the output voltages OutP and OutN while suppressing noise in the region where the input current value Iin is small.

[0123] The receiver circuit 104 also has an automatic offset control circuit AOC5 that connects the output and input of a buffer BUF2 that is arranged between the buffer BUF and the output terminals OutP / OutN. Therefore, even in an area where the automatic offset control circuit AOC1 is not operating, the automatic offset control circuit AOC5 can suppress an increase in the DC offset of the differential signals OutP / OutN, thereby achieving good amplification characteristics.

[0124] The receiver circuit 104 may have the automatic offset control circuit AOC2 shown in FIG. 7 instead of the automatic offset control circuit AOC1.

[0125] Although the embodiments of the present disclosure have been described above, the present disclosure is not limited to the above embodiments. Various changes, modifications, substitutions, additions, deletions, and combinations are possible within the scope of the claims. These changes also naturally fall within the technical scope of the present disclosure. [Explanation of symbols]

[0126] 100, 102, 104, 110 Receiver circuit AOC1, AOC2, AOC3, AOC4, AOC5 Automatic Offset Control Circuit BUF buffer CLS1, CLS2 capacitance elements DI differential integrator DTIA Dummy Transimpedance Amplifier Stage Iaoc1, Iaoc2 feedback current Iin Input current ILS1, ILS2 current source In Input terminal InN, InP input voltage INV1, INV2 inverter amplifier LS1, LS2 level shift circuit OutN, OutP output terminals RLS1, RLS2 resistor elements TIA Transimpedance Amplifier Stage TIAin input terminal TIAout output terminal Vcb Base-collector voltage Vref Reference voltage Vtia voltage

Claims

1. an input terminal for receiving an input current; a transimpedance amplifier having an input node and converting a current signal input to the input node into a voltage signal; a reference voltage circuit that generates a reference voltage in response to the first feedback current; a differential amplifier circuit that generates a differential signal in accordance with a voltage difference between the voltage signal and the reference voltage; an offset control circuit that generates the first feedback current and the second feedback current in response to an offset of the differential signal; Equipped with the input node is electrically connected to the input terminal; the offset control circuit adjusts the first feedback current so that the offset of the differential signal falls within a predetermined range when the average voltage value of the voltage signal is greater than the reference voltage, and subtracts the second feedback current from the input current so that the offset of the differential signal falls within the predetermined range when the average voltage value of the voltage signal is smaller than the reference voltage; The transimpedance amplifier a first amplifier circuit that converts a current signal input to the input node into an intermediate voltage signal; a first level shift circuit including a first resistor element and a first current source, the first level shift circuit level-shifting the intermediate voltage signal by a voltage drop caused by a first current supplied by the first current source flowing through the first resistor element to generate the voltage signal; Including, The reference voltage circuit a second amplifier circuit that generates a reference voltage; a second level shift circuit including a second resistor element and a second current source, the second level shift circuit level-shifting the reference voltage by a voltage drop caused by a second current supplied by the second current source flowing through the second resistor element to generate the reference voltage; Including, the first feedback current flows through the second resistor element in the same direction as the second current; the transimpedance amplifier generates the voltage signal such that the larger the current signal, the smaller the voltage signal; the differential signal includes a pair of positive and negative phase signals; The offset of the differential signal represents a difference between a DC component of the positive-phase signal and a DC component of the negative-phase signal. Receiver circuit.

2. an input terminal for receiving an input current; a transimpedance amplifier having an input node and converting a current signal input to the input node into a voltage signal; a reference voltage circuit that generates a reference voltage in response to the first feedback current; a differential amplifier circuit that generates a differential signal in accordance with a voltage difference between the voltage signal and the reference voltage; an offset control circuit that generates the first feedback current and the second feedback current in response to an offset of the differential signal; Equipped with the input node is electrically connected to the input terminal; the offset control circuit adjusts the first feedback current so that the offset of the differential signal falls within a predetermined range when the average voltage value of the voltage signal is greater than the reference voltage, and subtracts the second feedback current from the input current so that the offset of the differential signal falls within the predetermined range when the average voltage value of the voltage signal is smaller than the reference voltage; a value of the reference voltage when the first feedback current is zero is set to be smaller than an average voltage value of the voltage signal when the current signal is zero; the transimpedance amplifier generates the voltage signal such that the larger the current signal, the smaller the voltage signal; the differential signal includes a pair of positive and negative phase signals; The offset of the differential signal represents a difference between a DC component of the positive-phase signal and a DC component of the negative-phase signal. Receiver circuit.

3. The offset control circuit draws the first feedback current from an input node of the second amplifier circuit.

2. The receiving circuit according to claim 1.

4. The second amplifier circuit is configured with the same circuit elements as the first amplifier circuit.

2. The receiving circuit according to claim 1.

5. The offset control circuit includes: a differential integrator that generates a control voltage according to an offset of the differential signal; Inverting the magnitude relationship between the magnitude of the first feedback current and the magnitude of the second feedback current in response to the control voltage.

5. The receiving circuit according to claim 1.

6. the transimpedance amplifier, the reference voltage circuit, the differential amplifier circuit, and the offset control circuit are integrated into a single semiconductor integrated circuit chip; 6. The receiving circuit according to claim 1.

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