A trans-impedance amplifier circuit applied to 50G PON

Abstract

This invention discloses a transimpedance amplifier circuit for 50GPON. The main links of the transimpedance amplifier include a core amplifier, a burst switched-capacitor coupling module, a single-ended to differential variable gain amplifier, an output driver, a first automatic gain control module, a second automatic gain control module, a differential offset cancellation module, a differential amplifier, and a DC voltage operating point module. A current signal is input from the IN terminal, converted into a single-ended voltage signal by the core amplifier, and transmitted to the burst switched-capacitor coupling module. After processing, one end outputs a signal with a DC voltage boost, and the other end outputs the average signal voltage, which serves as the input common-mode level for the single-ended to differential variable gain amplifier. The single-ended to differential variable gain amplifier converts the single-ended signal voltage into a differential voltage. The output driver transmits this differential signal to the next stage chip, ensuring impedance matching during transmission.

Description

Technical Field

[0001] This invention relates to the field of microelectronics technology, and more specifically to a transimpedance amplifier circuit for 50GPON. Background Technology

[0002] The demands of high-bandwidth, low-jitter VR services and ultra-low latency, high-reliability industrial park services are driving the evolution of PON technology from GPON to 10G PON, and then to the next-generation 50G PON, continuously developing towards improved service bandwidth, enhanced intelligent bearer capabilities for all services, and improved operation and maintenance capabilities. From a demand perspective, 50G PON offers significant improvements in key characteristics such as line bandwidth, low latency, and channelization capabilities to meet the comprehensive bearer requirements of multiple scenarios. This will greatly promote the evolution and upgrading of industrial parks from PON 1.0 (device interconnection) to PON 2.0 (data interoperability), and then to PON 3.0 (industrial intelligence). From a standards perspective, standardization has generally entered the Amd1 development stage, clarifying the overall framework requirements for the next-generation PON, defining the single-wavelength TDM-PON architecture, requiring support for XG(S)-PON coexistence and evolution, and defining symmetrical 50G uplink and downlink rates.

[0003] As a front-end chip that converts photocurrent into differential voltage, the performance of the transimpedance amplifier (TIA) chip plays a crucial role in the performance of the link. In 50GPON system applications, TIAs are required to have fast burst response time, high linearity in the dynamic range, and low equivalent input noise. The architecture design of TIAs based on these core indicators becomes particularly difficult. Summary of the Invention

[0004] The purpose of this invention is to provide a transimpedance amplifier circuit for 50GPON, which enables rapid common-mode voltage establishment and rapid gain switching.

[0005] To achieve the above functions, this invention designs a transimpedance amplifier circuit for 50GPON. The transimpedance amplifier includes a core amplifier CORE_Amp, a burst cap-coupled module, a single-ended to differential variable gain amplifier S2D_VGA, an output driver Drv, a first automatic gain control module AGC1, a second automatic gain control module AGC2, a differential offset cancellation module DOC, a differential amplifier AMP, a DC voltage operating point module Dummy, a resistor R_Dummy, and a variable resistor Rf.

[0006] The core amplifier CORE_Amp is used to convert the input current signal into a single-ended voltage signal. The input terminal of the core amplifier CORE_Amp is the input current signal and is connected to one end of the variable resistor Rf. The output terminal of the core amplifier CORE_Amp is connected to the other end of the variable resistor Rf.

[0007] The DC voltage operating point module Dummy is used to generate the same DC voltage operating point as the core amplifier CORE_Amp. Its input is connected to one end of the resistor R_Dummy, and the other end of the resistor R_Dummy is connected to the output of the DC voltage operating point module Dummy.

[0008] The two input terminals of the first automatic gain control module AGC1 are connected to the output terminal of the core amplifier CORE_Amp and the output terminal of the DC voltage operating point module Dummy, respectively. The output terminal of the first automatic gain control module AGC1 is connected to the variable terminal of the variable resistor Rf.

[0009] The output of the core amplifier CORE_Amp is connected to the input of the burst cap module. The two outputs of the burst cap module are connected to the two inputs of the single-ended to differential variable gain amplifier S2D_VGA. The two outputs of the S2D_VGA are connected to the two inputs of the differential amplifier AMP. The two outputs of the AMP are connected to the two inputs of the output driver Drv. The two outputs of the Drv output voltage signal V. OUTP V OUTN ;

[0010] The two input terminals of the second automatic gain control module AGC2 are connected to the two output terminals of the differential amplifier AMP, respectively. The output terminal of the second automatic gain control module AGC2 is connected to the positive power supply terminal of the single-ended to differential variable gain amplifier S2D_VGA.

[0011] The two input terminals of the differential offset cancellation module DOC are connected to the two output terminals of the differential amplifier AMP, respectively. The output terminal of the differential offset cancellation module DOC is connected to the negative power supply terminal of the single-ended to differential variable gain amplifier S2D_VGA.

[0012] As a preferred embodiment of the present invention: the first automatic gain control module AGC1 includes a first resistor R1, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, a first capacitor C1, a second capacitor C2, a switch TG1, a first MOSFET M1, a second MOSFET M2, a third MOSFET M3, a fourth MOSFET M4, a fifth MOSFET M5, a sixth MOSFET M6, a first transistor Q1, a second transistor Q2, a third transistor Q3, a fourth transistor Q4, a first current source I1, and a second current source I2;

[0013] Among them, the first MOSFET M1, the second MOSFET M2, the third MOSFET M3, the fourth MOSFET M4, the fifth MOSFET M5, and the sixth MOSFET M6 are all PMOS transistors, and the first transistor Q1, the second transistor Q2, the third transistor Q3, and the fourth transistor Q4 are all NPN transistors.

[0014] The switch TG1 is composed of a PMOS transistor, a second resistor R2, and an NPMOS transistor connected in parallel. The gate of the NPMOS transistor is input with the control signal RST, and the gate of the PMOS transistor is input with the control signal RSTB. The control signal RSTB is the signal output by the control signal RST after passing through the inverter. The source of the NPMOS transistor, the source of the PMOS transistor, and one end of the second resistor R2 are connected together, and the drain of the NPMOS transistor, the drain of the PMOS transistor, and the other end of the second resistor R2 are connected together.

[0015] The connections of the resistors, MOSFETs, transistors, and current sources in the first automatic gain control module AGC1 are as follows:

[0016] One end of the first resistor R1 is connected to the output of the core amplifier CORE_Amp, inputting the Core_out signal, and the other end is connected to the source of the PMOS transistor of switch TG1. One end of the first capacitor C1 is connected to the drain of the NMOS transistor of switch TG1 and the gate of the third MOS transistor M3, and the other end of the first capacitor C1 is grounded. The drain of the third MOS transistor M3 is grounded, and its source is connected to one end of the fourth resistor R4. The other end of the fourth resistor R4 is connected to the drain of the first MOS transistor M1 and the base of the first transistor Q1. The gate input voltage Vbp of the first MOS transistor M1 is connected to the source of the first MOS transistor M1, the source of the second MOS transistor M2, the base and collector of the third transistor Q3, the source of the fifth MOS transistor M5, the source of the sixth MOS transistor M6, and the positive terminal of the second current source I2.

[0017] One end of the third resistor R3 is connected to the output terminal of the DC voltage operating point module Dummy, inputting the Dummy_out signal. The other end is connected to the gate of the fourth MOSFET M4 and one end of the second capacitor C2. The other end of the second capacitor C2 is grounded. The drain of the fourth MOSFET M4 is grounded, and its source is connected to the drain of the second MOSFET M2 and the base of the second transistor Q2. The negative terminal of the first current source I1 is grounded, and its positive terminal is connected to one end of the fifth resistor R5 and the sixth resistor R6. The other end of the fifth resistor R5 is connected to the emitter of the first transistor Q1. The collector of the first transistor Q1 is connected to the third transistor Q... The emitter of transistor 3 is connected to the emitter of transistor Q2. The collector of transistor Q2 is connected to the drain and gate of transistor M5. The gate of transistor M5 is connected to the gate of transistor M6. The drain of transistor M6, the negative terminal of current source I2, and one end of resistor R7 are connected. The negative terminal of current source I2 serves as the output terminal of the first automatic gain control module AGC1, outputting the voltage signal Vgf. The other end of resistor R7 is connected to the collector and base of transistor Q4. The emitter of transistor Q4 is grounded.

[0018] As a preferred technical solution of the present invention: the burst cap switching coupling module includes a third capacitor C3, a fourth capacitor C4, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a switch TG2, and a switch TG3.

[0019] In this circuit, switches TG2 and TG3 are each composed of an NPMOS transistor and a PMOS transistor connected in parallel. The source of the NPMOS transistor is connected to the source of the PMOS transistor, and the drain of the NPMOS transistor is connected to the drain of the PMOS transistor. The gate of the NPMOS transistor is input with the control signal RST, and the gate of the PMOS transistor is input with the control signal RSTB. The control signal RSTB is the output signal of the control signal RST after passing through an inverter. The control signal RST controls switches TG2 and TG3 respectively after passing through the inverter. If there is a sudden change in the common-mode level, switches TG2 and TG3 will be turned on under the action of the control signal RST.

[0020] The connection relationships of the resistors, capacitors, and switches in the burst capacitive coupling module are as follows:

[0021] One end of the third capacitor C3 is connected to the input voltage Vip, and the other end is connected to one end of the eighth resistor R8 and the ninth resistor R9. It also serves as the output terminal of the burst cap of the burst capacitor coupling module, outputting the voltage signal Vop. One end of the fourth capacitor C4 is grounded, and the other end is connected to one end of the tenth resistor R10 and the eleventh resistor R11. It also serves as the output terminal of the burst cap of the burst capacitor coupling module, outputting the voltage signal Von.

[0022] The other end of the ninth resistor R9 is connected to the source of the NPMOS transistor of switch TG2, the other end of the eleventh resistor R11 is connected to the source of the NPMOS transistor of switch TG3, the other ends of the eighth resistor R8 and the tenth resistor R10 are connected to the drain of the NPMOS transistors of switches TG2 and TG3, and the static voltage VCM is input.

[0023] As a preferred embodiment of the present invention: the second automatic gain control module AGC2 includes a twelfth resistor R12, a thirteenth resistor R13, a fourteenth resistor R14, a fifteenth resistor R15, a sixteenth resistor R16, a seventeenth resistor R17, an eighteenth resistor R18, a fifth capacitor C5, a sixth capacitor C6, a seventh capacitor C7, a fifth transistor Q5, a sixth transistor Q6, a seventh transistor Q7, an eighth transistor Q8, a ninth transistor Q9, a tenth transistor Q10, an eleventh transistor Q11, a twelfth transistor Q12, a seventh MOSFET M7, an eighth MOSFET M8, a ninth MOSFET M9, a tenth MOSFET M10, a switch TG4, and a differential amplifier OP1;

[0024] Among them, the seventh MOSFET M7, the eighth MOSFET M8, the ninth MOSFET M9, and the tenth MOSFET M10 are all PMOS transistors, while the fifth transistor Q5, the sixth transistor Q6, the seventh transistor Q7, the eighth transistor Q8, the ninth transistor Q9, the tenth transistor Q10, the eleventh transistor Q11, and the twelfth transistor Q12 are all NPN transistors.

[0025] Among them, switch TG4 is composed of an NPMOS transistor and a PMOS transistor connected in parallel. The source of the NPMOS transistor is connected to the source of the PMOS transistor, and the drain of the NPMOS transistor is connected to the drain of the PMOS transistor. The gate of the NPMOS transistor is input with control signal RST, and the gate of the PMOS transistor is input with control signal RSTB. The control signal RSTB is the signal output by the control signal RST after passing through the inverter.

[0026] One end of the twelfth resistor R12 is connected to the input voltage Vip and the base of the fifth transistor Q5. The other end of the twelfth resistor R12 is connected to one end of the thirteenth resistor R13 and the base of the seventh transistor Q7. The other end of the thirteenth resistor R13 is connected to the input voltage Vin and the base of the sixth transistor Q6. The emitter of the sixth transistor Q6, the emitter of the fifth transistor Q5, and the collector of the eleventh transistor Q11 are connected. The collector of the sixth transistor Q6 is connected to the emitter of the ninth transistor Q9. The collector of the fifth transistor Q5 is connected to the emitter of the eighth transistor Q8. The base and collector of the eighth transistor Q8, the base and collector of the ninth transistor Q9, the base and collector of the tenth transistor Q10, the source of the ninth MOSFET M9, and the source of the tenth MOSFET M10 are connected.

[0027] The base input voltage signal Vbn of the eleventh transistor Q11 is connected to one end of the fourteenth resistor R14 and the fifteenth resistor R15. The other end of the fifteenth resistor R15 is connected to the source of the NPMOS transistor of switch TG4. The drain of the NPMOS transistor of switch TG4, the other end of the fourteenth resistor R14, the sixteenth resistor R16, one end of the fifth capacitor C5, the sixth capacitor C6, the seventh capacitor C7, the drain of the seventh MOS transistor M7, and the drain of the eighth MOS transistor M8 are connected and grounded.

[0028] The base input voltage signal Vbn of the twelfth transistor Q12 is connected to its emitter, which is connected to the other end of the sixteenth resistor R16. The collector of the twelfth transistor Q12 is connected to the emitter of the seventh transistor Q7, one end of the seventeenth resistor R17, and the other end of the fifth capacitor C5. The other end of the seventeenth resistor R17 is connected to the gate of the seventh MOSFET M7. The collector of the seventh transistor Q7 is connected to the emitter of the tenth transistor Q10. The collector of the eleventh transistor Q11, the other end of the sixth capacitor C6, and one end of the eighteenth resistor R18 are connected. The other end of the eighteenth resistor R18 and the other end of the seventh capacitor C7 are connected to the gate of the eighth MOSFET M8.

[0029] The gate input voltage signal Vbp of the ninth MOSFET M9 is connected to the source of the seventh MOSFET M7 and the positive input terminal of the differential amplifier OP1. The gate input voltage signal Vbp of the tenth MOSFET M10 is connected to one end of the nineteenth resistor R19 and the negative input terminal of the differential amplifier OP1. The other end of the nineteenth resistor R19 is connected to the source of the eighth MOSFET M8. The output terminal of the differential amplifier OP1 serves as the output terminal of the second automatic gain control module AGC2, outputting the voltage signal Vagc2.

[0030] Beneficial effects: Compared with the prior art, the advantages of the present invention include:

[0031] This invention designs a transimpedance amplifier circuit for 50GPON, which has a fast burst response time, high linearity in the dynamic range, low equivalent input noise, and its output waveform can quickly establish a stable state. Attached Figure Description

[0032] Figure 1 This is a structural diagram of a transimpedance amplifier circuit applied to a 50GPON according to an embodiment of the present invention;

[0033] Figure 2 This is a circuit diagram of the first automatic gain control module AGC1 provided according to an embodiment of the present invention;

[0034] Figure 3 This is a circuit diagram of a burst cap switched capacitor coupling module provided according to an embodiment of the present invention;

[0035] Figure 4 This is a circuit diagram of the second automatic gain control module AGC2 provided according to an embodiment of the present invention;

[0036] Figure 5 This is a schematic diagram of the 50GPON burst mode provided according to an embodiment of the present invention;

[0037] Figure 6 This is a diagram showing the working state of a transimpedance amplifier in burst mode for 50GPON, provided according to an embodiment of the present invention.

[0038] Figure 7 This is a simulated eye diagram of a transimpedance amplifier applied to a 50GPON according to an embodiment of the present invention. Detailed Implementation

[0039] The present invention will be further described below with reference to the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present invention, and should not be used to limit the scope of protection of the present invention.

[0040] Reference Figure 1 This invention provides a transimpedance amplifier circuit for 50GPON, comprising a core amplifier CORE_Amp, a burst cap-coupled module, a single-ended to differential variable gain amplifier S2D_VGA, an output driver Drv, a first automatic gain control module AGC1, a second automatic gain control module AGC2, a differential offset cancellation module DOC, a differential amplifier AMP, a DC voltage operating point module Dummy, a resistor R_Dummy, and a variable resistor Rf;

[0041] The main links of the transimpedance amplifier circuit consist of the core amplifier CORE_Amp, the burst switched capacitor coupling module burstcap, the single-ended to differential variable gain amplifier S2D_VGA, the output driver Drv, the first automatic gain control module AGC1, the differential offset cancellation module DOC, the second automatic gain control module AGC2, the differential amplifier AMP, and the DC voltage operating point module Dummy.

[0042] The transimpedance amplifier circuit is packaged in a chip, see reference. Figure 1 The chip includes an input pin IN, a power supply pin VCC, a reset pin RST, a negative power supply pin VEE, and output pins OUTP and OUTN. The current signal is input from the IN pin, converted into a single-ended voltage signal by the core amplifier CORE_Amp, and then transmitted to the burst cap module. After processing, one end outputs a DC voltage boosted signal, and the other end outputs the average signal voltage, which serves as the input common-mode level for the single-ended to differential variable gain amplifier S2D_VGA. The single-ended to differential variable gain amplifier S2D_VGA converts the single-ended signal voltage into a differential voltage. The output driver Drv transmits this differential signal to the next stage chip, ensuring impedance matching during transmission.

[0043] The core amplifier CORE_Amp is used to convert the input current signal into a single-ended voltage signal. The input terminal of the core amplifier CORE_Amp is the input current signal and is connected to one end of the variable resistor Rf. The input terminal of the core amplifier CORE_Amp is used as the input pin IN of the chip. The output terminal of the core amplifier CORE_Amp is connected to the other end of the variable resistor Rf.

[0044] The DC voltage operating point module Dummy is used to generate the same DC voltage operating point as the core amplifier CORE_Amp. Its input is connected to one end of the resistor R_Dummy, and the other end of the resistor R_Dummy is connected to the output of the DC voltage operating point module Dummy.

[0045] The two input terminals of the first automatic gain control module AGC1 are connected to the output terminal of the core amplifier CORE_Amp and the output terminal of the DC voltage operating point module Dummy, respectively. The output terminal of the first automatic gain control module AGC1 is connected to the variable terminal of the variable resistor Rf.

[0046] The output of the core amplifier CORE_Amp is connected to the input of the burst cap module. The two outputs of the burst cap module are connected to the two inputs of the single-ended to differential variable gain amplifier S2D_VGA. The two outputs of the S2D_VGA are connected to the two inputs of the differential amplifier AMP. The two outputs of the AMP are connected to the two inputs of the output driver Drv. The two outputs of the Drv output voltage signal V. OUTP V OUTN ;

[0047] The two input terminals of the second automatic gain control module AGC2 are connected to the two output terminals of the differential amplifier AMP, respectively. The output terminal of the second automatic gain control module AGC2 is connected to the positive power supply terminal of the single-ended to differential variable gain amplifier S2D_VGA.

[0048] The two input terminals of the differential offset cancellation module DOC are connected to the two output terminals of the differential amplifier AMP, respectively. The output terminal of the differential offset cancellation module DOC is connected to the negative power supply terminal of the single-ended to differential variable gain amplifier S2D_VGA.

[0049] Reference Figure 2 The first automatic gain control module AGC1 includes a first resistor R1, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, a first capacitor C1, a second capacitor C2, a switch TG1, a first MOSFET M1, a second MOSFET M2, a third MOSFET M3, a fourth MOSFET M4, a fifth MOSFET M5, a sixth MOSFET M6, a first transistor Q1, a second transistor Q2, a third transistor Q3, a fourth transistor Q4, a first current source I1, and a second current source I2;

[0050] Among them, the first MOSFET M1, the second MOSFET M2, the third MOSFET M3, the fourth MOSFET M4, the fifth MOSFET M5, and the sixth MOSFET M6 are all PMOS transistors, and the first transistor Q1, the second transistor Q2, the third transistor Q3, and the fourth transistor Q4 are all NPN transistors.

[0051] The switch TG1 is composed of a PMOS transistor, a second resistor R2, and an NPMOS transistor connected in parallel. The gate of the NPMOS transistor is input with the control signal RST, and the gate of the PMOS transistor is input with the control signal RSTB. The control signal RSTB is the signal output by the control signal RST after passing through the inverter. The source of the NPMOS transistor, the source of the PMOS transistor, and one end of the second resistor R2 are connected together, and the drain of the NPMOS transistor, the drain of the PMOS transistor, and the other end of the second resistor R2 are connected together.

[0052] The connections of the resistors, MOSFETs, transistors, and current sources in the first automatic gain control module AGC1 are as follows:

[0053] The Core_out signal, after being filtered by the first capacitor C1, is input to the gate of the third MOSFET M3. One end of the first resistor R1 is connected to the output of the core amplifier CORE_Amp, and the other end is connected to the source of the PMOS transistor of switch TG1. One end of the first capacitor C1 is connected to the drain of the NMOS transistor of switch TG1 and the gate of the third MOSFET M3, and the other end of the first capacitor C1 is grounded. The drain of the third MOSFET M3 is grounded, and its source is connected to one end of the fourth resistor R4. The other end of the fourth resistor R4 is connected to the drain of the first MOSFET M1 and the base of the first transistor Q1. The gate input voltage Vbp of the first MOSFET M1 is connected to the source of the first MOSFET M1, the source of the second MOSFET M2, the base and collector of the third transistor Q3, the source of the fifth MOSFET M5, the source of the sixth MOSFET M6, and the positive terminal of the second current source I2.

[0054] The output signal dummy_out of the DC voltage operating point module Dummy is filtered by the third resistor R3 and the second capacitor C2, and then input to the gate of the fourth MOSFET M4. Specifically, one end of the third resistor R3 is connected to the output terminal of the DC voltage operating point module Dummy to input the Dummy_out signal, and the other end is connected to the gate of the fourth MOSFET M4 and one end of the second capacitor C2. The other end of the second capacitor C2 is grounded. The drain of the fourth MOSFET M4 is grounded, and its source is connected to the drain of the second MOSFET M2 and the base of the second transistor Q2. The negative terminal of the first current source I1 is grounded, and its positive terminal is connected to one end of the fifth resistor R5 and the sixth resistor R6. The other end of the fifth resistor R5 is connected to the first transistor... The emitter of transistor Q1 is connected to the collector of transistor Q1 and the emitter of transistor Q3. The other end of resistor R6 is connected to the emitter of transistor Q2. The collector of transistor Q2 is connected to the drain and gate of transistor M5. The gate of transistor M5 is connected to the gate of transistor M6. The drain of transistor M6, the negative terminal of current source I2, and one end of resistor R7 are connected. The negative terminal of current source I2 serves as the output terminal of automatic gain control module AGC1, outputting voltage signal Vgf. The other end of resistor R7 is connected to the collector and base of transistor Q4. The emitter of transistor Q4 is grounded.

[0055] The first transistor Q1, the second transistor Q2, the fifth resistor R5, the sixth resistor R6, and the first current source I1 together form a differential amplifier, which converts the input voltage change into an output current change iagc. The current is then transmitted through the fifth MOSFET M5 and the sixth MOSFET M6. The changing current is connected to the network formed by the fourth transistor Q4, the seventh resistor R7, and the second current source I2, and finally outputs a voltage Vgf.

[0056] Reference Figure 3 The burst capacitive coupling module includes a third capacitor C3, a fourth capacitor C4, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a switch TG2, and a switch TG3.

[0057] In this circuit, switches TG2 and TG3 are each composed of an NPMOS transistor and a PMOS transistor connected in parallel. The source of the NPMOS transistor is connected to the source of the PMOS transistor, and the drain of the NPMOS transistor is connected to the drain of the PMOS transistor. The gate of the NPMOS transistor is input with the control signal RST, and the gate of the PMOS transistor is input with the control signal RSTB. The control signal RSTB is the output signal of the control signal RST after passing through an inverter. The control signal RST controls switches TG2 and TG3 respectively after passing through the inverter. If there is a sudden change in the common-mode level, switches TG2 and TG3 will be turned on under the action of the control signal RST.

[0058] The third capacitor C3 transmits high-speed AC signals, the fourth capacitor C4 performs differential matching, and the eighth resistor R8 and the tenth resistor R10 connect the output and power supply, providing DC levels for the output pins Vop and Von. The ninth resistor R9 and the switch TG2 are connected in series and then in parallel with the eighth resistor R8, which is equivalent to... Figure 1 The variable resistor Rf_1 in the burst capacitive coupling module; the eleventh resistor R11 and switch TG3 are connected in series and then in parallel with the tenth resistor R10, which is equivalent to Figure 1 The variable resistor Rf_2 in the burst capacitive coupling module; the RST signal, after being inverted by an inverter, controls switches TG2 and TG3 respectively (NMOS gate connected to RST, PMOS gate connected to RSTB). When there is a sudden change in the common-mode level of Vip, switches TG2 and TG3 are turned on under the action of RST, providing a fast response to the common-mode level of output pins Vop and Von.

[0059] The connection relationships of the resistors, capacitors, and switches in the burst capacitive coupling module are as follows:

[0060] One end of the third capacitor C3 is connected to the input voltage Vip, and the other end is connected to one end of the eighth resistor R8 and the ninth resistor R9. It also serves as the output terminal of the burst cap of the burst capacitor coupling module, outputting the voltage signal Vop. One end of the fourth capacitor C4 is grounded, and the other end is connected to one end of the tenth resistor R10 and the eleventh resistor R11. It also serves as the output terminal of the burst cap of the burst capacitor coupling module, outputting the voltage signal Von.

[0061] The other end of the ninth resistor R9 is connected to the source of the NPMOS transistor of switch TG2, the other end of the eleventh resistor R11 is connected to the source of the NPMOS transistor of switch TG3, the other ends of the eighth resistor R8 and the tenth resistor R10 are connected to the drain of the NPMOS transistors of switches TG2 and TG3, and the static voltage VCM is input.

[0062] Reference Figure 4 The second automatic gain control module AGC2 includes the twelfth resistor R12, the thirteenth resistor R13, the fourteenth resistor R14, the fifteenth resistor R15, the sixteenth resistor R16, the seventeenth resistor R17, the eighteenth resistor R18, the fifth capacitor C5, the sixth capacitor C6, the seventh capacitor C7, the fifth transistor Q5, the sixth transistor Q6, the seventh transistor Q7, the eighth transistor Q8, the ninth transistor Q9, the tenth transistor Q10, the eleventh transistor Q11, the twelfth transistor Q12, the seventh MOSFET M7, the eighth MOSFET M8, the ninth MOSFET M9, the tenth MOSFET M10, the switch TG4, and the differential amplifier OP1.

[0063] Among them, the seventh MOSFET M7, the eighth MOSFET M8, the ninth MOSFET M9, and the tenth MOSFET M10 are all PMOS transistors, while the fifth transistor Q5, the sixth transistor Q6, the seventh transistor Q7, the eighth transistor Q8, the ninth transistor Q9, the tenth transistor Q10, the eleventh transistor Q11, and the twelfth transistor Q12 are all NPN transistors.

[0064] Among them, switch TG4 is composed of an NPMOS transistor and a PMOS transistor connected in parallel. The source of the NPMOS transistor is connected to the source of the PMOS transistor, and the drain of the NPMOS transistor is connected to the drain of the PMOS transistor. The gate of the NPMOS transistor is input with control signal RST, and the gate of the PMOS transistor is input with control signal RSTB. The control signal RSTB is the signal output by the control signal RST after passing through the inverter.

[0065] One end of the twelfth resistor R12 is connected to the input voltage Vip and the base of the fifth transistor Q5. The other end of the twelfth resistor R12 is connected to one end of the thirteenth resistor R13 and the base of the seventh transistor Q7. The other end of the thirteenth resistor R13 is connected to the input voltage Vin and the base of the sixth transistor Q6. The emitter of the sixth transistor Q6, the emitter of the fifth transistor Q5, and the collector of the eleventh transistor Q11 are connected. The collector of the sixth transistor Q6 is connected to the emitter of the ninth transistor Q9. The collector of the fifth transistor Q5 is connected to the emitter of the eighth transistor Q8. The base and collector of the eighth transistor Q8, the base and collector of the ninth transistor Q9, the base and collector of the tenth transistor Q10, the source of the ninth MOSFET M9, and the source of the tenth MOSFET M10 are connected.

[0066] The base input voltage signal Vbn of the eleventh transistor Q11 is connected to one end of the fourteenth resistor R14 and the fifteenth resistor R15. The other end of the fifteenth resistor R15 is connected to the source of the NPMOS transistor of switch TG4. The drain of the NPMOS transistor of switch TG4, the other end of the fourteenth resistor R14, the sixteenth resistor R16, one end of the fifth capacitor C5, the sixth capacitor C6, the seventh capacitor C7, the drain of the seventh MOS transistor M7, and the drain of the eighth MOS transistor M8 are connected and grounded.

[0067] The base input voltage signal Vbn of the twelfth transistor Q12 is connected to its emitter, which is connected to the other end of the sixteenth resistor R16. The collector of the twelfth transistor Q12 is connected to the emitter of the seventh transistor Q7, one end of the seventeenth resistor R17, and the other end of the fifth capacitor C5. The other end of the seventeenth resistor R17 is connected to the gate of the seventh MOSFET M7. The collector of the seventh transistor Q7 is connected to the emitter of the tenth transistor Q10. The collector of the eleventh transistor Q11, the other end of the sixth capacitor C6, and one end of the eighteenth resistor R18 are connected. The other end of the eighteenth resistor R18 and the other end of the seventh capacitor C7 are connected to the gate of the eighth MOSFET M8.

[0068] The gate input voltage signal Vbp of the ninth MOSFET M9 is connected to the source of the seventh MOSFET M7 and the positive input terminal of the differential amplifier OP1. The gate input voltage signal Vbp of the tenth MOSFET M10 is connected to one end of the nineteenth resistor R19 and the negative input terminal of the differential amplifier OP1. The other end of the nineteenth resistor R19 is connected to the source of the eighth MOSFET M8. The output terminal of the differential amplifier OP1 serves as the output terminal of the second automatic gain control module AGC2, outputting the voltage signal Vagc2. The ninth MOSFET M9 and the tenth MOSFET M10 provide bias currents for the seventh MOSFET M7 and the eighth MOSFET M8, respectively. The output terminal of the differential amplifier OP1 is connected to the positive power supply terminal of the single-ended to differential variable gain amplifier S2D_VGA.

[0069] The operating mode of the transimpedance amplifier circuit for 50GPON provided in this embodiment of the invention is as follows: Figure 5 As shown, there is only a short protection time between two signal packets with different power levels. During normal operation, RST is low, and the switch it controls is in the off state. The RC constants of the capacitive coupling and AGC loop are large, and the low-frequency cutoff frequency of the transimpedance amplifier link is low to ensure the CID performance of the link. During the burst reset, RST becomes high, and the RC constants of the capacitive coupling network and AGC1 and AGC2 decrease, realizing the rapid establishment of common-mode voltage and rapid gain switching. Figure 6This is a simulation of the working state of the transimpedance amplifier circuit applied to 50GPON during the switching process between large and small signals, provided by an embodiment of the present invention. The three waveforms are the change of input current (large signal before 150ns, small signal after 150ns), RST control signal, and output differential voltage, respectively. The simulation shows that under the action of RST signal, the output waveform can establish a stable state after a recovery time of 60ns. Figure 7 The simulated eye diagram of the small signal after the reset is displayed, and the crossover point and eye diagram quality are good.

[0070] The embodiments of the present invention have been described in detail above with reference to the accompanying drawings. However, the present invention is not limited to the above embodiments. Within the scope of knowledge possessed by those skilled in the art, various changes can be made without departing from the spirit of the present invention.

Claims

1. A transimpedance amplifier circuit for 50GPON, characterized in that, The transimpedance amplifier includes a core amplifier CORE_Amp, a burst cap-coupled module, a single-ended to differential variable gain amplifier S2D_VGA, an output driver Drv, a first automatic gain control module AGC1, a second automatic gain control module AGC2, a differential offset cancellation module DOC, a differential amplifier AMP, a DC voltage operating point module Dummy, a resistor R_Dummy, and a variable resistor Rf. The core amplifier CORE_Amp is used to convert the input current signal into a single-ended voltage signal. The input terminal of the core amplifier CORE_Amp is the input current signal and is connected to one end of the variable resistor Rf. The output terminal of the core amplifier CORE_Amp is connected to the other end of the variable resistor Rf. The DC voltage operating point module Dummy is used to generate the same DC voltage operating point as the core amplifier CORE_Amp. Its input is connected to one end of the resistor R_Dummy, and the other end of the resistor R_Dummy is connected to the output of the DC voltage operating point module Dummy. The two input terminals of the first automatic gain control module AGC1 are connected to the output terminal of the core amplifier CORE_Amp and the output terminal of the DC voltage operating point module Dummy, respectively. The output terminal of the first automatic gain control module AGC1 is connected to the variable terminal of the variable resistor Rf. The output of the core amplifier CORE_Amp is connected to the input of the burst cap module. The two outputs of the burst cap module are connected to the two inputs of the single-ended to differential variable gain amplifier S2D_VGA. The two outputs of the S2D_VGA are connected to the two inputs of the differential amplifier AMP. The two outputs of the AMP are connected to the two inputs of the output driver Drv. The two outputs of the Drv output voltage signal V. OUTP V OUTN ; The two input terminals of the second automatic gain control module AGC2 are connected to the two output terminals of the differential amplifier AMP, respectively. The output terminal of the second automatic gain control module AGC2 is connected to the positive power supply terminal of the single-ended to differential variable gain amplifier S2D_VGA. The two input terminals of the differential offset cancellation module DOC are connected to the two output terminals of the differential amplifier AMP, respectively. The output terminal of the differential offset cancellation module DOC is connected to the negative power supply terminal of the single-ended to differential variable gain amplifier S2D_VGA.

2. The transimpedance amplifier circuit for 50GPON according to claim 1, characterized in that, The first automatic gain control module AGC1 includes a first resistor R1, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, a first capacitor C1, a second capacitor C2, a switch TG1, a first MOSFET M1, a second MOSFET M2, a third MOSFET M3, a fourth MOSFET M4, a fifth MOSFET M5, a sixth MOSFET M6, a first transistor Q1, a second transistor Q2, a third transistor Q3, a fourth transistor Q4, a first current source I1, and a second current source I2; Among them, the first MOSFET M1, the second MOSFET M2, the third MOSFET M3, the fourth MOSFET M4, the fifth MOSFET M5, and the sixth MOSFET M6 are all PMOS transistors, and the first transistor Q1, the second transistor Q2, the third transistor Q3, and the fourth transistor Q4 are all NPN transistors. The switch TG1 is composed of a PMOS transistor, a second resistor R2, and an NPMOS transistor connected in parallel. The gate of the NPMOS transistor is input with the control signal RST, and the gate of the PMOS transistor is input with the control signal RSTB. The control signal RSTB is the signal output by the control signal RST after passing through the inverter. The source of the NPMOS transistor, the source of the PMOS transistor, and one end of the second resistor R2 are connected together, and the drain of the NPMOS transistor, the drain of the PMOS transistor, and the other end of the second resistor R2 are connected together. The connections of the resistors, MOSFETs, transistors, and current sources in the first automatic gain control module AGC1 are as follows: One end of the first resistor R1 is connected to the output of the core amplifier CORE_Amp, inputting the Core_out signal, and the other end is connected to the source of the PMOS transistor of switch TG1. One end of the first capacitor C1 is connected to the drain of the NMOS transistor of switch TG1 and the gate of the third MOS transistor M3, and the other end of the first capacitor C1 is grounded. The drain of the third MOS transistor M3 is grounded, and its source is connected to one end of the fourth resistor R4. The other end of the fourth resistor R4 is connected to the drain of the first MOS transistor M1 and the base of the first transistor Q1. The gate input voltage Vbp of the first MOS transistor M1 is connected to the source of the first MOS transistor M1, the source of the second MOS transistor M2, the base and collector of the third transistor Q3, the source of the fifth MOS transistor M5, the source of the sixth MOS transistor M6, and the positive terminal of the second current source I2. One end of the third resistor R3 is connected to the output terminal of the DC voltage operating point module Dummy, inputting the Dummy_out signal. The other end is connected to the gate of the fourth MOSFET M4 and one end of the second capacitor C2. The other end of the second capacitor C2 is grounded. The drain of the fourth MOSFET M4 is grounded, and its source is connected to the drain of the second MOSFET M2 and the base of the second transistor Q2. The negative terminal of the first current source I1 is grounded, and its positive terminal is connected to one end of the fifth resistor R5 and the sixth resistor R6. The other end of the fifth resistor R5 is connected to the emitter of the first transistor Q1. The collector of the first transistor Q1 is connected to the third transistor Q... The emitter of transistor 3 is connected to the emitter of transistor Q2. The collector of transistor Q2 is connected to the drain and gate of transistor M5. The gate of transistor M5 is connected to the gate of transistor M6. The drain of transistor M6, the negative terminal of current source I2, and one end of resistor R7 are connected. The negative terminal of current source I2 serves as the output terminal of the first automatic gain control module AGC1, outputting the voltage signal Vgf. The other end of resistor R7 is connected to the collector and base of transistor Q4. The emitter of transistor Q4 is grounded.

3. The transimpedance amplifier circuit for 50GPON according to claim 1, characterized in that, The burst capacitive coupling module includes a third capacitor C3, a fourth capacitor C4, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a switch TG2, and a switch TG3. In this circuit, switches TG2 and TG3 are each composed of an NPMOS transistor and a PMOS transistor connected in parallel. The source of the NPMOS transistor is connected to the source of the PMOS transistor, and the drain of the NPMOS transistor is connected to the drain of the PMOS transistor. The gate of the NPMOS transistor is input with the control signal RST, and the gate of the PMOS transistor is input with the control signal RSTB. The control signal RSTB is the output signal of the control signal RST after passing through an inverter. The control signal RST controls switches TG2 and TG3 respectively after passing through the inverter. If there is a sudden change in the common-mode level, switches TG2 and TG3 will be turned on under the action of the control signal RST. The connection relationships of the resistors, capacitors, and switches in the burst capacitive coupling module are as follows: One end of the third capacitor C3 is connected to the input voltage Vip, and the other end is connected to one end of the eighth resistor R8 and the ninth resistor R9. It also serves as the output terminal of the burst cap of the burst capacitor coupling module, outputting the voltage signal Vop. One end of the fourth capacitor C4 is grounded, and the other end is connected to one end of the tenth resistor R10 and the eleventh resistor R11. It also serves as the output terminal of the burst cap of the burst capacitor coupling module, outputting the voltage signal Von. The other end of the ninth resistor R9 is connected to the source of the NPMOS transistor of switch TG2, the other end of the eleventh resistor R11 is connected to the source of the NPMOS transistor of switch TG3, the other ends of the eighth resistor R8 and the tenth resistor R10 are connected to the drain of the NPMOS transistors of switches TG2 and TG3, and the static voltage VCM is input.

4. The transimpedance amplifier circuit for 50GPON according to claim 1, characterized in that, The second automatic gain control module AGC2 includes twelfth resistor R12, thirteenth resistor R13, fourteenth resistor R14, fifteenth resistor R15, sixteenth resistor R16, seventeenth resistor R17, eighteenth resistor R18, fifth capacitor C5, sixth capacitor C6, seventh capacitor C7, fifth transistor Q5, sixth transistor Q6, seventh transistor Q7, eighth transistor Q8, ninth transistor Q9, tenth transistor Q10, eleventh transistor Q11, twelfth transistor Q12, seventh MOSFET M7, eighth MOSFET M8, ninth MOSFET M9, tenth MOSFET M10, switch TG4, and differential amplifier OP1; Among them, the seventh MOSFET M7, the eighth MOSFET M8, the ninth MOSFET M9, and the tenth MOSFET M10 are all PMOS transistors, while the fifth transistor Q5, the sixth transistor Q6, the seventh transistor Q7, the eighth transistor Q8, the ninth transistor Q9, the tenth transistor Q10, the eleventh transistor Q11, and the twelfth transistor Q12 are all NPN transistors. Among them, switch TG4 is composed of an NPMOS transistor and a PMOS transistor connected in parallel. The source of the NPMOS transistor is connected to the source of the PMOS transistor, and the drain of the NPMOS transistor is connected to the drain of the PMOS transistor. The gate of the NPMOS transistor is input with control signal RST, and the gate of the PMOS transistor is input with control signal RSTB. The control signal RSTB is the signal output by the control signal RST after passing through the inverter. One end of the twelfth resistor R12 is connected to the input voltage Vip and the base of the fifth transistor Q5. The other end of the twelfth resistor R12 is connected to one end of the thirteenth resistor R13 and the base of the seventh transistor Q7. The other end of the thirteenth resistor R13 is connected to the input voltage Vin and the base of the sixth transistor Q6. The emitter of the sixth transistor Q6, the emitter of the fifth transistor Q5, and the collector of the eleventh transistor Q11 are connected. The collector of the sixth transistor Q6 is connected to the emitter of the ninth transistor Q9. The collector of the fifth transistor Q5 is connected to the emitter of the eighth transistor Q8. The base and collector of the eighth transistor Q8, the base and collector of the ninth transistor Q9, the base and collector of the tenth transistor Q10, the source of the ninth MOSFET M9, and the source of the tenth MOSFET M10 are connected. The base input voltage signal Vbn of the eleventh transistor Q11 is connected to one end of the fourteenth resistor R14 and the fifteenth resistor R15. The other end of the fifteenth resistor R15 is connected to the source of the NPMOS transistor of switch TG4. The drain of the NPMOS transistor of switch TG4, the other end of the fourteenth resistor R14, the sixteenth resistor R16, one end of the fifth capacitor C5, the sixth capacitor C6, the seventh capacitor C7, the drain of the seventh MOS transistor M7, and the drain of the eighth MOS transistor M8 are connected and grounded. The base input voltage signal Vbn of the twelfth transistor Q12 is connected to its emitter, which is connected to the other end of the sixteenth resistor R16. The collector of the twelfth transistor Q12 is connected to the emitter of the seventh transistor Q7, one end of the seventeenth resistor R17, and the other end of the fifth capacitor C5. The other end of the seventeenth resistor R17 is connected to the gate of the seventh MOSFET M7. The collector of the seventh transistor Q7 is connected to the emitter of the tenth transistor Q10. The collector of the eleventh transistor Q11, the other end of the sixth capacitor C6, and one end of the eighteenth resistor R18 are connected. The other end of the eighteenth resistor R18 and the other end of the seventh capacitor C7 are connected to the gate of the eighth MOSFET M8. The gate input voltage signal Vbp of the ninth MOSFET M9 is connected to the source of the seventh MOSFET M7 and the positive input terminal of the differential amplifier OP1. The gate input voltage signal Vbp of the tenth MOSFET M10 is connected to one end of the nineteenth resistor R19 and the negative input terminal of the differential amplifier OP1. The other end of the nineteenth resistor R19 is connected to the source of the eighth MOSFET M8. The output terminal of the differential amplifier OP1 serves as the output terminal of the second automatic gain control module AGC2, outputting the voltage signal Vagc2.

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