Doherty amplifier circuit

Abstract

This Doherty amplification circuit includes: a carrier amplifier for amplifying an inputted high-frequency signal; a peak amplifier for amplifying the inputted high-frequency signal; a first bias circuit for applying a bias to the carrier amplifier; a second bias circuit for applying a bias to the peak amplifier; and, a control circuit for controlling the second bias circuit on the basis of the inputted high-frequency signal and a signal for representing the drive level of the carrier amplifier.

Description

[Technical Field]

[0001] The present disclosure relates to a Doherty amplifier circuit. [Background technology]

[0002] A Doherty amplifier circuit is known as a highly efficient power amplifier circuit. A Doherty amplifier circuit generally has a configuration in which a carrier amplifier, which operates regardless of the power level of the input signal, and a peak amplifier, which is turned off when the power level of the input signal is low and turned on when the power level is high, are connected in parallel. In this configuration, when the power level of the high-frequency input signal is high, the carrier amplifier operates while maintaining saturation at the saturated output power level. This allows the Doherty amplifier circuit to have improved efficiency compared to ordinary power amplifier circuits.

[0003] The following Patent Documents 1 to 3 describe techniques for controlling the bias of a peak amplifier.

[0004] The technology described in Patent Document 1 detects saturation of a carrier amplifier via a bias circuit of the carrier amplifier, and controls the bias circuit of a peak amplifier in response to the detection signal.

[0005] The technology described in Patent Document 2 detects saturation of a carrier amplifier based on an output signal of the carrier amplifier, and controls a bias circuit of a peak amplifier in accordance with the detection signal.

[0006] The technology described in Patent Document 3 controls the bias circuit of a peak amplifier according to the level of a high-frequency input signal input to a Doherty amplifier circuit or the level of a high-frequency input signal input to a carrier amplifier. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] US Patent Application Publication No. 2016 / 0241209 [Patent Document 2] US Patent Application Publication No. 2020 / 0028472 [Patent Document 3] Japanese Patent Application Publication No. 2019-41277 Summary of the Invention [Problem to be solved by the invention]

[0008] In the techniques described in Patent Documents 1 and 2, the time required for the circuit for detecting carrier amplifier saturation to respond is approximately several tens of nanoseconds. Therefore, the following inconveniences may occur. For example, when a high-frequency input signal with a momentary (significantly shorter than several tens of nanoseconds) increase in power is input to a Doherty amplifier, the carrier amplifier may remain saturated for several tens of nanoseconds, from when the carrier amplifier begins to saturate until the bias point of the peak amplifier fluctuates. This may result in a failure to maintain high quality of the high-frequency output signal from the Doherty amplifier. Furthermore, when the Doherty amplifier is used in a communication device, high communication quality may not be maintained.

[0009] Although the technology described in Patent Document 3 operates in response to the high-frequency input signal level, the high-frequency input signal level is detected by a bias circuit, and therefore the response speed is considered to be basically slow, and it is thought that the quality of the high-frequency output signal from the Doherty amplifier circuit may not be maintained at a high level.

[0010] The present disclosure has been made in view of the above, and aims to suppress degradation in the quality of a high-frequency output signal. [Means for solving the problem]

[0011] A Doherty amplifier circuit according to one aspect of the present disclosure includes a carrier amplifier that amplifies an input high-frequency signal, a peak amplifier that amplifies the input high-frequency signal, a first bias circuit that provides a bias to the carrier amplifier, a second bias circuit that provides a bias to the peak amplifier, and a control circuit that controls the second bias circuit based on the input high-frequency signal and a drive level signal that indicates the drive level of the carrier amplifier. [Effects of the Invention]

[0012] According to the present disclosure, it is possible to suppress degradation in the quality of a high-frequency output signal. [Brief explanation of the drawings]

[0013] [Figure 1] FIG. 1 is a diagram illustrating a configuration of a power amplifier circuit according to a first embodiment. [Figure 2] FIG. 2 is a schematic diagram showing an example of the relationship between the power of the high-frequency signal of the power amplifier circuit according to the first embodiment and the signal output by the detection circuit. [Figure 3] FIG. 3 is a diagram illustrating a configuration of a detection circuit of the power amplifier circuit according to the first embodiment. [Figure 4] FIG. 4 is a diagram illustrating an example of the relationship between the power of the high-frequency signal of the power amplifier circuit according to the first embodiment and the bias voltage applied to the peak amplifier. [Figure 5] FIG. 5 is a diagram showing a specific example of a bias circuit that applies a bias to the final-stage carrier amplifier and a detection circuit in the power amplifier circuit of the first embodiment. [Figure 6] FIG. 6 is a diagram showing a configuration of a power amplifier circuit according to a first modified example of the first embodiment. [Figure 7] FIG. 7 is a diagram showing a configuration of a power amplifier circuit according to a second modified example of the first embodiment. [Figure 8] FIG. 8 is a diagram illustrating a configuration of a power amplifier circuit according to the second embodiment. [Figure 9] FIG. 9 is a diagram showing a specific example of a detection circuit and a variable attenuator in the power amplifier circuit according to the second embodiment. [Figure 10] FIG. 10 is a diagram illustrating a configuration of a power amplifier circuit according to the third embodiment. [Figure 11] FIG. 11 is a diagram illustrating a configuration of a power amplifier circuit according to the fourth embodiment. [Figure 12] FIG. 12 is a diagram showing a specific example of a detection circuit and an adder circuit in the power amplifier circuit according to the fourth embodiment. [Figure 13] FIG. 13 is a diagram illustrating a configuration of a power amplifier circuit according to the fifth embodiment. [Figure 14] FIG. 14 is a diagram showing a specific example of a detection circuit and a drive level detection circuit in the power amplifier circuit according to the fifth embodiment. [Figure 15] FIG. 15 is a diagram showing an equivalent circuit of a specific example of the detection circuit and the drive level detection circuit of the power amplifier circuit according to the fifth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0014] Hereinafter, embodiments of the Doherty amplifier circuit of the present disclosure will be described in detail with reference to the drawings. Note that the present disclosure is not limited to these embodiments. Each embodiment is an example, and it goes without saying that partial substitution or combination of the configurations shown in different embodiments is possible. From the second embodiment onwards, a description of matters common to the first embodiment will be omitted, and only the differences will be described. In particular, similar effects resulting from similar configurations will not be mentioned in each embodiment.

[0015] First Embodiment (Overall composition) 1 is a diagram showing the configuration of a power amplifier circuit according to a first embodiment. The power amplifier circuit 1 includes an amplifier 2, a bias circuit 3, and a Doherty amplifier circuit 10. The Doherty amplifier circuit 10 includes a 90° hybrid circuit 11, a first-stage (driver stage) carrier amplifier 12, a final-stage (power stage) carrier amplifier 13, bias circuits 14 and 15, a first-stage peak amplifier 16, a final-stage peak amplifier 17, bias circuits 18 and 19, a coupler 20, and a control circuit 21. The control circuit 21 includes a detection circuit 22.

[0016] Each of the bias circuits 14 and 15 corresponds to an example of a "first bias circuit" in the present disclosure. Each of the bias circuits 18 and 19 corresponds to an example of a "second bias circuit" in the present disclosure.

[0017] Although the number of stages in the Doherty amplifier circuit 10 is two, the present disclosure is not limited to this. The number of stages in the Doherty amplifier circuit 10 may be one, or three or more.

[0018] The bias circuit 3 applies a bias to the amplifier 2. The amplifier 2 amplifies the radio frequency signal RFin and outputs the amplified radio frequency signal RF1 to the 90° hybrid circuit 11. The 90° hybrid circuit 11 divides the radio frequency signal RF1 into radio frequency signals RF2 and RF5 that are approximately 90° out of phase with each other, outputs the radio frequency signal RF2 to the carrier amplifier 12, and outputs the radio frequency signal RF5 to the peak amplifier 16. Note that "approximately 90°" does not only include a phase difference of 90°, but also a phase difference of 90°±45°.

[0019] The phase of the high frequency signal RF5 is, for example, delayed by 90° from the phase of the high frequency signal RF2, and the power of the high frequency signal RF2 and the power of the high frequency signal RF5 are, for example, the same.

[0020] The bias circuit 14 applies a bias to the carrier amplifier 12. The bias circuit 15 applies a bias to the carrier amplifier 13. The carrier amplifier 12 amplifies the high frequency signal RF2 and outputs the amplified high frequency signal RF3 to the carrier amplifier 13. The carrier amplifier 13 amplifies the high frequency signal RF3 and outputs the amplified high frequency signal RF4 to the coupler 20.

[0021] The bias circuit 18 applies a bias to the peak amplifier 16. The bias circuit 19 applies a bias to the peak amplifier 17. The peak amplifier 16 amplifies the high frequency signal RF5 and outputs the amplified high frequency signal RF6 to the peak amplifier 17. The peak amplifier 17 amplifies the high frequency signal RF6 and outputs the amplified high frequency signal RF7 to the coupler 20.

[0022] The coupler 20 combines the high-frequency signal RF4 and the high-frequency signal RF7. In the first embodiment, the coupler 20 is a phase shifter, but the present disclosure is not limited to this. The coupler 20 delays the phase of the high-frequency signal RF4 by 90° and outputs the result. The sum of the high-frequency signal RF7 and the output signal of the coupler 20 is the high-frequency signal RFout.

[0023] The detection circuit 22 receives the high frequency signal RFin and a signal S1 indicating the drive level (operating level) of the carrier amplifier 13. Instead of the high frequency signal RFin, the detection circuit 22 may receive the high frequency signal RF1. The signal S1 may be output from the bias circuit 15 or from the carrier amplifier 13. When the signal S1 is output from the carrier amplifier 13, it may be the high frequency signal RF4. The signal S1 may also be a signal (inverted signal) that changes complementarily to the drive level of the carrier amplifier 13.

[0024] The detection circuit 22 outputs a signal S2 that controls the bias circuits 18 and 19 to the bias circuits 18 and 19 based on the radio frequency signal RFin and the signal S1. The bias circuit 18 applies a bias to the peak amplifier 16 based on the signal S2. The bias circuit 19 applies a bias to the peak amplifier 17 based on the signal S2.

[0025] FIG. 2 is a schematic diagram showing an example of the relationship between the power of a high-frequency signal of the power amplification circuit according to the first embodiment and the signal output from the detection circuit. In FIG. 2, the horizontal axis represents the power of the high-frequency signal RFin, and the vertical axis represents the signal S2 output from the detection circuit 22.

[0026] The detection circuit 22 varies the rising point of the signal S2 according to the signal S1. Waveform 31 shows the relationship between the power of the high-frequency signal RFin and the signal S2 when the drive level of the carrier amplifier 13 is relatively low. Waveform 32 shows the relationship between the power of the high-frequency signal RFin and the signal S2 when the drive level of the carrier amplifier 13 is relatively intermediate. Waveform 33 shows the relationship between the power of the high-frequency signal RFin and the signal S2 when the drive level of the carrier amplifier 13 is relatively high.

[0027] When the drive level of the carrier amplifier 13 is relatively low, as shown in waveform 31, the detection circuit 22 raises the signal S2 when the power of the high-frequency signal RFin reaches the value A. In the range where the power of the high-frequency signal RFin is greater than or equal to the value A, the detection circuit 22 increases the signal S2 as the power of the high-frequency signal RFin increases.

[0028] When the drive level of the carrier amplifier 13 is relatively intermediate, as shown in waveform 32, the detection circuit 22 raises the signal S2 when the power of the high-frequency signal RFin reaches the value B (B < A). In the range where the power of the high-frequency signal RFin is greater than or equal to the value B, the detection circuit 22 increases the signal S2 as the power of the high-frequency signal RFin increases.

[0029] When the drive level of the carrier amplifier 13 is relatively high, as shown in waveform 33, the detection circuit 22 raises the signal S2 when the power of the high-frequency signal RFin reaches the value C (C < B). In the range where the power of the high-frequency signal RFin is greater than or equal to the value C, the detection circuit 22 increases the signal S2 as the high-frequency signal RFin increases.

[0030] When a high-power radio frequency signal RFin is input, which is the main cause of saturation of the carrier amplifiers 12 and 13, the detection circuit 22 outputs a signal S2 to the bias circuits 18 and 19, causing the bias circuits 18 and 19 to activate the peak amplifiers 16 and 17. As a result, the carrier amplifiers 12 and 13 are basically not saturated.

[0031] What is important here is the response speed of the detection circuit 22. Because the detection circuit 22 detects the high frequency signal RFin, it can respond much faster than the techniques described in Patent Documents 1 and 2, which detect that the carrier amplifier is saturated. Therefore, even if the power of the high frequency signal RFin increases in a short period of time, the detection circuit 22 responds immediately and causes the bias circuits 18 and 19 to activate the peak amplifiers 16 and 17, preventing the carrier amplifiers 12 and 13 from being saturated even momentarily.

[0032] However, if the temperature or other surrounding environment changes (for example, if the gain of the carrier amplifiers 12 and 13 increases at extremely low temperatures), the carrier amplifiers 12 and 13 may become saturated even if the power of the high-frequency signal RFin is small. To handle such cases, the detection circuit 22 detects the signal S1 that indicates the drive level of the carrier amplifiers 12 and 13, and if the carrier amplifiers 12 and 13 are close to saturation, immediately activates the peak amplifiers 16 and 17 even if the power of the high-frequency signal RFin is small.

[0033] Because the detection circuit 22 detects the high-frequency signal RFin, even if it takes time to detect the drive levels of the carrier amplifiers 12 and 13, the bias circuits 18 and 19 can activate the peak amplifiers 16 and 17 without saturating the carrier amplifiers 12 and 13. This allows the Doherty amplifier circuit 10 to suppress degradation in the quality of the high-frequency signal RFout.

[0034] The detection circuit 22 can also be considered to operate in a feedforward manner in response to the high frequency signal RFin and in a feedback manner in response to the signal S1.

[0035] (Detection circuit configuration) Fig. 3 is a diagram showing the configuration of the detection circuit of the power amplifier circuit of the first embodiment. Fig. 3 also shows circuit elements for applying a bias to the detection circuit 22. Note that the low-pass filter 42 and bias circuits 18 and 19 shown in Fig. 3 may be omitted. The low-pass filter 42 can be omitted if a good differential signal can be obtained. The bias circuits 18 and 19 can be omitted if the transistors to which the bias is supplied (amplification transistors) are small.

[0036] The detector circuit 22 includes a transistor Q DE1 and Q DE2 and resistance R DEE1 and R DEE2 and,

[0037] In this disclosure, each transistor is a bipolar transistor, but the present disclosure is not limited to this. An example of a bipolar transistor is a heterojunction bipolar transistor (HBT), but the present disclosure is not limited to this. A transistor may be, for example, a field effect transistor (FET). A transistor may be a multi-finger transistor in which multiple unit transistors are electrically connected in parallel. A unit transistor refers to the minimum configuration that makes up a transistor.

[0038] Transistor Q DE1 The collector of the transistor Q is electrically connected to the power supply potential Vcc. DE1 The emitter of the resistor R DEE1 That is, the transistor Q DE1 and resistor R DEE1 Transistor Q is connected as an emitter follower. DE1 and resistor R DEE1 constitutes the first emitter follower circuit 22a.

[0039] The detection circuit 22 may include a source follower circuit instead of the first emitter follower circuit 22a.

[0040] Transistor Q DE2 The collector of the transistor Q is electrically connected to the power supply potential Vcc. DE2 The emitter of the resistor R DEE2 That is, the transistor Q DE2 and resistor R DEE2 Transistor Q is connected as an emitter follower. DE2 and resistor R DEE2 constitutes the second emitter follower circuit 22b.

[0041] The detection circuit 22 may include a source follower circuit instead of the second emitter follower circuit 22b.

[0042] Resistance R DEE1 The other end of the resistor R DEE2 The output current I1 of the detection circuit 22 is the sum of the output current of the first emitter follower circuit 22a and the output current of the second emitter follower circuit 22b.

[0043] Resistance R DEBB , R DEB1 and R DEB2 , and transistor Q DE5 , Q DE6 and Q DE7 is the transistor Q DE1 and Q DE2 A bias voltage is applied to the base of the

[0044] Resistance R DEBB and one end of the resistor R DEB1 and one end of the resistor R DEB2 The other end of the first electrode is electrically connected to the other end of the second electrode.

[0045] Resistance R DEBB The other end of the transistor Q DE7 The collector and base of the transistor Q are electrically connected to each other. DE7is diode-connected. Transistor Q DE7 The emitter of the transistor Q DE6 The collector and base of the transistor Q are electrically connected to each other. DE6 is diode-connected. Transistor Q DE6 The emitter of the transistor Q DE5 The collector and base of the transistor Q are electrically connected to each other. DE5 is diode-connected. Transistor Q DE5 The emitter of each of the transistors is electrically connected to a reference potential. The reference potential is exemplified by a ground potential, but the present disclosure is not limited thereto.

[0046] Resistance R DEBB One end of resistor R DEB1 One end of resistor R DEB2 The bias current BIAS1 is input to one end of the resistor R DEBB , transistor Q DE7 , transistor Q DE6 and transistor Q DE5 generates a constant voltage. This voltage is applied across the resistor R DEB1 Through the transistor Q DE1 and is input to the base of resistor R DEB2 Through the transistor Q DE2 is entered into the base.

[0047] Transistor Q DE3 and Q DE4 Each of the transistors Q DE5 Transistor Q is connected in a current mirror. DE3 The collector of the transistor Q DE1 This electrically connects the base of transistor Q DE3 is the transistor Q DE1 The base current of the transistor Q can be adjusted. DE4 The collector of the transistor Q DE2 This electrically connects the base of transistor Q DE4 is the transistor Q DE2The base current of the transistor is adjustable.

[0048] Transistor Q DE1 The base of the transistor Q DE2 The high frequency signals IN1 and IN2, which are obtained by converting the high frequency signal RFin into differential signals, are input to the bases of the amplifiers 1 and 2. The high frequency signals IN1 and IN2 can be obtained, for example, by inputting the high frequency signal RFin to a balun.

[0049] Resistance R DEE1 The other end of the resistor R DEE2 The other end is electrically connected to a constant current circuit 41. The constant current circuit 41 includes a transistor Q DE11 and Q DE12 The constant current circuit 41 is a current bias circuit for the detection circuit 22.

[0050] Transistor Q DE12 is diode-connected. Transistor Q DE12 A voltage BIAS2 representing the drive level of the carrier amplifier 13 (see FIG. 1) is input to the collector and base of this transistor.

[0051] In the first embodiment, the voltage BIAS2 is a voltage that changes complementarily to the drive level of the carrier amplifier 13. When the drive level of the carrier amplifier 13 is relatively high (close to saturation), the voltage BIAS2 becomes a relatively low voltage. When the drive level of the carrier amplifier 13 is relatively low (when the amplification factor is reduced), the voltage BIAS2 becomes a relatively high voltage.

[0052] Transistor Q DE11 is the transistor Q DE12 and are connected in a current mirror. Therefore, the transistor Q DE11 The collector current I2 is a current that corresponds to the voltage BIAS2.

[0053] Transistor Q DE11 The collector of the resistor R DEE1 The other end of the resistor R DEE2is electrically connected to the other end of the

[0054] The low-pass filter 42 is connected to a capacitor C env Includes capacitor C env One end of the resistor R DEE1 The other end of the resistor R DEE2 and the other end of transistor Q DE11 It is electrically connected to the collector of the capacitor C env The other end is electrically connected to a reference potential.

[0055] Capacitor C env is the output current I1 of the detector circuit 22 and the DE11 The capacitor C is charged or discharged by the difference between the collector current I2 and env The voltage at capacitor C is the signal S2. env The capacitor C env This allows the bias circuits 18 and 19 in the subsequent stages and the transistors to which the bias is supplied (amplifying transistors) to be appropriately biased.

[0056] The bias circuit 18 is connected to the transistor Q DE8 , Q DE9 and Q DE10 The circuit configuration of the bias circuit 19 (see FIG. 1) is the same as that of the bias circuit 18, and therefore a description thereof will be omitted.

[0057] Transistor Q DE9 is diode-connected. Transistor Q DE9 The collector and base of the capacitor C env One end of the transistor Q is electrically connected to DE9 The emitter of the transistor Q DE8 The collector and base of transistor Q are electrically connected to each other. DE8 is diode-connected. Transistor Q DE8The emitter of transistor Q is electrically connected to the reference potential. DE9 and Q DE8 The capacitor C env A current corresponding to the voltage flows.

[0058] Transistor Q DE10 The collector of the transistor Q is electrically connected to the power supply potential Vcc. DE10 The base of the transistor Q DE9 The collector and base of transistor Q are electrically connected to each other. DE10 The emitter voltage of 16 (BIAS 17 ) and output to the peak amplifier 16 (17).

[0059] The operation of the detection circuit 22 will now be described.

[0060] Transistor Q DE1 is that the high frequency signal IN1 flows through the transistor Q DE1 When the threshold voltage of transistor Q is equal to or greater than the threshold voltage of transistor Q, the transistor Q turns on and outputs an emitter current. DE2 is that the high frequency signal IN2 flows through the transistor Q DE2 When the threshold voltage is equal to or higher than this, the transistor is turned on and outputs an emitter current.

[0061] That is, the larger the amplitude of the radio frequency signals IN1 and IN2 (the larger the power of the radio frequency signal RFin), the larger the output current of the detection circuit 22. Conversely, the smaller the amplitude of the radio frequency signals IN1 and IN2 (the smaller the power of the radio frequency signal RFin), the smaller the output current of the detection circuit 22.

[0062] On the other hand, as explained above, when the drive level of the carrier amplifier 13 is relatively high (close to saturation), the voltage BIAS2 becomes a relatively low voltage, and when the drive level of the carrier amplifier 13 is relatively low (when the amplification factor is reduced), the voltage BIAS2 becomes a relatively high voltage.

[0063] In other words, the higher the drive level of the carrier amplifier 13 is (closer to saturation), the greater the transistor Q DE11 The collector current I2 of the transistor Q1 becomes smaller. DE11 The collector current I2 becomes larger.

[0064] To summarize the above, capacitor C env The voltage of the capacitor C tends to become higher as the drive level of the carrier amplifier 13 becomes relatively higher (closer to saturation). env The voltage of the capacitor C is less likely to become high as the drive level of the carrier amplifier 13 becomes relatively low (the amplification factor is reduced). env The voltage of the capacitor C env The lower the power of the high frequency signal RFin, the less likely the voltage of becomes high.

[0065] 4 is a diagram showing an example of the relationship between the power of the high frequency signal in the power amplifier circuit of the first embodiment and the bias voltage applied to the peak amplifier. In FIG. 4, the horizontal axis represents the power of the high frequency signal RFin, and the vertical axis represents the bias voltage BIAS applied from the bias circuit 18 (19) to the peak amplifier 16 (17). 16 (BIAS 17 )

[0066] Waveform 51 shows the bias voltage BIAS when the drive level of the carrier amplifier 13 is relatively low. 16 (BIAS 17 ) when the drive level of the carrier amplifier 13 is relatively intermediate. 16 (BIAS 17 ) when the drive level of the carrier amplifier 13 is relatively high. 16 (BIAS 17 ) changes.

[0067] As shown in waveform 53, when the drive level of the carrier amplifier 13 is relatively high, the detection circuit 22 can start up the peak amplifiers 16 and 17 even if the power of the high frequency signal RFin is low. Conversely, as shown in waveform 51, when the drive level of the carrier amplifier 13 is relatively low, the detection circuit 22 can delay the start-up of the peak amplifiers 16 and 17 until the power of the high frequency signal RFin becomes high.

[0068] Therefore, when the drive level of the carrier amplifier 13 is relatively high (close to saturation), the current of the constant current circuit 41 should be reduced so that the peak amplifiers 16 and 17 can be started up even when the power of the high frequency signal RFin is low. Conversely, when the drive level of the carrier amplifier 13 is relatively low, it is not necessary to start up the peak amplifiers 16 and 17 until the power of the high frequency signal RFin becomes large, so the current of the constant current circuit 41 should be increased. In other words, if the voltage BIAS2 input to the constant current circuit 41 is set to a voltage that changes complementarily to the drive level of the carrier amplifier 13, the desired operation can be achieved for the entire circuit.

[0069] The response of the detector circuit 22 is fast for the following reasons.

[0070] First, the first emitter follower circuit 22a and the second emitter follower circuit 22b operate differentially. Therefore, the capacitor C env This allows the capacitance of the capacitor C env This reduces the delay in the detection circuit 22, which speeds up the change in the signal S2.

[0071] Second, the emitter follower circuit is a circuit that can output a large current. Therefore, each of the first emitter follower circuit 22a and the second emitter follower circuit 22b can output a large current. In other words, the detection circuit 22 can output a large output current I1. This allows the detection circuit 22 to output a large output current I1. envThat is, the rising response of the detection circuit 22 becomes faster.

[0072] Third, the transistor Q DE11 is a constant current (collector current I2) that flows through the capacitor C env Therefore, the transistor Q DE11 is the capacitor C env That is, the falling edge response of the detection circuit 22 becomes faster.

[0073] (One specific example of a bias circuit and a detection circuit) FIG. 5 is a diagram showing a specific example of a bias circuit that applies a bias to the final-stage carrier amplifier and a detection circuit in the power amplifier circuit of the first embodiment.

[0074] The bias circuit 15 that provides a bias to the final stage carrier amplifier 13 has a resistor R CBB and transistor Q CB1 , Q CB2 and Q CB3 and,

[0075] Resistance R CBB One end of the bias current BIAS C is input. Resistor R CBB The other end of the transistor is connected to the base and collector terminals of the transistor, and the circuit operates like a diode. CB1 and Q CB2 Transistor Q CB3 The base of the transistor Q CB2 is electrically connected to the base of transistor Q CB3 The collector of the transistor Q is electrically connected to the power supply potential Vcc. CB3 is the bias current BIAS 13 is output from the emitter to the carrier amplifier 13.

[0076] In this example, transistor Q CB3 The emitter voltage corresponds to the signal S1.

[0077] The low-pass filter 43 is connected to a resistor R LPF and capacitor C LPF and,

[0078] Resistance R LPF One end of the transistor Q CB3 It is electrically connected to the emitter of resistor R LPF The other end of the capacitor C LPF It is electrically connected to one end of the capacitor C LPF The other end is electrically connected to a reference potential.

[0079] The constant current circuit 41A has a transistor Q DE12 However, the present disclosure is not limited to this. This specific example may include a constant current circuit 41 instead of the constant current circuit 41A.

[0080] Resistance R LPF The other end of the capacitor C LPF One end of the transistor Q DE11 The low-pass filter 43 passes the signal S1 through a low pass filter, and the low-pass filter 43 passes the signal S1 through a low pass filter. DE11 Output to the base of.

[0081] In the circuit shown in FIG. 5, when the drive level of the carrier amplifier 13 is high, the output terminal voltage of the bias circuit 15 (transistor Q CB3 This utilizes the principle that the emitter voltage of the transistor Q (signal S1) drops. In other words, signal S1 is a signal that changes in a complementary manner to the drive level of the carrier amplifier 13. DE11 converts the signal S1 from a voltage to a current (collector current I2) and uses it as a current bias for the detection circuit 22. In this way, the detection circuit 22 detects the drive level of the carrier amplifier 13 using the signal S1 and controls the bias circuit 18 (19).

[0082] In the circuit shown in FIG. 5, the output terminal of the bias circuit 15 (transistor Q CB3A low-pass filter 43 is provided in the path from the emitter of the detector 22 to the detection circuit 22. In Patent Documents 1 to 3, inserting a low-pass filter into the circuit is not preferable because it reduces the response speed of the circuit.

[0083] On the other hand, in the circuit shown in FIG. 5, the high frequency signals IN1 and IN2 are input to the transistor Q DE1 and Q DE2 The response speed of the path from the base of the bias circuit 15 to the bias circuit 18 (19) is important. CB3 Since there is no problem with a slight delay (for example, about a few seconds) occurring in the path from the emitter of the detector 22, a low-pass filter 43 can be provided.

[0084] Therefore, high isolation can be achieved in the high frequency signal band in the path of bias circuit 15 → detector circuit 22 → bias circuit 19 → peak amplifier 17 → coupler 20 → carrier amplifier 13 → bias circuit 15. If the isolation in this path is insufficient, this path may act as a feedback path and cause oscillation. However, in the circuit shown in Figure 5, oscillation can be suppressed by providing low-pass filter 43.

[0085] In addition, when the peak bias circuit has three or more stages, the control circuit 21 may control at least the bias circuit 18 that provides a bias to the peak amplifier 16 in the first stage and the bias circuit 19 that provides a bias to the peak amplifier 17 in the final stage.

[0086] (First Modification) In the first embodiment, the amplifier 2 in the front stage of the Doherty amplifier circuit 10 is a single-ended amplifier, but the present disclosure is not limited to this. The amplifier in the front stage of the Doherty amplifier circuit 10 may be a differential amplifier.

[0087] FIG. 6 is a diagram showing a configuration of a power amplifier circuit according to a first modified example of the first embodiment.

[0088] The power amplifier circuit 1A includes a balun 61, an amplifier 2A, a bias circuit 3, and a Doherty amplifier circuit 10A. The Doherty amplifier circuit 10A includes 90° hybrid circuits 11A and 11B, a first-stage carrier amplifier 12A, a final-stage carrier amplifier 13A, bias circuits 14 and 15, a first-stage peak amplifier 16A, a final-stage peak amplifier 17A, bias circuits 18 and 19, a coupler 20A, and a control circuit 21.

[0089] Although the number of stages in the Doherty amplifier circuit 10A is two, the present disclosure is not limited to this. The number of stages in the Doherty amplifier circuit 10A may be one, or three or more.

[0090] The amplifier 2A, the carrier amplifiers 12A and 13A, and the peak amplifiers 16A and 17A are each a differential amplifier.

[0091] In the present disclosure, it is preferable that the difference in voltage amplitude between the output signal of one amplifier and the output signal of the other amplifier in the differential amplifier is within 3 dB and the phase difference is within the range of 90° to 270°.

[0092] The balun 61 outputs high frequency signals RF11 and RF12 that constitute a differential signal based on the input high frequency signal RFin.

[0093] The bias circuit 3 applies a bias to the amplifier 2A. A first amplifier 71 in the amplifier 2A amplifies the radio frequency signal RF11 to generate a radio frequency signal RF13, which is output to the 90° hybrid circuit 11A. A second amplifier 72 in the amplifier 2A amplifies the radio frequency signal RF12 to generate a radio frequency signal RF14, which is output to the 90° hybrid circuit 11B.

[0094] The 90° hybrid circuit 11A divides the high frequency signal RF13 into high frequency signals RF15 and RF16 that are out of phase with each other by approximately 90°, outputs the high frequency signal RF15 to the carrier amplifier 12A, and outputs the high frequency signal RF16 to the peak amplifier 16A.

[0095] The 90° hybrid circuit 11B divides the high frequency signal RF14 into high frequency signals RF17 and RF18 that are out of phase with each other by approximately 90°, outputs the high frequency signal RF17 to the carrier amplifier 12A, and outputs the high frequency signal RF18 to the peak amplifier 16A.

[0096] The bias circuit 14 applies a bias to the carrier amplifier 12A. A first amplifier 73 in the carrier amplifier 12A amplifies the high-frequency signal RF15 to generate a high-frequency signal RF19, and outputs the amplified high-frequency signal RF19 to the carrier amplifier 13A. A second amplifier 74 in the carrier amplifier 12A amplifies the high-frequency signal RF17 to generate a high-frequency signal RF20, and outputs the amplified high-frequency signal RF20 to the carrier amplifier 13A.

[0097] The bias circuit 15 applies a bias to the carrier amplifier 13A. A first amplifier 75 in the carrier amplifier 13A amplifies the high-frequency signal RF19 to generate a high-frequency signal RF21, and outputs the amplified signal to the coupler 20A. A second amplifier 76 in the carrier amplifier 13A amplifies the high-frequency signal RF20 to generate a high-frequency signal RF22, and outputs the amplified signal to the coupler 20A.

[0098] The bias circuit 18 applies a bias to the peak amplifier 16A. A first amplifier 77 in the peak amplifier 16A amplifies the high frequency signal RF16 to generate a high frequency signal RF23, and outputs the amplified high frequency signal RF16 to the peak amplifier 17A. A second amplifier 78 in the peak amplifier 16A amplifies the high frequency signal RF18 to generate a high frequency signal RF24, and outputs the amplified high frequency signal RF18 to the peak amplifier 17A.

[0099] The bias circuit 19 applies a bias to the peak amplifier 17A. A first amplifier 79 in the peak amplifier 17A amplifies the high frequency signal RF23 to generate a high frequency signal RF25, and outputs the amplified high frequency signal RF23 to the coupler 20A. A second amplifier 80 in the peak amplifier 17A amplifies the high frequency signal RF24 to generate a high frequency signal RF26, and outputs the amplified high frequency signal RF24 to the coupler 20A.

[0100] The combiner 20A combines the high frequency signals RF21, RF22, RF25 and RF26 and outputs the high frequency signal RFout.

[0101] The detection circuit 22 receives the high frequency signals RF11 and RF12 and a signal S1 that indicates the drive level of the carrier amplifier 13A.

[0102] In the first modification, the high frequency signals RF11 and RF12 correspond to the high frequency signals IN1 and IN2 (see FIG. 3).

[0103] Instead of the high frequency signals RF11 and RF12, high frequency signals RF13 and RF14 may be input to the detection circuit 22. The signal S1 may be output from the bias circuit 15 or from the carrier amplifier 13A.

[0104] The detection circuit 22 outputs a signal S2 to the bias circuits 18 and 19 based on the radio frequency signals RF11 and RF12 and the signal S1. The bias circuit 18 biases the peak amplifier 16A based on the signal S2. The bias circuit 19 biases the peak amplifier 17A based on the signal S2.

[0105] (Second Modification) FIG. 7 is a diagram showing a configuration of a power amplifier circuit according to a second modified example of the first embodiment.

[0106] Compared to the power amplifier circuit 1A of the first modification (see FIG. 6), the power amplifier circuit 1B includes a Doherty amplifier circuit 10B instead of the Doherty amplifier circuit 10A. The Doherty amplifier circuit 10B includes a 90° hybrid circuit 11C instead of the 90° hybrid circuits 11A and 11B.

[0107] Although the number of stages in the Doherty amplifier circuit 10B is two, the present disclosure is not limited to this. The number of stages in the Doherty amplifier circuit 10B may be one, or three or more.

[0108] The 90° hybrid circuit 11C is a differentially operating 90° hybrid circuit and includes windings L1, L2, L3, and L4, and cores 81 and 82.

[0109] The winding L1 is wound around the core 81. The winding L2 is wound around the core 81 in the opposite direction (reverse rotation) to the winding L1. The winding L3 is wound around the core 82 in the opposite direction (reverse rotation) to the winding L1. The winding L4 is wound around the core 82 in the same direction (same rotation) as the winding L1.

[0110] One end of the winding L1 is electrically connected to a first amplifier 71 in the amplifier 2A. The other end of the winding L1 is electrically connected to a first amplifier 73 in the carrier amplifier 12A. One end of the winding L2 is electrically connected to a reference potential. The other end of the winding L2 is electrically connected to a first amplifier 77 in the peak amplifier 16A.

[0111] One end of the winding L3 is electrically connected to a reference potential. The other end of the winding L3 is electrically connected to a second amplifier 78 in the peak amplifier 16A. One end of the winding L4 is electrically connected to a second amplifier 72 in the amplifier 2A. The other end of the winding L4 is electrically connected to a second amplifier 74 in the carrier amplifier 12A.

[0112] The operation of the power amplifier circuit 1B is similar to that of the power amplifier circuit 1A, and therefore a description thereof will be omitted.

[0113] <Second embodiment> Of the components of the power amplifier circuit of the second embodiment, the same components as those of the first embodiment are given the same reference numerals, and the description thereof will be omitted.

[0114] (Overall composition) FIG. 8 is a diagram illustrating a configuration of a power amplifier circuit according to the second embodiment.

[0115] Compared to the power amplifier circuit 1 (see FIG. 1) of the first embodiment, the power amplifier circuit 101 includes a Doherty amplifier circuit 10C instead of the Doherty amplifier circuit 10. Compared to the Doherty amplifier circuit 10, the Doherty amplifier circuit 10C includes a control circuit 21A instead of the control circuit 21. Compared to the control circuit 21 (see FIG. 1), the control circuit 21A further includes a variable attenuator 23.

[0116] Although the number of stages in the Doherty amplifier circuit 10C is two, the present disclosure is not limited to this. The number of stages in the Doherty amplifier circuit 10C may be one, or three or more.

[0117] The variable attenuator 23 receives the high frequency signal RFin and a signal S1 indicating the drive level of the carrier amplifier 13. The variable attenuator 23 may receive the high frequency signal RF1 instead of the high frequency signal RFin.

[0118] The variable attenuator 23 attenuates the high frequency signal RFin based on the signal S1 and outputs the attenuated high frequency signal RF31 to the detection circuit 22. The detection circuit 22 outputs a signal S2 to the bias circuits 18 and 19 based on the high frequency signal RF31.

[0119] In the first embodiment, the bias point of the detection circuit 22 is changed by the signal S1. On the other hand, in the second embodiment, the bias point of the detection circuit 22 is fixed. The attenuation amount of the variable attenuator 23 provided in the upstream stage of the detection circuit 22 is changed by the signal S1. This allows the control circuit 21A to output a signal S2 according to the drive level of the carrier amplifier 13.

[0120] (One example of a detection circuit and a variable attenuator) FIG. 9 is a diagram showing a specific example of a detection circuit and a variable attenuator in the power amplifier circuit according to the second embodiment.

[0121] Transistor Q DE11 The base of the transistor Q DE5 Therefore, in the second embodiment, the collector current I2 is fixed.

[0122] The variable attenuator 23 is a resistor R AT1 , R AT2 , R AT3 and R AT4 and transistor Q AT1, Q AT2 and Q AT3 and capacitor C AT1 and C AT2 and,

[0123] Resistance R AT2 One end of the resistor R is electrically connected to the power supply potential Vcc. AT2 The other end of the transistor Q AT3 That is, the collector and base of the transistor Q AT3 is diode-connected. Transistor Q AT3 The emitter of is electrically connected to node N2.

[0124] Transistor Q AT2 The collector and base of the transistor Q are electrically connected to the node N2. AT2 is diode-connected. Transistor Q AT2 The emitter of is electrically connected to node N1.

[0125] Resistance R AT1 One end of the resistor R is electrically connected to the node N1. AT1 The other end of the transistor Q AT1 is electrically connected to the collector of transistor Q AT1 The emitter of transistor Q is electrically connected to the reference potential. AT1 A signal S1 that has been low-pass filtered by a low-pass filter 43 is input to the base of this amplifier.

[0126] Resistance R AT3 A high frequency signal IN1 is input to one end of the resistor R AT3 The other end of the capacitor C is electrically connected to the node N1. AT1 One end of the capacitor C is electrically connected to the node N1. AT1 The other end of the transistor Q DE1 is electrically connected to the base of the

[0127] Resistance R AT4A high frequency signal IN2 is input to one end of the resistor R AT4 The other end of the capacitor C is electrically connected to the node N2. AT2 One end of the capacitor C is electrically connected to the node N2. AT2 The other end of the transistor Q DE2 is electrically connected to the base of the

[0128] The variable attenuator 23 is a transistor Q AT1 When the current flowing through the transistor Q AT1 This is an attenuator that uses the principle that the equivalent resistance of

[0129] When the drive level of the carrier amplifier 13 is relatively low, the control terminal of the variable attenuator 23, the transistor Q AT1 A relatively high voltage is input to the base of the transistor Q. AT1 The collector current of transistor Q AT2 and Q AT3 Therefore, a large current flows through the transistor Q AT1 , Q AT2 and Q AT3 The equivalent resistance value of the high frequency signals IN1 and IN2 decreases, and the nodes N1 and N2 through which the high frequency signals IN1 and IN2 are transmitted become close to short-circuited. Therefore, the variable attenuator 23 does not allow the high frequency signals IN1 and IN2 to pass.

[0130] On the other hand, when the drive level of the carrier amplifier 13 is relatively high, the transistor Q AT1 , Q AT2 and Q AT3 Therefore, the variable attenuator 23 passes the high frequency signals IN1 and IN2.

[0131] The detection circuit 22 is capable of outputting a signal S2 according to the drive level of the carrier amplifier 13 by providing a variable attenuator 23 in the preceding stage.

[0132] The variable attenuator 23 is essentially required to be capable of controlling the pass characteristics (attenuation characteristics) and to minimize delay in the input / output characteristics of the high frequency signals IN1 and IN2. Therefore, various variations of the variable attenuator 23, such as a variable gain amplifier, can be used.

[0133] By providing the variable attenuator 23 as in the second embodiment, the sensitivity of the output of the detection circuit 22 relative to the drive level of the carrier amplifier 13 can be freely designed, which obviously makes the design easier.

[0134] In addition to the same stabilization effect as in the first embodiment, the second embodiment also provides the effect of making stabilization easier, for the following reasons.

[0135] In the configuration of the first embodiment (see FIG. 5), the point where the carrier amplifier 13 is biased (transistor Q CB3 The emitter of the transistor Q DE10 The path from the transistor Q to the emitter of the transistor Q includes the low-pass filter 43, but is directly connected in terms of DC. In other words, the path is directly connected in the DC range (DC and low frequency range). DE11 is connected for emitter ground amplification, and transistor Q DE10 Since this is a collector grounded amplification connection, there is a possibility that amplification will occur in the above path. If amplification occurs in the above path, there is a possibility that oscillation will occur in the worst case.

[0136] On the other hand, in the configuration of the second embodiment (see FIG. 9), the portion that biases the carrier amplifier 13 (transistor Q CB3 The emitter of the transistor Q DE10 The path to the emitter of the AT1 and C AT2This provides isolation between the carrier amplifier 13 and the peak amplifier 16 (17) near DC (in the DC and low frequency range), which has the effect of suppressing oscillation in the above-mentioned path.

[0137] (Variation) In the second embodiment, each amplifier may be a differential amplifier, similar to the first modified example (see FIG. 6) and the second modified example (see FIG. 7) of the first embodiment.

[0138] <Third embodiment> Of the components of the power amplifier circuit of the third embodiment, the same components as those in the other embodiments are given the same reference numerals, and the description thereof will be omitted.

[0139] FIG. 10 is a diagram illustrating a configuration of a power amplifier circuit according to the third embodiment.

[0140] The power amplifier circuit 111 (Doherty amplifier circuit 10D) includes a 90° hybrid circuit 11, baluns 121, 122, 127, and 128, a first-stage carrier amplifier 12A, a middle-stage carrier amplifier 123, a final-stage carrier amplifier 13A, bias circuits 14, 15, and 124, a first-stage peak amplifier 16A, a middle-stage peak amplifier 125, a final-stage peak amplifier 17A, bias circuits 18, 19, and 126, a coupler 20A, and a control circuit 21B.

[0141] Although the number of stages in the Doherty amplifier circuit 10D is three, the present disclosure is not limited to this. The number of stages in the Doherty amplifier circuit 10D may be two or less, or four or more.

[0142] Each of the carrier amplifiers 12A, 13A, and 123 and the peak amplifiers 16A, 17A, and 125 is a differential amplifier.

[0143] The 90° hybrid circuit 11 divides the radio frequency signal RFin into radio frequency signals RF41 and RF42 that are out of phase with each other by approximately 90°, and outputs the radio frequency signal RF41 to one end of a primary winding of a balun 121, and outputs the radio frequency signal RF42 to one end of a primary winding of a balun 122. The other end of the primary winding of the balun 121 and the other end of the primary winding of the balun 122 are electrically connected to a reference potential.

[0144] Based on the input high frequency signal RF41, the balun 121 outputs high frequency signals RF43 and RF44 that constitute a differential signal from both ends of the secondary winding.

[0145] Based on the input high frequency signal RF42, the balun 122 outputs high frequency signals RF45 and RF46 that constitute a differential signal from both ends of the secondary winding.

[0146] A first amplifier 73 in the carrier amplifier 12A amplifies the high frequency signal RF43 to generate a high frequency signal RF47, and outputs the amplified high frequency signal RF47 to the carrier amplifier 123. A second amplifier 74 in the carrier amplifier 12A amplifies the high frequency signal RF44 to generate a high frequency signal RF48, and outputs the amplified high frequency signal RF44 to the carrier amplifier 123.

[0147] Bias circuit 124 applies a bias to carrier amplifier 123. First amplifier 131 in carrier amplifier 123 amplifies high frequency signal RF47 to generate high frequency signal RF49, which is output to one end of the primary winding of balun 127. Second amplifier 132 in carrier amplifier 123 amplifies high frequency signal RF48 to generate high frequency signal RF50, which is output to the other end of the primary winding of balun 127.

[0148] The balun 127 outputs high frequency signals RF51 and RF52, which constitute a differential signal, from both ends of the secondary winding, based on the input high frequency signals RF49 and RF50.

[0149] A first amplifier 75 in the carrier amplifier 13A amplifies the high-frequency signal RF51 to generate a high-frequency signal RF53, which is output to one end of the first winding L5 of the coupler 20A. A second amplifier 76 in the carrier amplifier 13A amplifies the high-frequency signal RF52 to generate a high-frequency signal RF54, which is output to the other end of the first winding L5 of the coupler 20A.

[0150] A first amplifier 77 in the peak amplifier 16A amplifies the high frequency signal RF45 to generate a high frequency signal RF55, and outputs the amplified signal to the peak amplifier 125. A second amplifier 78 in the peak amplifier 16A amplifies the high frequency signal RF46 to generate a high frequency signal RF56, and outputs the amplified signal to the peak amplifier 125.

[0151] The bias circuit 126 applies a bias to the peak amplifier 125. A first amplifier 133 in the peak amplifier 125 amplifies the high frequency signal RF55 to generate a high frequency signal RF57, and outputs the amplified high frequency signal RF57 to one end of the primary winding of the balun 128. A second amplifier 134 in the peak amplifier 125 amplifies the high frequency signal RF56 to generate a high frequency signal RF58, and outputs the amplified high frequency signal RF56 to the other end of the primary winding of the balun 128.

[0152] The balun 128 outputs high frequency signals RF59 and RF60, which constitute a pair of differential signals, from both ends of the secondary winding, based on the input high frequency signals RF57 and RF58.

[0153] A first amplifier 79 in the peak amplifier 17A amplifies the high frequency signal RF59 to generate a high frequency signal RF61, which is output to one end of the third winding L7 of the coupler 20A. A second amplifier 80 in the peak amplifier 17A amplifies the high frequency signal RF60 to generate a high frequency signal RF62, which is output to the other end of the third winding L7 of the coupler 20A.

[0154] The first winding L5 in the coupler 20A is wound around the core 141. The second winding L6 in the coupler 20A is wound around the core 141 in the same direction (same winding) as the first winding L5. The third winding L7 in the coupler 20A is wound around the core 142 in the same direction (same winding) as the first winding L5. The fourth winding L8 in the coupler 20A is wound around the core 142 in the same direction (same winding) as the third winding L7. One end of the second winding L6 and one end of the fourth winding L8 are electrically connected. The other end of the fourth winding L8 is electrically connected to the reference potential. A high-frequency signal RFout is output from the other end of the second winding L6 via a capacitor 143.

[0155] The control circuit 21B further includes an attenuator 24 in comparison with the control circuit 21A (see FIG. 8).

[0156] High frequency signals RF45 and RF46 constituting a differential signal are input to the attenuator 24. Instead of the high frequency signals RF45 and RF46, high frequency signals RF43 and RF44 may be input to the attenuator 24. The attenuator 24 outputs high frequency signals RF63 and RF64, which are obtained by attenuating the high frequency signals RF45 and RF46, respectively, to the variable attenuator 23. It is preferable that the amount of attenuation of the attenuator 24 be adjustable by an external control signal S3.

[0157] The variable attenuator 23 receives the high frequency signals RF63 and RF64 and a signal S1 that indicates the drive level of the carrier amplifier 13A.

[0158] The control circuit 21B controls not only the bias circuit 19 that applies a bias to the peak amplifier 17A in the final stage, but also the bias circuit 18 that applies a bias to the peak amplifier 16A in the first stage.

[0159] The following describes the changes made to the power amplifier circuit 101 (see FIG. 8) of the second embodiment and the power amplifier circuit 111 (see FIG. 10) of the third embodiment, and the effects resulting from the changes.

[0160] First, when the peak amplifiers 16 and 17 are single-ended amplifiers, as in the power amplifier circuit 101 of the second embodiment, the high-frequency signal not only fluctuates the peak amplifiers 16 and 17 but also partially flows through the transistors Q DE10 (See Figure 9) vibrates the emitter of transistor Q. DE10 However, there is a possibility that detection will be performed, resulting in unintended operation.

[0161] On the other hand, in the power amplifier circuit 111 of the third embodiment, all stages of the carrier amplifier and peak amplifier are differential amplifiers, thereby reducing the possibility that high-frequency signals will flow into the bias circuit side from the bias voltage input terminals of the peak amplifiers 16A, 125, and 17A.

[0162] Secondly, as described above, in the power amplifier circuit 111 of the third embodiment, the peak amplifiers 16A, 125, and 17A are each a differential amplifier, so that the transistor Q DE10 However, even if each of the peak amplifiers 16A, 125, and 17A is a differential amplifier, it is rare that the differential amplifiers can operate in strictly opposite phase due to individual differences caused by processes. Therefore, high-frequency signals can still flow into the bias circuit side from the bias voltage input terminals of each of the peak amplifiers 16A, 125, and 17A.

[0163] Therefore, in the power amplifier circuit 111 of the third embodiment, the control circuit 21B controls not only the bias circuit 19 that biases the peak amplifier 17A in the final stage, but also the bias circuit 18 that biases the peak amplifier 16A in the first stage. As a result, the power amplifier circuit 111 of the third embodiment can suppress the high-frequency signal flowing from the peak amplifier 16A to the bias circuit 18 side, and therefore the transistor Q DE10 This can further reduce the possibility that the detection operation will occur.

[0164] Third, consider the case where the overall gain of all stages of the carrier amplifier increases due to a drop in the ambient temperature. In general, in this case, the gain is large, so even if the input power is small, the final stage carrier amplifier 13A may become saturated.

[0165] In the power amplifier circuit 1 of the first embodiment (see FIG. 1) and the power amplifier circuit 101 of the second embodiment (see FIG. 8), the drive level of the carrier amplifier 13 (13A) is detected to control the bias of the peak amplifier 16 (17). Therefore, even in a low-temperature state, a mechanism for starting up the peak amplifier 16 (17) with a small input power works, so the carrier amplifier 13 (13A) is unlikely to saturate on its own. However, if a low-temperature state is compounded by load fluctuations, the control range of a single variable attenuator 23 may not be able to cope with the situation.

[0166] Therefore, the power amplifier circuit 111 of the third embodiment includes an attenuator 24 whose attenuation can be adjusted by an external control signal S3. The attenuation of the attenuator 24 is preferably adjusted when it is known that the input power that starts up the peak amplifier 16A (17A) has changed due to a change in the environment or situation. In the power amplifier circuit 111 of the third embodiment, it is preferable to externally adjust the attenuation of the attenuator 24 based on information on the ambient temperature, external load status, and input signal properties (center frequency, average power, PAPR (Peak to Average Power Ratio), etc.) and historical information about these.

[0167] As a result, the power amplifier circuit 111 of the third embodiment can reduce the possibility that the carrier amplifier 13A will be saturated even if the environment or situation changes.

[0168] In the third embodiment, the control circuit 21B controls the bias circuits 18 and 19, but the present disclosure is not limited to this. The control circuit 21B may also control the bias circuit 126. The control circuit 21B may control at least the bias circuit 18 that applies a bias to the peak amplifier 16A in the first stage and the bias circuit 19 that applies a bias to the peak amplifier 17A in the last stage.

[0169] <Fourth embodiment> Of the components of the power amplifier circuit of the fourth embodiment, the same components as those of the other embodiments are given the same reference numerals, and the description thereof will be omitted.

[0170] In the first and second embodiments, the signal S1 representing the drive level of the carrier amplifier 13 is processed by the detection circuit 22 or a stage prior to the detection circuit 22 and reflected in the signal S2, but the present disclosure is not limited to this. The signal S1 representing the drive level of the carrier amplifier 13 may be added to the signal output from the detection circuit 22.

[0171] (Overall composition) FIG. 11 is a diagram illustrating a configuration of a power amplifier circuit according to the fourth embodiment.

[0172] Compared to the power amplifier circuit 1 (see FIG. 1) of the first embodiment, the power amplifier circuit 151 includes a Doherty amplifier circuit 10E instead of the Doherty amplifier circuit 10. Compared to the Doherty amplifier circuit 10, the Doherty amplifier circuit 10E includes a control circuit 21C instead of the control circuit 21. Compared to the control circuit 21 (see FIG. 1), the control circuit 21C further includes an adder circuit 25.

[0173] The addition circuit 25 corresponds to an example of a "bias control circuit" of the present disclosure.

[0174] Although the number of stages in the Doherty amplifier circuit 10E is two, the present disclosure is not limited to this. The number of stages in the Doherty amplifier circuit 10E may be one, or three or more.

[0175] The high frequency signal RFin is input to the detection circuit 22. The high frequency signal RF1 may be input to the detection circuit 22 instead of the high frequency signal RFin.

[0176] The detection circuit 22 outputs a signal S4 to the adder circuit 25 based on the high frequency signal RFin.

[0177] A signal S1 indicating the drive level of the carrier amplifier 13 is input to the adder circuit 25. The signal S1 may be output from the bias circuit 15 or may be output from the carrier amplifier 13.

[0178] The adder circuit 25 outputs the signal S2 obtained by adding the signal S1 and the signal S4 to the bias circuits 18 and 19.

[0179] (One specific example of a detection circuit and an addition circuit) FIG. 12 is a diagram showing a specific example of a detection circuit and an adder circuit in the power amplifier circuit according to the fourth embodiment.

[0180] The adder circuit 25 includes a resistor R OP and transistor Q OP and,

[0181] Resistance R OP One end of the transistor Q DE10 It is electrically connected to the emitter of resistor R OP The other end of the transistor Q OP is electrically connected to the collector of transistor Q OP The base of the resistor R LPF The other end of the capacitor C LPF One end of the transistor Q is electrically connected to OP The emitter of the resistor R is electrically connected to the reference potential. OP and the other end of transistor Q OP The bias voltage BIAS 16 (BIAS 17 ) is output.

[0182] As explained in the other embodiments, the signal S1 is a signal (inverted signal) that changes complementarily to the drive level of the carrier amplifier 13. Therefore, the adder circuit 25 subtracts the signal S1 from the signal S2 (adds the signal −S1) to obtain the bias voltage BIAS 16 (BIAS 17 ) is output.

[0183] Transistor Q OP converts the signal S1 input to the base into a collector current. 16 (BIAS 17 ) is generated from the output voltage of the bias circuit 18 (19) by the transistor Q OP Collector current value and resistance R OP This is the voltage obtained by subtracting the voltage drop expressed as the product of the resistance value of

[0184] (Variation) In the fourth embodiment, each amplifier may be a differential amplifier, similar to the first modified example (see FIG. 6) and the second modified example (see FIG. 7) of the first embodiment.

[0185] <Fifth embodiment> Of the components of the power amplifier circuit of the fifth embodiment, the same components as those of the other embodiments are given the same reference numerals and descriptions thereof will be omitted.

[0186] (Overall composition) FIG. 13 is a diagram illustrating a configuration of a power amplifier circuit according to the fifth embodiment.

[0187] Compared to the power amplifier circuit 1 (see FIG. 1) of the first embodiment, the power amplifier circuit 161 includes a Doherty amplifier circuit 10F instead of the Doherty amplifier circuit 10. Compared to the Doherty amplifier circuit 10, the Doherty amplifier circuit 10F includes a control circuit 21D instead of the control circuit 21. Compared to the control circuit 21 (see FIG. 1), the control circuit 21D further includes a drive level detection circuit 26.

[0188] Although the number of stages in the Doherty amplifier circuit 10F is two, the present disclosure is not limited to this. The number of stages in the Doherty amplifier circuit 10F may be one, or three or more.

[0189] The drive level detection circuit 26 outputs a signal S1 representing the drive level of the carrier amplifier 13 to the detection circuit 22 based on the high frequency signal RF4 output by the carrier amplifier 13.

[0190] The high frequency signal RFin and the signal S1 are input to the detection circuit 22. The detection circuit 22 may also receive the high frequency signal RF1 instead of the high frequency signal RFin.

[0191] The detection circuit 22 outputs a signal S2 that controls the bias circuits 18 and 19 to the bias circuits 18 and 19 based on the radio frequency signal RFin and the signal S1. The bias circuit 18 applies a bias to the peak amplifier 16 based on the signal S2. The bias circuit 19 applies a bias to the peak amplifier 17 based on the signal S2.

[0192] (One specific example of a detection circuit and a drive level detection circuit) FIG. 14 is a diagram showing a specific example of a detection circuit and a drive level detection circuit in the power amplifier circuit according to the fifth embodiment.

[0193] The drive level detection circuit 26 includes a resistor R MO1 , R MO2 , R MO3 , R MO4 and R MO5 and transistor Q MO1 , Q MO2 , Q MO4 , Q MO5 , Q MO6 and Q MO7 and capacitor C MO1 and,

[0194] In this specific example, the carrier amplifier 13 (see FIG. 13) is a differential amplifier that outputs high frequency signals RF71 and RF72 that constitute a pair of differential signals.

[0195] Transistor Q MO1 A high frequency signal RF71 is input to the emitter of the transistor Q. MO1 The emitter of the carrier amplifier 13 is electrically connected to the output terminal (collector or drain of the output transistor) of one of the amplifiers in the carrier amplifier 13, for example.

[0196] Transistor Q MO2 A high frequency signal RF72 is input to the emitter of the transistor Q. MO2 The emitter of the second amplifier is electrically connected to the output terminal (collector or drain of the output transistor) of the other amplifier in the carrier amplifier 13, for example.

[0197] Transistor Q MO1 The base of the transistor Q MO2 The base of is electrically connected to node N3.

[0198] Transistor Q MO1 collector and transistor Q MO2 The collector of is electrically connected to node N4.

[0199] Resistance R MO1 , R MO2 and R MO3 , and transistor Q MO4 applies a voltage to node N3. That is, resistor R MO1 , R MO2 and R MO3 , and transistor Q MO4 is the transistor Q MO1 The base of the transistor Q MO2 Gives a bias to the base.

[0200] Resistance R MO3 One end of the resistor R is electrically connected to the power supply potential Vcc. MO3 The other end of the MO4 collector and resistor R MO1 One end of the resistor R is electrically connected toMO1 The other end of the transistor Q MO4 The base and resistor R MO2 One end of the transistor Q is electrically connected to MO4 emitter and resistor R MO2 The other end of the resistor R is electrically connected to the reference potential. MO1 and R MO2、 and transistor Q MO4 generates a constant voltage, which becomes the voltage at node N3.

[0201] Resistance R MO4 and R MO5 , and transistor Q MO6 and Q MO7 applies a voltage to node N4. That is, resistor R MO4 and R MO5 , and transistor Q MO6 and Q MO7 is the transistor Q MO1 collector and transistor Q MO2 A bias is applied to the collector of the

[0202] Resistance R MO5 One end of the resistor R is electrically connected to the power supply potential Vcc. MO5 The other end of the transistor Q MO6 The collector and base of the transistor Q are electrically connected to each other. MO6 is diode-connected. Transistor Q MO6 The emitter of the transistor Q MO7 The collector and base of the transistor Q are electrically connected to each other. MO7 is diode-connected. Transistor Q MO7 The emitter of the resistor R is electrically connected to the reference potential. MO4 One end of the resistor R MO5 The other end of the transistor Q MO6 The collector and base of the transistor are electrically connected to the resistor R MO4 The other end of the transistor Q is electrically connected to the node N4. MO6 and Q MO7generates a constant voltage. This voltage is applied across the resistor R MO4 This voltage becomes the voltage of node N4 via

[0203] Transistor Q MO5 The collector and base of the transistor Q are electrically connected to the node N4. MO5 is diode-connected. Transistor Q MO5 The emitter of the capacitor C MO1 One end of the capacitor C is electrically connected to MO1 The other end is electrically connected to a reference potential.

[0204] Transistor Q MO5 outputs the signal S1 from the emitter. MO1 shunts and smooths the high frequency components of the signal S1.

[0205] Resistance R MO1 , R MO2 and R MO3 , and transistor Q MO4 It is sufficient for the resistor R to output a roughly constant voltage, and it can be thought of as a constant voltage source. MO5 , and transistor Q MO6 and Q MO7 The transistor Q can be thought of as a constant voltage source, as it only needs to output a roughly constant voltage. MO5 It is sufficient that a roughly constant voltage drop occurs, and it can be thought of as being replaced by a constant voltage source.

[0206] FIG. 15 is a diagram showing an equivalent circuit of a specific example of the detection circuit and the drive level detection circuit of the power amplifier circuit according to the fifth embodiment.

[0207] The constant voltage source V in Figure 15 MO1 is the resistance R in Figure 14 MO1 , R MO2 and R MO3 , and transistor Q MO4 This corresponds to the constant voltage source V in Figure 15. MO2 is the resistance R in Figure 14 MO5, and transistor Q MO6 and Q MO7 This corresponds to the constant voltage source V in Figure 15. MO3 is the transistor Q in Figure 14. MO5 is equivalent to

[0208] (Drive level detection circuit operation) The operation of the drive level detection circuit 26 will be described with reference to the equivalent circuit of FIG.

[0209] Generally, the output terminal voltage of the final-stage carrier amplifier oscillates with the voltage amplitude of the high-frequency signal, centered around the bias voltage. When the final-stage carrier amplifier saturates, a situation occurs in which the voltage amplitude of the high-frequency signal increases and becomes almost equal to the bias voltage. In this situation, there is a moment in the oscillation cycle of the high-frequency signal when the output terminal voltage approaches 0V. This is the moment when no amplification effect is obtained, leading to the phenomenon of amplifier saturation.

[0210] The circuit of this specific example detects the drive level of the carrier amplifier 13 by utilizing this principle of saturation.

[0211] Specifically, within the period of the high frequency signals RF71 and RF72, the voltages of the high frequency signals RF71 and RF72 are MO1 From the voltage of transistor Q MO1 and Q MO2 The voltage drop of transistor Q MO1 and Q MO2 is turned on.

[0212] When the carrier amplifier 13 is operating with a sufficient margin against saturation, the transistor Q MO1 and Q MO2 Since there is no period when the transistor is in the on state, no collector current flows. MO4 Since no current flows, there is no voltage drop. Therefore, the signal S1 is MO2 from the voltage of the constant voltage source V MO3 The voltage is the voltage obtained by subtracting the voltage of

[0213] On the other hand, when the amplitude of the high frequency signals RF71 and RF72 increases, the transistor Q MO1 and Q MO2 Since there is a period when the transistor is in the on state, collector current flows. MO4 Since current flows, a voltage drop occurs.

[0214] When the amplitude of the high frequency signals RF71 and RF72 becomes larger, the transistor Q MO1 and Q MO2 The on-state period is longer, so more collector current flows. MO4 will carry more current and therefore will have a larger voltage drop.

[0215] Therefore, as the drive level of the carrier amplifier 13 increases, the signal S1 changes from the voltage at the time when the high frequency signals RF71 and RF72 are small to the voltage at the time when the high frequency signals RF71 and RF72 are small. MO4 The voltage S1 is reduced by the amount of the voltage drop at the input terminal. This signal S1 can be regarded as a signal (inverted signal) that changes complementarily to the drive level of the carrier amplifier 13. Therefore, the circuit configurations of the bias of the detection circuit 22, the variable attenuator 23, and the adder circuit 25 described in the first to fourth embodiments can be used as they are.

[0216] (Variation) In the fifth embodiment, each amplifier may be a differential amplifier, similar to the first modified example (see FIG. 6) and the second modified example (see FIG. 7) of the first embodiment.

[0217] In the fifth embodiment, similarly to the second embodiment, a variable attenuator 23 may be provided in front of the detection circuit 22, and the drive level detection circuit 26 may output the signal S1 to the variable attenuator 23.

[0218] In the fifth embodiment, as in the third embodiment, an attenuator 24 may be provided in front of the variable attenuator 23.

[0219] In the fifth embodiment, as in the fourth embodiment, an adder circuit 25 may be provided in the subsequent stage of the detection circuit 22, and the adder circuit 25 may add the signal S4 output by the detection circuit 22 and the signal S1 output by the drive level detection circuit 26.

[0220] The above-described embodiments are intended to facilitate understanding of the present invention and are not intended to limit the present invention. The present invention may be modified or improved without departing from the spirit and scope of the present invention, and equivalents thereof are also included in the present invention. [Explanation of symbols]

[0221] 1, 1A, 1B, 101, 111, 151, 161 Power amplifier circuit 2, 2A amplifier 3, 14, 15, 18, 19, 124, 126 Bias circuit 10, 10A, 10B, 10C, 10D, 10E, 10F Doherty amplifier circuit 11, 11A, 11B, 11C 90° hybrid circuit 12, 12A, 13, 13A, 123 Carrier Amplifier 16, 16A, 17, 17A, 125 Peak Amplifier 20, 20A combiner 21, 21A, 21B, 21C, 21D control circuit 22 Detector circuit 23 Variable attenuator 24 Attenuator 25 Addition circuit 26 Drive level detection circuit 41, 41A constant current circuit 42, 43 Low-pass filter 61, 121, 122, 127, 128 Balun

Claims

1. a carrier amplifier that amplifies an input high-frequency signal; a peak amplifier that amplifies an input high-frequency signal; a first bias circuit that applies a bias to the carrier amplifier; a second bias circuit that biases the peak amplifier; a control circuit that controls the second bias circuit based on an input high-frequency signal and a signal that indicates a drive level of the carrier amplifier; Including, the input high-frequency signal is a differential signal, The control circuit a variable attenuator that attenuates the differential signal by an amount of attenuation corresponding to a signal that indicates a drive level of the carrier amplifier; a detection circuit to which the differential signal attenuated by the variable attenuator is input and which outputs a signal for controlling the second bias circuit; Including, Doherty amplifier circuit.

2. 2. The Doherty amplifier circuit of claim 1, The control circuit a detection circuit including: a first emitter follower or source follower circuit, one of the differential signals attenuated by the variable attenuator being input to a base; and a second emitter follower or source follower circuit, the other of the differential signals attenuated by the variable attenuator being input to a base, wherein a connection point between an output terminal of the first emitter follower or source follower circuit and an output terminal of the second emitter follower or source follower circuit serves as an output terminal; a constant current circuit electrically connected to an output terminal of the detection circuit and causing a constant current to flow; a capacitor having one end electrically connected to the output terminal of the detection circuit; further comprising controlling the second bias circuit so as to output a bias current according to the voltage of the capacitor; Doherty amplifier circuit.

3. 3. The Doherty amplifier circuit according to claim 2, The control circuit an attenuator that is provided in front of the variable attenuator and attenuates the differential signal by an amount of attenuation corresponding to an input control signal and outputs the attenuated signal to the variable attenuator; Further comprising: Doherty amplifier circuit.

4. a carrier amplifier that amplifies an input high-frequency signal; a peak amplifier that amplifies an input high-frequency signal; a first bias circuit that applies a bias to the carrier amplifier; a second bias circuit that biases the peak amplifier; a control circuit that controls the second bias circuit based on an input high-frequency signal and a signal that indicates a drive level of the carrier amplifier; Including, the high-frequency signal input to the control circuit is a differential signal, The control circuit a detection circuit including a first emitter follower or source follower circuit, one of the differential signals being input to a base or a gate thereof, and a second emitter follower or source follower circuit, the other of the differential signals being input to a base or a gate thereof, wherein a connection point between an output terminal of the first emitter follower or source follower circuit and an output terminal of the second emitter follower or source follower circuit serves as an output terminal; a constant current circuit electrically connected to an output terminal of the detection circuit, for supplying a current corresponding to a signal representing a drive level of the carrier amplifier; a capacitor having one end electrically connected to the output terminal of the detection circuit; Including, controlling the second bias circuit so as to output a bias current according to the voltage of the capacitor; Doherty amplifier circuit.

5. 5. A Doherty amplifier circuit according to claim 1, a signal representing a drive level of the carrier amplifier is output from the first bias circuit; Doherty amplifier circuit.

6. 5. A Doherty amplifier circuit according to claim 1, The control circuit a drive level detection circuit that outputs a signal representing the drive level of the carrier amplifier based on the high frequency signal output by the carrier amplifier; Further comprising: Doherty amplifier circuit.

7. 5. A Doherty amplifier circuit according to claim 1, the carrier amplifier and the peak amplifier are differential amplifiers; Doherty amplifier circuit.

8. 5. A Doherty amplifier circuit according to claim 1, Multiple peak amplifiers connected in multiple stages; a plurality of second bias circuits that respectively apply biases to the plurality of peak amplifiers; Including, The control circuit controlling at least one second bias circuit among the plurality of second bias circuits that applies a bias to a peak amplifier in a first stage among the plurality of peak amplifiers, and another second bias circuit that applies a bias to a peak amplifier in a final stage among the plurality of peak amplifiers; Doherty amplifier circuit.

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