Method for fabricating nanostructured devices

Abstract

This method for fabricating a nanostructure device (1) comprises: a step for forming a second insulating film (15) on an upper surface of a semiconductor nanostructure substrate, the semiconductor nanostructure substrate comprising a basal layer (111_1), a fine feature portion (11_2), and a first electrode (12) in order on an upper surface of a first substrate (10); a step for bonding the upper surface of the semiconductor nanostructure substrate to an upper surface of a second substrate (16) with a metal film (17) therebetween; a step for removing part of the first substrate (10) and the basal layer (111_1) from a back surface of the first substrate (10); a step for forming a second electrode (18) and a third insulating film (19) successively on the back surface of the basal layer (111_1) so as to be substantially aligned with the position of the fine feature portion (11_2); a step for performing second dry etching on the basal layer (111_1) using the third insulating film (19) as a mask; a step for performing annealing; and a step for removing the second and third insulating films (15, 19).　Thus, the method for manufacturing a nanostructure device according to the present invention can provide a low-damage nanostructure device in which an ohmic electrode is formed.

Description

[Technical Field]

[0001] The present invention relates to a method for fabricating nanostructure devices for use in photonic crystal optical devices. [Background technology]

[0002] In recent years, research and development of photonic crystal optical devices that operate in the optical communication wavelength band has progressed. In particular, a nanowire-photonic crystal laser, in which a nanowire is arranged in the optical waveguide portion of a photonic crystal, has been disclosed (Patent Document 1), which was realized using a Si photonic crystal processed on an SOI substrate and an InAsP-based nanowire, which is a III-V compound.

[0003] Nanowire-photonic crystal lasers use Si photonic crystals, which are fabricated using advanced and mature Si processing technology, making it possible to precisely fabricate elements with high Q values. This holds promise for the realization of optical circuits that integrate ultra-low threshold lasers, highly sensitive photodetectors, high-speed modulation elements, etc.

[0004] There are two methods for fabricating nanowires that have device structures such as lasers and photodiodes: bottom-up and top-down methods.

[0005] The former method mainly involves selective crystal growth from holes in SiO2 or other materials formed on a substrate, or by the VLS (Vapor-Liquid-Solid) method, which uses fine particles of gold or other materials to grow crystals through a catalytic reaction. While this method makes it possible to create nanowires with a relatively large aspect ratio through crystal growth alone, it is difficult to accurately control the film thickness and doping concentration during growth.

[0006] The latter is a technique in which the multilayer film constituting the device is previously grown on an epitaxial substrate, which is patterned with resist or other materials, and then etched to create the structure. This technique uses an epitaxial substrate grown with controlled film thickness and doping concentration, allowing for the accurate fabrication of the device's film configuration. However, devices fabricated by dry etching are subject to damage from defects and impurities introduced during etching, resulting in current leakage and optical loss at the surface, resulting in inferior device performance compared to those fabricated using the bottom-up method.

[0007] Furthermore, when various optical elements are arranged on a photonic crystal, electricity must be supplied to drive each light-emitting element, light-receiving element, and optical switch. Here, when forming electrodes after arranging the nanowire device on the photonic crystal, it is necessary to heat the device to a temperature of 300°C or higher to form ohmic contacts. [Prior art documents] [Patent documents]

[0008] [Patent Document 1] Patent No. 6863909 Summary of the Invention [Problem to be solved by the invention]

[0009] However, the high temperature heating required for forming the ohmic contacts can cause damage to other elements in the circuit due to distortion, etc. Therefore, it is desirable to place individual nanowire devices on the photonic crystal with the ohmic contacts already formed.

[0010] Furthermore, nanowire devices require efficient element structures using pn doping and heterostructures, so it is necessary to fabricate elements with minimal damage using a top-down approach. [Means for solving the problem]

[0011] In order to solve the above-mentioned problems, the method for producing a nanostructure device according to the present invention includes the steps of: forming a second insulating film on the surface of the semiconductor nanostructure substrate that has the fine pattern, the surface of the semiconductor nanostructure substrate that has the second insulating film formed thereon, and bonding the surface of the semiconductor nanostructure substrate on which the second insulating film has been formed to the surface of a second substrate via a metal film; and removing a portion of the first substrate from the other surface of the first substrate. After that, the method includes a step of performing a first dry etching on other parts of the first substrate and part of the base layer, a step of forming a second electrode and a third insulating film, in that order, on the surface of the base layer on which the first dry etching has been performed so that they are positioned approximately in line with the position of the fine shape portion, a step of performing a second dry etching on the base layer using the third insulating film as a mask, a step of converting the first electrode and the second electrode into ohmic electrodes by annealing, and a step of removing the second insulating film and the third insulating film.

[0012] A method for producing a nanostructure device according to the present invention includes the steps of: forming a second insulating film on the surface of the semiconductor nanostructure substrate having a base layer and a microstructure portion, the microstructure portion being columnar, the surface having the microstructure portion; forming a first photoresist pattern having a first opening on the second insulating film; using the first photoresist pattern as a mask, performing third dry etching on the second insulating film and the base layer to a predetermined depth; performing first wet etching on the second insulating film through the first opening, followed by second wet etching, to process the microstructure portion into a semiconductor nanowire; and etching the first photoresist pattern. The method includes the steps of: removing the photoresist pattern, then removing the second insulating film, and placing the semiconductor nanowire in a groove formed in the base layer by transferring the first opening; forming a third insulating film to cover the semiconductor nanowire and the surface of the base layer; forming a second photoresist pattern having a second opening on the third insulating film; forming a second electrode at the other end of the semiconductor nanowire using the second photoresist pattern; converting the first electrode and the second electrode into ohmic electrodes by annealing; and removing the third insulating film, wherein the first opening is formed to surround at least one side of the fine shape portion, and the second opening is formed to be positioned in line with the other end of the semiconductor nanowire. [Effects of the Invention]

[0013] According to the present invention, a nanostructure device having an ohmic electrode formed thereon can be easily fabricated with reduced damage. [Brief explanation of the drawings]

[0014] [Figure 1A] FIG. 1A is a schematic diagram showing a nanostructure device according to a first embodiment of the present invention. [Figure 1B]FIG. 1B is a schematic diagram showing an example of a nanostructure device according to the first embodiment of the present invention. [Figure 2A] FIG. 2A is a diagram illustrating a method for producing a nanostructure device according to a first embodiment of the present invention. [Figure 2B] FIG. 2B is a diagram for explaining the method for producing a nanostructure device according to the first embodiment of the present invention. [Figure 2C] FIG. 2C is a diagram illustrating a method for producing a nanostructure device according to the first embodiment of the present invention. [Figure 2D] FIG. 2D is a diagram illustrating a method for producing a nanostructure device according to the first embodiment of the present invention. [Figure 2E] FIG. 2E is a diagram illustrating a method for producing a nanostructure device according to the first embodiment of the present invention. [Figure 2F] FIG. 2F is a diagram for explaining the method for producing a nanostructure device according to the first embodiment of the present invention. [Figure 2G] FIG. 2G is a diagram for explaining the method for producing a nanostructure device according to the first embodiment of the present invention. [Figure 2H] FIG. 2H is a diagram for explaining the method for producing a nanostructure device according to the first embodiment of the present invention. [Figure 3A] FIG. 3A is a diagram illustrating a method for producing a nanostructure device according to a first embodiment of the present invention. [Figure 3B] FIG. 3B is a diagram illustrating a method for fabricating an example of a nanostructure device according to the first embodiment of the present invention. [Figure 4A] FIG. 4A is a schematic diagram of an example of application of the nanostructure device according to the first embodiment of the present invention to a photonic crystal device. [Figure 4B] FIG. 4B is a schematic diagram of an example of application of the nanostructure device according to the first embodiment of the present invention to a photonic crystal device. [Figure 5A] FIG. 5A is a diagram illustrating a method for producing a nanostructure device according to a second embodiment of the present invention. [Figure 5B] FIG. 5B is a diagram for explaining a method for producing a nanostructure device according to the second embodiment of the present invention. [Figure 5C] FIG. 5C is a diagram illustrating a method for producing a nanostructure device according to a second embodiment of the present invention. [Figure 5D] FIG. 5D is a diagram illustrating a method for producing a nanostructure device according to a second embodiment of the present invention. [Figure 5E] FIG. 5E is a diagram illustrating a method for producing a nanostructure device according to a second embodiment of the present invention. [Figure 5F] FIG. 5F is a diagram illustrating a method for producing a nanostructure device according to a second embodiment of the present invention. [Figure 5G] FIG. 5G is a diagram illustrating a method for producing a nanostructure device according to the second embodiment of the present invention. [Figure 5H] FIG. 5H is a diagram for explaining a method for producing a nanostructure device according to the second embodiment of the present invention. [Figure 5I] FIG. 5I is a diagram for explaining a method for producing a nanostructure device according to the second embodiment of the present invention. [Figure 6A] FIG. 6A is a diagram illustrating a method for producing a nanostructure device according to a second embodiment of the present invention. [Figure 6B] FIG. 6B is a diagram illustrating a method for fabricating an example of a nanostructure device according to the second embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0015] First Embodiment A method for producing a nanostructure device according to a first embodiment of the present invention will be described with reference to FIGS. 1A to 4B.

[0016] <Configuration of nanostructure devices> 1A, the nanostructure device 1 according to this embodiment is a cylindrical nanowire device, and includes electrodes 12 and 18 on both ends of an active layer 11. The active layer 11 includes an InP first layer 111, an InGaAsP-based MQW 112, and an InP second layer 113.

[0017] Furthermore, the nanostructure device 2 according to this embodiment may be a nanostructure device with a line-shaped structure, as shown in FIG. 1B.

[0018] <Method for fabricating nanostructure devices> A method for fabricating a nanostructure device 1 according to this embodiment will be described with reference to Figures 2A-H. Figures 2A-H show schematic cross-sectional side views of a sample at each step in the method for fabricating a nanostructure device 1. In this embodiment, as an example of a method for fabricating a nanostructure device, a method for fabricating a nanowire device by top-down processing an epitaxial crystal grown on an InP substrate is shown.

[0019] The sample used is an epitaxial crystal substrate (semiconductor active layer substrate) with a laser structure emitting light at 1550 nm. The epitaxial crystal substrate comprises an active layer 11, which is crystal-grown in sequence on one surface of an InP (100) substrate (first substrate) 10. The active layer 11 comprises an InP first layer 111, an InGaAsP-based MQW 112, and an InP second layer 113, each with a thickness of 1 μm, 100 nm, and 3 μm, respectively.

[0020] First, a circular photoresist pattern (photoresist pattern for nano-fabrication) 14 is formed on an AuZnNi (first electrode) 12 and an SiO2 film (first insulating film) 13, which are formed in this order on the upper surface of an active layer 11 (FIG. 2A). Here, the thicknesses of the AuZnNi and SiO2 films are 50 nm and 2000 nm, respectively.

[0021] FIG. 3A shows an SEM photograph (left) and a schematic diagram (right) of the photoresist pattern 14. The photoresist pattern 14 has an upwardly convex lens shape with a diameter of about 1 μm. As shown, the side surfaces of the photoresist pattern (nano-fabrication photoresist pattern) 14 are inclined. Here, the diameter of the photoresist pattern is preferably greater than 500 nm and less than or equal to 1.5 μm.

[0022] Next, the unmasked AuZnNi12 / SiO2 film 13 is removed (etched) by RIE (reactive ion etching, pattern forming dry etching) using CF3 with the photoresist pattern 14 as a mask (FIG. 2B).

[0023] At this time, the removal of the photoresist pattern 14 also progresses during the process of removing the AuZnNi12 / SiO2 film 13 by RIE, so that the thin portions at the edges of the photoresist pattern 14 are removed and the thick portion near the center of the photoresist pattern remains. Therefore, the AuZnNi12 / SiO2 film 13 in the thin portions at the edges of the photoresist pattern 14 is also removed, leaving the thick portion of the AuZnNi12 / SiO2 film 13 near the center of the photoresist pattern 14, allowing a nano-sized pattern to be fabricated.

[0024] Furthermore, a line-shaped pattern can be created by using the line-shaped nano-processing photoresist pattern shown in Figure 3B. This nano-processing photoresist pattern also has inclined sides, so nano-sized patterns can be created in the same way as circular patterns.

[0025] Next, the active layer 11 is etched to a thickness of 4 μm by ICP (inductively coupled plasma) etching (dry etching for semiconductor processing) using Cl2, and then wet etching (wet etching for semiconductor processing) is performed for 5 minutes using a 70°C TMAH (Tetramethyl ammonium hydroxide) aqueous solution (Fig. 2C). Here, the TMAH aqueous solution wet etching removes the surface damage layer caused by dry etching, forming a stable facet.

[0026] At this time, the photoresist pattern 14 is removed by ICP etching, but if the photoresist remains, the photoresist pattern 14 is removed by oxygen plasma treatment or the like.

[0027] As a result, the side surface of the active layer 11, which was tapered after dry etching, becomes perpendicular to the substrate after wet etching. In other words, the active layer 11 becomes cylindrical, and the diameter of the active layer 11 in the vertical direction becomes uniform.

[0028] As a result, a cylindrical active layer (microscopically shaped portion) 11_2 and a planar InP first layer (hereinafter referred to as "base layer") 111_1 are formed on the InP substrate 10. In detail, the cylindrical active layer 11_2 includes a cylindrical InP first layer 111_2, an MQW 112, and an InP second layer 113, and includes an AuZnNi12 / SiO2 film 13 on the upper surface of the active layer 11_2 (InP second layer 113).

[0029] Here, the diameter of the cylindrical active layer 11_2 is about 200 nm. The diameter of the cylindrical active layer 11_2 may be 20 nm or more and 500 nm or less.

[0030] As described above, in this embodiment, the semiconductor nanostructure substrate includes a base layer 111_1 and a cylindrical active layer (microscopically shaped portion) 11_2 on one surface of an InP substrate (first substrate) 10, and an AuZnNi (first electrode) 12 on one end of the cylindrical active layer (microscopically shaped portion) 11_2. Also, an SiO2 film (first insulating film) 13 is provided on the AuZnNi (first electrode) 12.

[0031] Next, a SiO2 film (second insulating film) 15 is formed to a thickness of 10 nm on the entire surface (the surface having the cylindrical active layer 11_2) of the sample (semiconductor nanostructure substrate) by, for example, vapor deposition or sputtering (FIG. 2D).

[0032] Next, a glass substrate (second substrate) 16 for bonding is prepared, with In attached as the metal film 17. The surface of the glass substrate 16 with the metal film (In) 17 attached faces the surface of the SiO2 film 15 on the surface of the sample (semiconductor nanostructure substrate), and the two substrates are bonded at 250°C (Figure 2E). Here, In, which has a melting point of 197°C, is used, but metals with relatively low melting points such as Ga (melting point 30°C) or Sn (melting point 232°C) may also be used. Furthermore, the second substrate is not limited to a glass substrate; it may be a substrate made of other dielectrics, metals, semiconductors, or other materials.

[0033] Next, the other surface of the InP substrate 10 is polished to a thickness of 10 μm, and then the InP substrate 10 and a part of the base layer 111_1 are etched by ICP dry etching (first dry etching). Here, the etching is performed until the shape of the cylindrical active layer 11_2 can be seen through the thinned base layer 111_1.

[0034] Next, a circular pattern of AuZnNi (second electrode) 18 and a SiO2 film (third insulating film) 19 are fabricated in this order on the etched surface (front surface) of the thinned base layer 111_1 by photolithography or EB lithography (FIG. 2F), as in the embodiment of FIG. 2B. The diameter of the circular shape is about 200 nm, and the thicknesses of the AuZnNi 18 and the SiO2 film 19 are 50 nm and 2000 nm, respectively.

[0035] Here, the position of the AuZnNi18 / SiO2 film 19 is arranged so as to approximately coincide with the position of the cylindrical active layer (microscopic shape portion) 11_2 via the thinned base layer 111_1. Here, "approximately coincident" includes a perfect coincidence, and includes an error of about 10% of the diameter.

[0036] Next, the base layer 111_1 is etched by ICP dry etching (second dry etching) using the SiO2 film 19 as a mask. As a result of this ICP dry etching, the edges of the circular patterned SiO2 film 19 and AuZnNi 18 are etched, and the side shape of the active layer 11, which was tapered after dry etching, becomes perpendicular to the substrate after wet etching with a TMAH aqueous solution. In other words, the active layer 11 becomes cylindrical, and the diameter of the active layer 11 in the vertical direction becomes uniform. The diameter becomes about 200 nm, which is similar to that of the cylindrical active layer 11_2.

[0037] As a result, a nanowire device (nanostructure device) 1 having electrodes 12 and 18 on both ends of a nanowire made of the active layer 11 is formed.

[0038] Next, the electrodes (AuZnNi) 12, 18 on both ends of the cylindrical active layer 11_2 are made into ohmic electrodes by annealing at 400° C. (FIG. 2G). The annealing temperature may be about 300° C. to 700° C.

[0039] Finally, SiO2 films 15 and SiO2 films 19 are removed. This separates nanowire device (nanostructure device) 1, leaving it free and unconstrained (FIG. 2H). Here, RIE or hydrofluoric acid-based wet etching is used to remove SiO2 films 15 and 19.

[0040] In the above-described manufacturing process, if a line-shaped photoresist pattern (FIG. 3B) is used, a nanostructure device 2 having a line-shaped structure as shown in FIG. 1B can be manufactured.

[0041] The nanowire device (nanostructure device) 1 fabricated by the method according to this embodiment can be placed in a trench 101 of a Si photonic crystal 100 as shown in FIG. 4A using an AFM (A. Yokoo, M. Takiguchi, M.D. Birowosuto, K. Tateno, G. Zhang, E. Kuramochi, A. Shinya, H. Taniyama, and M. Notomi, “Subwavelength Nanowire Lasers on a Silicon Photonic Crystal Operating at Telecom Wavelengths,”ACS Photonics 4, pp.355-362, 2017.)

[0042] In this way, by forming wiring electrodes in advance on the Si photonic crystal 100 and positioning the electrodes 12, 18 of the nanowire device (nanostructure device) 1 so that they align with the wiring electrodes, current can be injected into the nanowire device (nanostructure device) 1.

[0043] Similarly, a nanostructure device 2 having a line-shaped structure can be disposed in a trench 201 of a Si photonic crystal 200 as shown in FIG. 4B.

[0044] <Effects> According to the method for fabricating a nanostructure device according to the present embodiment, a nanowire device having an ohmic electrode with little damage can be fabricated.

[0045] Therefore, a low-resistance electrical connection can be easily achieved by simply placing a nanowire device with pre-formed ohmic electrodes on a substrate such as a Si photonic crystal on which wiring electrodes have been formed. This eliminates the need to heat the device after placement on the Si photonic crystal substrate, and does not affect other functional elements already incorporated on the optical IC.

[0046] Furthermore, the nanowires themselves have controlled thickness and doping, and the wet etching process reduces surface damage caused by dry etching, enabling the realization of highly efficient device characteristics.

[0047] Furthermore, since nanowires are fabricated by top-down processing of the epitaxial crystal substrate, nanowire devices can be fabricated with high efficiency.

[0048] In this embodiment, a cylindrical active layer and nanowires are used as an example, but a cylindrical active layer and nanowires with a polygonal cross section may also be used. Here, the diameter of the active layer and nanowire is the diameter when the cross section is circular, and is about twice the length from the apex to the center when the cross section is polygonal.

[0049] <Second embodiment> A method for producing a nanostructure device according to a second embodiment of the present invention will be described with reference to FIGS. 5A to 6B.

[0050] <Configuration of nanostructure devices> The nanostructure device 3 according to this embodiment is a columnar nanowire device, similar to the first embodiment, and has electrodes on both ends of the active layer. The active layer includes a GaN first layer, a GaInN-based MQW, and a GaN second layer, each with a thickness of 3 μm, 100 nm, and 500 nm. The cross section of the nanowire is circular or polygonal.

[0051] <Method for fabricating nanowire devices> A method for fabricating a nanostructure device 1 according to this embodiment will be described with reference to Figures 5A-I. The left and right diagrams in Figures 5A-I show a schematic cross-sectional side view and a schematic perspective top view of a sample at each step in the method for fabricating a nanostructure device 1, respectively.

[0052] The sample used was a nitride semiconductor epitaxial crystal substrate (semiconductor active layer substrate) with a laser structure emitting at 400 nm. The nitride semiconductor epitaxial crystal substrate had an active layer grown on a c-plane sapphire substrate (first substrate). The active layer included a GaN first layer, a GaInN-based MQW, and a GaN second layer, with respective layer thicknesses of 3 μm, 100 nm, and 500 nm.

[0053] As in the first embodiment, after forming a circular or polygonal patterned electrode 32 and an SiO2 film (not shown), a columnar active layer is fabricated by dry etching and wet etching. As a result, a columnar active layer (fine shape portion) 31_2 and a planar GaN first layer (hereinafter referred to as "base layer") 311_1 are formed on the sapphire substrate 30.

[0054] The columnar active layer (microscopically shaped portion) 31_2 includes a columnar GaN first layer 311_2, a GaInN-based MQW 312, and a GaN second layer 313. An electrode 32 is formed on the upper surface of the columnar active layer 31_2 (FIG. 5A). Hereinafter, the structure consisting of the columnar active layer 31_2 and the electrode 32 will be referred to as a "columnar nanostructure 3_1."

[0055] In detail, in this embodiment, Pd, Pt, and Au are formed as an electrode (first electrode) 32 and a SiO2 film (first insulating film) as a mask in a circular or polygonal pattern on the upper surface of the active layer, with respective film thicknesses of 30 nm, 30 nm, 50 nm, and 100 nm, and annealing is performed at 600°C for 2 minutes.

[0056] The semiconductor processing dry etching was performed using ICP etching using BCl3 / Cl2, with an etching depth of 1.1 μm. Figure 6A shows an SEM photograph (left) and a schematic diagram (right) of the active layer 31_1 taken from an oblique angle after dry etching. The active layer 31_1 has a tapered structure with a large diameter at the bottom, with a top diameter of approximately 610 nm and a bottom diameter of approximately 1020 nm.

[0057] After the dry etching for semiconductor processing, wet etching for semiconductor processing is performed using a TMAH aqueous solution at 70°C for 20 minutes. Figure 6B shows an SEM photograph (left) and a schematic diagram (right) of the active layer 31_2 after wet etching. The tapered shape of the active layer 31_2 after dry etching becomes a columnar shape with a uniform diameter, the side surfaces of which are perpendicular to the substrate. The diameter of the columnar active layer 31_2 is reduced to approximately 300 nm. The diameter of the columnar active layer 31_2 may be between 20 nm and 500 nm. The diameter of the active layer is the diameter when the cross section is circular, and approximately twice the length from the apex to the center when the cross section is polygonal.

[0058] Thus, in this embodiment, the semiconductor nanostructure substrate comprises, on one surface of a sapphire substrate (first substrate) 30, a base layer 311_1 and a columnar active layer (fine-shaped portion) 31_2, in that order, and an electrode (first electrode) 32 made of Pd, Pt, and Au at one end of the columnar active layer (fine-shaped portion) 31_2.

[0059] Next, an SiO2 film (fourth insulating film) 33 is formed by, for example, vapor deposition on the entire surface (surface having the columnar active layer 31_2) of the sample (semiconductor nanostructure substrate) to a thickness of 50 nm.

[0060] Next, as shown in FIG. 5B, a photoresist pattern 34 is formed near the pillar nanostructure 3_1 by photolithography. The photoresist pattern (first photoresist pattern) 34 covers the pillar nanostructure 3_1 and has a first opening. The first opening has a U-shaped opening at one end of a rectangular opening (rectangular portion), and is formed so that the U-shaped opening surrounds the pillar nanostructure 3_1, i.e., the pillar-shaped active layer (fine-shaped portion) 31_2. In this way, the first opening is formed so as to surround at least one side of the side of the pillar-shaped active layer (fine-shaped portion) 31_2 (the side where the rectangular portion of the first opening is located).

[0061] Next, using the photoresist pattern 34 as a mask, the SiO2 film 33 and the base layer 311_1 in the opening are dry-etched (third dry etching) to a depth of 3 μm (FIG. 5C). Here, as the third dry etching, for example, RIE for removing the SiO2 film 33 is followed by ICP etching using BCl3 / Cl2.

[0062] As a result, a U-shaped groove is formed at one end of a rectangle in the base layer 311_1 near the columnar nanostructure 3_1. Here, the U-shaped groove is formed so as to surround at least one side of the side surface of the active layer 31_2 of the columnar nanostructure 3_1 (the side where the rectangular portion of the first opening is located).

[0063] Next, using a hydrofluoric acid solution (first wet etching), the SiO2 film 33 is etched (removed) horizontally through the openings in the photoresist pattern 34 to expose the side of the lower part of the active layer 31_2 of the columnar nanostructure 3_1 that is close to the U-shaped groove (Figure 5D).

[0064] Next, the lower part of the active layer 31_2 of the columnar nanostructure 3_1 and part of the base layer 311_1 are wet-etched (second wet etching) from the side of the U-shaped groove using a TMAH aqueous solution at 70°C. As a result, the lower part of the active layer 31_2 of the columnar nanostructure 3_1 is removed, and the remaining active layer 31_2 becomes the nanowire 31_3. Here, the columnar nanostructure 3_2 has the nanowire 31_3 and an electrode 32 at one end thereof. At this time, the first opening of the first photoresist pattern 34 is transferred to the base layer 311_1 to form a groove. After the second wet etching, the photoresist pattern 34 is removed by oxygen plasma irradiation or the like (Figure 5E).

[0065] Next, the SiO2 film 33 is etched by dry etching (fourth dry etching). As the etching progresses, the SiO2 film 33 supporting the side surfaces of the nanowires 31_3 of the columnar nanostructure 3_2 and the top surface of the base layer 311_1, i.e., the contact points between the SiO2 film 33 on the side surfaces of the nanowires 31_3 and the SiO2 film 33 on the top surface of the base layer 311_1, become thinner. As a result, the columnar nanostructure 3_2 breaks, allowing the columnar nanostructure 3_2 to fall toward the groove formed in the base layer 311_1 (Figure 5F).

[0066] In this way, the columnar nanostructure 3_2 is tilted in the direction of the rectangular portion of the groove formed by transferring the first opening to the base layer 311_1, and the columnar nanostructure 3_2 is separated from the support of the SiO2 film 33. As a result, the columnar nanostructure 3_2 can be placed in the groove (rectangular portion), and the step of the groove allows the other end of the nanowire 31_3 in the columnar nanostructure 3_2 (the end opposite to the surface having the electrode 32) to face upward.

[0067] Next, an SiO2 film (fifth insulating film) 35 is deposited or sputtered to cover the columnar nanostructure 3_2 and the surface of the base layer 311_1, thereby fixing the columnar nanostructure 3_2 to the surface of the base layer 311_1 (FIG. 5G).

[0068] Next, a photoresist pattern (second photoresist pattern) 36 is formed by photolithography or electron beam lithography, and an opening (second opening) 36_2 is formed in the SiO2 film 35 by RIE, aligned with the position of the surface of the other end of the nanowire 31_3 (FIG. 5H).

[0069] Next, a second electrode 38 is formed by deposition and lift-off using Ti, Pt, and Au in the order of thicknesses of 10 nm, 30 nm, and 250 nm, respectively, on the surface of the other end of the nanowire 31_3.

[0070] Specifically, after Ti, Pt, and Au are vapor-deposited, the sample is immersed in an organic solvent or the like to remove the photoresist, leaving the electrode metals (Ti, Pt, and Au) 38 vapor-deposited on the surface of the other end of the nanowire 31_3 through the photoresist pattern (second photoresist pattern) 36 and the opening (second opening) 36_2 in the SiO2 film 35.

[0071] In this way, since the surface of the other end of the nanowire 31_3 faces upward, electrode metals (Ti, Pt, and Au) 38 can be formed on the surface of the other end by vapor deposition from above.

[0072] Next, the electrodes 32 and 38 at both ends of the nanowire 31_3 are made into ohmic electrodes by annealing at 400°C. The annealing temperature may be about 300°C to 700°C.

[0073] Finally, the SiO2 film 35 is removed to leave the nanowire device 3, including the nanowire 31_3 and the ohmic contact electrodes 32, 38 at both ends, free from the base layer 311_1 and the substrate 30 (FIG. 5I). The SiO2 film 35 is removed by RIE or hydrofluoric acid-based wet etching.

[0074] In this way, the nanowire device (nanostructure device) 3 can be fabricated and placed at a predetermined location (eg, a groove) on the base layer 311_1 (substrate).

[0075] <Effects> According to the fabrication method of this embodiment, the same effects as those of the first embodiment can be achieved, and the nanowires can be disposed directly on the substrate used for fabricating the nanowires.

[0076] Furthermore, the end face of the nanowire separated from the substrate faces upward due to the step of the groove formed in the substrate, making it possible to form an electrode on the end face by evaporating metal (electrode material) from above.

[0077] This makes it possible to easily fabricate and place nanowires with ohmic electrodes, i.e., nanowire devices (nanostructure devices), on substrates such as photonic crystals with wiring electrodes, and pass current through them.

[0078] The nanostructure device according to the embodiment of the present invention functions as a light-emitting device such as a laser or an LED when a current is injected into it.

[0079] In the embodiments of the present invention, examples have been shown in which InP-based semiconductors and GaN-based semiconductors are used for the active layer, but other semiconductors such as GaAs-based semiconductors, ZnSe, and SiGe may also be used. Furthermore, while examples have been shown in which the active layer includes MQW, a double heterostructure may be formed by including an alloy semiconductor such as InGaAsP instead of MQW, as long as it functions as a light-emitting layer in a light-emitting device. Furthermore, the first substrate may be a substrate suitable for crystal growth of the active layer.

[0080] In the embodiments of the present invention, examples of dry etching using RIE, ICP (inductively coupled plasma) etching using Cl2, and ICP etching using BCl3 / Cl2 have been shown, but the present invention is not limited to these, and any dry etching suitable for the material to be etched may be used.

[0081] In the embodiment of the present invention, an example has been shown in which hydrofluoric acid and a TMAH (tetramethylammonium hydroxide) aqueous solution are used for wet etching, but the present invention is not limited to this, and any dry etching suitable for the material to be etched may be used.

[0082] In the embodiment of the present invention, the electrode metals are AuGeNi and Ti / Pt / Au, but the present invention is not limited to these, and any metal that can form an ohmic contact may be used. Also, although the dielectric film is an SiO2 film, other dielectric films such as SiN may be used.

[0083] In an embodiment of the present invention, the nanostructure device may have a p-type semiconductor layer and an n-type semiconductor layer at each end.

[0084] In the embodiments of the present invention, examples of the structure, dimensions, materials, etc. of each component in the method for fabricating a semiconductor nanowire diode are shown, but the present invention is not limited to these examples. Any material may be used as long as it provides the effects of the method for fabricating a semiconductor nanowire diode. [Industrial Applicability]

[0085] The present invention can be applied to photonic crystal optical devices operating in the optical communication wavelength band. [Explanation of symbols]

[0086] 1 Nanostructure devices 10 First substrate 11_2 Fine shape part 12 First electrode 13 First insulating film 15 Second insulating film 16 Second board 17 Metal Film 18 Second electrode 19 Third insulating film 111_1 Basal layer

Claims

1. A semiconductor nanostructure substrate having a base layer and a microstructure portion on one surface of a first substrate, in that order, and a first electrode at one end of the microstructure portion, forming a second insulating film on the surface of the semiconductor nanostructure substrate that includes the microstructure portion; a step of bonding the surface of the semiconductor nanostructure substrate on which the second insulating film is formed to a surface of a second substrate via a metal film; a step of removing a portion of the first substrate from the other surface of the first substrate, and then performing a first dry etching on the other portion of the first substrate and a portion of the base layer; forming a second electrode and a third insulating film in this order on the surface of the base layer on the side where the first dry etching has been performed, so that the second electrode and the third insulating film are disposed so as to substantially coincide with the position of the finely shaped portion; performing a second dry etching on the base layer using the third insulating film as a mask; a step of converting the first electrode and the second electrode into ohmic electrodes by annealing; removing the second insulating film and the third insulating film; A method for fabricating a nanostructure device comprising:

2. A semiconductor nanostructure substrate having a base layer and a microstructure portion on one surface of a first substrate, in that order, and a first electrode at one end of the microstructure portion, The fine shape portion is a pillar shape, forming a fourth insulating film on the surface of the semiconductor nanostructure substrate that includes the fine shape portion; forming a first photoresist pattern having a first opening on the fourth insulating film; using the first photoresist pattern as a mask, performing a third dry etching on the fourth insulating film and the base layer to a predetermined depth; a step of performing a first wet etching on the fourth insulating film through the first opening, and subsequently performing a second wet etching to process the fine shape portion into a semiconductor nanowire; removing the first photoresist pattern, and then removing the fourth insulating film, and disposing the semiconductor nanowires in grooves formed in the base layer by transferring the first openings; forming a fifth insulating film to cover the semiconductor nanowires and the surface of the base layer; forming a second photoresist pattern having a second opening on the fifth insulating film; forming a second electrode on the other end of the semiconductor nanowire using the second photoresist pattern; a step of converting the first electrode and the second electrode into ohmic electrodes by annealing; removing the fifth insulating film; Equipped with The first opening is formed to surround at least one side of the finely shaped portion, and the second opening is formed to be positioned in alignment with the other end of the semiconductor nanowire. A method for producing a nanostructure device.

3. A semiconductor active layer substrate including a semiconductor active layer, the first electrode, and a first insulating film on one surface of the first substrate, in this order, forming a nano-processing photoresist pattern on the upper surface of the first insulating film; a step of performing pattern formation dry etching on the first electrode and the first insulating film using the nano-processing photoresist pattern as a mask; Subsequently, the semiconductor active layer is subjected to semiconductor processing dry etching to a predetermined thickness, and subsequently subjected to semiconductor processing wet etching to produce the semiconductor nanostructure substrate. The method for producing a nanostructure device according to claim 1 or 2, comprising:

4. The side surface of the nano-processing photoresist pattern is inclined.

4. The method for producing a nanostructure device according to claim 3.

5. A tetramethylammonium hydroxide aqueous solution is used for the wet etching for semiconductor processing.

5. A method for producing a nanostructure device according to claim 3 or 4.

6. The diameter of the nano-processing photoresist pattern is longer than 500 nm and 1.5 μm or less, The cross-sectional diameter of the finely shaped portion is 20 nm or more and 500 nm or less. A method for producing a nanostructure device according to any one of claims 3 to 5.

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