Communication device and communication system

Abstract

[Problem] To enable audio signals to be transmitted between communication devices and correctly reproduced. [Solution] The communication device comprises: a measurement unit for measuring, on the basis of an audio master clock the frequency of which is a multiple of the frequency of a sampling clock with which audio signals are sampled, the divide ratio of a frequency-divided signal of the audio master clock, and a prescribed reference clock, the number of clocks of the prescribed reference clock included in one cycle of the frequency-divided signal; and a packet generation unit for generating a packet that includes information that includes the number measured by the measurement unit, the bit width of serial data (SD) conforming to I2S standard, the frequency of the sampling clock, the divide ratio of the frequency-divided signal with respect to the audio master clock, the frequency ratio of the frequency of the audio master clock with respect to the frequency of the sampling clock, and the SD.

Description

[Technical Field]

[0001] The present disclosure relates to a communication device and a communication system. [Background technology]

[0002] A technique has been proposed for performing high-speed serial communication between a Master SerDes and a Slave SerDes (see Patent Document 1).

[0003] When transmitting audio signals between two SerDes, it is conceivable to transmit signals conforming to the I2S (Inter-IC Sound) protocol. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2011-239011 Summary of the Invention [Problem to be solved by the invention]

[0005] However, signals conforming to the I2S protocol are asynchronous to the signals transmitted between the two SerDes and have different frequency bands. Furthermore, audio signals do not necessarily have a single sampling clock frequency; the sampling clock frequency may vary depending on the audio source. These audio signals must be transmitted between the two SerDes so they can be played back correctly.

[0006] Therefore, the present disclosure provides a communication device and a communication system that can transmit an audio signal between communication devices that transmit signals asynchronously with the audio signal, and can reproduce the audio signal correctly. [Means for solving the problem]

[0007] In order to solve the above-mentioned problems, according to the present disclosure, there is provided a measurement unit that measures the number of predetermined reference clocks included in one cycle of a frequency-divided signal based on an audio master clock having a frequency obtained by multiplying the frequency of a sampling clock that samples an audio signal, a frequency division ratio of a frequency-divided signal of the audio master clock, and a predetermined reference clock; A communication device is provided, comprising: a packet generation unit that generates a packet including information including the number measured by the measurement unit, the bit width of SD (Serial Data) conforming to the I2S standard, the frequency of the sampling clock, the division ratio of the divided signal to the audio master clock, the frequency ratio of the frequency of the audio master clock to the frequency of the sampling clock, and the SD.

[0008] the packet generated by the packet generation unit includes a header portion and a data portion, the header section includes the number measured by the measurement section, the bit width of the SD, the frequency of the sampling clock, the division ratio, and the frequency ratio; The data section may include a plurality of the SDs.

[0009] The header section may include the bit width of the SD, the number of channels of the SD, the frequency of the sampling clock, the division ratio of the divided signal to the audio master clock, the frequency ratio of the audio master clock frequency to the sampling clock frequency, the frequency of the reference clock, and the number measured by the measurement section.

[0010] The data section may include the SDs for the number of channels and the number of samples.

[0011] a physical layer clock generating unit that generates a clock that is commonly used in the physical layers of both the communication device and the communication partner device; The physical layer clock generating unit may further include a frequency dividing unit that divides the frequency of the clock generated by the physical layer clock generating unit to generate the reference clock.

[0012] The frequency of the clock generated by the physical layer clock generating unit may be 250 MHz.

[0013] The frequency of the audio master clock is 25.6 MHz, The frequency of the sampling clock may be 50 kHz.

[0014] The sampling clock and the audio master clock may be asynchronous with the reference clock.

[0015] The sampling clock and the audio master clock may be synchronized with the reference clock.

[0016] a PTB (Precision Time Base) clock generating unit that generates a PTB clock used to generate timestamp information commonly used between the communication device and the communication partner device; The reference clock may be the PTB clock.

[0017] The audio master clock may be synchronized with the PTB clock.

[0018] The PTB clock may have a frequency of 250 MHz.

[0019] According to the present disclosure, a measurement unit receives a WS (Word Select) signal conforming to the I2S standard, and measures, among a plurality of SDs (Serial Data) included in one packet transmitted to a communication partner device, first timing information indicating the timing of a logic change of the WS signal in the first SD and second timing information indicating the timing of a logic change of the WS signal in the last SD, based on a predetermined reference clock shared with the communication partner device; A communication device is provided, comprising: a bit width of the SD, a frequency of a sampling clock for sampling an audio signal, the first timing information, the second timing information, the number of the SDs included in one packet, and a packet generation unit that generates the packet including the SDs.

[0020] The packet generation unit may generate the packet further including information on the number of channels of the SD.

[0021] According to the present disclosure, a restoration unit receives a packet transmitted from a communication partner device and restores from the packet the following: SD (Serial Data) conforming to the I2S standard, the bit width of the SD, the frequency of a sampling clock for sampling an audio signal, the frequency ratio of an audio master clock frequency to the sampling clock frequency, the number of predetermined first reference clocks included in one cycle of a divided signal of the audio master clock, the frequency of the sampling clock, and the division ratio of the divided signal to the audio master clock; an audio master clock reproducing unit that reproduces the audio master clock based on the number of the first reference clocks, the frequency of the first reference clock, and the frequency division ratio; There is provided a communication device including an SCK reproducing unit that reproduces an SCK (Serial Clock) based on the bit width information of the SD, the frequency ratio, and the audio master clock.

[0022] a clock recovery circuit that generates a second reference clock synchronized with a signal change of the SD based on the packet; a frequency ratio calculation unit that calculates a frequency ratio between the frequency of the first reference clock and the frequency of the second reference clock, The audio master clock reproducing unit may reproduce the audio master clock based on the number of the first reference clocks, frequency information of the first reference clocks, the division ratio, and the frequency ratio calculated by the frequency ratio calculating unit.

[0023] a PTB (Precision Time Base) clock generation unit that generates a PTB clock used to generate timestamp information commonly used between the communication partner device and the communication partner device; The first reference clock may be the PTB clock.

[0024] According to the present disclosure, a restoration unit receives a packet transmitted from a communication partner device, and restores from the packet SD (Serial Data) conforming to the I2S standard, bit width information of the SD, frequency information of an SCK (Serial Clock), first timing information indicating the timing at which a WS (Word Select) signal included in one of the packets first changed in logic, second timing information indicating the timing at which a WS signal last changed in logic, and the number of the SDs included in one of the packets; a clock generating unit that generates a reference clock that is used in common with the communication partner device; a WS signal reproducing unit that reproduces the WS signal based on the first timing information, the second timing information, the number of SDs, and the reference clock; an audio master clock reproducing unit that regenerates an audio master clock by multiplying the frequency of the WS signal reproduced by the WS signal reproducing unit; There is provided a communication device comprising: an SCK regenerator that regenerates the SCK based on the WS signal regenerated by the WS signal regenerator and bit width information of the SD.

[0025] a PTB (Precision Time Base) clock generating unit that generates a PTB clock used to generate timestamp information commonly used between the communication device and the communication partner device; The reference clock may be the PTB clock.

[0026] The packets may be transmitted within a time period allocated in TDD (Time Division Duplex).

[0027] According to the present disclosure, there is provided a communication system comprising: a first communication device; a second communication device that performs serial communication with the first communication device; the first communication device, a measurement unit that measures the number of predetermined reference clocks included in one cycle of a frequency-divided signal based on an audio master clock having a frequency obtained by multiplying the frequency of a sampling clock for sampling an audio signal, a frequency division ratio of a frequency-divided signal of the audio master clock, and a predetermined reference clock; a packet generation unit that generates a packet including information including the number measured by the measurement unit, a bit width of SD (Serial Data) conforming to the I2S standard, the frequency of the sampling clock, a division ratio of the divided signal to the audio master clock, a frequency ratio of the frequency of the audio master clock to the frequency of the sampling clock, and the SD; the second communication device, a restoration unit that receives a packet transmitted from the first communication device and restores from the packet the SD, the bit width of the SD, the frequency of the sampling clock, the frequency ratio of the audio master clock frequency to the sampling clock frequency, the number of predetermined first reference clocks included in one cycle of the divided signal of the audio master clock, the frequency of the sampling clock, and the division ratio of the divided signal to the audio master clock; an audio master clock reproducing unit that reproduces the audio master clock based on the number of the first reference clocks, the frequency of the first reference clock, and the frequency division ratio; There is provided a communication system having an SCK reproducing unit that reproduces an SCK (Serial Clock) based on the bit width information of the SD, the frequency ratio, and the audio master clock.

[0028] According to the present disclosure, there is provided a communication system comprising: a first communication device; a second communication device that performs serial communication with the first communication device; the first communication device, a measurement unit that receives a WS (Word Select) signal conforming to the I2S standard, and measures, based on a predetermined reference clock shared with the second communication device, first timing information indicating the timing of a logic change of the WS signal in the first SD among a plurality of SDs (Serial Data) included in one packet transmitted to the second communication device, and second timing information indicating the timing of a logic change of the WS signal in the last SD; a packet generation unit that generates a packet including the bit width of the SD, the frequency of a sampling clock that samples an audio signal, the first timing information, the second timing information, the number of the SDs included in one packet, and the SDs; the second communication device, a restoration unit that receives a packet transmitted from the second communication device and restores from the packet SD (Serial Data) conforming to the I2S standard, bit width information of the SD, frequency information of an SCK (Serial Clock), first timing information indicating the timing at which a WS (Word Select) signal included in one of the packets first changed in logic, second timing information indicating the timing at which a WS signal last changed in logic, and the number of the SDs included in one of the packets; a clock generating unit that generates a reference clock that is used in common with the first communication device; a WS signal reproducing unit that reproduces the WS signal based on the first timing information, the second timing information, the number of SDs, and the reference clock; an audio master clock reproducing unit that regenerates an audio master clock by multiplying the frequency of the WS signal reproduced by the WS signal reproducing unit; A communication system is provided, comprising: an SCK regenerator that regenerates the SCK based on the WS signal regenerated by the WS signal regenerator and bit width information of the SD. [Brief explanation of the drawings]

[0029] [Figure 1] FIG. 1 is a block diagram showing the basic configuration of a communication system 1. [Figure 2A] FIG. 1 is a diagram illustrating a frequency division multiplexing system. [Figure 2B] FIG. 1 is a diagram illustrating a time division multiplexing system. [Figure 3] A diagram showing the I2S format. [Figure 4] 1 is a block diagram showing a schematic configuration of a communication system including a communication device according to a first embodiment. [Figure 5] A diagram showing the structure of packets and frames generated within the SerDes in Figure 4. [Figure 6] This is a block diagram showing the internal configuration of the transmitting I2S device, the encapsulator in the SerDes, and the PHY clock generation unit. [Figure 7] This is a timing diagram of TxREFCK and MCK generated based on the symbol clock of the PHY clock generation unit. [Figure 8] FIG. 10 is a diagram showing transmission parameters used to regenerate MCK at the receiving end. [Figure 9] A diagram of the application packet generated by SerDes. [Figure 10A] FIG. 1 shows the configuration of the header (I2S header) of an application packet for I2S signal transmission. [Figure 10B] A diagram showing the data and CRC configuration of an application packet for I2S signal transmission. [Figure 11A] Timing diagram of the original I2S format. [Figure 11B] Timing diagram for left-justified format. [Figure 11C] Timing diagram for Right Justified format. [Figure 12] FIG. 1 is a block diagram showing the internal configuration of a decapsulator in a SerDes. [Figure 13] FIG. 10 is a block diagram showing the internal configuration of an I2S device according to a second embodiment, and an encapsulator and a PHY clock generation unit in a SerDes. [Figure 14] FIG. 10 is a diagram showing parameter values ​​used when a SerDes according to the second embodiment reproduces an MCK. [Figure 15] FIG. 10 is a block diagram showing the internal configuration of an encapsulator in a SerDes according to a third embodiment. [Figure 16] FIG. 10 is a block diagram showing the internal configuration of a decapsulator in a SerDes according to a third embodiment. [Figure 17] FIG. 10 is a block diagram showing the internal configuration of an I2S device and an encapsulator in a SerDes according to a fourth embodiment. [Figure 18] FIG. 11 is a block diagram showing the internal configuration of an I2S device and an encapsulator in a SerDes according to a fifth embodiment. [Figure 19] Timing diagram of a packet transmitted between two SerDes. [Figure 20] A diagram showing the structure of an application packet generated by SerDes. [Figure 21] FIG. 11 is a block diagram showing the internal configuration of a decapsulator in a SerDes according to a fifth embodiment. [Figure 22A] FIG. 10 is a diagram showing the header structure of an application packet for I2S signal transmission. [Figure 22B] A diagram showing the data and CRC configuration of an application packet for I2S signal transmission. [Figure 23] FIG. 10 is a diagram showing an example of transmitting an I2S signal included in an application packet for transmitting video data. DETAILED DESCRIPTION OF THE INVENTION

[0030] Hereinafter, embodiments of a communication device, a communication system, and a communication method will be described with reference to the drawings. The following description will focus on the main components of the communication device and the communication system, but the communication device and the communication system may include components and functions that are not shown or described. The following description does not exclude components and functions that are not shown or described.

[0031] (Basic configuration of communication system) Fig. 1 is a block diagram showing the basic configuration of a communication system 1 that transmits and receives signals conforming to the I2S protocol between two SerDes 130, 230. The communication system 1 in Fig. 1 includes a first communication module 100 and a second communication module 200, each having a SerDes that performs high-speed serial communication. The first communication module 100 and the second communication module 200 are connected by a cable 300 that is several meters to several tens of meters long.

[0032] The first communication module 100 and the second communication module 200 can transmit audio signals using I2S, an audio signal transmission protocol between ICs, which is specified in the FPD-LINK standard, which is one of the in-vehicle high-speed interface technologies.

[0033] Currently, the Automotive SerDes Alliance (ASA), an organization that sets standards for in-vehicle high-speed serial interfaces, is working on standardizing in-vehicle high-speed serial interface technology. The difference between FPD-LINK and ASA is that FPD-LINK uses frequency division multiplexing as shown in Figure 2A to achieve bidirectional communication, while ASA uses time division multiplexing as shown in Figure 2B, called TDD (Time Division Duplex).

[0034] 1 includes a microphone (hereinafter, referred to as a microphone) 110, a first I2S device (I2S audio device) 120, a SerDes (SerDes device) 130, an X'tal 140, a camera 150, and an X'tal 160. The second communication module 200 includes a speaker (SPK) 210, an I2S device (I2S audio device) 220, a SerDes (SerDes device) 230, a video decoder 250, and an ADAS / ADS processor 260.

[0035] An audio signal collected by a microphone 110 in the first communication module 100 is input to an I2S device 120. The I2S device 120 has an ADC 120-1, an I2S encoder (I2S ENC) 120-2, and a clock generation unit (CLK GEN) 120-3.

[0036] The clock generating unit 120-3 synchronizes with the reference clock generated by the crystal 140 to generate an audio sampling clock, an audio serial clock, and an audio master clock (hereinafter, referred to as MCK).

[0037] The ADC 120-1 performs AD conversion on the audio signal from the microphone 110 in synchronization with the audio sampling clock to generate audio data. The I2S encoder 120-2 encodes the audio data in synchronization with the audio serial clock to generate an SCK (Serial Clock), a WS (Word Select) signal, and SD (Serial Data) that comply with the I2S protocol. In this specification, SCK, WS, and SD may be collectively referred to as I2S signals.

[0038] The SCK, WS signal, SD, and MCK generated by the I2S device 120 are input to the SerDes 130. In addition, the SerDes 130 also receives video data captured by a camera 150 and a reference clock generated by a crystal 160.

[0039] The SerDes 130 generates packets containing audio data corresponding to the audio signal collected by the microphone 110 and transmits the packets to the SerDes 230 via the cable 300. The packets are transmitted within the period allocated by the TDD. The SerDes 230 receives the packets transmitted from the SerDes 130 and restores the original SCK, WS signal, SD, and MCK, as well as the video data captured by the camera 150.

[0040] The SCK, WS signal, SD, and MCK restored by the SerDes 230 are input to an I2S device (I2S audio device) 220. The I2S device 220 has an I2S decoder (I2S DEC) 220-1, a DAC 220-2, and a clock divider unit (CLK divider) 220-3.

[0041] The clock divider unit 220-3 generates an audio sampling clock and an audio serial clock in synchronization with the MCK reproduced by the SerDes 230. The I2S decoder 220-1 restores the original audio data in synchronization with the audio serial clock. The restored audio data is supplied to the DAC 220-2 and the ADAS / ADS processor 260. The DAC 220-2 performs digital-to-analog conversion of the audio data to generate an audio signal, which is input to the speaker 210. As a result, the audio signal collected by the microphone 110 is reproduced from the speaker 210. The ADAS / ADS processor 260 analyzes the audio data and uses it for, for example, peripheral recognition.

[0042] As described above, in the communication system 1 shown in FIG. 1 , an audio signal collected by the microphone 110 in the first communication module 100 is AD converted by the I2S device 120, then converted to the I2S protocol, and then packetized in the SerDes transmission format by the SerDes 130 and transmitted to the second communication module 200. The SerDes 230 in the second communication module 200 restores the I2S SCK, WS signal, SD, and MCK from the received packets. The I2S device 220 performs the reverse conversion of the I2S device 120 to restore the audio signal and output it as sound from the speaker 210. The I2S device 220 also supplies the I2S formatted audio data to the ADAS / ADS processor 260.

[0043] (I2S format) Figure 3 is a diagram showing the I2S format. Figure 3 shows the signal waveforms of MCK, the WS signal, SCK, and SD. MCK has a frequency that is a multiple K of the sampling clock frequency fs [Hz]. The multiple K is, for example, 128, 256, or 512. The WS signal has the same frequency fs as the sampling clock. One cycle of the WS signal is the bit width of the SD. The bit width of SD within one cycle of the WS signal is arbitrary. The frequency of SCK changes depending on the bit width of SD. SCK is a clock that determines the timing of serial transmission of each bit in SD.

[0044] Figure 3 shows an example in which serial data for the left channel is transmitted while the WS signal is low, and serial data for the right channel is transmitted while the WS signal is high. SD is transmitted bit by bit, starting from the MSB.

[0045] Digital audio processing typically uses an audio master clock MCK, which is the sampling frequency fs multiplied by K. Therefore, as shown in FIG. 3, MCK may also be transmitted in addition to the WS signal, SCK, and SD. The I2S device 120 in FIG. 1 generates the WS signal, SCK, and SD in synchronization with MCK. Therefore, when transmitting audio signals, it is important that the MCK signal from the transmitting side be accurately reproduced on the receiving side, with minimal jitter being particularly required. This is because, when a digital signal is converted into an audio signal by the DAC 220-2 on the receiving side, if a sampling clock containing jitter is used, modulation distortion in the time domain occurs, resulting in degradation of audio quality (S / N).

[0046] In recent years, the widespread use of high-quality audio equipment has led to the transmission of high-dynamic-range signals at high sampling clock frequencies, placing increasingly stringent demands on clock jitter on the playback side. High-quality audio signal transmission using high-speed serial interface technology requires accurate transmission of the sampling clock frequency (fs) and its integer multiples (MCK). However, the frequencies used in high-speed serial interface technologies such as SerDes 130 and 230 are unrelated to the sampling clock frequencies (44.1 kHz, 48 kHz, 96 kHz, 192 kHz, etc.) and MCK (22.5792 MHz, 24.576 MHz, etc.) used in typical audio signal processing. Even if the sampling clock frequency used in audio signal processing and the frequency used in the high-speed serial interface are asynchronous, audio signals transmitted via a high-speed serial interface must be reproduced correctly at the destination. However, existing high-speed serial transmission protocols such as the FPD-LINK mentioned above do not clearly define the specific procedures for serially transmitting asynchronous audio signals.

[0047] The communication device and communication system 1 according to the present disclosure, which will be described below, are characterized by their ability to transmit and correctly reproduce audio signals that comply with the I2S standard in high-speed serial interface technology, for example, the ASA standard.

[0048] (First embodiment) Fig. 4 is a block diagram showing a schematic configuration of a communication system 1 including a communication device according to the first embodiment. In Fig. 4, components common to Fig. 1 are assigned the same reference numerals, and the following description will focus on the differences. In Fig. 4, the flow of signal processing of I2S signals is indicated by arrows.

[0049] The communication system 1 in FIG. 4 includes a first communication module (first communication device) 10 and a second communication module (second communication device) 20.

[0050] The first communication module 10 includes a microphone 110, an I2S device 120, a SerDes 130, and a crystal 160. The second communication module 20 includes a speaker 210, an I2S device 220, and a SerDes 230.

[0051] The SerDes 130 is a PHY clock master. That is, the SerDes 130 generates a PHY clock used in the physical layer of the SerDes 130 based on the X'tal 160. Meanwhile, the SerDes 230 is a PHY clock follower that operates in synchronization with the PHY clock generated by the SerDes 130. More specifically, the SerDes 130 generates downlink transmission symbols using the PHY clock as a symbol clock and transmits them to the SerDes 230 via the cable 300. The SerDes 230 recovers the PHY clock from the received transmission symbols and decodes the received transmission symbols using the recovered PHY clock. Here, a transmission symbol is the smallest unit of a transmission signal change interval. In the case of PAM (Pulse Amplitude Modulation)2, one transmission symbol is a section in which one bit is transmitted, and in the case of PAM4, one transmission symbol is a section in which two bits are transmitted.

[0052] 4, the SerDes 130 includes a PHY block 130-1, a LINK block 130-2, an encapsulator (Application System Encapsulator) 130-3, a deencapsulator (Application System Deencapsulator) 130-4, and control registers 130-5. The encapsulator 130-3 and the deencapsulator 130-4 are provided for each application, such as I2S signal transmission. This specification and the drawings will mainly describe the encapsulator 130-3 and deencapsulator 130-4 for I2S signal transmission.

[0053] The PHY unit 130-1 includes a Down Link transmitter (Down Link Tx) 130-1-1, a PHY clock generator (CLK GEN) 130-1-3, and an Up Link receiver (UP Link Rx) 130-1-2. The LINK unit 130-2 includes a frame constructor 130-2-1, an OAM (Operation Application Maintenance) unit 130-2-3, and a frame deconstructor 130-2-2.

[0054] (Packet and frame structure) Fig. 5 is a diagram showing the configuration of packets and frames generated within the SerDes 130 in Fig. 4. In order to transmit an audio signal from the microphone 110 or a video signal from the camera 150, the encapsulator 130-3 in Fig. 4 packetizes signals from applications such as the microphone 110 and the camera 150, and adds a header to the packet to generate an application packet ((5-1) in Fig. 5). The application packet generated by the encapsulator 130-3 is sent to the frame construction unit 130-2-1 in the LINK unit 130-2.

[0055] The OAM unit 130-2-3 in the LINK unit 130-2 generates information for controlling the SerDes 130 and monitoring the transmission status, and includes it in the application packet. The frame construction unit 130-2-1 generates a container including a container header ((5-2) in FIG. 5), and further generates a link frame that aggregates multiple containers ((5-3) in FIG. 5). The container includes multiple application packets. For each of the multiple application packets, the container header includes the address of the SerDes 130 itself, the address of the connected SerDes 230, the recipient of the application packet, and content information of the application packet.

[0056] The Link frame generated by the frame construction unit 130-2-1 is sent to the Down Link transmission unit 130-1-1 in the PHY unit 130-1. The processing in the LINK unit 130-2 uses a clock of a predetermined frequency synchronized with the symbol clock generated by the PHY clock generation unit 130-1-3 in the PHY unit 130-1.

[0057] The Down Link transmitter 130-1-1 in the PHY unit 130-1 adds a synchronization signal having a special pattern to the Link frame to generate a transmission frame ((5-4) in FIG. 5).

[0058] Meanwhile, the PHY clock generation unit 130-1-3 in the PHY unit 130-1 generates a symbol clock ((5-5) in Figure 5) of the transmission symbol rate (e.g., 2 GHz, 4 GHz, 8 GHz, etc.) of the transmission signal generated in synchronization with the reference clock generated by the crystal 160, and supplies it to the Down Link transmission unit 130-1-1.

[0059] The Down Link transmitter 130-1-1 converts the transmission frame into a transmission symbol ((5-6) in FIG. 5) in synchronization with the symbol clock, and transmits the symbol to the transmission cable 300 ((5-7) in FIG. 5).

[0060] Next, we will explain the reception process of the receiving-side SerDes 230. The SerDes 230 in Fig. 4 has a PHY unit 230-1, a LINK unit 230-2, an encapsulator (Application Stream Encapsulator) 230-3, a deencapsulator (Application Stream Deencapsulator) 230-4, and control registers 230-5.

[0061] The PHY unit 230-1 has an UP Link transmitter (UP Link Tx) 230-1-1, a Down Link receiver (Down Link Rx) 230-1-2, a CDR (Clock Data Recovery) 230-1-3, and a clock divider 230-1-4.

[0062] When Down Link receiver 230-1-2 receives a transmission symbol, it sends the received transmission symbol to CDR 230-1-3. CDR 230-1-3 extracts the change point of the signal level of the received transmission symbol and recovers a symbol clock synchronized with the transmission symbol rate ((5-9) in FIG. 5). CDR 230-1-3 sends the recovered symbol clock to Down Link receiver 230-1-2 and clock divider 230-1-4.

[0063] The Down Link receiver 230-1-2 synchronizes with the symbol clock recovered by the CDR 230-1-3 and determines the reception level of the transmission symbols received at the appropriate timing. This allows the Down Link receiver 230-1-2 to correctly receive the transmission symbols. The Down Link receiver 230-1-2 restores the transmission frame from the transmission symbols. The Down Link receiver 230-1-2 also determines the position of the following Link frame using a synchronization signal (sync) added to the transmission frame.

[0064] Clock divider unit 230-1-4 generates an appropriate symbol clock for UP Link transmission processing by SerDes 230. The frequency of the symbol clock generated by clock divider unit 230-1-4 is, for example, 2 GHz or 4 GHz. Clock divider unit 230-1-4 generates an UP Link symbol clock in synchronization with the Down Link symbol clock recovered by CDR 230-1-3, and supplies this to the UP Link transmitter. Clock divider unit 230-1-4 also supplies LINK unit 230-2 with a clock of an appropriate frequency used for Link frame processing in LINK unit 230-2.

[0065] The LINK unit 230-2 has a frame deconstructor 230-2-2, an OAM unit 230-2-3, and a frame constructor 230-2-1.

[0066] The frame decomposition unit 230-2-2 decodes the container header of each container ((5-2) in Figure 5) included in the Link frame ((5-3) in Figure 5) input from the Down Link receiving unit 230-1-2, and if it is a container for the OAM unit 230-2-3, sends the container payload to the OAM unit 230-2-3, or if it is an application container, sends the container payload to the decapsulator 230-4 corresponding to each application.

[0067] The decapsulator 230-4 decodes the packet header of the application packet ((5-1) in FIG. 5) corresponding to the container payload sent from the frame disassembly unit 230-2-2, determines the contents of the subsequent application packet, performs appropriate processing, and restores the application signal (I2S signal in the case of FIG. 4) before transmission. The restored application signal is sent to the corresponding application. In the case of FIG. 4, the restored I2S signal is sent to the I2S device 220. The I2S device 220 restores the I2S signal to an audio signal and plays sound from the speaker 210.

[0068] The above is the signal processing when an audio signal collected by microphone 110 is converted into an I2S protocol by I2S device 120 to generate an application packet, the generated application packet is transmitted from SerDes 130 to SerDes 230, the signal is restored to an I2S signal within SerDes 230, the I2S signal is restored to an audio signal by I2S device 220, and sound is output from speaker 210.

[0069] Conversely, it is also possible to generate an application packet in SerDes 230 based on a signal from an application connected to SerDes 230, and then transmit the packet to SerDes 130 via the UP Link in the reverse order of the above, and have the application connected to SerDes 130 regenerate the signal.

[0070] At this time, the symbol clock used for processing by UP Link transmitter 230-1-1 in SerDes 230 is synchronized with the symbol clock ((5-9) in FIG. 5) recovered by Down Link receiver 230-1-2 and CDR 230-1-3. In this way, the symbol clocks of the Down Link and the Up Link between SerDes 130 and SerDes 230 are in a synchronous relationship based on PHY clock generator 130-1-3 in SerDes 130, and UP Link receiver 130-1-2 in SerDes 130, which is the receiving side of the Up Link, can easily receive the Up Link signal from SerDes 230 using the Up Link symbol clock generated by PHY clock generator 130-1-3.

[0071] (sender details) FIG. 6 is a block diagram showing the internal configuration of the I2S device 120 on the transmitting side, the encapsulator 130-3 in the SerDes 130, and the PHY clock generating unit 130-1-3.

[0072] 6 includes an ADC 120-1, an I2S encoder 120-2, and a clock generation unit 120-3, similar to the I2S device 120 in Fig. 1. The clock generation unit 120-3 generates an audio sampling clock, an audio serial clock, and an audio master clock MCK in synchronization with the reference clock generated by the crystal 140.

[0073] The encapsulator 130-3 in FIG. 6 corresponds to the I2S device 120, and includes a FIFO 130-3-1, an MCK divider 130-3-2, a PMC (Period Measurement Counter) 130-3-3, and a packet constructor 130-3-4.

[0074] The PHY clock generation unit 130-1-3 includes a PLL circuit 130-1-3-1 and a clock divider unit 130-1-3-2. A reference clock generated by the crystal 160 is input to the PHY clock generation unit 130-1-3. The PLL circuit 130-1-3-1 generates a clock synchronized with the reference clock generated by the crystal 160. The clock divider unit 130-1-3-2 divides the clock generated by the PLL circuit 130-1-3-1 to generate a PHY clock. The PHY clock is used for internal processing in the Down Link transmitter unit 130-1-1, the Up Link receiver unit 130-1-2, and the LINK unit 130-2, as well as a reference clock for transmitting MCK. In FIG. 6, the PHY clock generated by the PHY clock generation unit 130-1-3 is called the reference clock TxREFCK.

[0075] Generally, although it depends on the individual implementation, the symbol rates of signals transmitted on the Down Link and Up Link are standardized, and for example, 2 GHz, 4 GHz, 6 GHz, and 8 GHz are standardized corresponding to the transmission speed. It is easy to generate frequencies that are divisions of these symbol rates, such as 1 GHz, 500 MHz, 250 MHz, 125 MHz, and 62.5 MHz. Therefore, in this embodiment, an example will be described in which one of 1 GHz, 500 MHz, 250 MHz, 125 MHz, and 62.5 MHz is used as the reference clock TxREFCK.

[0076] Fig. 7 is a timing diagram of TxREFCK and MCK generated based on the symbol clock of PHY clock generation unit 130-1-3. Fig. 8 is a diagram showing an example of transmission parameters used to regenerate MCK on the receiving side. Fig. 9 is a diagram showing the configuration of an application packet generated by SerDes 130.

[0077] The first I2S device 120 is connected to a crystal 140. The clock generating unit 120-3 synchronizes with the clock generated by the crystal 140 to generate a sampling clock 120-3-1, an MCK 120-3-3, and an SCK 120-3-2.

[0078] The ADC 120-1 converts the sound signal (audio signal) collected by the microphone 110 into a digital signal using a sampling clock 120-3-1. The I2S encoder 120-2 converts the digital signal into the I2S format shown in Fig. 3 and inputs it to the connected encapsulator 130-3 for I2S transmission.

[0079] The encapsulator 130-3 synchronizes the WS signal and SD from the I2S encoder 120-2 with SCK and stores them in the FIFO 130-3-1. The I2S signal in the FIFO 130-3-1 is read out with a read clock of an appropriate speed, and an application packet is generated in the packet constructor 130-3-4 ((9-3) in FIG. 9).

[0080] 7, the MCK dividing unit 130-3-2 counts the integer value N set in the control register 130-5 using the MCK input from the I2S device 120, generates a start flag every N, and outputs it to the PMC 130-3-3 ((9-1) and (9-2) in FIG. 9).

[0081] The PMC 130-3-3 counts TxREFCK to determine the length of the start flag section output from the MCK frequency division unit 130-3-2, and outputs the count value (PMC result value = M) to the packet construction unit 130-3-4 (7-3 in FIG. 7). The MCK frequency division unit 130-3-2 and PMC 130-3-3 are measurement units that measure the number of reference signals TxREFCK included in one cycle of the MCK frequency division signal.

[0082] The control register 130-5 outputs the bit length (SD bit width) of the SD (I2S audio data) to be transmitted, the number of audio channels to be transmitted, the sampling clock frequency (fs frq), the sampling clock multiplication factor K (frequency of the audio master clock MCK fmck = K × fs frq), the MCK division factor N, and frequency information of TxRFECK (TxREFCK INFO) to the packet construction unit 130-3-4.

[0083] The packet construction unit 130-3-4 stores this information and the PMC result value M in the packet header ((9-2) in FIG. 9). As described above, the packet construction unit 130-3-4 generates an application packet based on the information from the control register 130-5, the PMC result value, and the I2S signal (SD) ((9-1) in FIG. 9), and outputs it to the frame construction unit 130-2-1.

[0084] Figure 8 shows the audio master clock MCK division number N and the predicted TxREFCK count value (PMC result value M) when the TxREFCK frequency is 250 MHz, the sampling clock frequency fs is 44.1 kHz, and the audio master clock MCK is 512 times 48 kHz (K=512).

[0085] (Application packet configuration for I2S transmission) 10A and 10B are diagrams showing the configuration of an application packet for I2S signal transmission. Fig. 10A shows the configuration of the header (I2S header) of an application packet for I2S signal transmission, and Fig. 10B shows the configuration of the data (I2S data) and CRC of the application packet for I2S signal transmission.

[0086] Bits [7:5] of the first byte of the I2S header shown in Figure 10A indicate the I2S frame format. If bits [7:5] are 000, it is the I2S format, if they are 001, it is left-justified, if they are 010, it is right-justified, and if they are 011 to 111, it is reserved.

[0087] Figure 11A is a timing diagram for the original I2S format, Figure 11B is a timing diagram for the left-justified format, and Figure 11C is a timing diagram for the right-justified format.

[0088] As shown in Figure 11A, in the original I2S format, SD is transmitted bit by bit, starting with the MSB, while the WS signal is low. As shown in Figure 11B, in the left-justified format, SD is transmitted bit by bit, starting with the MSB, in synchronization with the transition of the WS signal from low to high. In other words, the SD signal is transmitted left-justified, coinciding with the rising edge of the WS signal. On the other hand, in the right-justified format, as shown in Figure 11C, SD is transmitted right-justified, with the LSB of the SD signal transmitted when the WS signal transitions from high to low. Bits [7:5] of the first byte in Figure 10A specify whether the SD signal is left-justified or right-justified.

[0089] Bits [4:3] of the first byte of the I2S header shown in Figure 10A indicate the I2S data bit width. If bits [4:3] are 00, it is 16 bits, if they are 01, it is 18 bits, if they are 10, it is 20 bits, and if they are 11, it is 24 bits.

[0090] Bits [2:0] of the first byte of the I2S header shown in Figure 10A are a 3-bit integer that represents the number of stereos. If bits [2:0] are 1, one stereo (L x R) is transmitted, and if they are 4, four stereos are transmitted.

[0091] Bits [7:5] of the second byte of the I2S header shown in Figure 10A represent the sampling clock frequency Fs. If bits [7:5] are 000, it is 44.1 kHz, if they are 001, it is 48 kHz, if they are 010, it is 96 kHz, if they are 011, it is 192 kHz, and 100 to 111 are reserved.

[0092] Bits [4:0] of the second byte of the I2S header shown in Fig. 10A are the multiplication value K for generating the audio master clock MCK. If bits [4:0] are 0x00, the value is 32; if they are 0x01, the value is 64; if they are 0x02, the value is 128; if they are 0x03, the value is 256; if they are 0x04, the value is 512; if they are 0x05, the value is 1024; and 0x06 to 0x1F are reserved.

[0093] Bits [7:5] of the third byte of the I2S header shown in FIG. 10A are reserved.

[0094] Bits [4:0] of the third byte of the I2S header shown in Figure 10A are the most significant 5 bits N[12:8] of the division ratio N of the audio master clock MCK. The division ratio N is a 13-bit integer. Bits [7:0] of the fourth byte of the I2S header shown in Figure 10A are N[7:0], which are the least significant 8 bits of the audio master clock MCK.

[0095] The division ratio N of the audio master clock MCK depends on the frequency Fm (= 24.576 MHz, 22.5792 MHz, etc.) of the audio master clock MCK. If Fm = 24.576 MHz, then N = 1536, and if Fm = 22.5792 MHz, then N = 7056.

[0096] Bit 7 of the fifth byte of the I2S header shown in Figure 10A is reserved. Bits [6:4] of the fifth byte of the I2S header shown in Figure 10A are TxREFCK information. If bits [6:4] are 000, it is 1 GHz, if they are 001, it is 500 MHz, if they are 010, it is 250 MHz, if they are 100, it is 125 MHz, if they are 101, it is 62.5 MHz, if they are 110, it is 31.25 MHz, and if they are 111, it is another frequency.

[0097] Bits [3:2] of the fifth byte of the I2S header shown in FIG. 10A are reserved. Bits [1:0] of the fifth byte of the I2S header shown in FIG. 10A are the PMC result value [17:16]. The PMC result value is 18-bit integer data. Bits [7:0] of the sixth byte of the I2S header shown in FIG. 10A are the PMC result value [15:8], and bits [7:0] of the seventh byte are the PMC result value [7:0]. The PMC result value is the value obtained by counting Fm / N (seconds) using the 250 MHz reference clock TxREFCK. Ideally, when Fm = 24.576 MHz and N = 1536, the PMC result value is 15625. When Fm = 22.5792 MHz and N = 7056, the PMC result value is 78125. The receiving device can regenerate Fm using the PMC result value and N.

[0098] The I2S data shown in FIG. 10B starts from the mth byte. Bits [7:0] of each byte are the I2S data field. More specifically, bits [7:0] of the (m+n-1+p)th byte in the I2S data are the nth stereo data, and are the I2S data [15:8] of the L channel of sample p. Bits [7:0] of the (m+1+n-1+p)th byte are the nth stereo data, and are the I2S data [7:0] of the L channel of sample p. These two bytes are the nth stereo data, and are in a data format with a 16-bit data width for the L channel.

[0099] 10B, bit [7:0] of the (m+2+n-1+p)th byte of the I2S data is the nth stereo data, and is the I2S data [15:8] of the R channel of sample p, and bit [7:0] of the (m+3+n-1+p)th byte is the nth stereo data, and is the I2S data [7:0] of the R channel of sample p. These two bytes are the nth stereo data, and are in a data format with a 16-bit data width for the R channel.

[0100] 10B, bit [7:0] of the (m+n-1+p)th byte of the I2S data is the nth stereo data, and is the I2S data [23:16] of the L channel of sample p. Bit [7:0] of the (m+1+n-1+p)th byte is the nth stereo data, and is the I2S data [15:8] of the L channel of sample p. Bit [7:0] of the (m+2+n-1+p)th byte is the nth stereo data, and is the I2S data [7:0] of the L channel of sample p. These three bytes are the nth stereo data, and are in a data format with a data width of 18, 20, or 24 bits for the L channel. If the data width is 18 or 20 bits, bit fields larger than the data width are filled with zeros.

[0101] 10B, bit [7:0] of the (m+3+n-1+p)th byte of the I2S data is the nth stereo data, and is the I2S data [23:16] of the R channel of sample p. Bit [7:0] of the (m+4+n-1+p)th byte is the nth stereo data, and is the I2S data [15:8] of the R channel of sample p. Bit [7:0] of the (m+5+n-1+p)th byte is the nth stereo data, and is the I2S data [7:0] of the R channel of sample p. These three bytes are the nth stereo data, and are in a data format with a data width of 18, 20, or 24 bits for the R channel. If the data width is 18 or 20 bits, bit fields larger than the data width are filled with zeros.

[0102] In Figure 10B, bits [7:0] of the kth byte of the CRC are CRC32[31:24], bits [7:0] of the k+1th byte are CRC32[23:16], bits [7:0] of the k+2th byte are CRC32[15:8], and bits [7:0] of the k+3rd byte are CRC32[7:0]. The CRC32 checks each GPIO payload from the GPIO header to the end of the GPIO data. The cyclic redundancy check (CRC) uses the polynomial ring 0xF4ACFB13.

[0103] (Receiver details) Next, we will explain the internal configuration and operation of the SerDes 230. Fig. 12 is a block diagram showing the internal configuration of the de-encapsulator 230-4 in the SerDes 230. The de-encapsulator 230-4 has a packet deconstructor 230-4-1, a FIFO 230-4-2, an I2S encoder (I2S ENC) 230-4-3, a REFCK ratio calculation unit (REFCK ratio Calc) 230-4-4, a TxREFCK regenerator (TxREFCK regenerator) 230-4-5, a TxREFCK divider (TxREFCK Divider) 230-4-6, an MCK regenerator (MCK regenerator) 230-4-7, and an SCK regenerator (SCK regenerator) 230-4-8.

[0104] The SerDes 230 recovers the frequency fmck of the MCK generated by the transmitting I2S device 120 and transmits it to the I2S device 220 together with the recovered I2S signals (SCK, WS signal, SD).

[0105] As already explained, CDR 230-1-3 in PHY unit 230-1 in SerDes 230 on the receiving side extracts the signal level change points from the received transmission symbols and regenerates a symbol clock ((5-9) in FIG. 5) synchronized with the transmission symbol rate transmitted from SerDes 130. Clock divider unit (230-1-4) divides the symbol clock ((5-9) in FIG. 5) supplied from CDR 230-1-3 to generate the clocks required for processing in each unit. As with SerDes 130 on the transmitting side, these clock frequencies depend on the individual implementation, but frequencies such as 1 GHz, 500 MHz, 250 MHz, 125 MHz, and 62.5 MHz, which are in a division relationship with the symbol rate, can be easily generated while maintaining synchronization with the transmitting-side symbol clock.

[0106] The reference clock (RxREFCK) for reproducing the I2S audio master clock MCK on the playback side uses one of the above-mentioned frequencies, such as 1 GHz, 500 MHz, 250 MHz, 125 MHz, or 62.5 MHz. Which frequency is used depends on the implementation, so control register 230-5 supplies that information (RxREFCK_INFO) to de-encapsulator 230-4 for I2S signal transmission. At the same time, clock divider 230-1-4 supplies de-encapsulator 230-4 with the reference clock (RxREFCK) of the frequency specified by control register 230-5.

[0107] Next, the operation of the decapsulator 230-4 will be described. The frame disassembly unit 230-2-2 extracts the application packet ((9-1) in FIG. 9) that transmits the I2S signal, and supplies it to the packet disassembly unit 230-4-1.

[0108] The packet disassembly unit 230-4-1 analyzes the packet header ((9-2) in Figure 9) of the application packet ((9-1) in Figure 9) and obtains information for playing the I2S protocol, the bit width of the SD (I2S audio data) to be transmitted, the number of audio channels to be transmitted, the sampling clock frequency (fs frq), the sampling clock multiplication factor K (frequency of the audio master clock MCK fmck = K × fs frq), the MCK division factor N, the reference clock frequency information (TxREFCK INFO), and the TxREFCK count value (PMC result value).

[0109] The RFECK ratio calculation unit 230-4-4 calculates the frequency ratio R (=TxREFCK frequency / RxREFCK frequency) using the frequency information of the transmitting side REFCK (TxREFCK INFO) and the frequency information of the receiving side REFCK (RxREFCK INFO) obtained from the control register 230-5.

[0110] The TxREFCK regenerator 230-4-5 uses the obtained frequency ratio R to regenerate TxREFCK synchronized with RxREFCK by multiplying the frequency of RxREFCK by R if R≧1, or by dividing RxREFCK by R if R<1. The regenerated TxREFCK has the same frequency as TxREFCK on the transmitting side.

[0111] The TxRFECK divider 230-4-6 divides the TxREFCK supplied from the TxREFCK reproducing unit 230-4-5 by the PMC result value M acquired by the packet disassembling unit 230-4-1, and outputs the divided TxREFCK / M to the MCK reproducing unit 230-4-7.

[0112] The MCK reproduction unit 230-4-7 reproduces the audio master clock MCK synchronized with the audio master clock MCK on the transmitting side by multiplying TxREFCK / M by N using the MCK frequency division number N on the transmitting side acquired by the packet disassembly unit 230-4-1. The above operation is the most important part of the MCK reproduction procedure.

[0113] The SCK reproducing unit 230-4-8 reproduces SCK by multiplying the cycle of MCK by the reciprocal of K, which is the ratio of the sampling clock frequencies fs and frq, and twice the bit width (SDBW) of SD.

[0114] On the other hand, the packet disassembler 230-4-1 extracts packetized SD (audio serial data) ((9-3) in FIG. 9) from the application packet ((9-1) in FIG. 9) and writes it to the FIFO 230-4-2 using a write clock with an appropriate frequency.

[0115] The SD written to the FIFO 230-4-2 is read out by SCK and supplied to the I2S encoder 230-4-3.

[0116] The I2S encoder 230-4-3 reproduces the I2S signal shown in Fig. 3 using the SD, as well as information required for conversion into an I2S signal supplied from the packet disassembly unit 230-4-1, the bit width of the SD, the number of audio channels to be transmitted, and the sampling clock frequency (fs frq). The I2S signal including the SCK, WS signal, and SD is output to the I2S device 220 connected to the SerDes 230, and the MCK reproduced by the MCK reproduction unit 230-4-7 is also output to the I2S device 220.

[0117] The I2S device 220 converts the I2S signal into an analog audio signal in synchronization with MCK, and the signal is finally output as sound from the speaker 210.

[0118] Through the above procedure, the frequency information of the MCK on the transmitting side is transmitted to the receiving side, and the MCK can be accurately reproduced on the receiving side using the PHY clock that is synchronized between the transmitting and receiving sides.

[0119] As described above, in the first embodiment, the SerDes 130 receives the WS signal, SD, and SCK conforming to the I2S standard, and the MCK signal having a frequency obtained by multiplying the SCK frequency. The SerDes 130 measures the number of reference clocks TxREFCK included in a predetermined cycle of the MCK frequency-divided signal. The SerDes 230 generates a packet including the measured number, frequency information of the reference clock TxREFCK, the division ratio N of the MCK frequency-divided signal, and the frequency ratio K of the MCK frequency to the sampling clock frequency fs, and transmits the packet to the SerDes 230. The SerDes 230 receives the packet and can restore the MCK based on the information included in the packet. Therefore, even when the SerDes 130 and the SerDes 230 transmit and receive packets at timings asynchronous with the I2S signal, the SerDes 230 can restore and correctly reproduce the I2S signal from the packet received.

[0120] (Second embodiment) In the first embodiment, the I2S device 120 operates asynchronously with the SerDes 130, but the I2S device 120 and the SerDes 130 may operate with clocks that are synchronized with each other.

[0121] FIG. 13 is a block diagram showing the internal configuration of an I2S device 120 according to a second embodiment, and the encapsulator 130-3 and PHY clock generation units 130-1-3 in the SerDes 130. The I2S device 120 in FIG. 13 is connected to a clock generation unit 130-6 instead of the crystal 140 in FIG. 6. The reference clock TxREFCK generated by the PHY unit 130-1 is input to the clock generation unit 130-6. The clock generation unit 130-6 generates a reference clock of, for example, 250 MHz in synchronization with the reference clock TxREFCK. The clock generation unit 120-3 in the I2S device 120 generates a sampling clock of, for example, 50 kHz and a 25.6 MHz MCK in synchronization with the 250 MHz reference clock generated by the clock generation unit 130-6.

[0122] The SerDes 130 according to the second embodiment operates in the same manner as the SerDes 130 according to the first embodiment, but the parameters set by the control register 130-5 are different. Fig. 14 is a diagram showing the values ​​of parameters used when the SerDes 230 according to the second embodiment regenerates MCK. In the second embodiment, TxREFCK and MCK are in an integer multiple relationship, with N=64 and the PMC result value M=625.

[0123] As described above, in the second embodiment, the I2S device 120 operates in synchronization with the reference clock TxREFCK generated by the PHY unit 130-1 in the SerDes 130, so the frequencies of the audio master clocks MCK and TxREFCK can be integer multiples. Furthermore, in the second embodiment, the I2S device 120 generates an I2S signal in synchronization with a PHY clock shared by the physical layers of the transmitting SerDes 130 and the receiving SerDes 230, eliminating the need for the crystal 140 in FIG. 6. Furthermore, the I2S device 120 according to the second embodiment generates an I2S signal at a higher frequency than in the first embodiment, thereby improving jitter characteristics on the playback side.

[0124] (Third embodiment) The SerDes 130 and the SerDes 230 can manage time stamp information synchronized with each other. For example, when the SerDes 130 and the SerDes 230 perform high-speed serial communication in accordance with the ASA standard, the ASA standard defines a Precision Time Base (PTB). The PTB allows the SerDes 130 and the SerDes 230 to synchronize time information with a resolution of 4 ns by exchanging packets that serve as a time reference between them. The time information of the PTB is synchronized with a 250 MHz clock (hereinafter referred to as the PTB clock), and this clock is used as TxREFCK. In this case, since the frequency of TxREFCK is fixed at 250 MHz, it is not necessary to transmit the frequency information of TxREFCK to the receiving side. As in the first embodiment, other information (such as N and K) needs to be included in the header of the application packet and transmitted to the SerDes 230. Similarly, the SerDes 230 does not need the frequency information of RxREFCK.

[0125] Fig. 15 is a block diagram showing the internal configuration of an encapsulator 130-3 in a SerDes 130 according to the third embodiment. The encapsulator 130-3 in Fig. 15 has a FIFO 130-3-1, an MCK frequency divider 130-3-2, a PMC 130-3-3, and a packet constructor 130-3-4, similar to Fig. 6. Instead of receiving the reference clock TxREFCK generated by the PHY clock generator 130-1-3 in Fig. 6, the encapsulator 130-3 in Fig. 15 receives the PTB clock generated by the PTB clock generator 130-7.

[0126] Fig. 16 is a block diagram showing the internal configuration of a de-encapsulator 230-4 in a SerDes 230 according to the third embodiment. The de-encapsulator 230-4 in Fig. 16 includes a packet disassembly unit 230-4-1, a FIFO 230-4-2, an I2S encoder (I2S ENC) 230-4-3, a TxREFCK frequency division unit 230-4-6, an MCK regeneration unit 230-4-7, and an SCK regeneration unit 230-4-8, similar to Fig. 12. Instead of receiving the reference clock RxREFCK generated by the PHY unit 230-1 in Fig. 12, the de-encapsulator 230-4 in Fig. 16 receives the PTB clock generated by the PTB clock generation unit 230-6.

[0127] The PTB clock generation unit 130-7 and the PTB clock generation unit 230-6 generate a PTB clock that synchronizes the Precision Time Base (PTB) standardized in the ASA standard. The PTB can synchronize time information with a resolution of 4 nsec by exchanging packets that serve as a time reference between the SerDes 130 and SerDes 230. The 250 MHz PTB clock used to generate this PTB information is used as TxREFCK and RxREFCK. In this case, TxREFCK and RxREFCK are fixed at 250 MHz, and PTB clocks of the same frequency are generated on the transmitting and receiving sides, so there is no need to transmit TxREFCK INFO to the receiving side. Other information and operations are the same as those of the SerDes 130 and SerDes 230 according to the first embodiment.

[0128] In this way, the PTB clock used to generate PTB information used by SerDes 130 and SerDes 230 to manage timestamp information is used as the reference clocks TxREFCK and RxREFCK, so there is no need to send information about TxREFCK from SerDes 130 to SerDes 230 and regenerate TxREFCK within SerDes 230, which reduces the amount of information sent and received between SerDes 130 and SerDes 230 and simplifies the internal configuration of SerDes 130 and SerDes 230.

[0129] (Fourth embodiment) In the fourth embodiment, not only the SerDes 130 and the SerDes 230 but also the I2S device 120 uses the PTB clock.

[0130] 17 is a block diagram showing the internal configuration of an I2S device 120 and an encapsulator 130-3 in a SerDes 130 according to the fourth embodiment. Instead of receiving a clock generated by the crystal 140, the I2S device 120 receives a 250 MHz PTB clock generated by a PTB clock generation unit 130-7.

[0131] This allows the I2S signals (SCK, SD, WS signals, and MCK) generated by the I2S device 120 to be synchronized with the PTB clock. Also, the crystal 140 can be omitted.

[0132] (Fifth embodiment) The fifth embodiment is characterized in that, instead of transmitting MCK frequency information from the SerDes 130 to the SerDes 230, a WS signal indicating the frequency of the sampling clock is transmitted.

[0133] Fig. 18 is a block diagram showing the internal configuration of the I2S device 120 and the encapsulator 130-3 in the SerDes 130 according to the fifth embodiment. Fig. 19 is a timing diagram of packets transmitted between the SerDes 130 and the SerDes 230. Fig. 20 is a diagram showing the configuration of an application packet generated by the SerDes 130.

[0134] The internal configuration of the I2S device 120 in Figure 18 is the same as that in Figures 6 and 15. The encapsulator 130-3 in the SerDes 130 in Figure 18 has a FIFO 130-3-1, a packet assembly unit 130-3-4, and a PTB timestamp ler 130-3-5. The PTB timestamp ler 130-3-5 is provided in place of the MCK divider unit 130-3-2 and PMC 130-3-3 in Figure 15. The PTB timestamp ler 130-3-5 operates in synchronization with the PTB clock.

[0135] The PTB timestamp maker 130-3-5 receives a WS signal indicating the frequency of the sampling clock from the I2S device 120 and a PTB time with a resolution of 4 nsec (250 MHz) from the PTB timer 130-8. This PTB time is synchronized with the PTB time on the receiving side by the PTB synchronization process standardized by the ASA standard.

[0136] The PTB timestamp maker 130-3-5 samples the rising edge of the input WS, i.e., approximately the center of one sample interval of the I2S data, using the PTB time with 4 nsec resolution (250 MHz) supplied from the PTB timer 130-8, and supplies the PTB time to the packet assembly unit 130-3-4.

[0137] The packet constructor 130-3-4 obtains the speed-adjusted I2S audio data SD and WS via the FIFO 130-3-1. The packet constructor 130-3-4 includes the obtained SD in an application packet at the timing requested by the frame constructor (130-2-1) ((19-2) and 19-4) in FIG. 19. The SD arrangement may be the same as that shown in (9-3) in FIG. 9. Therefore, the number of SD samples included in each application packet is not constant but increases or decreases. In the example in FIG. 19, the nth packet includes an SD consisting of L samples, and the (n+1)th packet includes an SD consisting of J samples ((19-2) in FIG. 19).

[0138] The packet construction unit 130-3-4 includes the number of SD samples in the header of each application packet (19-4 in FIG. 19).

[0139] Furthermore, the packet construction unit 130-3-4 includes in the packet header the PTB times TS1 and TS2 of the first and last SDs to be included in the application packet, out of the PTB times of the rising edge of WS for each SD output from the PTB timestamp maker 130-3-5 (19-4 in Figure 19).

[0140] The packet construction unit 130-3-4 further obtains from the control register 130-5 the bit length (SD bit width) of the SD (I2S audio data) to be transmitted, the number of audio channels to be transmitted, and the sampling clock frequency (fs frq) as reference information, and includes this information, TS1, TS2, and the number of samples together in the packet header.

[0141] In this way, the packet header generated by the packet constructor 130-3-4 has the SD bit width, the number of channels, the sampling clock frequency fs frq, TS1, TS2, and the number of samples, as shown in FIG.

[0142] The SD bit width is the bit width of the SD (I2S audio serial data) for each channel. The number of channels is the number of audio channels. For example, if the number of channels = 2, it means normal stereo. fs frq is the frequency of the audio sampling clock, such as 44.1 kHz or 48 kHz. TS1 is the timing of the rising edge of WS in the first SD of the multiple SDs in a packet. TS2 is the timing of the rising edge of WS in the last SD of the multiple SDs in a packet. The number of samples is the number of SD samples contained in one packet.

[0143] The application packet following the packet header contains multiple SDs, the number of which corresponds to the number of samples. Each SD is serial data specified by a sample number and a channel number. The packet construction unit 130-3-4 assembles the packet header and the application packet containing the multiple SDs into an application packet (19-4 in FIG. 19) and outputs it to the frame construction unit 130-2-1.

[0144] The frame constructor 130-2-1 adds a synchronization signal to each of the application packets to construct a transmission frame, which is then finally output to the channel. These processes are the same as those in ((5-4)) to ((5-7)) of Figure 5, so a detailed description will be omitted.

[0145] Next, the processing on the receiving side will be described. The processing operation of the frame decomposition unit in the SerDes 230 is the same as in the first to fourth embodiments.

[0146] Fig. 21 is a block diagram showing the internal configuration of a de-encapsulator 230-4 in the SerDes 230 according to the fifth embodiment. The de-encapsulator 230-4 in Fig. 21 includes a packet disassembly unit 230-4-1, a FIFO 230-4-2, an I2S encoder 230-4-3, an MCK regeneration unit 230-4-7, an SCK regeneration unit 230-4-8, a WS frequency calculation unit, and a PTB clock division unit.

[0147] The processing operation of the packet disassembler 230-4-1 is the same as in the first to fourth embodiments. The packet disassembler 230-4-1 acquires PTB timestamps TS1 and TS2 representing the rising edge positions of the WS of the first and last data of the SD of the sample number L included in the packet header of the received application packet, and the sample number, and supplies these to the WS frequency calculator 230-4-9. The WS frequency calculator 230-4-9 calculates (TS2-TS1) / (sample number). The calculation result represents the average period of the audio sampling clock frequency.

[0148] In addition, by adding and averaging the calculation results of (TS2-TS1) / (number of samples) obtained for each of multiple packets, it is possible to obtain a more accurate sampling clock frequency period. The WS frequency calculation unit 230-4-9 outputs the obtained period to the PTB clock division unit 230-4-10.

[0149] The PTB clock frequency divider 230-4-10 divides the 250 MHz clock supplied from the PTB clock 230-6 by the value obtained from the WS frequency calculator 230-4-9 to generate a WS signal. The frequency of the WS signal is the same as the frequency of the sampling clock.

[0150] The MCK reproduction unit 230-4-7 reproduces the audio master clock MCK required for processing in the I2S device 220 by multiplying the WS signal generated by the PTB clock frequency division unit 230-4-10 by K, using the constant K obtained from the control register 230-5.

[0151] Furthermore, the SCK regenerator 230-4-8 regenerates the SCK by setting the SCK period to the period of the WS signal multiplied by the bit width of the SD and 2. In synchronization with this SCK, the SD is read from the FIFO 230-4-2 and the read SD is encoded by the I2S encoder 230-4-3. The processing after the I2S encoder 230-4-3 is the same as that of the SerDes 230 in the first to fourth embodiments, and therefore a description thereof will be omitted.

[0152] 22A and 22B are diagrams showing in more detail the configuration of an application packet for I2S signal transmission generated by the SerDes 130 according to the fifth embodiment. Fig. 22A shows the configuration of the header (I2S header) of the application packet for I2S signal transmission, and Fig. 22B shows the configuration of the data (I2S data) and CRC of the application packet for I2S signal transmission.

[0153] Figure 22B is the same as Figure 10B, so a description will be omitted. The latter half of the I2S header in Figure 22A is different from the I2S header in Figure 10A. The following description will focus on the differences from the I2S header in Figure 10A.

[0154] Bits [7:5] of the first and second bytes of the I2S header shown in Figure 22A are the same as those in Figure 10A. Bits [4:0] of the second byte of the I2S header shown in Figure 22A are reserved. Bits [7:0] of the third byte of the I2S header shown in Figure 22A are TS1[23:16], bits [7:0] of the fourth byte are TS1[15:8], and bits [7:0] of the fifth byte are TS1[7:0]. In these third to fifth bytes, TS1 is a 24-bit integer, and is the PTB time of the rising edge of the WS signal in the first SD of the multiple SDs in the packet.

[0155] 22A, bits [7:0] of the 6th byte are TS2[23:16], bits [7:0] of the 7th byte are TS2[15:8], and bits [7:0] of the 8th byte are TS2[7:0]. In these 6th to 8th bytes, TS2 is a 24-bit integer, and is the PTB time of the rising edge of the WS signal in the last SD of the multiple SDs in the packet.

[0156] In the I2S header shown in Figure 22A, bits [7:0] of the 9th byte are the number of samples [15:8], and bits [7:0] of the 10th byte are the number of samples [7:0]. These 9th and 10th bytes are a 16-bit integer that represents the number of I2S data samples transmitted in this packet.

[0157] Of the values ​​included in the packet headers shown in Figures 9, 10A, 20, and 22A described above, setting information such as the bit width of the SD (I2S audio data) to be transmitted, the number of audio channels to be transmitted, the sampling clock frequency (fs frq), the sampling clock multiplication factor K (MCK frequency fmck = K × fs frq), the MCK division factor N, and reference clock frequency information (TxREFCK INFO) that does not need to be transmitted for each packet transmission once may be transmitted from the transmitting side to the receiving side using an OAM channel or other information transmission means, in addition to being included in the packet header.

[0158] Furthermore, the application packets ((9-1) in Fig. 9 and (20-1) in Fig. 20) that transmit I2S signals as explained above and shown in Fig. 9 and Fig. 20 may not only be transmitted as a single independent application, but may also be placed in an application packet that transmits video data and transmitted, as shown in Fig. 23. In the example of Fig. 23, multiple pieces of video data are included in the application packet, and I2S audio data is included between these pieces of video data.

[0159] In this way, in the fifth embodiment, the timing TS1 of the rising edge of the WS signal in the first SD among the multiple SDs in the application packet, the timing TS2 of the rising edge of the WS signal in the last SD, and the number of SD samples are included in the packet header, so that the average period of the sampling clock frequency can be calculated and the WS signal can be generated based on the calculation result. Therefore, according to the fifth embodiment, it is no longer necessary to transmit MCK from the SerDes 130 on the transmitting side to the SerDes 230 on the receiving side as in the first to fourth embodiments and to count the number of reference clocks TxREFCK included in the MCK frequency-divided signal in the SerDes 230, and the configuration within the SerDes 230 can be simplified.

[0160] The present technology can be configured as follows: (1) a measurement unit that measures the number of predetermined reference clocks included in one cycle of an audio master clock having a frequency obtained by multiplying the frequency of a sampling clock for sampling an audio signal, based on a division ratio of a frequency-divided signal of the audio master clock, and the predetermined reference clock; a packet generation unit that generates a packet including information including the number measured by the measurement unit, a bit width of SD (Serial Data) conforming to the I2S standard, the frequency of the sampling clock, a division ratio of the divided signal to the audio master clock, a frequency ratio of the frequency of the audio master clock to the frequency of the sampling clock, and the SD. (2) the packet generated by the packet generation unit includes a header portion and a data portion; the header section includes the number measured by the measurement section, the bit width of the SD, the frequency of the sampling clock, the division ratio, and the frequency ratio; The communication device according to (1), wherein the data section includes a plurality of the SDs. (3) A communication device as described in (2), wherein the header section includes the bit width of the SD, the number of channels of the SD, the frequency of the sampling clock, the division ratio of the divided signal to the audio master clock, the frequency ratio of the audio master clock frequency to the sampling clock frequency, the frequency of the reference clock, and the number measured by the measurement section. (4) The communication device according to (3), wherein the data section includes the SD for the number of channels and the number of samples. (5) a physical layer clock generating unit that generates a clock that is commonly used in the physical layers of both the communication device and the communication partner device; The communication device according to any one of (1) to (4), further comprising: a frequency divider that divides the frequency of the clock generated by the physical layer clock generator to generate the reference clock. (6) The communication device according to (5), wherein the frequency of the clock generated by the physical layer clock generating unit is 250 MHz. (7) the frequency of the audio master clock is 25.6 MHz; The communication device according to (6), wherein the frequency of the sampling clock is 50 kHz. (8) A communication device according to any one of (1) to (7), wherein the sampling clock and the audio master clock are asynchronous with the reference clock. (9) A communication device according to any one of (1) to (7), wherein the sampling clock and the audio master clock are synchronized with the reference clock. (10) A PTB (Precision Time Base) clock generating unit is provided for generating a PTB clock used to generate timestamp information commonly used with a communication partner device; The communication device according to any one of (1) to (4), wherein the reference clock is the PTB clock. (11) The communication device according to (10), wherein the audio master clock is synchronized with the PTB clock. (12) A communication device according to (10) or (11), wherein the frequency of the PTB clock is 250 MHz. (13) A measurement unit that receives a WS (Word Select) signal conforming to the I2S standard, and measures, based on a predetermined reference clock shared with the communication partner device, first timing information indicating the timing of a logic change of the WS signal in the first SD among a plurality of SDs (Serial Data) included in one packet transmitted to the communication partner device, and second timing information indicating the timing of a logic change of the WS signal in the last SD; A communication device comprising: a bit width of the SD, a frequency of a sampling clock for sampling an audio signal, the first timing information, the second timing information, the number of the SDs included in one packet, and a packet generation unit that generates the packet including the SDs. (14) The communication device according to (13), wherein the packet generation unit generates the packet further including information on the number of channels of the SD. (15) A restoration unit that receives a packet transmitted from a communication partner device and restores from the packet the following: SD (Serial Data) conforming to the I2S standard, the bit width of the SD, the frequency of a sampling clock for sampling an audio signal, the frequency ratio of an audio master clock to the frequency of the sampling clock, the number of predetermined first reference clocks included in one cycle of a frequency-divided signal of the audio master clock, the frequency of the sampling clock, and the frequency division ratio of the frequency-divided signal to the audio master clock; an audio master clock reproducing unit that reproduces the audio master clock based on the number of the first reference clocks, the frequency of the first reference clock, and the frequency division ratio; a SCK reproducing unit that reproduces an SCK (Serial Clock) based on the bit width information of the SD, the frequency ratio, and the audio master clock; (16) a clock recovery circuit that generates a second reference clock synchronized with a signal change of the SD based on the packet; a frequency ratio calculation unit that calculates a frequency ratio between the frequency of the first reference clock and the frequency of the second reference clock, The communication device described in (15), wherein the audio master clock reproduction unit reproduces the audio master clock based on the number of the first reference clocks, frequency information of the first reference clock, the division ratio, and the frequency ratio calculated by the frequency ratio calculation unit. (17) A PTB (Precision Time Base) clock generating unit is provided for generating a PTB clock used to generate timestamp information commonly used between the communication partner device and the communication partner device; The communication device according to (15) or (16), wherein the first reference clock is the PTB clock. (18) A restoration unit that receives a packet transmitted from a communication partner device and restores from the packet an SD (Serial Data) conforming to the I2S standard, bit width information of the SD, frequency information of an SCK (Serial Clock), first timing information indicating the timing at which a WS (Word Select) signal included in one of the packets first changed in logic, second timing information indicating the timing at which a WS signal last changed in logic, and the number of the SDs included in one of the packets; a clock generating unit that generates a reference clock that is used in common with the communication partner device; a WS signal reproducing unit that reproduces the WS signal based on the first timing information, the second timing information, the number of SDs, and the reference clock; an audio master clock reproducing unit that regenerates an audio master clock by multiplying the frequency of the WS signal reproduced by the WS signal reproducing unit; a SCK reproducing unit that reproduces the SCK based on the WS signal reproduced by the WS signal reproducing unit and bit width information of the SD; (19) A PTB (Precision Time Base) clock generating unit is provided for generating a PTB clock used to generate timestamp information commonly used between the communication partner device and the communication partner device; The communication device according to (14) or (18), wherein the reference clock is the PTB clock. (20) The communication device according to any one of (1) to (19), wherein the packet is transmitted within a period allocated by TDD (Time Division Duplex). (21) a first communication device; a second communication device that performs serial communication with the first communication device; the first communication device, a measurement unit that measures the number of predetermined reference clocks included in one cycle of a frequency-divided signal based on an audio master clock having a frequency obtained by multiplying the frequency of a sampling clock for sampling an audio signal, a frequency division ratio of a frequency-divided signal of the audio master clock, and a predetermined reference clock; a packet generation unit that generates a packet including information including the number measured by the measurement unit, a bit width of SD (Serial Data) conforming to the I2S standard, the frequency of the sampling clock, a division ratio of the divided signal to the audio master clock, a frequency ratio of the frequency of the audio master clock to the frequency of the sampling clock, and the SD; the second communication device, a restoration unit that receives a packet transmitted from the first communication device and restores from the packet the SD, the bit width of the SD, the frequency of the sampling clock, the frequency ratio of the audio master clock frequency to the sampling clock frequency, the number of predetermined first reference clocks included in one cycle of the divided signal of the audio master clock, the frequency of the sampling clock, and the division ratio of the divided signal to the audio master clock; an audio master clock reproducing unit that reproduces the audio master clock based on the number of the first reference clocks, the frequency of the first reference clock, and the frequency division ratio; a SCK reproducing unit that reproduces an SCK (Serial Clock) based on the bit width information of the SD, the frequency ratio, and the audio master clock; (22) a first communication device; a second communication device that performs serial communication with the first communication device; the first communication device, a measurement unit that receives a WS (Word Select) signal conforming to the I2S standard, and measures, based on a predetermined reference clock shared with the second communication device, first timing information indicating the timing of a logic change of the WS signal in the first SD among a plurality of SDs (Serial Data) included in one packet transmitted to the second communication device, and second timing information indicating the timing of a logic change of the WS signal in the last SD; a packet generation unit that generates a packet including the bit width of the SD, the frequency of a sampling clock that samples an audio signal, the first timing information, the second timing information, the number of the SDs included in one packet, and the SDs; the second communication device, a restoration unit that receives a packet transmitted from the second communication device and restores from the packet SD (Serial Data) conforming to the I2S standard, bit width information of the SD, frequency information of an SCK (Serial Clock), first timing information indicating the timing at which a WS (Word Select) signal included in one of the packets first changed in logic, second timing information indicating the timing at which a WS signal last changed in logic, and the number of the SDs included in one of the packets; a clock generating unit that generates a reference clock that is used in common with the first communication device; a WS signal reproducing unit that reproduces the WS signal based on the first timing information, the second timing information, the number of SDs, and the reference clock; an audio master clock reproducing unit that regenerates an audio master clock by multiplying the frequency of the WS signal reproduced by the WS signal reproducing unit; a SCK regenerator that regenerates the SCK based on the WS signal regenerated by the WS signal regenerator and bit width information of the SD;

[0161] The aspects of the present disclosure are not limited to the individual embodiments described above, but include various modifications that may be conceived by those skilled in the art, and the effects of the present disclosure are not limited to the above-described contents. In other words, various additions, modifications, and partial deletions are possible within the scope of the conceptual idea and spirit of the present disclosure, which is derived from the contents defined in the claims and their equivalents. [Explanation of symbols]

[0162] 1 communication system, 10 first communication module, 20 second communication module, 100 first communication module, 110 microphone (hereinafter referred to as microphone), 120 first I2S device, 120-2 I2S encoder, 120-3 clock generation unit, 130 SerDes, 130-1 PHY unit, 130-1-1 Link transmission unit, 130-1-2 Link reception unit, 130-1-3 PHY clock generation unit, 130-1-3-1 PLL circuit, 130-1-3-2 clock division unit, 130-2 LINK unit, 130-2-1 frame construction unit, 130-2-2 frame disassembly unit, 130-2-3 OAM unit, 130-3 encapsulator, 130-3-2 MCK division unit, 130-3-4 packet construction unit, 130-3-5 PTB timestamp maker, 130-4 de-encapsulator, 130-5 control register, 130-6 clock generation unit, 130-7 PTB clock generation unit, 130-8 PTB timer, 130t SerDes, 150 camera, 200 second communication module, 210 speaker, 220 I2S device, 220-1 I2S decoder, 220-3 clock division unit, 230 SerDes, 230-1 PHY unit, 230-1-1 Link transmission unit, 230-1-2 Link reception unit, 230-1-4 clock division unit, 230-2 LINK unit, 230-2-2 frame disassembly unit, 230-2-3 OAM unit, 230-3 encapsulator, 230-4-3 I2S encoder, 230-4 de-encapsulator, 230-4-1 Packet disassembly unit, 230-4-10 PTB clock division unit, 230-4-3 I2S encoder, 230-4-4 RFECK ratio calculation unit, 230-4-5 TxREFCK regeneration unit, 230-4-6 TxREFCK division unit, 230-4-7 MCK regeneration unit, 230-4-7 Regeneration unit, 230-4-8 SCK regeneration unit, 230-4-8 Regeneration unit, 230-4-9 WS frequency calculation unit, 230-5 Control register, 230-6 PTB clock generation unit, 230-6 Clock, 250 Video decoder, 250MHz resolution, 260 ADAS / ADS processor, 300 Transmission cable

Claims

1. a measurement unit that measures the number of predetermined reference clocks included in one cycle of a frequency-divided signal based on an audio master clock having a frequency obtained by multiplying the frequency of a sampling clock for sampling an audio signal, a frequency division ratio of a frequency-divided signal of the audio master clock, and a predetermined reference clock; a packet generation unit that generates a packet including information including the number measured by the measurement unit, a bit width of SD (Serial Data) conforming to the I2S standard, the frequency of the sampling clock, a division ratio of the divided signal to the audio master clock, a frequency ratio of the frequency of the audio master clock to the frequency of the sampling clock, and the SD.

2. the packet generated by the packet generation unit includes a header portion and a data portion, the header section includes the number measured by the measurement section, the bit width of the SD, the frequency of the sampling clock, the division ratio, and the frequency ratio; The communication device according to claim 1 , wherein the data section includes a plurality of the SDs.

3. 3. The communication device according to claim 2, wherein the header section includes the bit width of the SD, the number of channels of the SD, the frequency of the sampling clock, the division ratio of the divided signal to the audio master clock, the frequency ratio of the frequency of the audio master clock to the frequency of the sampling clock, the frequency of the reference clock, and the number measured by the measurement section.

4. The communication device according to claim 3 , wherein the data section includes the SDs for the number of channels and the number of samples.

5. a physical layer clock generating unit that generates a clock that is commonly used in the physical layers of both the communication device and the communication partner device; The communication device according to claim 1 , further comprising: a frequency divider that divides the frequency of the clock generated by the physical layer clock generator to generate the reference clock.

6. 6. The communication device according to claim 5, wherein the frequency of the clock generated by said physical layer clock generating unit is 250 MHz.

7. The frequency of the audio master clock is 25.6 MHz, 7. The communication device according to claim 6, wherein the frequency of the sampling clock is 50 kHz.

8. The communication device according to claim 1 , wherein the sampling clock and the audio master clock are asynchronous with the reference clock.

9. The communication device according to claim 1 , wherein the sampling clock and the audio master clock are synchronized with the reference clock.

10. a PTB (Precision Time Base) clock generating unit that generates a PTB clock used to generate timestamp information commonly used between the communication device and the communication partner device; The communication device according to claim 1 , wherein the reference clock is the PTB clock.

11. The communication device of claim 10 , wherein the audio master clock is synchronized with the PTB clock.

12. 12. The communication device according to claim 10, wherein the frequency of the PTB clock is 250 MHz.

13. a restoration unit that receives a packet transmitted from a communication partner device and restores from the packet the following: SD (Serial Data) conforming to the I2S standard, the bit width of the SD, the frequency of a sampling clock for sampling an audio signal, the frequency ratio of an audio master clock to the frequency of the sampling clock, the number of predetermined first reference clocks included in one cycle of a frequency-divided signal of the audio master clock, the frequency of the sampling clock, and the frequency division ratio of the frequency-divided signal to the audio master clock; an audio master clock reproducing unit that reproduces the audio master clock based on the number of the first reference clocks, the frequency of the first reference clock, and the frequency division ratio; a SCK reproducing unit that reproduces an SCK (Serial Clock) based on the bit width information of the SD, the frequency ratio, and the audio master clock;

14. a clock recovery circuit that generates a second reference clock synchronized with a signal change of the SD based on the packet; a frequency ratio calculation unit that calculates a frequency ratio between the frequency of the first reference clock and the frequency of the second reference clock, 14. The communication device according to claim 13, wherein the audio master clock reproducing unit reproduces the audio master clock based on the number of the first reference clocks, frequency information of the first reference clocks, the frequency division ratio, and the frequency ratio calculated by the frequency ratio calculating unit.

15. a PTB (Precision Time Base) clock generation unit that generates a PTB clock used to generate timestamp information commonly used between the communication partner device and the communication partner device; 15. The communication device according to claim 13, wherein the first reference clock is the PTB clock.

16. The communication device according to claim 1 , wherein the packet is transmitted within a period allocated in TDD (Time Division Duplex).

17. a first communication device; a second communication device that performs serial communication with the first communication device, the first communication device, a measurement unit that measures the number of predetermined reference clocks included in one cycle of a frequency-divided signal based on an audio master clock having a frequency obtained by multiplying the frequency of a sampling clock for sampling an audio signal, a frequency division ratio of a frequency-divided signal of the audio master clock, and a predetermined reference clock; a packet generation unit that generates a packet including information including the number measured by the measurement unit, a bit width of SD (Serial Data) conforming to the I2S standard, the frequency of the sampling clock, a division ratio of the divided signal to the audio master clock, a frequency ratio of the frequency of the audio master clock to the frequency of the sampling clock, and the SD; the second communication device a restoration unit that receives a packet transmitted from the first communication device and restores from the packet the SD, the bit width of the SD, the frequency of the sampling clock, the frequency ratio of the audio master clock frequency to the sampling clock frequency, the number of predetermined first reference clocks included in one cycle of the divided signal of the audio master clock, the frequency of the sampling clock, and the division ratio of the divided signal to the audio master clock; an audio master clock reproducing unit that reproduces the audio master clock based on the number of the first reference clocks, the frequency of the first reference clock, and the frequency division ratio; a SCK reproducing unit that reproduces an SCK (Serial Clock) based on the bit width information of the SD, the frequency ratio, and the audio master clock;

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