High frequency power supply device and control method thereof

Abstract

Provided is a high-frequency power supply device (10) wherein a class E inverter (30) converts DC power into AC power by on / off operation of a first switching element (SW1). A second switching element (SW2) switches whether DC power is input to the class E inverter. A rectifying element (D) allows current to flow from a ground (GND) to the class E inverter (30) when the second switching element (SW2) is off. A control unit (40) causes on / off operation of the first switching element (SW1) to be performed cyclically and maintains the second switching element (SW2) in the on state during an operation period, maintains both the first and second switching elements (SW1, SW2) in the off state during a stop period, and causes on / off operation of the first switching element (SW1) to be performed cyclically while maintaining the second switching element (SW2) in the off state during a transition period directly prior to the stop period in the operation period.

Description

[Technical Field]

[0001] The present disclosure relates to a high frequency power supply device and a control method thereof. [Background technology]

[0002] A power transmission device in a wireless power supply system is provided with an inverter circuit that generates high-frequency AC power from a DC power source.

[0003] Patent Document 1 (Japanese Patent No. 5670869) discloses a class E inverter in which the above inverter circuit is configured with a class E amplifier. Class E inverters can reduce losses that occur during switching due to resonance within the circuit, and are therefore expected to improve the efficiency and miniaturization of the entire wireless power transfer system.

[0004] In a wireless power transfer system, it is necessary to control the output power of the inverter circuit depending on the load state of the power supply destination. A known method for controlling the output power of an inverter circuit is to use intermittent operation. By providing a period in which no power is output through intermittent operation, the average output power of the inverter circuit can be adjusted without changing the switching frequency and duty ratio of the switching elements that make up the inverter circuit. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Patent No. 5670869 Summary of the Invention [Problem to be solved by the invention]

[0006] When intermittent operation is combined with a class E inverter, there is a problem in that the voltage applied between the main electrodes of the switching elements that make up the class E inverter increases above the withstand voltage when the class E inverter transitions from an operating period to a stopped period. Note that this problem is not limited to power transmission equipment in wireless power transfer systems, but is a common problem for high-frequency power supply devices equipped with class E inverters.

[0007] The present disclosure has been made in consideration of the above-mentioned problems, and one of its purposes is to prevent overvoltage between the main electrodes of the switching elements that constitute the E-class inverter when performing intermittent operation in a high-frequency power supply device equipped with an E-class inverter. [Means for solving the problem]

[0008] In one embodiment, a high-frequency power supply includes a class E inverter, the class E inverter having a first switching element that converts DC power into AC power by turning the first switching element on and off. The high-frequency power supply further includes a second switching element and a rectifying element. The second switching element switches between inputting DC power to the class E inverter and not inputting it. When the second switching element is off, the rectifying element passes current from ground to the class E inverter. A control unit controls the on and off of the first switching element and the second switching element. During an operating period of the class E inverter, the control unit periodically turns the first switching element on and off and maintains the second switching element in an on state. During a non-operating period of the class E inverter, the control unit maintains both the first switching element and the second switching element in an off state. During a transition period immediately before the non-operating period during the operating period, the control unit periodically turns the first switching element on and off and maintains the second switching element in an off state. [Effects of the Invention]

[0009] According to the above embodiment, when a high-frequency power supply device including an E-class inverter performs intermittent operation, during a transition period immediately before a stop period in an operating period, the first switching element is periodically turned on and off, and the second switching element is maintained in an off state, thereby preventing an overvoltage between the main electrodes of the first switching element constituting the E-class inverter. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a configuration diagram of a high-frequency power supply device according to a first embodiment. [Figure 2] FIG. 2 is a configuration diagram showing a first modified example of the class E inverter of FIG. [Figure 3] FIG. 2 is a configuration diagram showing a second modified example of the class E inverter of FIG. [Figure 4] FIG. 2 is a configuration diagram showing a third modified example of the class E inverter of FIG. [Figure 5A] FIG. 10 is a diagram for explaining the flow of a direct current when a switching element SW2 is on. [Figure 5B] FIG. 10 is a diagram for explaining the flow of a direct current immediately after the switching element SW2 is switched off. [Figure 6] 2 is a diagram showing the resonance part 35 of the class E inverter 30 of FIG. 1. FIG. [Figure 7] 3 is a diagram showing the resonance part 36 of the class E inverter 31 of FIG. 2. FIG. [Figure 8] 4 is a diagram conceptually illustrating an example of an on / off control signal for a switching element SW1 and a detection signal of a current detector 41. FIG. [Figure 9] 4 is a diagram conceptually showing an ON / OFF operation signal of a switching element SW2. FIG. [Figure 10] FIG. 10 is a timing diagram showing changes in collector-emitter voltage Vce1 of switching element SW1 when no leading time is provided. [Figure 11] FIG. 10 is a timing diagram showing changes in collector-emitter voltage Vce1 of switching element SW1 when a leading time is provided. [Figure 12] 10 is a flowchart showing the control operation of a control unit in the high frequency power supply device of the second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, each embodiment will be described in detail with reference to the drawings. Note that the same or corresponding parts will be denoted by the same reference characters, and their description may not be repeated.

[0012] Embodiment 1 [Configuration of high frequency power supply] FIG. 1 is a configuration diagram of a high-frequency power supply device according to a first embodiment. As shown in FIG. 1, the high-frequency power supply device 10 includes a direct-current (DC) power supply 20, a current detector 41, a switching element SW2, a diode D, a class E inverter 30, a voltage detector 42, and a control unit 40. The class E inverter 30 includes an input inductor L1, a switching element SW1, a parallel capacitor C1, a resonant inductor L2, and a resonant capacitor C2. The class E inverter 30 is also referred to as a class E amplifier. In FIG. 1, the output capacitance of the switching element SW1 is indicated as Coss. The switching element SW1 is also referred to as a first switching element, and the switching element SW2 is also referred to as a second switching element.

[0013] First, the connections of the above components will be briefly described below. The class E inverter 30 is connected between the input node N1 and the output node N3. The switching element SW2 is connected between the DC power supply 20 and the input node N1. The diode D is connected in a reverse bias direction between the input node N1 and ground GND. A load R is connected between the output node N3 and ground GND. The load R may be, for example, a motor that consumes power or a battery for storing power. Alternatively, the high frequency power supply device 10 may be connected to a wireless power supply system as the load R.

[0014] Regarding internal connections of the class E inverter 30, the input inductor L1 is connected between the input node N1 and the intermediate node N2. The switching element SW1 and the parallel capacitor C1 are connected in parallel with each other between the intermediate node N2 and the ground GND. The resonant capacitor C2 and the resonant inductor L2 are connected in series in this order between the intermediate node N2 and the output node N3.

[0015] In the class E inverter 30, the switching element SW1 is switched in accordance with the resonant frequency of a resonant circuit formed by a capacitor and an inductor. This makes it possible to turn on the switching element SW1 (ZVS: zero volt switching) when the voltage between the main electrodes of the switching element SW1 (corresponding to the collector-emitter voltage Vce1 of a bipolar transistor) is 0V. As a result, it is possible to reduce the power loss that occurs when the switching element SW1 is turned on.

[0016] The class E inverter 30 can have a configuration other than that shown in Fig. 1. A brief description will be given below with reference to Figs.

[0017] Fig. 2 is a configuration diagram showing a first modified example of the class E inverter of Fig. 1. Class E inverter 31 of high frequency power supply device 11 of Fig. 2 differs from class E inverter 30 of high frequency power supply device 10 of Fig. 1 in that it further includes an output capacitor C3 connected in parallel with load R. Since other points in Fig. 2 are the same as in Fig. 1, the same or corresponding parts are designated with the same reference numerals and description thereof will not be repeated.

[0018] Fig. 3 is a configuration diagram showing a second modified example of the class E inverter of Fig. 1. The class E inverter 32 of the high frequency power supply device 12 of Fig. 3 differs from the class E inverter 30 of the high frequency power supply device 10 of Fig. 1 in that it includes switching elements SW1a and SW1b with a push-pull structure.

[0019] 3, the class E inverter 32 includes input inductors L1a and L1b, switching elements SW1a and SW1b, parallel capacitors C1a and C1b, resonant capacitors C2a and C2b, and resonant inductors L2a and L2b. The class E inverter 32 is connected between an input node N1 and a first output node N3a and a second output node N3b.

[0020] Regarding the internal connections of the class E inverter 32, the input inductor L1a is connected between the input node N1 and the first intermediate node N2a. The input inductor L1b is connected between the input node N1 and the second intermediate node N2b. The switching elements SW1a and SW1b are connected in series between the intermediate nodes N2a and N2b. The emitters of the switching elements SW1a and SW1b are connected to a common connection node N4. The connection node N4 is connected to the ground GND. The parallel capacitor C1a is connected in parallel with the switching element SW1a, and the parallel capacitor C1b is connected in parallel with the switching element SW1b. and The resonant capacitor C2a and the resonant inductor L2a are connected in parallel between the first intermediate node N2a and the first output node N3a. The resonant capacitor C2b and the resonant inductor L2b are connected in this order between the second intermediate node N2b and the second output node N3b. The load R is connected between the first output node N3a and the second output node N3b.

[0021] Fig. 4 is a configuration diagram showing a third modified example of the class E inverter of Fig. 1. The class E inverter 33 of the high frequency power supply 13 of Fig. 4 is a modified version of the class E inverter 32 of the high frequency power supply 12 of Fig. 3. Specifically, the class E inverter 33 of Fig. 4 differs from the class E inverter 32 of Fig. 3 in that it further includes output capacitors C3a and C3b. The output capacitor C3a is connected between the first output node N3a and ground GND. The output capacitor C3b is connected between the second output node N3b and ground GND.

[0022] As another modification, the class E inverter may be a circuit in which the basic circuit configuration of the class E amplifier circuit is improved.

[0023] 1, the DC power supply 20 is a circuit that outputs DC power. The DC power supply 20 may include a switching circuit such as a DC / DC converter, or may be a circuit that rectifies AC power from a power grid and outputs DC power.

[0024] The input inductor L1 functions as an input filter that passes only DC current, thereby suppressing the ripple current generated by the on / off operation of the switching element SW1.

[0025] 1 shows NPN bipolar transistors as the switching elements SW1 and SW2, but they are not limited to this. For example, the switching elements SW1 and SW2 may be MOSFETs (Metal Oxide Semiconductor Field-Effect Transistors) or IGBTs (Insulated Gate Bipolar Transistors).

[0026] The switching elements SW1 and SW2 are switched on and off based on a control signal supplied from the control unit 40. As will be described later, the switching element SW2 is switched on and off in synchronization with the intermittent operation of the class E inverter 30. The switching element SW1 repeats on and off operations in accordance with a control signal having a constant duty ratio of, for example, 50% at a fundamental frequency f0. If the inductance of the resonant inductor L2 is L2 and the resistance of the load R is R, then the Q factor is expressed as Q = ω L2 / R, where ω = 2π f0. The inductance L2 and resistance R are designed so that the Q factor is sufficiently large at the fundamental frequency f0 of the class E inverter 30.

[0027] The function of diode D differs depending on whether switching element SW2 is on or off. Fig. 5A is a diagram illustrating the flow of DC current when switching element SW2 is on. As shown in Fig. 5A, diode D prevents current from flowing from the collector of switching element SW2 to ground when switching element SW2 is on.

[0028] 5B is a diagram for explaining the flow of DC current immediately after the switching element SW2 is turned off. Immediately after the switching element SW2 is turned off, the current that continues to flow through the input inductor L1 is made to flow from ground GND via diode D.

[0029] 1, a switching element SW3 (so-called synchronous rectification element) configured by a MOSFET, a bipolar transistor, an IGBT, or the like may be used instead of the diode D. When the switching element SW3 is used, the on / off timing of the switching element SW3 is the inverse of the on / off timing of the switching element SW2. In the present disclosure, the diode D and the synchronous rectification switching element SW3 are collectively referred to as a rectification element.

[0030] Next, a method for designing each component of the resonant section of the class E inverter 30 in FIG. 1 will be described in more detail.

[0031] Fig. 6 is a diagram showing the resonant unit 35 of the class E inverter 30 of Fig. 1. In Fig. 6, the output capacitance of the switching element SW1 is Coss, the capacitance of the parallel capacitor C1 is C1, the capacitance of the resonant capacitor C2 is C2, and the inductance of the resonant inductor L2 is L2.

[0032] 6, the resonant frequency f1 of the resonant unit 35 is determined. Specifically, the parallel combined capacitance of the output capacitance Coss and the parallel capacitor C1 is C1+Coss. The series combined capacitance of this parallel combined capacitance and the resonant capacitor C2 is 1 / [1 / (C1+Coss)+1 / C2]. f1 is defined as the resonant frequency of this series combined capacitance and the resonant inductor L2. In this case, the capacitance of the parallel capacitor C1, the capacitance of the resonant capacitor C2, and the inductance of the resonant inductor L2 are designed so that the resonant frequency f1 satisfies f1≧f0 with respect to the fundamental frequency f0.

[0033] Furthermore, if the resonant frequency of the resonant capacitor C2 and the resonant inductor L2 is f2, then the capacitance of the resonant capacitor C2 and the inductance of the resonant inductor L2 are designed so that the resonant frequency f2 is f2≦f0 relative to the fundamental frequency f0. Furthermore, as mentioned above, the Q value (=ω·L2 / R) is made sufficiently large.

[0034] 7 is a diagram showing the resonant section 36 of the class E inverter 31 of FIG. 2. The parallel circuit of the output capacitor C3 and the load R of FIG. 2 is equivalently converted into a series circuit of the output capacitor C3' and the resistance value R' of the load in FIG. 7. The resistance value R' of the load after the impedance conversion and the capacitance C3' of the output capacitor C3' are expressed as follows, assuming ω=2π·f0: R'=R / (1+(ω·C3·R) 2 ) …(1) C3'=R 2 / (1+(ω·C3·R) 2 ) …(2) is given by

[0035] 6, the resonant frequency of the resonant unit 36 ​​is set to f1, and the resonant frequency of the resonant capacitor C2, the resonant inductor L2, and the output capacitor C3' is set to f2. The capacitances of the parallel capacitor C1, the resonant capacitor C2, and the output capacitor C3, as well as the inductance of the resonant inductor L2, are designed to satisfy f0≦f1 and f0≧f2 and to obtain a sufficiently large Q value (=ω·L2 / R').

[0036] By satisfying the design conditions described above with reference to Figures 6 and 7, the voltage between the main electrodes of the switching element SW1 (collector-emitter voltage Vce1 in the case of a bipolar transistor) becomes 0V before the switching element SW1 turns on. Also, the switching element SW1 turns on before the collector-emitter voltage Vce1 increases again from 0V (ZVS). This has the effect of reducing the power loss that occurs when the switching element SW1 switches on.

[0037] 1 again, the current detector 41 detects the input current Iin input from the DC power supply 20 to the switching element SW2. The current detector 41 inputs a detection signal representing the value of the detected input current Iin to the control unit 40. The current detector 41 may be a sensor for detecting DC current, such as a Hall element or a Rogowski coil. Alternatively, the current detector 41 may be configured as a detector that uses a shunt resistor inserted in a DC line and detects a voltage generated across the shunt resistor.

[0038] The voltage detector 42 detects the voltage of the intermediate node N2, i.e., the voltage between the main electrodes of the switching element SW1 (collector-emitter voltage Vce1 in the case of a bipolar transistor). The voltage detector 42 inputs a detection signal representing the value of the detected voltage to the control unit 40.

[0039] The control unit 40 may be configured based on a computer including a CPU (Central Processing Unit) and memory that operates according to a program, may be configured by an FPGA (Field Programmable Gate Array), may be configured by a dedicated circuit, or may be configured by a combination of these, and its hardware configuration is not particularly limited.

[0040] [Control operation of the control unit] Next, a description will be given of the control operation of the control unit 40. The control unit 40 receives a signal representing the value of the input current Iin detected by the current detector 41. Furthermore, the control unit 40 outputs a control signal to each of the switching elements SW1 and SW2 to control the on / off state.

[0041] FIG. 8 is a diagram conceptually showing an example of an on / off control signal for the switching element SW1 and a detection signal for the current detector 41. In FIG.

[0042] 8, the control unit 40 outputs an on / off signal of a fundamental frequency f0 to the switching element SW1. Furthermore, the control unit 40 performs control to repeat a period in which the switching element SW1 is turned on and off and a period in which the on / off operation of the switching element SW1 is stopped, for example, at a frequency fx (corresponding to a period Tx) that is 1 / 10 or less of the fundamental frequency f0. In the present disclosure, the switching operation at this frequency fx is referred to as intermittent operation.

[0043] 8, the period from time t1 to time t3 is the ON / OFF operation period of the switching element SW1, and the period from time t3 to time t4 is the period during which the ON / OFF operation is stopped. The period from time t1 to time t4 corresponds to the cycle Tx of the intermittent operation.

[0044] The control unit 40 also acquires current detection values ​​from the current detector 41 at regular time intervals and integrates the acquired current detection values. After integrating the current detection values ​​multiple times, the control unit 40 obtains the average value of the input current by dividing the integrated value by the number of integrations. Furthermore, the control unit 40 changes the duty ratio d of the intermittent operation so that the obtained average current value approaches the target current value.

[0045] Here, duty ratio d is the ratio of the period during which switching element SW1 performs on / off operation at frequency f0 to the entire period Tx of intermittent operation. As shown in Fig. 8, the on / off operation period (also simply referred to as the "operation period") is expressed as the product (d x Tx) of duty ratio d and the period Tx of intermittent operation. Furthermore, if the value of the input current during the on / off operation period of switching element SW1 is I, the average current is expressed as I x d.

[0046] 9 is a diagram conceptually showing the on / off operation signals of the switching element SW2, in which the on / off operation signals of the switching element SW1 are indicated by solid lines and the on / off operation signals of the switching element SW2 are indicated by dashed lines.

[0047] Referring to FIG. 9, the control unit 40 outputs to the switching element SW2 an on / off signal of a frequency fx (period Tx) synchronized with the intermittent operation of the switching element SW1. Here, the timing at which the switching element SW2 switches on coincides with the start of the on / off operation period of the switching element SW1. Meanwhile, the timing at which the switching element SW2 switches off is earlier than the timing at which the on / off operation of the switching element SW1 stops by a time toff (hereinafter referred to as the "leading time toff"). Hereinafter, the effect of providing the leading time toff will be described with reference to FIGS. 10 and 11. In the following description, the period corresponding to the leading time toff will be referred to as the transition period. The transition period is the period during which the switching element SW2 is controlled to the off state within the on / off operation period of the switching element SW1, and is the period immediately before the period at which the on / off operation of the switching element SW1 is stopped.

[0048] Figure 10 is a timing diagram showing the change in the collector-emitter voltage Vce1 of switching element SW1 when no lead time is provided. From the top to bottom, Figure 10 shows the on / off signal for switching element SW1 (solid line), the on / off signal for switching element SW2 (dashed line), the collector-emitter voltage Vce1 of switching element SW1, and the input current Iin.

[0049] As shown in FIG. 10, because the advance time toff = 0, at time t3 when switching element SW1 switches from an on / off operating period (also simply referred to as the "operating period") to an on / off operation stop period (also simply referred to as the "stop period"), switching element SW2 also switches from on to off. In this case, at the timing when switching element SW1 switches from the on / off operating period to the on / off operation stop period (immediately after time t3), the collector-emitter voltage Vce1 increases and exceeds the upper limit Vth, which is a predetermined allowable limit. As a result, a voltage exceeding the element's breakdown voltage may be applied to switching element SW1. In FIG. 10, the waveform of input current Iin is the same as that in FIG. 8, so a description thereof will not be repeated.

[0050] Figure 11 is a timing diagram showing the change in the collector-emitter voltage Vce1 of switching element SW1 when a lead time is provided. From the top to bottom, Figure 10 shows the on / off signal of switching element SW1 (solid line), the on / off signal of switching element SW2 (dashed line), the collector-emitter voltage Vce1 of switching element SW1, and the input current Iin.

[0051] 11, switching element SW2 is switched off at time t2, which is earlier by the lead time toff than time t3 when switching element SW1 switches from an on-off operation period to a period when on-off operation is stopped. This makes it possible to keep the peak value of collector-emitter voltage Vce1 lower than the upper limit value Vth, compared to the case in FIG. 10 where lead time toff=0.

[0052] 11, the average value of the input current Iin is given by I×(d×Tx−toff) / Tx. When the lead time toff=0, the average current value is I×d as shown in FIG.

[0053] The value of the lead time toff is determined, for example, by circuit analysis, so that the peak value of the collector-emitter voltage Vce1 does not exceed a predetermined upper limit Vth when the switching element SW1 switches from an on-off operation period to a non-on-off operation period. The upper limit Vth is set, for example, to a voltage value that is 80% or less of the withstand voltage of the switching element.

[0054] Alternatively, the following method may be used to determine the lead time toff. First, the control unit 40 sets the initial value of the lead time toff to a value between 0 and d×Tx. Next, the control unit 40 drives the high-frequency power supply 10 and detects the value of the collector-emitter voltage Vce1 using the voltage detector 42. If the peak value of the collector-emitter voltage Vce1 exceeds a predetermined upper limit value Vth after the switching element SW2 switches from on to off, the control unit 40 increases the value of the lead time toff by one clock cycle. Conversely, if the peak value of the collector-emitter voltage Vce1 does not exceed the upper limit value Vth after the switching element SW2 switches from on to off, the control unit 40 decreases the value of the lead time toff by one clock cycle. However, if the lead time toff is equal to or less than 0, the lead time toff is set to 0.

[0055] The control relating to the change of the duty ratio d of intermittent operation and the control relating to the change of the lead time toff may be performed by first fixing the lead time toff and changing the duty ratio d of intermittent operation, and then fixing the duty ratio d and changing the lead time toff. Alternatively, the controls may be performed in the reverse order, or the duty ratio d and the lead time toff may be changed simultaneously. In the class E inverters 32 and 33 with the push-pull structure described with reference to Figures 3 and 4, the duty ratio d and the lead time toff can also be determined using the same design method as above.

[0056] [Effects of the First Embodiment] As described above, according to the high-frequency power supply devices 10 to 13 of the first embodiment, the switching element SW2 is switched from the ON state to the OFF state earlier than the timing at which the switching element SW1 is switched from the ON / OFF operation period to the ON / OFF operation suspension period by the leading time toff. This makes it possible to suppress an increase in the collector-emitter voltage Vce1 at the timing at which the switching element SW1 switches from the ON / OFF operation period to the ON / OFF operation suspension period, and to prevent an overvoltage exceeding the element's breakdown voltage from being applied to the switching element SW1.

[0057] Furthermore, by performing control to increase the lead time toff when the peak value of the collector-emitter voltage Vce1 of the switching element SW1 exceeds the upper limit value Vth and to decrease the lead time toff when the peak value of the collector-emitter voltage Vce1 does not exceed the upper limit value Vth, it is not necessary to determine an appropriate lead time toff in advance by circuit analysis, etc. Therefore, when the operation of the high frequency power supply devices 10 to 13 changes due to load fluctuations, element failure, etc., it is possible to prevent an overvoltage from being applied to the switching element SW1.

[0058] Embodiment 2 In the second embodiment, the preceding time toff is not preset. Instead, when the control unit 40 detects a collector-emitter voltage Vce1 exceeding a predetermined upper limit Vth, the control unit 40 controls the switching element SW1 to continue its on-off operation and turns off only the switching element SW2 (i.e., transitions to a transition period). Hereinafter, this type of control is referred to as a protection mode. The protection mode prevents an overvoltage exceeding the element's breakdown voltage from being applied to the switching element SW1.

[0059] The basic configuration of the high frequency power supply device of embodiment 2 is the same as that of the high frequency power supply devices 10 to 13 described in embodiment 1. Also, as in embodiment 1, the control unit 40 performs control to change the duty ratio d of the intermittent operation so that the average value of the input current Iin approaches a target current value.

[0060] [Control operation of the control unit] FIG. 12 is a flowchart showing the control operation of the control unit in the high frequency power supply device according to the second embodiment.

[0061] 12 for each cycle of the clock signal. A voltage detector 42 detects the collector-emitter voltage Vce1 of the switching element SW1, and the control unit 40 acquires the detected value of the collector-emitter voltage Vce1 from the voltage detector 42 at regular intervals. The control unit 40 integrates the acquired detected voltage values, integrates them multiple times, and then divides the integrated value by the number of integrations to obtain the average value of the collector-emitter voltage Vce1.

[0062] In the initial state (step ST10), the time t is set to 0 and the protection mode is turned off. The control unit 40 increments the time t by 1 every clock cycle (NO in step ST90). When the time t reaches the period Tx of the intermittent operation (YES in step ST90), the control unit 40 initializes the time t to 0 and, if the protection mode is on, returns it to off.

[0063] If the protection mode is off (NO in step ST20), the control unit 40 advances the process to step S30, and if the protection mode is on (YES in step ST20), the control unit 40 advances the process to step ST70.

[0064] In step ST30, the control unit 40 determines whether the peak value of the collector-emitter voltage Vce1 of the switching element SW1 is greater than the upper limit value Vth. If the peak value of the collector-emitter voltage Vce1 of the switching element SW1 is greater than the upper limit value Vth (YES in step ST30), the control unit 40 switches the protection mode on and proceeds to step ST70 (i.e., transitions to the transition period).

[0065] When the protection mode is on, the control unit 40 determines in step ST70 whether the average value of the collector-emitter voltage Vce1 of the switching element SW1 is smaller than a reference value near 0V. The reference value is set to, for example, 1 / 10 of the upper limit value Vth. If the average value of the collector-emitter voltage Vce1 of the switching element SW1 is equal to or greater than the reference value (NO in step ST70), the control unit 40 maintains the on / off operation of the switching element SW1 at the fundamental frequency f0 and turns off the switching element SW2 (step ST80). In other words, the transition period is continuation On the other hand, if the average value of the collector-emitter voltage Vce1 of the switching element SW1 is lower than the reference value (YES in step ST70), the control unit 40 stops the on / off operation of the switching element SW1 and keeps it in the off state, and keeps the switching element SW2 off (step ST60). That is, the transition period is switched to the stop period. This turns off the protection mode. However, the control unit 40 may also control the switching element SW1 to continue the on / off operation and maintain the protection mode (i.e., the transition period) regardless of the average value of the collector-emitter voltage Vce1 of the switching element SW1.

[0066] If the protection mode is off (NO in step ST20) and the peak value of the collector-emitter voltage Vce1 of switching element SW1 is lower than the upper limit value Vth (NO in step ST30), the control unit 40 performs the same control as when the advance time toff is 0 in the first embodiment. Specifically, if the time t is less than d×Tx (NO in step ST40), that is, during the on / off operation period of switching element SW1, the control unit 40 repeatedly turns on and off switching element SW1 at the fundamental frequency f0 and turns on switching element SW2 (step ST50). On the other hand, if the time t is equal to or greater than d×Tx and less than Tx (YES in step ST40), that is, during the period when the on / off operation of switching element SW1 is stopped, the control unit 40 maintains both switching elements SW1 and SW2 in the off state (step ST60).

[0067] [Effects of the second embodiment] As described above, according to the high frequency power supply device of the second embodiment, when a voltage between the main electrodes of switching element SW1 (collector-emitter voltage Vce1) exceeding a predetermined upper limit value Vth is detected, switching element SW1 continues to perform on-off operation, and only switching element SW2 is controlled to be in the off state. This makes it possible to prevent an overvoltage exceeding the element's withstand voltage from being applied to switching element SW1.

[0068] In the above control, even during periods when the on / off operation of switching element SW1 is normally stopped during intermittent operation, switching element SW1 continues to perform on / off operation, and only switching element SW2 is controlled to the off state. Then, the on / off operation of switching element SW1 is stopped after the average value of collector-emitter voltage Vce1 of switching element SW1 reaches a reference value near 0 V. This allows switching element SW2 to be controlled to the off state earlier than the timing at which switching element SW1 switches from an on / off operation period to an on / off operation suspension period, even without setting the advance time toff in the first embodiment. As a result, the increase in collector-emitter voltage Vce1 of switching element SW1 can be suppressed at the timing at which switching element SW1 switches from an on / off operation period to an on / off operation suspension period, thereby preventing an overvoltage exceeding the element's breakdown voltage from being applied to switching element SW1.

[0069] To turn on and off the switching element SW1, power for the gate drive signal is required in addition to the power input from the main DC power supply 20. In this embodiment, after the switching element SW2 is controlled to the off state, the on and off operation of the switching element SW1 is stopped once the average value of the collector-emitter voltage Vce1 of the switching element SW1 reaches approximately 0 V, thereby reducing the period during which the switching element SW1 is turned on and off. As a result, the power of the gate drive signal required for the on and off operation of the switching element SW1 can be reduced.

[0070] The embodiments disclosed herein should be considered to be illustrative in all respects and not restrictive. The scope of this application is defined by the claims, not the above description, and is intended to include all modifications within the meaning and scope of the claims. [Explanation of symbols]

[0071] 10-13 high frequency power supply, 20 DC power supply, 30-33 Class E inverter, 35, 36 resonance unit, 40 control unit, 41 current detector, 42 voltage detector, C1 parallel capacitor, C2 resonance capacitor, C3 output capacitor, Coss output capacitance of switching element SW1, D diode, GND ground, L1 input inductor, L2 resonance inductor, N1 input node, N2 intermediate node, N3 output node, N4 connection node, R load, SW1, SW2 switching elements, Tx intermittent control period, Vce1 collector-emitter voltage, Vth upper limit value, d duty ratio, f0 fundamental frequency, f1, f2 resonance frequencies, toff leading time.

Claims

1. a class E inverter having a first switching element, the class E inverter converting DC power into AC power by an on / off operation of the first switching element; a second switching element that switches between input and output of the DC power to the class E inverter; a rectifying element that causes a current to flow from ground to the class E inverter when the second switching element is off; a control unit that controls on / off of the first switching element and the second switching element, The control unit During an operation period of the class E inverter, the first switching element is periodically turned on and off, and the second switching element is maintained in an on state; During a stop period of the class E inverter, the first switching element and the second switching element are both maintained in an off state; a high frequency power supply device that periodically turns on and off the first switching element and maintains the second switching element in an off state during a transition period immediately before the stop period within the operation period.

2. a current detector that detects a DC input current input to the class E inverter via the second switching element; 2. The high frequency power supply device according to claim 1, wherein the control unit controls a ratio between a length of the operation period and a length of the stop period so that an average value of the detected input current becomes equal to a target value.

3. 3. The high frequency power supply device according to claim 1, wherein a length of the transition period is set so that a peak value of a voltage applied between the main electrodes of the first switching element does not exceed a predetermined upper limit value when switching from the operation period to the stop period.

4. a voltage detector that detects a voltage applied between the main electrodes of the first switching element; 4. The high frequency power supply device according to claim 3, wherein the control unit sets an initial value of the length of the transition period, increases the length of the transition period from a current setting value when the detected peak value of the voltage exceeds the upper limit value, and decreases the length of the transition period from a current setting value when the detected peak value of the voltage does not exceed the upper limit value.

5. a voltage detector that detects a voltage applied between main electrodes of the first switching element; 3. The high frequency power supply device according to claim 1, wherein the control unit transitions to the transition period when the detected peak value of the voltage is equal to or greater than a predetermined upper limit value.

6. 6. The high frequency power supply device according to claim 5, wherein the control unit continues the periodic on / off operation of the first switching element during the transition period until the average value of the detected voltage becomes equal to or less than a reference value, and transitions to the stop period when the average value of the detected voltage becomes equal to or less than the reference value.

7. A method for controlling a high frequency power supply device, comprising: The high frequency power supply device a class E inverter having a first switching element, the class E inverter converting DC power into AC power by an on / off operation of the first switching element; a second switching element that switches between input and output of the DC power to the class E inverter; a rectifying element that causes a current to flow from ground to the class E inverter when the second switching element is off, The control method includes: During an operation period of the class E inverter, periodically turning on and off the first switching element and maintaining the second switching element in an on state; maintaining both the first switching element and the second switching element in an off state during a stop period of the class E inverter; and periodically turning on and off the first switching element and maintaining the second switching element in an off state during a transition period immediately before the stop period within the operation period.

8. detecting a DC input current input to the class E inverter via the second switching element; 8. The method for controlling a high frequency power supply device according to claim 7, further comprising the step of controlling a ratio between a length of the operation period and a length of the stop period so that an average value of the detected input current is equal to a target value.

9. 9. The control method for a high frequency power supply device according to claim 7, wherein a length of the transition period is set so that a peak value of a voltage applied between the main electrodes of the first switching element does not exceed a predetermined upper limit value when switching from the operation period to the stop period.

10. detecting a voltage applied between the main electrodes of the first switching element; setting an initial value for the length of the transition period; increasing the length of the transition period from a currently set value when the detected peak value of the voltage exceeds the upper limit value; 10. The method for controlling a high frequency power supply device according to claim 9, further comprising the step of: reducing the length of the transition period from a current set value when the detected peak value of the voltage does not exceed the upper limit value.

11. detecting a voltage applied between main electrodes of the first switching element; 9. The method for controlling a high frequency power supply device according to claim 7, further comprising the step of transitioning to the transition period when the detected peak value of the voltage is equal to or greater than a predetermined upper limit value.

12. during the transition period, continuing the periodic on / off operation of the first switching element until the average value of the detected voltage becomes equal to or less than a reference value; 12. The method for controlling a high frequency power supply device according to claim 11, further comprising the step of transitioning to the stop period when the average value of the detected voltage becomes equal to or less than the reference value.

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