Encoding circuit, decoding circuit, encoding method, decoding method, and computer program

Abstract

This encoding circuit comprises: a serial-to-parallel circuit that performs a serial-to-parallel conversion of input uniform sequence data to a plurality of divided pieces of data; a sequence conversion unit that encodes and converts a divided piece of data to a divided piece of non-uniform sequence data; a parallel-to-serial circuit that performs a parallel-to-serial conversion of the divided piece of data and the divided piece of non-uniform sequence data as converted by the sequence conversion unit to a series of data; an external encoding unit that encodes the series of data by adding an error correction code thereto; a division unit that divides the series of data to which the error correction code has been added into a plurality of divided pieces of data; a bit conversion circuit that regards the plurality of divided pieces of data as the pieces of data to be transmitted by use of respective ones of different subchannels and that converts bit sequences so as to make the communication path capacities of the respective subchannels nonuniform; and a conversion unit that allocates the uniform sequence data to the least significant bit in the plurality of divided pieces of data and that allocates the nonuniform sequence data to the most significant bit.　

Description

[Technical Field]

[0001] The present invention relates to an encoding circuit, a decoding circuit, an encoding method, a decoding method, and a computer program. [Background technology]

[0002] The increase in Internet traffic has led to a demand for higher capacity optical transmission. Therefore, research is being conducted into technologies for improving spectral efficiency and reducing power consumption in forward error correction (FEC) processing in coherent digital signal processors (DSPs) used in optical transmission networks. Conventionally, to improve spectral efficiency, probabilistic constellation shaping (PCS) optimizes the probability distribution shape of transmitted symbols according to the communication path, and multilevel coding (MLC) efficiently reduces the computational complexity of soft-decision FEC (SD-FEC), which is high-performance but requires a large amount of computation. When PCS is used, probabilistic amplitude shaping (PAS), which simultaneously achieves both PCS and FEC, is commonly used (see, for example, Non-Patent Document 1).

[0003] Furthermore, a technology combining PCS technology and MLC technology (PCS+MLC) is also being studied (see, for example, Non-Patent Documents 2 and 3). However, in conventional MLC technology, a symbol mapper is used to make the channel capacity between bit levels uneven in order to reduce the amount of calculation, and SD-FEC at the bit level with a large channel capacity is eliminated. Therefore, the amount of calculation that can be reduced is limited at low modulation levels (for example, 16QAM (Quadrature Amplitude Modulation)). Therefore, the same problem occurs in the technology combining PCS technology and MLC technology.

[0004] Therefore, CP-MLC (Channel-Polarized multilevel coding) has been proposed as a technology similar to MLC (see, for example, Non-Patent Document 4). In CP-MLC, a phenomenon called channel polarization is used to divide and unbalance a communication channel into highly reliable subchannels (subchannels with high channel capacity) and less reliable subchannels (subchannels with low channel capacity), and SD-FEC is applied only to the subchannels with low channel capacity, thereby reducing the amount of FEC calculation within the binary code framework and independent of the modulation method. [Prior art documents] [Non-patent literature]

[0005] [Non-Patent Document 1] G. Bocherer et al., “Bandwidth Efficient and Rate-Matched Low-Density Parity-Check Coded Modulation”, IEEE Trans Commun., vol. 63, no.12, pp4651-4655 (2015). [Non-patent document 2] T. Yoshida, M. Karlsson and E. Agrell, “Multilevel Coding with Flexible Probabilistic Shaping for Rate-Adaptive and Low-Power Optical Communications”, 2020 Optical Fiber Communications Conference and Exhibition (OFC), 2020, pp. 1-3. [Non-patent document 3] K. Sugitani, Y. Koganei, H. Irie and H. Nakashima, “Performance Evaluation of WDM Channel Transmission for Probabilistic Shaping With Partial Multilevel Coding”, in Journal of Lightwave Technology, vol. 39, no. 9, pp. 2873-2879, 1 May1, 2021, doi: 10.1109 / JLT.2021.3061177. [Non-patent document 4] T. Kakizaki et al., “Low-complexity Channel Polarized Multilevel Coding for Modulation-format-independent Forward Error Correction”, ECOC2021, (2021) Summary of the Invention [Problem to be solved by the invention]

[0006] If the CP-MLC configuration can be applied to PAS, it will be possible to realize a configuration that has high frequency utilization efficiency and reduces the amount of FEC calculations regardless of the modulation level. However, when applying the CP-MLC configuration to PAS, there is a problem that it cannot be applied to PAS because it is not a systematic code depending on the modulation level and configuration.

[0007] In view of the above circumstances, an object of the present invention is to provide a technology that can achieve high frequency utilization efficiency and reduce the amount of FEC calculations regardless of the modulation multi-level level. [Means for solving the problem]

[0008] One aspect of the present invention is a coding circuit used in coherent digital signal processing, the coding circuit comprising: a serial-parallel circuit that divides input uniform sequence data into a plurality of divided data segments by serial-parallel conversion; a sequence conversion unit that encodes the divided data and converts it into non-uniform sequence divided data; a parallel-serial circuit that converts the divided data output from the serial-parallel circuit and the non-uniform sequence divided data converted by the sequence conversion unit into serial data by parallel-serial conversion; an outer coding unit that adds an error correcting code to the serial data and encodes it; a division unit that divides the serial data with the error correcting code added into a plurality of divided data segments; a bit conversion circuit that regards the plurality of divided data segments divided by the division unit as data to be transmitted on separate sub-channels and converts bit sequences to make the communication path capacities of the sub-channels uneven; and a conversion unit that assigns uniform sequence data to the least significant bit and non-uniform sequence data to the most significant bit in the plurality of divided data segments output from the bit conversion circuit.

[0009] One aspect of the present invention is a decoding circuit used in coherent digital signal processing, comprising: a serial-parallel circuit that divides input data into a plurality of divided data by serial-parallel conversion; a first likelihood calculation circuit that calculates a likelihood by soft decision based on some of the plurality of divided data and information on noise occurring in a communication channel; a decoding unit that uses the likelihood as an input and corrects errors in the divided data input to the first likelihood calculation circuit; and a codeword error-corrected by the decoding unit, the some of the plurality of divided data, and information on noise occurring in the communication channel, and calculates a likelihood related to a conditional probability. The decoding circuit includes one or more second likelihood calculation circuits that calculate likelihoods and perform hard decisions; a combining unit that combines the obtained bit sequence with decoded information bits; an outer code decoding unit that decodes the outer code; a serial-parallel circuit that divides input data into uniform sequence divided data and non-uniform sequence divided data by serial-parallel conversion; a sequence conversion unit that decodes the non-uniform sequence divided data and converts it into uniform sequence divided data; and a parallel-serial circuit that restores uniform sequence data by parallel-serial conversion of the uniform sequence divided data output from the sequence conversion unit and the divided uniform sequence divided data.

[0010] One aspect of the present invention is an encoding method used in coherent digital signal processing, which comprises: dividing input uniform sequence data into a plurality of divided data by serial-parallel conversion; encoding the divided data to convert it into non-uniform sequence divided data; converting the divided data and the non-uniform sequence divided data into serial data by parallel-serial conversion; adding an error correction code to the serial data and encoding it; dividing the serial data with the error correction code added into a plurality of divided data; regarding each of the divided plurality of divided data as data to be transmitted on a separate sub-channel; converting the bit sequence to make the communication path capacity of each sub-channel uneven; and assigning uniform sequence data to the least significant bit and non-uniform sequence data to the most significant bit in the plurality of divided data.

[0011] One aspect of the present invention is a decoding method used in coherent digital signal processing, which divides input data into a plurality of divided data by serial-parallel conversion, calculates a likelihood by soft decision based on some of the plurality of divided data and information on noise occurring in a communication channel, uses the likelihood as input to correct errors in the divided data, calculates a likelihood related to a conditional probability based on the error-corrected codeword, some of the plurality of divided data, and information on noise occurring in the communication channel, makes a hard decision, combines the obtained bit sequence with decoded information bits, decodes an outer code, divides the input data into a uniform sequence of divided data and a non-uniform sequence of divided data by serial-parallel conversion, decodes the non-uniform sequence of divided data and converts it into a uniform sequence of divided data, and restores the uniform sequence of data by parallel-serial conversion of the converted uniform sequence of divided data and the divided uniform sequence of divided data.

[0012] One aspect of the present invention is a computer program for causing a computer to execute processes that cause a computer to divide input uniform sequence data into a plurality of divided data by performing serial-to-parallel conversion, encode the divided data and convert it into non-uniform sequence divided data, convert the divided data and the non-uniform sequence divided data into serial data by performing parallel-to-serial conversion, add an error correction code to the serial data and encode it, divide the serial data with the error correction code added into a plurality of divided data, regard the divided plurality of divided data as data to be transmitted on separate sub-channels, convert the bit sequence to make the communication path capacity of each sub-channel uneven, and assign uniform sequence data to the least significant bit and non-uniform sequence data to the most significant bit in the plurality of divided data.

[0013] One aspect of the present invention is a computer program for causing a computer to execute the following processes: divide input data into a plurality of divided data by serial-parallel conversion; calculate a likelihood by soft decision based on some of the plurality of divided data and information on noise occurring in a communication channel; correct errors in the divided data using the likelihood as input; calculate a likelihood related to a conditional probability based on the error-corrected codeword, some of the plurality of divided data, and information on noise occurring in the communication channel; make a hard decision; combine the obtained bit sequence with decoded information bits; decode the outer code; divide the input data into a uniform sequence of divided data and a non-uniform sequence of divided data by serial-parallel conversion; decode the non-uniform sequence of divided data and convert it into a uniform sequence of divided data; and restore the uniform sequence of data by parallel-serial conversion of the converted uniform sequence of divided data and the divided uniform sequence of divided data. [Effects of the Invention]

[0014] According to the present invention, it is possible to achieve high frequency utilization efficiency and reduce the amount of FEC calculations regardless of the modulation multi-level level. [Brief explanation of the drawings]

[0015] [Figure 1] 1 is a block diagram showing an example of the configuration of a transmission device according to a first embodiment. [Figure 2] 1 is a block diagram showing an example of the configuration of a receiving device according to a first embodiment. [Figure 3] 10 is a diagram for explaining details of the processing performed by an S / P conversion unit, a stream conversion unit, a P / S conversion unit, and an outer encoder provided in the transmitting device. FIG. [Figure 4] 10 is a diagram for explaining details of a process performed by a 1:d converter provided in the transmission device. FIG. [Figure 5] 10 is a diagram for explaining details of the processing performed by an SD-FEC encoding unit and a bit conversion circuit included in the transmitting device. FIG. [Figure 6]10 is a diagram for explaining details of the processing performed by a d:m converter and a symbol mapper provided in the transmitting device. FIG. [Figure 7] FIG. 10 is a diagram illustrating an example of allocation by a symbol mapper. [Figure 8] 5 is a flowchart showing a flow of processing by the transmitting device in the first embodiment. [Figure 9] FIG. 10 is a block diagram showing an example of the configuration of a transmission device according to a second embodiment. [Figure 10] FIG. 10 is a diagram for explaining details of processing performed by a preprocessing circuit included in a transmission device according to a second embodiment. [Figure 11] FIG. 10 is a block diagram showing an example of the configuration of a receiving device according to a second embodiment. [Figure 12] FIG. 10 is a diagram showing the results of numerical simulations of the present invention and the conventional PAS technology. DETAILED DESCRIPTION OF THE INVENTION

[0016] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. (First embodiment) 1 is a block diagram showing an example of the configuration of a transmitting device 1 in the first embodiment. The transmitting device 1 is part of a digital coherent communication system and is a transmitting device used to transmit data to be transmitted (hereinafter referred to as "transmission data"). The transmitting device 1 transmits the transmission data to a receiving device connected via a communication path. The communication path is assumed to be, for example, an AWGN (Additive White Gaussian Noise) communication path.

[0017] The transmitting device 1 includes a coding circuit 10, a symbol mapper 11, and a transmitting unit 12. The coding circuit 10 includes an S / P conversion unit 110, a sequence conversion unit 120, a P / S conversion unit 130, an outer encoder 140, a 1:d converter 150, an SD-FEC coding unit 160, a bit conversion circuit 170, and a d:m converter 180.

[0018] The S / P converter 110 divides the input data to be transmitted into a plurality of pieces of data by serial-to-parallel conversion. For example, the S / P converter 110 divides the data to be transmitted into two pieces of data. The data to be transmitted is a uniform sequence of data. Here, a uniform sequence refers to an information sequence in which an information sequence (e.g., bits) is generated according to a uniform distribution.

[0019] The sequence converter 120 converts a uniform sequence into a non-uniform sequence. Specifically, the sequence converter 120 is a converter that reversibly converts a uniform bit sequence of a certain length k (k is an integer equal to or greater than 1) into a non-uniform symbol sequence of length n (n is an integer equal to or greater than 1). Note that k≦n×(m−1), and the redundancy nk is determined according to the shape of the non-uniform distribution. m is the bit length per symbol (bit / symbol). Here, a non-uniform sequence refers to an information sequence that is not a uniform sequence. In the first embodiment, d≧m. d represents the number of lanes in the 1:d converter 150.

[0020] The P / S converter 130 converts the uniform sequence data output from the S / P converter 110 and the non-uniform sequence data converted by the sequence converter 120 into serial data by performing parallel-to-serial conversion.

[0021] The outer encoder 140 simultaneously corrects errors that cannot be corrected by the SD-FEC and all remaining errors. The outer encoder 140 is one aspect of an outer encoding unit.

[0022] The 1:d converter 150 divides the output from the outer encoder 140 into d lanes (d is an integer equal to or greater than 2), assigning a portion of the uniform sequence data to lane 1 and the remaining uniform sequence and amplitude sequence to lanes 2 to d. Note that the 1:d converter 150 may perform interleaving as necessary to prevent burst errors caused by the inner code.

[0023] The SD-FEC encoding unit 160 performs encoding using an error correction code.

[0024] The bit conversion circuit 170 is a conversion circuit in which the ratio of input to output as is is (d-1) / d or less for the number of bits d per symbol. By combining it with a receiver, errors are concentrated in the bits of the first lane, and errors in the bits of the second to dth lanes are virtually reduced.

[0025] The d:m converter 180 converts the data streams transmitted on the 1st to dth lanes into data streams on m lanes.

[0026] As with conventional PAS, the symbol mapper 11 generates transmission data by allocating uniformly distributed bits to LSBs (Least Significant Bits) corresponding to the positive and negative signs of the symbols, and non-uniformly distributed bits to MSBs (Most Significant Bits) corresponding to the amplitude.

[0027] The transmitter 12 transmits the transmission data generated by the symbol mapper 11 .

[0028] 2 is a block diagram showing an example of the configuration of a receiving device 2 according to the first embodiment. The receiving device 2 is a transmitting device used in a digital coherent communication system. The receiving device 2 receives transmission data transmitted from a transmitting device 1 connected via a communication path.

[0029] The receiving device 2 includes a receiving unit 20, a symbol demapper 21, and a decoding circuit 22.

[0030] The receiving unit 20 receives the transmission data transmitted from the transmitting device 1 via a communication path.

[0031] The symbol demapper 21 demodulates the transmission data received by the receiving unit 20 using a demodulation method corresponding to the modulation method.

[0032] The decoding circuit 22 is composed of an S / P conversion unit 220, an SD likelihood calculation unit 230, an SD-FEC decoding unit 240, a plurality of HD likelihood calculation units 250-1 to 250-d, a d:1 converter 260, an outer code decoder 270, an S / P conversion unit 280, an inverse sequence conversion unit 290, and a P / S conversion unit 300.

[0033] The S / P conversion unit 220 divides the transmission data into multiple pieces of data by serial-to-parallel converting the transmission data demodulated by the symbol demapper 21. For example, the S / P conversion unit 220 divides the transmission data into a number d corresponding to the number of lanes.

[0034] The SD likelihood calculation unit 230 calculates a likelihood based on the data output from the S / P conversion unit 220 and communication channel information. The communication channel information represents the distribution of noise on the communication channel. The communication channel information can be measured using a spectrum analyzer or the like. It is assumed that the communication channel information has been measured in advance and stored in the SD likelihood calculation unit 230.

[0035] The processing of the SD likelihood calculation unit 230 will be described in more detail. The SD likelihood calculation unit 230 calculates the codeword z output from the SD-FEC encoding unit 160 from the received word y and the channel information P(y|x). (1) In order to estimate the probability P(y|z (1) ) probability likelihood L (1) For example, the communication path P(y|z (1) ) is y=[y1y2…y n´ ], the SD likelihood calculation unit 230 calculates the likelihood L based on the following equation 1. i (1) Calculate.

[0036]

number

[0037] Here, n' = n / d, which is an integer. Here, it is assumed that the code length and the number of divisions are designed so that n' is an integer. Furthermore, y i =[yi (1) y i (2) …y i (d) ].

[0038] The SD-FEC decoder 240 receives the likelihood L calculated by the SD likelihood calculator 230. i (1) The error-corrected codeword z (1) Get.

[0039] The plurality of HD likelihood calculation units 250-1 to 250-d calculates the corrected codeword z (1) Based on the received word y and the channel information P(y|x), the conditional probability P(y,z (1) |z (s) ) is calculated. For example, similar to the SD likelihood calculation unit 230, the likelihood of the communication channel P(y|z (1) ) is y=[y1y2…y n´ ], each HD likelihood calculation unit 250 makes a hard decision based on the following equation 2, and (s) where s is an integer between 2 and d.

[0040]

number

[0041] The d:1 converter 260 converts the codeword z transmitted on one lane into (1) and the information bit sequence corresponding to each z (s) Combine the above into one.

[0042] The outer code decoder 270 converts the bit sequence and then decodes the outer code.

[0043] The S / P conversion unit 280 divides the input data into multiple pieces of data by serial-to-parallel conversion. For example, the S / P conversion unit 280 divides the data into two pieces of data. The S / P conversion unit 280 outputs the non-uniform sequence data to the inverse sequence conversion unit 290, and outputs the uniform sequence data to the P / S conversion unit 300.

[0044] The inverse sequence converter 290 converts a non-uniform sequence into a uniform sequence. Specifically, the inverse sequence converter 290 is a converter that reversibly converts a non-uniform symbol sequence of length n into a uniform bit sequence of length k. This restores the original uniform sequence.

[0045] The P / S conversion unit 300 converts the uniform sequence data output from the S / P conversion unit 280 and the uniform sequence data converted by the inverse sequence conversion unit 290 into serial data by performing parallel-to-serial conversion, thereby enabling the transmission data to be decoded.

[0046] Next, the processing performed by the transmitting device 1 will be described in detail with reference to Figs. 3 to 6. Fig. 3 is a diagram for explaining in detail the processing performed by the S / P conversion unit 110, the sequence conversion unit 120, the P / S conversion unit 130, and the outer encoder 140 provided in the transmitting device 1. As shown in Fig. 3, it is assumed that data to be transmitted of a uniform sequence i is input to the S / P conversion unit 110. The S / P conversion unit 110 divides the input data to be transmitted of the uniform sequence i into multiple pieces of data. For example, the S / P conversion unit 110 divides the data to be transmitted of the uniform sequence i into data to be transmitted of a uniform sequence i1 and data to be transmitted of a uniform sequence i2. In Figs. 3 to 6, the data to be transmitted of the uniform sequence i1 is indicated as uniform sequence i1, and the data to be transmitted of the uniform sequence i2 is indicated as uniform sequence i2.

[0047] The S / P converter 110 outputs the data to be transmitted of the uniform sequence i1 to the P / S converter 130, and outputs the data to be transmitted of the uniform sequence i2 to the sequence converter 120. The sequence converter 120 encodes the input data to be transmitted of the uniform sequence i2 to obtain data to be transmitted of the non-uniform sequence j2. In this way, the sequence converter 120 encodes the data to be transmitted of the uniform sequence i=[i1i2]∈{0,1}k Among these, the data to be transmitted of the uniform sequence i2 is encoded to obtain the data to be transmitted of the non-uniform sequence j2. In Figs. 3 to 6, the data to be transmitted of the non-uniform sequence j2 is shown as the non-uniform sequence j2.

[0048] The sequence converter 120 converts bits into non-uniform symbols, and then converts them into a bit string that corresponds to a symbol mapper that creates a one-to-one correspondence between m-bits and 1-symbols in a lookup table. The input to the sequence converter 120 is a bit sequence, and the output is a bit sequence that corresponds to the non-uniform symbol sequence.

[0049] The P / S converter 130 receives transmission data of a uniform sequence i1 and transmission data of a non-uniform sequence j2. The P / S converter 130 converts the input transmission data into serial data by parallel-to-serial conversion. As a result, the transmission data of the uniform sequence i1 and the transmission data of the non-uniform sequence j2 are connected in series, as shown in FIG. 3. The transmission data [i1j2] is input to the outer encoder 140. Because the outer code is a systematic code, the outer encoder 140 calculates a parity bit p1 from the transmission data [i1j2] and adds it to the transmission data [i1j2] sequence. As a result, the sequence of the entire transmission data becomes b=[p1i1j2].

[0050] FIG. 4 is a diagram illustrating the details of the processing performed by the 1:d converter 150 included in the transmitting device 1. As shown in FIG. 4, transmission target data of a sequence b=[p1i1j2] is input to the 1:d converter 150. The 1:d converter 150 interleaves and divides the transmission target data of a sequence b=[p1i1j2] so that the uniform sequence is in the first stage. The processing performed by the 1:d converter 150 has three characteristics. The first characteristic is that the uniform sequence and the non-uniform sequence are interleaved separately. The second characteristic is that a portion of the uniform sequence data and the non-uniform sequence data are output to the second stage and thereafter. The third characteristic is that the division length is determined based on each code parameter and the multi-level degree.

[0051] In the first feature, the 1:d converter 150 performs interleaving on a symbol-by-symbol basis when interleaving a non-uniform sequence. The reason for performing interleaving on a symbol-by-symbol basis when interleaving a non-uniform sequence is that a non-uniform sequence has a one-to-one correspondence between m-bits and 1-symbols under the correspondence of a lookup table specified by a symbol mapper. Therefore, interleaving in the non-uniform sequence must be performed on a symbol-by-symbol basis corresponding to m bits. This is because interleaving on a bit-by-bit basis would destroy the non-uniform sequence.

[0052] The 1:d converter 150 interleaves the data to be transmitted of the uniform sequence [p1i1]. The 1:d converter 150 interleaves the data to be transmitted of the non-uniform sequence j2. After that, the 1:d converter 150 divides the data of the uniform sequence after interleaving. The division length is determined based on each code parameter and the multi-level degree as described above. The 1:d converter 150 outputs a part of the divided data of the uniform sequence (hereinafter referred to as "data b1") to the first lane. The 1:d converter 150 adds the rest of the divided data of the uniform sequence to the data of the non-uniform sequence after interleaving, and then divides it. The 1:d converter 150 divides each of the divided data z2, z3, z4, z5, z6, z7, z8, z9, z10, z11, z12, z13, z14, z15, z15, z16, z17, z18, z19, z20, z21, z22, z23, z24, z25, z26, z27, z28, z29, z30, z31, z32, z33, z34, z35, z36, z37, z38, z39, z40, z41, z42, z43, z44, z45, z46, z47, z48, z49, z50, z51, z52, z53, z54, z55, z56, z57, z58, z59, z59, z60, z61, z62, z63, z64, z65, z66, z67, z68, z69, z70, z71, z72, z73, z74, z75, z76, z75, z76, z81, d The data b1 output to the first lane is input to the SD-FEC encoding unit 160, and the data z2, z3, z4 output to the second lane, ..., d-th lane are input to the SD-FEC encoding unit 160. d is input to the bit conversion circuit 170.

[0053] 5 is a diagram for explaining the details of the processing performed by the SD-FEC encoding unit 160 and the bit conversion circuit 170 provided in the transmitting device 1. As shown in FIG. 5, for each of the divided sequences, in the first lane, the SD-FEC encoding unit 160 encodes data b1 and outputs sequence z1 to the bit conversion circuit 170. Furthermore, in the first lane, the bit conversion circuit 170 converts the sequence z1 encoded by the SD-FEC encoding unit 160 into the sequence z2, z3, z4, and z5 output to the second to d lanes. dThe bit conversion circuit 170 performs an exclusive OR on each element of a uniform sequence and any bit sequence, and outputs a sequence x1 obtained by performing an exclusive OR on the uniform sequence and any bit sequence, while outputting the sequence as is in the second to dth lanes. The bit conversion circuit 170 performs an exclusive OR on each element of a uniform sequence and any bit sequence. Based on information theoretical properties, if there is no correlation, the exclusive OR of a uniform sequence and an arbitrary bit sequence also results in a bit sequence that follows a uniform distribution, and therefore the output will also be a uniform sequence.

[0054] Fig. 6 is a diagram for explaining the details of the processing performed by the d:m converter 180 and symbol mapper 11 provided in the transmitting device 1. As shown in Fig. 6, the d:m converter 180 assigns a uniform sequence to the LSBs and a non-uniform sequence to the MSBs. The symbol mapper 11 assigns a uniform sequence to the positive and negative signs of symbols and a non-uniform sequence to the amplitude of the symbols. This makes it possible to assign a non-uniform sequence to the amplitude and a uniform sequence to the positive and negative signs in Gray labeling, just like conventional PAS, and shaping can be performed by performing this on both the I and Q sides.

[0055] Fig. 7 is a diagram showing an example of allocation by the symbol mapper 11. Fig. 7 shows, for example, allocation by the symbol mapper 11 in 64QAM (one-sided 8PAM). As shown in Fig. 7, a uniform sequence is allocated to the LSB (first bit on the left), and a bit sequence corresponding to the amplitude sequence is allocated to the MSB (second and third bits).

[0056] Next, the input / output length and rate design of each functional unit in the transmitting device 1 will be explained. It is possible to design the relationship between the coding rate of each element code and the overall coding rate R from the rate of the sequence conversion unit 120 as follows. The following equation (3) shows the bit length at the time of input / output of each functional unit shown in FIG. 1. In equation (3), n represents the bit length of the sequence finally output from the d:m converter 180, and k represents the bit length of the data to be transmitted input to the S / P conversion unit 110. Furthermore, R in equation (3) LSB ,R out ,R DM represent the coding rates of the SD-FEC encoder 160, the outer encoder 140, and the sequence converter 120, respectively.

[0057] Furthermore, in equation (3), (A1) represents the bit length of the uniform sequence output from the S / P conversion unit 110 and input to the P / S conversion unit 130, (A2) represents the bit length of the uniform sequence output from the S / P conversion unit 110 and input to the sequence conversion unit 120, (A3) represents the bit length of the non-uniform sequence output from the sequence conversion unit 120, (A4) represents the bit length of the sequence output from the first lane in the 1:d converter 150, (A5) represents the bit lengths of the sequences output from the second lane to the dth lane in the 1:d converter 150, and (A6) represents the bit length of the sequence exclusive ORed by the bit conversion circuit 170.

[0058]

number

[0059] Furthermore, the relationship (theoretical value) between the coding rate of each element code and the overall coding rate R is expressed by the following equation (4).

[0060]

number

[0061] FIG. 8 is a flowchart showing the flow of processing by the transmission device 1 in the first embodiment. The S / P converter 110 performs serial-to-parallel conversion on the data to be transmitted (step S101). For example, the S / P converter 110 divides the data to be transmitted into two pieces of data. The S / P converter 110 outputs one piece of divided data to the P / S converter 130, and outputs the remaining data to the sequence converter 120. The sequence converter 120 converts the uniform sequence data into non-uniform sequence data by encoding the input data (step S102). The sequence converter 120 outputs the non-uniform sequence data to the P / S converter 130.

[0062] The P / S conversion unit 130 converts the data output from the S / P conversion unit 110 and the non-uniform sequence data output from the sequence conversion unit 120 into serial data by performing parallel-to-serial conversion on them (step S103). Specifically, the P / S conversion unit 130 combines the data output from the S / P conversion unit 110 and the non-uniform sequence data output from the sequence conversion unit 120 and converts them into serial data. The P / S conversion unit 130 outputs the converted data to the outer encoder 140.

[0063] The outer encoder 140 calculates a parity bit using the uniform sequence data and the non-uniform sequence data (step S104). The outer encoder 140 adds the calculated parity bit to the serial data and outputs it to the 1:d converter 150. The 1:d converter 150 interleaves the data output from the outer encoder 140 (step S105). Here, the 1:d converter 150 interleaves the uniform sequence data and the non-uniform sequence data separately. Thereafter, the 1:d converter 150 divides each piece of interleaved data (step S106).

[0064] Specifically, as described in FIG. 4, the 1:d converter 150 first divides the interleaved uniform sequence data into predetermined code lengths. The 1:d converter 150 outputs a portion of the divided uniform sequence data to the first lane. The 1:d converter 150 divides the remaining uniform sequence data and non-uniform sequence data into predetermined code lengths. The 1:d converter 150 outputs the divided data to the second lane to the d-th lane. The data output to the second lane to the d-th lane is input to the bit conversion circuit 170.

[0065] The SD-FEC encoder 160 encodes some data of a uniform sequence (step S107). The SD-FEC encoder 160 outputs the encoded data to the bit conversion circuit 170. The bit conversion circuit 170 converts the bit sequence of the input data (step S108). The d:m converter 180 assigns the data of the uniform sequence output from the bit conversion circuit 170 to the LSBs and the data of the non-uniform sequence to the MSBs (step S109). The symbol mapper 11 generates transmission data by assigning the uniform sequence to the positive and negative of the symbol and the non-uniform sequence to the amplitude of the symbol (step S110). The transmitter 12 transmits the generated transmission data (step S111).

[0066] According to the transmission device 1 configured as described above, CP-MLC can be incorporated into PAS, and it becomes possible to realize FEC and PCS technologies with high frequency efficiency and low computational complexity regardless of the modulation order.

[0067] (Second Embodiment) In the first embodiment, the case where d≥m has been described. In the second embodiment, the case where d<m will be described. FIG. 9 is a block diagram showing a configuration example of the transmission device 1a in the second embodiment. The transmission device 1a includes an encoding circuit 10a, a symbol mapper 11, and a transmitter 12. The encoding circuit 10a is composed of a serial / parallel (S / P) conversion unit 110, a sequence conversion unit 120, a parallel / serial (P / S) conversion unit 130, an outer encoder 140, a 1:d converter 150, an SD-FEC encoder 160a, a bit conversion circuit 170, a d:m converter 180, and a preprocessing circuit 190.

[0068] The encoding circuit 10a is different in configuration from the encoding circuit 10 in that it includes an SD-FEC encoder 160a instead of the SD-FEC encoder 160 and newly includes a preprocessing circuit 190. Other configurations of the encoding circuit 10a are the same as those of the encoding circuit 10. Therefore, the SD-FEC encoder 160a and the preprocessing circuit 190 will be described.

[0069] The preprocessing circuit 190 performs preprocessing on the data output to each lane from the 1:d converter 150. Specifically, the preprocessing circuit 190 exclusive-ORs in advance the bit sequences of the lanes after the second lane that are added by the bit conversion circuit 170 only to the non-uniform sequence bits used for the amplitude among the bits b1 included in the top subchannel.

[0070] The SD-FEC encoding unit 160a encodes the data to which bits are added by the preprocessing circuit 190. The SD-FEC encoding unit 160a uses an organizational code only when d < m.

[0071] FIG. 10 is a diagram for explaining the details of the processing performed by the preprocessing circuit 190 included in the transmission device 1a in the second embodiment. In the example shown in FIG. 10, the number of lanes is set to 2 (d = 2), and the number of bits per symbol is set to 4 (m = 4). The preprocessing circuit 190 exclusive-ORs the non-uniform sequence data input from the first lane at a ratio of (m - 1) / m - (d - 1) / d for the whole. In the example shown in FIG. 10, the preprocessing circuit 190 adds 1 / 4 bits to the data input from the first lane. Since the exclusive-OR is a reversible operation, by providing the preprocessing circuit 190, it is possible to prevent the non-uniform sequence from being disrupted by the exclusive-OR with the bit sequences of the lanes after the second lane in the bit conversion circuit 170, and it becomes possible to equalize the reliability by polarization while outputting the non-uniform sequence as it is.

[0072] FIG. 11 is a block diagram showing a configuration example of the receiving device 2a in the second embodiment. The receiving device 2a includes a receiving unit 20, a symbol demapper 21, and a decoding circuit 22a. The decoding circuit 22a includes an S / P conversion unit 220, an SD likelihood calculation unit 230, an SD-FEC decoding unit 240, a plurality of HD likelihood calculation units 250-1 to 250-d, a d:1 converter 260, an outer code decoder 270, an S / P conversion unit 280, an inverse sequence conversion unit  290, a P / S conversion unit 300, and an inverse preprocessing circuit 310.

[0073] The decoding circuit 22a differs in configuration from the decoding circuit 22 in that it additionally includes an inverse pre-processing circuit 310. The other configuration of the decoding circuit 22a is the same as that of the decoding circuit 22. Therefore, only the inverse pre-processing circuit 310 will be described.

[0074] The inverse preprocessing circuit 310 performs the inverse processing of the preprocessing circuit 190 in the encoding circuit 10a. As a result, the inverse preprocessing circuit 310 outputs a bit sequence corresponding to the amplitude as is.

[0075] FIG. 12 shows the results of a numerical simulation of the present invention and the conventional PAS technology. In the example shown in FIG. 12, the simulation was performed using the numerical simulation parameters shown in the legend. Note that "PAS" in FIG. 12 indicates the results when only the conventional PAS technology was used, and "PAS+CP-MLC (d=2)" indicates the results when the technology of the present invention was used. In the numerical simulation, rSNR was evaluated, and the performance difference from the Shannon limit was evaluated by varying the number of iterations of sum-product decoding of the LDPC code from 1 to 20. Here, HD-FEC was assumed to be virtually concatenated, and the Es / No that achieved the post-FEC-BER that achieved the pre-FEC BER threshold was defined as rSNR. The rate of the sequence conversion unit 120 was set to bit / amplitude = 0.9. The computational complexity was evaluated using the following equation (5) based on Reference 1 below. The LDPC codes used were a (3,15)-regular LDPC code and a (3,25)-regular LDPC code with a row weight of 15 and a column weight of 3. (Reference 1: M. Barakatain, D. Lentner, G. Boecherer and FR Kschischang, “Performance-Complexity Tradeoffs of Concatenated FEC for Higher-Order Modulation”, in Journal of Lightwave Technology, vol. 38, no. 11, pp. 2944-2953, June 1, 2020, doi: 10.1109 / JLT.2020.2983912.)

[0076]

number

[0077] (-)d in Equation 5 c ((-) above d) represents the average degree of the row weights in the LDPC matrix, ν represents the average number of variable nodes with degree 1 connected to each check node on the factor graph in sum-product decoding, and I represents the number of iterations. It can be confirmed that the amount of calculation has been reduced compared to when using only conventional PAS.

[0078] Some of the functional units (e.g., encoding circuits 10, 10a) of the transmitting device 1, 1a and some of the functional units (e.g., decoding circuits 22, 22a) of the receiving device 2, 2a in the above-described embodiments may be implemented by a computer. In this case, a program for implementing these functions may be recorded on a computer-readable recording medium, and the program may be loaded into a computer system and executed. Note that the term "computer system" as used herein includes hardware such as an OS and peripheral devices. Furthermore, the term "computer-readable recording medium" refers to portable media such as flexible disks, optical magnetic disks, ROMs, and CD-ROMs, as well as storage devices such as hard disks built into a computer system. Furthermore, the term "computer-readable recording medium" may also include devices that dynamically store programs for a short period of time, such as communication lines when transmitting programs via networks such as the Internet or communication lines such as telephone lines, or devices that store programs for a certain period of time, such as volatile memory within the computer systems that serve as the server or client in such cases. Furthermore, the above program may be one that realizes part of the above-mentioned functions, or may be one that can realize the above-mentioned functions in combination with a program already recorded in a computer system, or may be one that is realized using a programmable logic device such as an FPGA (Field Programmable Gate Array).

[0079] Although an embodiment of the present invention has been described above in detail with reference to the drawings, the specific configuration is not limited to this embodiment, and includes designs within the scope of the gist of the present invention. [Industrial Applicability]

[0080] The present invention is applicable to communication systems that use encoders and decoders. [Explanation of symbols]

[0081] 1a...transmitting device, 2a...receiving device, 10a...encoding circuit, 20...receiving unit, 21...symbol demapper, 22a...decoding circuit, 110...S / P conversion unit, 120...sequence conversion unit, 130...P / S conversion unit, 140...outer encoder, 150...1:d converter, 160...SD-FEC encoding unit, 170...bit conversion circuit, 180...d:m converter, 190...preprocessing circuit, 220...S / P conversion unit, 230...SD likelihood calculation unit, 240...SD-FEC decoding unit, 250...HD likelihood calculation unit, 260...d:1 converter, 270...outer code decoder, 280...S / P conversion unit, 290...inverse sequence conversion unit, 300...P / S conversion unit, 310...

Claims

1. 1. A coding circuit for use in coherent digital signal processing, comprising: a serial-parallel circuit that converts input uniform sequence data into a plurality of divided data by serial-parallel conversion; a sequence conversion unit that encodes the divided data and converts it into non-uniform sequence divided data; a parallel-serial circuit that converts the divided data output from the serial-parallel circuit and the non-uniform series divided data converted by the series converter into serial data by performing parallel-to-serial conversion; an outer coding unit that adds an error correction code to the serial data and encodes it; a division unit that divides the serial data to which the error correction code has been added into a plurality of divided data; a bit conversion circuit that regards the plurality of divided data divided by the dividing unit as data to be transmitted on different sub-channels, and converts bit sequences to make the communication path capacities of the sub-channels unequal; a conversion unit that performs gray labeling on the plurality of divided data output from the bit conversion circuit to assign uniform sequence data to the least significant bit and non-uniform sequence data to the most significant bit; An encoding circuit comprising:

2. further comprising a pre-processing circuit for outputting a bit sequence corresponding to the amplitude as is when the number of bits per symbol is greater than the number of divisions made by the division unit; 2. The encoding circuit according to claim 1.

3. A decoding circuit for use in coherent digital signal processing, comprising: a serial-parallel circuit that converts input data into serial-parallel data and divides the data into a plurality of divided data; a first likelihood calculation circuit that calculates a likelihood by soft decision based on some of the plurality of divided data and information on noise occurring in a communication channel; a decoding unit that receives the likelihood as an input and corrects an error in the divided data input to the first likelihood calculation circuit; one or more second likelihood calculation circuits that calculate likelihoods related to conditional probabilities and perform hard decisions based on the codewords error-corrected by the decoding unit, some of the divided data among the plurality of divided data, and information on noise occurring in a communication channel; a combining unit that combines the obtained bit sequence with the decoded information bits; an outer code decoding unit that decodes the outer code; a serial-parallel circuit that converts input data from serial to parallel to divide the data into uniform sequence divided data and non-uniform sequence divided data; a sequence conversion unit that decodes the non-uniform sequence of divided data and converts it into uniform sequence of divided data; a parallel-serial circuit that restores the uniform sequence data by performing parallel-to-serial conversion between the uniform sequence divided data output from the sequence conversion unit and the divided uniform sequence divided data; an inverse pre-processing circuit for outputting a bit sequence corresponding to the amplitude as is when the number of bits per symbol is greater than the number of divisions by the serial-parallel circuit; A decoding circuit comprising:

4. 1. An encoding method for use in coherent digital signal processing, comprising: The input uniform sequence data is divided into multiple divided data by serial-to-parallel conversion, Encoding the divided data to convert it into a non-uniform sequence of divided data; converting the divided data and the non-uniform sequence divided data into serial data by performing parallel-to-serial conversion; encoding the serial data by adding an error correction code; Dividing the serial data to which the error correction code has been added into a plurality of divided data; The divided data are regarded as data to be transmitted on separate sub-channels, and a bit sequence is converted to make the communication path capacities of the sub-channels unequal; performing gray labeling on the plurality of divided data, so that uniform sequence data is assigned to the least significant bit and non-uniform sequence data is assigned to the most significant bit; Encoding method.

5. 1. A decoding method for use in coherent digital signal processing, comprising: The input data is divided into multiple divided data by serial-to-parallel conversion, calculating likelihoods by soft decision based on some of the divided data sets and information on noise occurring in a communication channel; correcting errors in the divided data using the likelihood as an input; calculating likelihoods related to conditional probabilities based on the error-corrected codeword, some of the divided data pieces, and information on noise occurring in the communication channel, and making hard decisions; The obtained bit sequence is combined with the decoded information bits, Decode the outer code, The input data is serial-to-parallel converted to divide the data into uniformly-spaced divided data and non-uniformly-spaced divided data, Decoding the non-uniform sequence of divided data and converting it into uniform sequence of divided data; The uniform sequence data is restored by performing parallel-to-serial conversion between the converted uniform sequence divided data and the divided uniform sequence divided data; When the number of bits per symbol is greater than the number of divisions by the serial-parallel conversion, a bit sequence corresponding to the amplitude is output as is. Decryption method.

6. On the computer, The input uniform sequence data is divided into multiple divided data by serial-to-parallel conversion, Encoding the divided data to convert it into a non-uniform sequence of divided data; converting the divided data and the non-uniform series divided data into serial data by parallel-to-serial conversion; Encoding the serial data by adding an error correction code; Dividing the serial data to which the error correction code has been added into a plurality of divided data; The divided data are regarded as data to be transmitted through separate sub-channels, and bit sequences are converted to make the communication path capacities of the sub-channels uneven; A computer program for executing a process of assigning uniform sequence data to the least significant bits and non-uniform sequence data to the most significant bits by performing gray labeling on the plurality of divided data.

7. On the computer, The input data is divided into multiple divided data by serial-to-parallel conversion, calculating likelihoods by soft decision based on some of the divided data sets and information on noise occurring in a communication channel; correcting errors in the divided data using the likelihood as an input; calculating likelihoods related to conditional probabilities based on the error-corrected codeword, some of the divided data pieces, and information on noise occurring in the communication channel, and making hard decisions; The obtained bit sequence is combined with the decoded information bits, Decode the outer code, The input data is serial-to-parallel converted to divide the data into uniformly-spaced divided data and non-uniformly-spaced divided data, Decoding the non-uniform sequence of divided data and converting it into uniform sequence of divided data; performing a process of restoring uniform sequence data by performing parallel-to-serial conversion between the converted uniform sequence divided data and the divided uniform sequence divided data; A computer program for outputting a bit sequence corresponding to the amplitude as is when the number of bits per symbol is greater than the number of divisions by the serial-to-parallel conversion.

Images