Multi-step process inspection method

Abstract

To provide improved metrology methods for use in lithographic device manufacturing processes.SOLUTION: Two adjacent lithographically defined features have variations in their edges. When a conformal coating process is performed to create first spacers 301b-301d, the first spacers take the shape of respective edges of the lithographically defined features and therefore are not straight. It is possible that variations in the width of the first spacers may also occur at this stage. Second spacers 302a-302g are formed in a second conformal coating process, and then the first spacers 301b-301d are removed to reach the final stage.SELECTED DRAWING: Figure 3C

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to European Patent Application Publication No. 20156290.7, filed February 10, 2020, the entire contents of which are incorporated herein by reference.

[0002]

[0002] The present disclosure relates to inspection methods, particularly for device manufacturing using lithographic apparatus. [Background technology]

[0003] A lithographic apparatus is a machine that applies a desired pattern onto a substrate, usually onto a target portion of the substrate. Lithographic apparatus can be used, for example, in the manufacture of integrated circuits (ICs). In doing so, a patterning device (alternatively referred to as a mask or reticle) can be used to generate the circuit pattern configured in an individual layer of the IC. This pattern can be transferred onto a target portion (e.g. comprising part of, one, or several dies) on the substrate (e.g. a silicon wafer). Transfer of the pattern is typically via imaging onto a layer of radiation-sensitive material (resist) provided on the substrate. In general, a single substrate will contain a network of adjacent target portions that are successively patterned.

[0004]

[0004] To meet the continuing demand for shrinking the size of features that can be formed in lithographic techniques, various processes involving multiple steps have been proposed to create a single layer at a smaller size or pitch than can be formed in a single optical patterning step. Examples of such processes include litho-etch-litho-etch (LELE), self-aligned double patterning (SADP), and self-aligned quadruple patterning (SAQP). These processes make inspection and metrology processes difficult. Summary of the Invention

[0005]

[0005] The present disclosure aims to provide improved metrology methods, for example for use in lithographic device manufacturing processes.

[0006] According to one embodiment, there is provided an image analysis method for identifying features in an image of a portion of an array of features formed by a multi-step process, comprising: Analyzing the variability of features seen in the image; Associating features of the image with steps of a multi-step process based at least in part on results of the analysis; and An image analysis method is provided, comprising:

[0007]

[0007] According to one embodiment, there is provided a device manufacturing method, comprising: forming an array of features on a substrate using a multi-step process; acquiring an image of a portion of the array; analyzing the image as described above to associate features with steps in a multi-step process; Detecting defects in features of the array; Associating features to steps and taking corrective actions based on detected defects; A device manufacturing method is provided, comprising:

[0008] According to one embodiment, there is provided an image analysis apparatus for identifying features in an image of a portion of an array of features formed by a multi-step process, comprising: an image analysis module configured to analyze variability of features found in the image; an association module configured to associate features of the image with steps of a multi-step process based at least in part on results of the analysis; An image analysis device is provided, comprising:

[0009] According to one embodiment, there is provided a method for analyzing an image of a portion of an array of features formed by a self-aligned quadruple patterning process, comprising: Identifying a plurality of features within the image; assigning a characteristic value to each respective identified feature, the characteristic value representing a variability in the position or shape of the feature; grouping the features into first, second, third and fourth groups, each group containing a set of aligned features, the first, second, third and fourth groups being adjacent to one another in that order; determining a first correlation value between the variability of the characteristic values ​​of the first group and the variability of the characteristic values ​​of the second group; determining a second correlation value between the variability of the characteristic values ​​of the second group and the variability of the characteristic values ​​of the third group; if the first correlation value is higher than the second correlation value, associating the first and second groups with the first spacer of the self-aligned quadruple patterning process, and if not, associating the second and third groups with the first spacer of the self-aligned quadruple patterning process. A method is provided which includes:

[0010]

[0010] Some embodiments will now be described, by way of example, with reference to the accompanying drawings, in which: [Brief explanation of the drawings]

[0011] [Figure 1]

[0011] A lithographic apparatus is shown together with other equipment that forms a semiconductor device manufacturing facility. [Figure 2A]

[0012] 1 illustrates steps in a self-aligned quadruple patterning process. [Figure 2B]

[0012] Steps in a self-aligned quadruple patterning process are shown. [Figure 2C]

[0012] Steps in a self-aligned quadruple patterning process are shown. [Figure 2D]

[0012] Steps in a self-aligned quadruple patterning process are shown. [Figure 2E]

[0012] Steps in a self-aligned quadruple patterning process are shown. [Figure 2F]

[0012] Steps in a self-aligned quadruple patterning process are shown. [Figure 3A]

[0013] 1 illustrates the effect of errors in a self-aligned quadruple patterning process. [Figure 3B]

[0013] The effect of errors in a self-aligned quadruple patterning process is shown. [Figure 3C]

[0013] The effect of errors in a self-aligned quadruple patterning process is shown. [Figure 3D]

[0013] The effect of errors in a self-aligned quadruple patterning process is shown. [Figure 4]

[0014] 1 shows an example image of a portion of an array of features. [Figure 5]

[0015] 1 shows an example image of a portion of an array of features including a defect. [Figure 6]

[0016] 1 illustrates an example of the results of a process for defining feature contours and determining feature centroids. [Figure 7]

[0017] Shows grouping of features into multiple columns. [Figure 8]

[0018] 1 is a flowchart of a device manufacturing method. DETAILED DESCRIPTION OF THE INVENTION

[0012]

[0019] Electronic devices consist of circuits formed on a piece of silicon called a substrate. Many circuits can be formed together on the same piece of silicon, called an integrated circuit, or IC. The size of these circuits is shrinking dramatically so that more and more circuits can fit on a substrate. For example, the IC chip in a smartphone can be as small as a thumbnail, but contain over 2 billion transistors, each less than 1 / 1000 the size of a human hair.

[0013]

[0020] The manufacturing of these tiny ICs is a complex, time-consuming, and expensive process, often involving hundreds of individual steps. An error in even one step can result in a defect in the finished IC, rendering it useless. Therefore, one goal of the manufacturing process is to avoid such defects and maximize the number of functional ICs created in the process, i.e., to increase the overall yield of the process.

[0014]

[0021] One factor in improving yield is monitoring the chip manufacturing process to ensure that a sufficient number of functional integrated circuits are being produced. One way to monitor the process is to inspect the chip circuit structures at various stages of their formation. Inspection can be performed using tools such as scanning electron microscopes (SEMs) or optical inspection systems. Such systems can be used to image these structures, effectively taking "pictures" of the structures on the wafer; SEMs can image the smallest of these structures. The images can be used to determine whether the structures were properly formed in the correct locations. If the structures are defective, the process can be adjusted, thus reducing the likelihood of the defect recurring.

[0015]

[0022] A key step in the lithography manufacturing process for chips is the optical step, in which an image of a feature is projected onto a substrate (wafer), but there is a limit to how small the features can be formed this way. To create even smaller features, a process uses a chemical step to build several (e.g., four) smaller features based on one larger feature created by the optical step. One example is creating every other feature in one step, and creating the features between them in a second step. One example is the lines used in high-capacity memory chips. Such ICs often have large areas filled with regular arrays of lines, and if one of the features is defective, it can be difficult to determine in which step of the process the defective feature was formed. Because the features are all assumed to be identical, it may be necessary to count the features from the edge of the array to determine in which step a particular feature was formed.

[0016]

[0023] This disclosure proposes a technique for identifying in which step of a multi-step process a given feature was formed by examining small variations in the shape and / or position of features in an array. The inventors have determined that such variations, which are not large enough to affect the device's functionality or be considered defects, have characteristics that depend on the process step in which they were formed. In one example, a process step may produce similar variations in all of the features created in that step, and therefore, by examining correlations between the variations in the features, it is possible to identify the features created in that step.

[0017]

[0024] Before describing the embodiments in detail, it is beneficial to present an exemplary environment in which the techniques disclosed herein can be implemented.

[0018]

[0025] Figure 1 shows a typical layout of a semiconductor manufacturing facility. A lithographic apparatus 100 applies a desired pattern to a substrate. Lithographic apparatus are used, for example, in the manufacture of integrated circuits (ICs). In doing so, a patterning device MA (alternatively called a mask or reticle) contains the circuit pattern of features (often referred to as "product features") to be formed in an individual layer of the IC. This pattern is transferred onto a target portion (e.g. comprising part of, one, or several dies) on a substrate "W" (e.g. a silicon wafer) by exposing 104 the patterning device onto a layer of radiation-sensitive material (resist) provided on the substrate. In general, a single substrate will contain a network of adjacent target portions that are successively patterned.

[0019]

[0026] Known lithographic apparatus irradiate each target portion of the substrate by illuminating the patterning device while synchronously positioning the target portion at an image position of the patterning device. The illuminated target portion of the substrate is called an "exposure field" or simply a "field." The layout of the field on the substrate is typically a network of adjacent rectangles or other shapes aligned according to an orthogonal two-dimensional coordinate system (e.g., aligned along mutually orthogonal X and Y axes).

[0020]

[0027] A lithography system's requirement is to accurately reproduce the desired pattern on the substrate. The position and dimensions of the applied product features must be within certain tolerances. Position errors can result in overlay errors (sometimes called "overlay"). Overlay is the error in locating a first product feature in a first layer relative to a second product feature in a second layer. Lithography systems reduce overlay errors by precisely aligning each wafer to a reference before patterning. This is done by measuring the position of alignment marks applied to the substrate. To prevent unacceptable overlay errors, the substrate's position is controlled during the patterning process based on the alignment measurements. Alignment marks are typically created as part of the product image, generating a reference against which overlay is measured. Alternatively, alignment marks from a previously formed layer can be used.

[0021]

[0028] If the applied dose associated with exposure 104 is not within specifications, errors in the critical dimension (CD) of the product features can occur. For this reason, lithography apparatus 100 must be able to accurately control the dose of radiation applied to the substrate. CD errors can also occur when the substrate is not correctly positioned with respect to the focal plane associated with the pattern image. Focus position errors are typically related to non-flatness of the substrate surface. Lithography apparatuses reduce these focus position errors by measuring the substrate surface topography using a level sensor before patterning. Substrate height correction is applied during subsequent patterning to ensure accurate imaging (focus) of the patterning device onto the substrate.

[0022]

[0029] The patterned substrate is inspected by a metrology tool 140 to verify overlay and CD errors associated with the lithography process. Common examples of metrology tools are scatterometers and scanning electron microscopes. Traditionally, scatterometers measure the characteristics of dedicated metrology targets. These metrology targets represent product features, but their dimensions are typically larger to enable accurate measurements. Scatterometers measure overlay by detecting asymmetries in the diffraction pattern associated with an overlay metrology target. Critical dimensions are measured by analyzing the diffraction pattern associated with a CD metrology target. The CD metrology target is used to measure the results of the most recently exposed layer. An overlay target is used to measure the positional difference between the previous and latest layers. Electron beam (e-beam)-based inspection tools, such as scanning electron microscopes (SEMs), can often provide superior results in measuring small overlay and CD values.

[0023]

[0030] Within a semiconductor manufacturing facility, lithography apparatus 100 and metrology apparatus 140 form part of a "lithocell" or "lithocluster." The lithocluster also includes a coating apparatus 108 for applying photoresist to substrate W, a bake apparatus 110, a developer apparatus 112 for developing the exposed pattern into a physical resist pattern, an etching station 122, an apparatus 124 for performing a post-etch annealing step, and possibly further processing apparatus 126. The metrology apparatus is configured to inspect the substrate after development 112 or after further processing (e.g., etching). The various apparatus within the lithocell are controlled by a supervisory control system SCS, which issues control signals 166 to control the lithography apparatus via lithography apparatus control unit LACU 106 to implement recipe R. The SCS operates the various apparatus to enable maximum throughput and product yield. An important control mechanism is the metrology tool 140's feedback 146 (via the SCS) to various tools, particularly the lithography tool 100. Based on the characteristics of the metrology feedback, corrective actions are determined to improve the processing quality of subsequent substrates. The SCS can be a single computer or multiple computers, which may or may not be in communication with each other. The recipe R can be implemented as a single recipe or multiple independent recipes. For example, a recipe for a process step, such as etching, may be completely independent from a recipe for inspecting the results of that process step (e.g., etching). For example, two or more recipes for individual steps may be interrelated, with one recipe being adjusted to take into account the results of another recipe being performed on the same or different substrates.

[0024]

[0031] The performance of lithographic apparatus is conventionally controlled and corrected by methods such as advanced process control (APC), as described in, for example, U.S. Patent Application Publication No. 2012008127A1. The advanced process control technique uses measurements of metrology targets applied to the substrate. A manufacturing execution system (MES) schedules the APC measurements and communicates the measurement results to a data processing unit. The data processing unit converts the characteristics of the measurement data into a recipe containing instructions for the lithographic apparatus. This method is very effective in suppressing drift phenomena associated with the lithographic apparatus.

[0025]

[0032] In semiconductor manufacturing, processing of metrology data for corrective actions taken by processing equipment is important. In addition to metrology data, characteristics of individual patterning devices, substrates, processing equipment, and other context data may also be required to further optimize the manufacturing process. A framework for optimizing the entire lithography process using available metrology and context data is generally represented as part of integrated lithography. For example, context data regarding CD errors at a reticle can be used to control various tools (lithography tools, etching stations) so that the CD errors do not affect the yield of the manufacturing process. Subsequent metrology data can then be used to verify the effectiveness of the control strategy and determine further corrective actions.

[0026]

[0033] Self-aligned quadruple patterning (SAQP), also known as sidewall-assisted quadruple patterning, is a technique for creating features at one-quarter the pitch of features created by the exposure (lithography) step. SAQP has been developed to print lines or regular holes at denser pitches without using reduced exposure wavelengths. This process is described with reference to Figures 2A-2F.

[0027]

[0034] In each of Figures 2A-2F, the left image is a plan view of the result of a process step, and the right image is a cross-sectional view. In a first step, a resist feature 200, e.g., a line, is formed on the wafer. The line has a width equal to 3P and is part of an array of similar lines with a pitch of 8P. In a second step, as shown in Figure 2B, a conformal coating process is performed to apply first spacers 201 to each sidewall of the resist feature 200. The coating process is carefully controlled so that the first spacers 201 each have a width P.

[0028]

[0035] As shown in Figure 2C, the original resist feature 200 is removed, leaving two first spacers 201, where the spacers 201 are separated by a gap of width 3P. Then, as shown in Figure 2D, a second conformal coating process is performed to form second spacer layers 202 on either side of each first spacer 201. Again, the coating process is carefully controlled so that each second spacer 202 has a width P. This leaves a gap of width P between the two spacer clusters.

[0029]

[0036] Then, as shown in FIG. 2E, the first spacers 201 are chemically removed, leaving only the second spacers 202. Each second spacer 202 has a width P, and the gaps between the second spacers 202 also have a width P. Thus, while the original pitch was 8P, the pitch of the new pattern is 2P. Finally, a pattern transfer step, such as an etching step, is performed to remove the spacers (if not removed during the etching process), resulting in a set of trenches 203 as shown in FIG. 2F.

[0030]

[0037] It should be understood that the above process represents an idealized form of the SAQP process. In reality, there will be some variation in feature position (e.g., due to overlay) and / or width (CD error) from the ideal (or nominal) pattern. Thus, due to overlay, CD and CD uniformity (CDu) errors, as well as random variations and imperfections, lithographically defined features 200 may have non-straight edges. This effect is illustrated in Figures 3A-D, where the variation from the nominal feature size is exaggerated.

[0031]

[0038] FIG. 3A shows two adjacent lithographically defined features 300a, 300b, in this example lines, with variations in their edges. As shown in FIG. 3B, when a conformal coating process is performed to create first spacers 301a-301d, the first spacers take the shape of the edges of the lithographically defined features 300a-301d and are therefore not straight. Variations in the width of the first spacers may also occur at this stage. As shown in FIG. 3C, a second conformal coating process forms second spacers 302a-302g, and then the first spacers 301a-301d are removed, leading to the final stage shown in FIG. 3D. In FIG. 3, uniform rows are numbered 0, 1, 2, and 3.

[0032]

[0039] When variations occur, knowing which lines in the final pattern correspond to which lines in intermediate process steps is valuable to lithographers because it allows them to determine which process steps are most error-prone and therefore which should be optimized. One approach to determining how lines end up in the final pattern is to acquire addressed SEM images—SEM images of known locations within the pattern. However, the addressing accuracy of the SEM is often not sufficient to reliably distinguish lines based on their location within the image. Figure 4 is a schematic diagram of what such an image might look like. Line widths can be on the order of 20–30 nm, so it can be seen that positioning errors in the SEM image on that order can lead to incorrect attribution of lines within the image. Figure 5 is a similar schematic diagram to Figure 4, but shows the case where some features have merged to form defects.

[0033]

[0040] Note that Figures 4 and 5 show the array of features after a cutting process step has been performed, thus dividing each of the original line features into a number of shorter, but still elongated, line segments. The technique can be applied to an image of the array of lines before the cutting step or to an image of the array of features after the cutting step. For applications after the cutting step, line segments within a column or region that originate from the same line feature can be grouped and treated as one feature. Note that the pattern of elongated features can be aligned with either the x-axis or y-axis of the lithographic apparatus, or can have features at intermediate angles. It is desirable, but not necessary, for the coordinate system of the SEM to be aligned with the coordinate system of the lithographic apparatus.

[0034]

[0041] A method that may provide greater certainty about line distinction is to image the boundary of the array and count the lines from the boundary to determine line distinction. However, this approach has the disadvantage that only a small portion of the array can be imaged, and the array boundary itself may be prone to error. Furthermore, imaging only the side or corner of the array may not be representative of the whole.

[0035]

[0042] Thus, the present disclosure provides a method for determining which lines in an array are associated with which process steps in a multi-step process, e.g., which gap corresponds to the first spacer in a SAQP process, by correlating the placement variations of adjacent lines.

[0036]

[0043] The techniques disclosed herein are applicable to a variety of multi-step processes, i.e., processes in which a single lithographically defined feature is transformed through additional process steps into multiple features in the final device. The techniques are particularly applicable when the multi-step process includes a conformal coating process, i.e., a process that forms a layer of a constant width or thickness.

[0037]

[0044] From FIG. 3D, it can be seen that the lines labeled 0 and 1 have similar contours and the same variations. The reason for this is that the deposition step, when performed by ALD (atomic layer deposition), is usually very conformal. Therefore, the resulting placement variations are the same as the original line edge roughness (LER) on the left side of the left line printed in the first lithography step (FIG. 3A), and the gap between these lines corresponds to the first spacer 301a. Therefore, the correlation of placement variations between lines 0 and 1 is expected to be high.

[0038]

[0045] For the same reason, the alignment correlation between lines 2 and 3 is expected to be high, while the alignment correlation between lines 1 and 2 or between lines 3 and 0 is expected to be lower or insignificant. Thus, by determining the alignment correlation between neighboring lines, two of the four pairs of neighboring lines (0-1, 1-2, 2-3, 3-4) are expected to have large correlations, while the other two pairs are expected to have small correlations, where the large correlations correspond to gaps caused by the first spacer.

[0039]

[0046] A more detailed exemplary procedure will now be described with reference to FIG.

[0040]

[0047] A pattern comprising an array of features in a single layer is formed on a substrate (S1) and imaged using a scanning electron microscope or similar tool (S2). The pattern may be formed in a multi-step process such as SAQP, where different features or portions of features are defined by different steps of the multi-step process. The imaging step may be performed, for example, after the pattern has been transferred to the substrate by etch features or while the pattern is still defined by sacrificial features such as spacers.

[0041]

[0048] Processing of images from an SEM begins with defining the contours of the structures (S3), followed by the process of determining the center of each structure. Any suitable algorithm for determining the contours of objects in an image can be used. In particular, it is desirable to select an algorithm specifically adapted to the shape of the structure to be contoured. The center of a feature can be defined as its centroid, although other definitions of the center of a feature are possible. Examples include the center of a region, the geometric midpoint (i.e., the point midway between the endpoints of the contour in two orthogonal directions, such as x and y), or the centerline. The present invention can also utilize other characteristics of a feature, such as the position of an edge or the magnitude of a dimension, e.g., line width. A center point or centerline can be defined for a portion of a feature. Weighting can be applied to points, e.g., boundary points, to calculate an average position.

[0042]

[0049] In some cases, it may be desirable to remove distortions from the SEM images (S4), particularly by decomposing the determined centroid grid distortion into static and time-varying SEM contributions and actual distortions at the wafer. A suitable method for this is described in European Patent Application Publication No. 18210026.3, which is incorporated herein by reference. While distortion removal can be performed before defining the contours and determining the centroids, the amount of processing required is reduced if performed at the centroids. Without distortion removal, differences in correlation values ​​obtained and used later in the process may be reduced, if not eliminated.

[0043]

[0050] The next step is to label (S5), e.g., number, all the lines of the structure. Suitable labeling schemes include 0, 1, 2, 3, 0, 1, 2, etc. Which line is called 0 is arbitrary.

[0044]

[0051] The multiple correlation coefficients between a structure on a given line and neighboring structures on adjacent lines are then determined (S6). This is illustrated in Figure 7, which shows a column (or group) of labeled features, with the center of each feature indicated by an X. To determine the multiple correlation coefficients, we define a correlation vector for the portion of the misalignment of a structure on a given line that is explained by the variation in hole positions on neighboring lines:

number

[0045]

[0052] Furthermore, we define the correlation matrix of neighboring structures on the right line Q as follows:

number

number

[0046]

[0053] In experiments conducted using 15 different images of instances of patterns formed using SAQP, we found that there was a large R between two pairs of neighboring lines. 2 A significant correlation was observed for one pair, but a small correlation was observed for the other two pairs. The line pair with the larger correlation is associated with the first spacer, and the line pair with the smaller correlation is associated with the second spacer (S7).

[0047]

[0054] Defects in the pattern imaged by the SEM are detected (S8). Defect detection can be performed before, after, or in parallel with the above steps to associate lines with specific process steps. By combining knowledge of which features are associated with which process steps and defect locations, it is possible to determine corrective action to take (S9). Possible forms of corrective action can range from adjusting the process to be applied to subsequent substrates to reworking already processed substrates. In some cases, defects can be addressed by adjusting subsequent steps performed on the same substrate. In some cases, corrective action can include discarding substandard substrates and then performing further processing on the substrate. Any action intended to improve yield or throughput or otherwise address detected defects can be considered a corrective action.

[0048]

[0055] Other features that may be used in the techniques disclosed herein include truncations related to SADP and SAQP processes, and the techniques described herein can be used to analyze correlations in the placement of such truncated features.

[0049]

[0056] Another possibility is to measure the line before the cut is made and determine the power spectral density (PSD) of the correlation, which may provide a stronger signal to distinguish different features and therefore be more important for "better printing" at smaller LER.

[0050]

[0057] Also, the high frequency content of the PSD of the LER can be examined for all edges. Specifically, in some cases, it is expected that there will be differences in the high frequency content inside and outside the original lithographically defined line, and therefore the location of the original lithographically defined line (Gap 1-2 or Gap 3-0) can also be determined.

[0051]

[0058] Thus, the techniques described herein allow for the distinction of gaps from the first spacers as well as the lines and spaces of the original lithographically defined pattern, even without good addressing of the SEM.

[0052]

[0059] While particular techniques have been described above, it will be appreciated that the present disclosure may be practiced in ways other than those described above.

[0053]

[0060] One embodiment may include a computer program including one or more sequences of machine-readable instructions configured to instruct various apparatus such as those shown in Figure 1 to perform the measurement and optimization steps as described above to control the subsequent exposure process. The computer program may, for example, be executed in the control unit LACU or supervisory control system SCS of Figure 1, or a combination of both. Also provided may be a data storage medium (e.g., a semiconductor memory, a magnetic disk, or an optical disk) having such a computer program stored thereon.

[0054]

[0061] Although specific reference has been made above to optical lithography, it will be appreciated that the techniques disclosed herein may also be used for other applications, such as imprint lithography. In imprint lithography, a topography in a patterning device defines the pattern to be created on a substrate. The topography of the patterning device may be written into a layer of resist supplied to the substrate and the resist is cured by applying electromagnetic radiation, heat, pressure or a combination thereof. The patterning device is moved out of the resist, leaving a pattern in it after the resist is cured.

[0055]

[0062] As used herein, the terms "radiation" and "beam" encompass all types of electromagnetic radiation, including ultraviolet (UV) radiation (e.g., having wavelengths of about 365, 355, 248, 193, 157, or 126 nm) and extreme ultraviolet (EUV) radiation (e.g., having wavelengths in the range of 1-100 nm) and particle beams such as ion beams or electron beams. Implementations of scatterometers and other inspection devices can be performed at UV and EUV wavelengths using appropriate radiation sources, and this disclosure is not limited to systems using IR and visible radiation.

[0056]

[0063] The term "lens", where the context allows, may refer to any one or combination of various types of optical components, including refractive, reflective, magnetic, electromagnetic and electrostatic optical components. Reflective components are often used in devices operating in the UV and / or EUV range.

[0057]

[0064] As used herein, the term "or" includes all possible combinations unless otherwise specified or infeasible. For example, if a component is described as being able to include A or B, the component can include A or B, or A and B, unless otherwise specified or infeasible. As a second example, if a component is described as being able to include A, B, or C, the component can include A, or B, or C, or A and B, or A and C, or B and C, or A, B, and C, unless otherwise specified or infeasible.

[0058]

[0065] Certain aspects of the disclosure are described in the following numbered clauses. 1. An image analysis method for identifying features in an image of a portion of an array of features formed by a multi-step process, comprising: Analyzing the variability of features seen in the image; Associating features of the image with steps of a multi-step process based at least in part on results of the analysis; and Image analysis methods including: 2. The method of clause 1, wherein the variation is a variation in the position or shape of a feature. 3. Variation is feature centroids, The geometric midpoint of the feature, Centerlines of features, Edges of features, Feature dimensions, Center of part of a feature 3. The method of claim 2, wherein the variation is at one or more positions of 4. The method of any one of clauses 1 to 3, wherein the analysis includes analyzing correlations between variations of different features. 5. The method of clause 4, wherein the analyzing includes determining a correlation between a variability of the first feature and a variability of each of n adjacent features, where n is less than four. 6. The method of clause 4, wherein the analysis includes determining correlations between variations of adjacent features. 7. The method of clause 4, 5 or 6, wherein the associating associates features with correlated variations to the same process step. 8. The method of clause 4, 5, 6 or 7, wherein the association comprises dividing the features into sets having similar correlation levels and associating each set with a respective one of the process steps. 9. A method according to any one of the preceding clauses, wherein the analysis comprises selecting a plurality of regions of the image, each region containing a plurality of features, and determining correlations between features in different regions. 10. The method of clause 9, wherein each region comprises a plurality of aligned features. 11. The method of any one of the preceding clauses, wherein the multi-step process includes a step of conformal deposition. 12. The method of any one of the preceding clauses, wherein the analyzing includes determining a contour of each of the features. 13. The method of any one of the preceding clauses, wherein the image is an image obtained by scanning electron microscopy. 14. A device manufacturing method comprising: forming an array of features on a substrate using a multi-step process; acquiring an image of a portion of the array; Analysing the image according to the method of any one of clauses 1 to 13 to associate features with steps of a multi-step process; Detecting defects in features of the array; Associating features to steps and taking corrective actions based on detected defects; A device manufacturing method comprising: 15. An image analysis apparatus for identifying features in an image of a portion of an array of features formed by a multi-step process, comprising: an image analysis module configured to analyze variability of features visible in the image; an association module configured to associate features of the image with steps of a multi-step process based at least in part on results of the analysis; An image analysis device comprising: 16. The apparatus of clause 15, wherein the variation is a variation in the position or shape of a feature. 17. Variation is feature centroids, The geometric midpoint of the feature, Centerlines of features, Edges of features, Feature dimensions, Center of part of a feature 17. The apparatus of claim 16, wherein the variation in the position of one or more of 18. The apparatus of any one of clauses 15 to 17, wherein the image analysis module is configured to analyze correlations between variations of different features. 19. An apparatus described in any one of clauses 15 to 17, wherein the image analysis module is configured to determine a correlation between the variation of a first feature and the variation of each of n adjacent features, where n is less than 4. 20. The apparatus of clause 18, wherein the image analysis module is configured to determine correlations between variations in adjacent features. 21. The apparatus of clause 18, 19 or 20, wherein the association module is configured to associate features having correlated variations with the same process step. 22. An apparatus according to any one of clauses 18 to 21, wherein the association module is configured to divide the features into a plurality of sets having similar correlation levels, and associate each set with a respective one of the process steps. 23. An apparatus described in any one of clauses 15 to 22, wherein the image analysis module is configured to select multiple regions of the image, each region containing multiple features, and determine correlations between features in different regions. 24. The apparatus of clause 22, wherein each region includes a plurality of aligned features. 25. An apparatus according to any one of clauses 15 to 24, wherein the multi-step process includes a conformal deposition step. 26. An apparatus according to any one of clauses 15 to 25, wherein the analysis includes determining the contours of each of the features. 27. An inspection apparatus comprising a scanning electron microscope and an image analysis apparatus according to any one of clauses 15 to 26 configured to analyze an image produced by the scanning electron microscope. 28. A method of analyzing an image of a portion of an array of features formed by a self-aligned quadruple patterning process, comprising: Identifying a plurality of features within the image; assigning a characteristic value to each identified feature, the characteristic value representing a variability in the position or shape of the feature; grouping the features into first, second, third and fourth groups, each group containing a set of aligned features, the first, second, third and fourth groups being adjacent to one another in that order; determining a first correlation value between the variability of the characteristic values ​​of the first group and the variability of the characteristic values ​​of the second group; determining a second correlation value between the variability of the characteristic values ​​of the second group and the variability of the characteristic values ​​of the third group; if the first correlation value is higher than the second correlation value, associating the first and second groups with the first spacer of the self-aligned quadruple patterning process, and if not, associating the second and third groups with the first spacer of the self-aligned quadruple patterning process. A method comprising: 29. The characteristic value is · The location of the feature's centroid, The location of the geometric midpoint of the feature, · feature centerline location, the location of the feature's edges, Feature dimensions, The center position of a part of a feature The method described in clause 17, which is one of the methods described in clause 17. 30. The method of clause 28 or 29, wherein the feature is a line feature with or without a break. 31. A method for identifying pairs of features generated from one edge of a printed feature using a manufacturing process including a conformal coating step, comprising: analyzing a plurality of features to determine correlations between adjacent pairs of features; determining, based on the correlation, that the feature pair were both generated based on an edge of one of the printed features to which the conformal coating was applied; and A method comprising: 32. The method of clause 31, further comprising determining, based on the correlation, the steps in the manufacturing process involved in creating the defect. 33. The method of clause 32 or 33, wherein the analysis includes analyzing the arrangement of different features. 34. A computer program comprising computer readable code means which, when executed by a computer system, instructs the computer system to perform a method according to any one of clauses 1 to 13 or 28 to 33.

[0059] The breadth and scope of the techniques disclosed herein should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

1. When executed by a computer system, the computer system:

1. A method for identifying a pair of features generated from one edge of a printed feature using a manufacturing process that includes a conformal coating step, comprising: analyzing a plurality of features to determine correlations between adjacent pairs of features; determining, based on the correlation, that the plurality of pairs of features were both generated based on an edge of one of the printed features to which the conformal coating was applied; and 1. A computer program comprising computer readable code means for instructing the computer to carry out a method comprising:

2. The computer program of claim 1 , wherein the analyzing comprises analyzing variations in contour or shape of the plurality of features.

3. The computer program of claim 1 , wherein the analyzing comprises analyzing variations in the positions or placements of the plurality of features.

4. The variation is centroids of said plurality of features; the geometric midpoints of the plurality of features; a centerline of said plurality of features; edges of the plurality of features; dimensions of the plurality of features; Centers of some of the plurality of features The computer program of claim 3 , wherein the variation is one or more positions of

5. 2. The computer program of claim 1, wherein the plurality of features are formed on a substrate, and wherein the analyzing comprises analyzing variations in the plurality of features seen in an image of the substrate obtained by a scanning electron microscope.

6. The computer program of claim 1 , wherein each of the plurality of features comprises a line feature.

7. The computer program of claim 1 , wherein each of the plurality of features comprises a plurality of elongated segments aligned with a line.

8. The computer program of claim 1 , wherein the edges of the printed features are non-straight edges, and variations in contours or positions of the determined pairs of the plurality of features are due to the non-straight edges.

9. 2. The computer program product of claim 1, further comprising dividing the plurality of features into a plurality of sets having similar correlation levels based on the correlation, and associating each set with a respective one of a plurality of process steps in the manufacturing process.

10. detecting defects in the plurality of features; The computer program of claim 1 , further comprising determining a process step in the manufacturing process responsible for creating the defect based on the correlation.

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