Circuit device and error detection method

Abstract

To provide a circuit board and the like that can accurately detect an abnormality in image conversion through coordinate transformation.SOLUTION: A circuit board 100 includes a storage circuit 120, an image conversion circuit 130, and an error detection circuit 150. The storage circuit 120 stores input first image data IMA. The image conversion circuit 130 outputs reference coordinates RCRD indicating a pixel position on the first image data IMA, and outputs second image data IMB based on pixel data PXDT read out from the storage circuit 120 based on the output reference coordinates RCRD, thereby performing image conversion through coordinate transformation on the first image data IMA. The error detection circuit 150 performs error detection in the reference coordinates RCRD output by the image conversion circuit 130.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a circuit device, an error detection method, and the like. [Background technology]

[0002] Patent Document 1 discloses a circuit device including an image processing circuit and a comparison circuit. The image processing circuit performs a mapping process on an input first image onto a second image, and converts the second image into a third image through an inverse mapping process. The comparison circuit performs a comparison between the first image and the third image to detect errors in the second image. Specifically, the comparison circuit performs the comparison between the first image and the third image by comparing image values ​​or visibility indices of edge images. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2019-149760 Summary of the Invention [Problem to be solved by the invention]

[0004] Although the above-mentioned Patent Document 1 is capable of detecting errors in the second image, it has a problem in that it is difficult to detect abnormalities in the image processing circuit with high accuracy. Specifically, the third image after inverse mapping does not completely return to the original first image, so the comparison involves ambiguity. While there is no problem in checking whether the content of the second image is appropriate, ambiguity remains in detecting abnormalities in the image processing circuit. [Means for solving the problem]

[0005] One aspect of the present disclosure relates to a circuit device including: a memory circuit that stores input first image data; an image conversion circuit that performs image conversion on the first image data by outputting reference coordinates indicating pixel positions on the first image data and outputting second image data based on pixel data read from the memory circuit based on the output reference coordinates; and an error detection circuit that performs error detection on the reference coordinates output by the image conversion circuit.

[0006] Another aspect of the present disclosure relates to an error detection method including storing first image data in a memory circuit, performing image transformation on the first image data by coordinate transformation, and outputting second image data after the image transformation, outputting reference coordinates indicating pixel positions on the first image data in the image transformation, outputting the second image data based on pixel data read from the memory circuit based on the output reference coordinates, and performing error detection on the output reference coordinates. [Brief explanation of the drawings]

[0007] [Figure 1] 1 shows a first configuration example of a circuit device. [Figure 2] FIG. 4 is a diagram illustrating error detection in the first configuration example. [Figure 3] 6 is a timing chart of error detection in the first configuration example. [Figure 4] FIG. 10 is a diagram showing the correspondence between correction parameters and expected values ​​of error code values. [Figure 5] 10 is a timing chart of error detection in the second configuration example. [Figure 6] 10 shows a third configuration example of a circuit device. [Figure 7] FIG. 10 is a diagram illustrating error detection in the third configuration example. [Figure 8] FIG. 10 is a diagram illustrating error detection in the fourth configuration example. [Figure 9] 5 shows a fifth example of a circuit device configuration. [Figure 10] FIG. 13 is a diagram illustrating error detection in the fifth configuration example. DETAILED DESCRIPTION OF THE INVENTION

[0008] Preferred embodiments of the present disclosure will be described in detail below. Note that the embodiments described below do not unduly limit the scope of the claims, and not all of the configurations described in the embodiments are necessarily essential components.

[0009] 1. First configuration example 1 shows a first configuration example of a circuit device 100 according to this embodiment. The circuit device 100 is a circuit device that performs image distortion correction, image scaling, or both, and is provided, for example, before a display controller in a display device. Alternatively, the circuit device 100 may be a display controller that has built-in functions of image distortion correction, image scaling, or both.

[0010] The circuit device 100 can be used in various display devices, one example of which is a head-up display. A head-up display projects an image onto a transparent screen, superimposing a virtual image in the field of view of a user looking at the screen. At this time, the displayed image is distorted due to distortion of the screen or an optical system such as a projection optical system. However, by correcting the image with an inverse distortion, a distortion-free display image is displayed. This correction is called distortion correction.

[0011] Scaling is a process of enlarging or reducing all or part of an image. Specifically, scaling is a process of increasing or decreasing the number of horizontal pixels, the number of vertical pixels, or both of the horizontal and vertical pixels of an image.

[0012] The circuit device 100 includes an input circuit 110, a memory circuit 120, an image conversion circuit 130, an output circuit 140, an error detection circuit 150, a coordinate address conversion circuit 160, and an interface circuit 190. The circuit device 100 is, for example, an integrated circuit device in which a plurality of circuit elements are integrated on a semiconductor substrate.

[0013] The input circuit 110 receives the first image data IMA from the processing device 200. The input circuit 110 may be a receiving circuit for various communication interfaces, examples of which include LVDS, DVI, DisplayPort, GMSL, and GVIF. LVDS stands for Low Voltage Differential Signaling, DVI stands for Digital Visual Interface, GMSL stands for Gigabit Multimedia Serial Link, and GVIF stands for Gigabit Video Interface.

[0014] The memory circuit 120 stores the first image data IMA received by the input circuit 110. The memory circuit 120 is a line buffer that stores image data for a predetermined number of lines, or a frame memory that stores image data for one frame. The memory circuit 120 is, for example, a line latch circuit, or a semiconductor memory such as an SRAM or a DRAM.

[0015] The image conversion circuit 130 performs image conversion on the first image data IMA using coordinate conversion, and outputs second image data IMB after the image conversion. Image conversion using coordinate conversion is image conversion that generates second image data IMB by moving pixel data of the first image data IMA to pixel positions on the second image data IMB indicated by the coordinate conversion. Specifically, the image conversion circuit 130 generates the second image data IMB by performing distortion correction or scaling on the first image data IMA. Note that the image conversion circuit 130 may perform both distortion correction and scaling. The meanings of distortion correction and scaling are as described above.

[0016] When the image transformation is distortion correction, the image transformation circuit 130 corresponds to a reverse warp engine. Reverse warp is a warp process that moves pixel positions on the second image data IMB to corresponding reference coordinates and obtains pixel data of the second image data IMB from pixel data of the first image data IMA at those reference coordinates. At this time, the image transformation circuit 130 outputs reference coordinates RCRD on the first image data IMA that correspond to pixel positions on the second image data IMB based on correction parameters WP, which are warp parameters.

[0017] When the image transformation is scaling, the image transformation circuit 130 outputs reference coordinates RCRD on the first image data IMA corresponding to pixel positions on the second image data IMB based on the correction parameters WP, which are scaling parameters. The scaling parameters are, for example, parameters that indicate the enlargement or reduction ratio of the image. The scaling parameters may also include coordinates of the scaling center. When a portion of the image is scaled, the scaling parameters may also include parameters that specify the region to be scaled.

[0018] The coordinate address conversion circuit 160 converts the reference coordinate RCRD into a read address RADD of the memory circuit 120. The read address RADD is the address at which pixel data corresponding to the reference coordinate RCRD is stored. If the correction parameter WP is the same and there is no abnormality in the image conversion circuit 130, the same read address RADD is output for the same reference coordinate RCRD for each frame. For example, if the memory circuit 120 is operated as a rotation line buffer, the physical address at which the first pixel data of a frame is stored is different for each frame. In this case, the coordinate address conversion circuit 160 outputs the same logical address for each frame, and the memory circuit 120 converts the logical address into an appropriate physical address for each frame. If the physical address at which the first pixel data of a frame is stored is the same for each frame, the read address RADD may be a physical address.

[0019] The memory circuit 120 reads out the pixel data PXDT from the read address RADD and outputs it to the image conversion circuit 130. The image conversion circuit 130 composes the second image data IMB from the pixel data PXDT. As will be described later, multiple pixel data may be read for one reference coordinate RCRD, and the image conversion circuit 130 may obtain the pixel data of the second image data IMB by performing an interpolation process on the multiple pixel data.

[0020] The output circuit 140 transmits the second image data IMB to a downstream display controller, etc. The output circuit 140 may be a transmission circuit of various communication interfaces, and examples include a transmission circuit of LVDS, DVI, DisplayPort, GMSL, or GVIF.

[0021] The error detection circuit 150 detects an error in the reference coordinates RCRD, thereby detecting an abnormality in the image conversion circuit 130. The error detection circuit 150 includes an arithmetic circuit 151 that calculates an error code value CDQ from the reference coordinates RCRD, and a comparison circuit 152 that compares the error code value CDQ with an expected value CDEX of the error code value.

[0022] For each frame, the calculation circuit 151 calculates one error code value CDQ from the reference coordinates RCRD for that frame. The error code value CDQ is, for example, a CRC code. CRC stands for Cyclic Redundancy Check. Alternatively, the error code value CDQ may be a checksum, a Hamming code, or an ECC code. ECC stands for Error Correcting Code.

[0023] The comparator 152 outputs an error detection signal ERQ indicating an error when the error code value CDQ and the expected value CDEX do not match, and outputs an error detection signal ERQ indicating no error when the error code value CDQ and the expected value CDEX match. The expected value CDEX is associated with a correction parameter WP, and when the correction parameter WP is changed, the expected value CDEX is also changed accordingly.

[0024] The interface circuit 190 transmits and receives setting information, control information, and the like to and from the processing device 200. The interface circuit 190 is, for example, an SPI (Serial Peripheral Interface) or I2C serial communication interface. The processing device 200 stores the correction parameters WP and pre-calculated expected values ​​CDEX in a non-volatile memory or the like, and transmits the correction parameters WP and expected values ​​CDEX to the interface circuit 190. The interface circuit 190 receives the correction parameters WP and the error code value expected values ​​CDEX from the processing device 200, outputs the correction parameters WP to the image conversion circuit 130, and outputs the expected values ​​CDEX to the comparison circuit 152. The interface circuit 190 also outputs an error detection signal ERQ from the comparison circuit 152 to the processing device 200.

[0025] When the processing device 200 receives the error detection signal ERQ indicating that an error has been detected, the processing device 200 performs processing to deal with the error. For example, when the processing device 200 receives the error detection signal ERQ indicating that an error has been detected, the processing device 200 stops transmitting image data to the circuit device 100 or resets the circuit device 100.

[0026] The image conversion circuit 130, coordinate address conversion circuit 160, and error detection circuit 150 are configured by logic circuits. These circuits may be integrated into one circuit using an automatically placed and wired gate array or the like.

[0027] FIG. 2 is a diagram illustrating error detection in the first configuration example. Here, an example is described in which the image transformation is distortion correction and a lookup table is used as the correction parameter WP. Also, here, the number of pixels in the second image data IMB is assumed to be 64 x 48. Note that distortion correction may be performed using a polynomial that indicates the relationship between coordinates on the first image data IMA and coordinates on the second image data IMB, in which case the correction parameter WP is the coefficient of the polynomial.

[0028] As shown in FIG. 2, the correction parameters WP are a lookup table that associates coordinates on the output side with the amount of movement from the coordinates on the output side to reference coordinates on the input side. The coordinates on the output side refer to coordinates on the second image data IMB, and the reference coordinates on the input side refer to coordinates on the first image data IMA. xa1, xa2, . . . xa10 are coordinates in the horizontal scanning direction on the output side, and ya1, ya2, . . . , ya10 are coordinates in the vertical scanning direction on the output side. ua1, ua2, . . . , ua10 are coordinate movement amounts in the horizontal scanning direction, and va1, va2, . . . , va10 are coordinate movement amounts in the vertical scanning direction. For example, the reference coordinates on the input side corresponding to (xa1, ya1) on the output side are (xa1 + ua1, ya1 + va1).

[0029] The image conversion circuit 130 uses the above correction parameters WP to determine reference coordinates (sa1, ta1), (sa2, ta2), (sa3, ta3), . . . , (sa3072, ta3072) on the first image data IMA corresponding to the coordinates (1, 1), (2, 1), (3, 1), . . . , (64, 48) of each pixel in the second image data IMB. For pixel positions not included in the lookup table of the correction parameters WP, the image conversion circuit 130 determines the reference coordinates by, for example, interpolation processing.

[0030] The calculation circuit 151 calculates an error code value CDQ from the reference coordinates (sa1, ta1), (sa2, ta2), (sa3, ta3), ..., (sa3072, ta3072) for one frame output by the image conversion circuit 130. If the reference coordinates are calculated correctly, the same reference coordinates should be output for the same correction parameters WP, so one expected value CDEX corresponds to one correction parameter WP. The comparison circuit 152 compares the error code value CDQ calculated by the calculation circuit 151 with the expected value CDEX to check whether the image conversion circuit 130 has output the correct reference coordinates.

[0031] Fig. 3 is a timing chart of error detection in the first configuration example. Note that Fig. 3 shows an overview of the operation timing, and the operation timing of the circuit device 100 is not limited to Fig. 3. For example, in Fig. 3, the data enable period TDE and the output period of the reference coordinate RCRD coincide with each other, but the relationship between these periods may be set appropriately in accordance with the read / write control of the storage circuit 120.

[0032] As shown in Figure 3, a first frame F1 and a subsequent second frame F2 are defined by a vertical synchronization signal VSYNC. Each frame includes a data enable period TDE defined by a data enable signal. A vertical blanking period TBL is provided between the data enable period TDE and the next data enable period TDE.

[0033] During the data enable period TDE of the first frame F1, the input circuit 110 receives the first image data IMA, writes the first image data IMA to the memory circuit 120, and the image conversion circuit 130 sequentially outputs the reference coordinates RCRD. After the reference coordinates RCRD for one frame are output, the calculation circuit 151 outputs an error code value CDQa calculated from the reference coordinates RCRD for that frame. The calculation circuit 151 updates the error code value during, for example, the vertical blanking period TBL. The comparison circuit 152 compares the error code value CDQa with the expected value CDEX and outputs an error detection signal ERQ. Figure 3 shows an example in which the error code value CDQa matches the expected value CDEX and a low-level error detection signal ERQ is output. Here, a high level indicates an error.

[0034] Similarly, in the second frame F2, the calculation circuit 151 outputs an error code value CDQb calculated from the reference coordinates RCRD for one frame. The comparison circuit 152 compares the error code value CDQb with the expected value CDEX and outputs an error detection signal ERQ. Figure 3 shows an example in which the error code value CDQb and the expected value CDEX do not match, and a high-level error detection signal ERQ is output.

[0035] In the above embodiment, the circuit device 100 includes a memory circuit 120, an image conversion circuit 130, and an error detection circuit 150. The memory circuit 120 stores input first image data IMA. The image conversion circuit 130 outputs reference coordinates RCRD indicating pixel positions on the first image data IMA, and outputs second image data IMB based on pixel data PXDT read from the memory circuit 120 based on the output reference coordinates RCRD, thereby performing image conversion on the first image data IMA through coordinate conversion. The error detection circuit 150 detects errors in the reference coordinates RCRD output by the image conversion circuit 130.

[0036] According to this embodiment, error detection is performed on the reference coordinates RCRD output by the image conversion circuit 130, thereby checking with high accuracy whether the reference coordinates RCRD output by the image conversion circuit 130 are correct. This makes it possible to detect abnormalities in the image conversion circuit 130 with higher accuracy than in Patent Document 1 described above.

[0037] Note that the error detection for the reference coordinates may be an error detection that detects whether the reference coordinates are correct. That is, in the first configuration example, the error detection circuit 150 detects an error in the reference coordinates RCRD, but this is not limited thereto. The error detection circuit 150 may perform error detection for the reference coordinates RCRD by detecting an error in data generated based on the reference coordinates RCRD. For example, in a third configuration example described later, the error detection circuit 150 detects an error in the read address RADD output based on the reference coordinates RCRD. In this case, whether the reference coordinates RCRD are correct is checked by checking whether the read address RADD is correct.

[0038] In this embodiment, the error detection circuit 150 performs error detection by comparing the error code value CDQ calculated from the reference coordinates RCRD output by the image conversion circuit 130 with the expected value CDEX of the error code value.

[0039] According to this embodiment, the error code value CDQ calculated from the reference coordinate RCRD is compared with its expected value CDEX to check whether the reference coordinate RCRD output by the image conversion circuit 130 is correct. Because the reference coordinate RCRD is a real value, it is expected that error detection accuracy will be higher when error detection is performed on the reference coordinate RCRD than when error detection is performed after conversion into the read address RADD, which is an integer value.

[0040] In this embodiment, the coordinate transformation is a coordinate transformation for image distortion correction or image scaling.

[0041] Distortion correction and scaling are image transformations that involve coordinate transformation. By detecting errors in the reference coordinates RCRD output by the image transformation circuit 130 during this coordinate transformation, it becomes possible to detect abnormalities in the image transformation circuit 130.

[0042] In this embodiment, the error detection circuit 150 performs error detection using CRC.

[0043] According to this embodiment, the error detection circuit 150 can obtain a CRC code by sequentially performing an encoding operation on the reference coordinates RCRD sequentially output by the image conversion circuit 130. Furthermore, the use of a CRC enables relatively high-precision error detection. For example, when a 16-bit CRC is used, the error detection accuracy is 1 / 65536.

[0044] This embodiment can also be implemented as an error detection method as follows. Specifically, the error detection method includes storing first image data IMA in the storage circuitry 120. The error detection method includes performing image transformation using coordinate transformation on the first image data IMA and outputting second image data IMB after the image transformation. The error detection method includes outputting reference coordinates RCRD indicating pixel positions on the first image data IMA during the image transformation, and outputting second image data IMB based on pixel data PXDT read from the storage circuitry 120 based on the output reference coordinates RCRD. The error detection method includes performing error detection on the output reference coordinates RCRD.

[0045] 2. Second configuration example The second configuration example is an example in which coordinate transformation is performed by switching between a plurality of correction parameters. The configuration of the circuit device 100 is the same as that shown in FIG.

[0046] 4 is a diagram showing the correspondence between correction parameters and expected values ​​of error code values. The correction parameters WP1 to WPn are different from one another. That is, coordinate transformations using the correction parameters WP1 to WPn are different from one another. n is an integer of 2 or greater.

[0047] When the image conversion circuit 130 outputs a reference coordinate RCRD using the correction parameter WP1, the error detection circuit 150 performs error detection using the expected value CDEX1 of the error code corresponding to the correction parameter WP1. Similarly, when the image conversion circuit 130 outputs a reference coordinate RCRD using the correction parameters WP2 to WPn, the error detection circuit 150 performs error detection using the expected values ​​CDEX2 to CDEXn of the error code corresponding to the correction parameters WP2 to WPn.

[0048] The interface circuit 190 receives the correction parameters WP1 to WPn and the expected values ​​CDEX1 to CDEXn from the processing device 200. For example, the interface circuit 190 may receive the correction parameters and the expected values ​​from the processing device 200 every time the correction parameters are switched. Alternatively, the circuit device 100 may include a register or memory (not shown), and the interface circuit 190 may receive the correction parameters WP1 to WPn and the expected values ​​CDEX1 to CDEXn from the processing device 200 all at once and store them in the register or memory.

[0049] It is not necessary for the interface circuit 190 to receive all of the correction parameters WP1 to WPn. For example, the interface circuit 190 may receive only the correction parameter WP1, and the image conversion circuit 130 may generate the correction parameters WP2 to WPn from the correction parameter WP1. In this case, the error detection circuit 150 performs error detection using the expected values ​​CDEX1 to CDEXn received by the interface circuit 190 that correspond to the correction parameters generated by the image conversion circuit 130.

[0050] 5 is a timing chart of error detection in the second configuration example. Note that Fig. 5 shows an outline of the operation timing, and the operation timing of the circuit device 100 is not limited to Fig. 5.

[0051] The image conversion circuit 130 sets the correction parameter to WP1 during the vertical blanking period TBL before the start of the data enable period TDE of the first frame F1. At the same time, the error detection circuit 150 sets the expected value of the error code value to CDEX1. However, the update timing of the expected value is not limited to this, as long as the expected value is updated before the comparison is performed. The image conversion circuit 130 outputs a reference coordinate RCRD based on the correction parameter WP1, and the calculation circuit 151 calculates the error code value CDQ1 from the reference coordinate RCRD. The comparison circuit 152 compares the error code value CDQ1 with the expected value CDEX1.

[0052] Similarly, the image conversion circuit 130 sets the correction parameter to WP2 during the vertical blanking period TBL before the start of the data enable period TDE of the second frame F2. At the same time, the error detection circuit 150 sets the expected value of the error code value to CDEX2. The image conversion circuit 130 outputs a reference coordinate RCRD based on the correction parameter WP2, and the calculation circuit 151 calculates the error code value CDQ2 from the reference coordinate RCRD. The comparison circuit 152 compares the error code value CDQ2 with the expected value CDEX2.

[0053] In the above embodiment, the circuit device 100 includes the interface circuit 190 that acquires the expected value CDEX.

[0054] According to this embodiment, the expected value CDEX corresponding to the correction parameter WP can be input to the circuit device 100 from outside the circuit device 100. The correction parameter WP differs depending on the type of coordinate transformation to be performed, and the expected value CDEX corresponding to the correction parameter WP can be set from outside the circuit device 100.

[0055] In this embodiment, the interface circuit 190 acquires an expected value CDEX associated with a correction parameter WP representing coordinate transformation. The image conversion circuit 130 outputs a reference coordinate RCRD based on the correction parameter WP. The error detection circuit 150 performs error detection using the expected value CDEX associated with the correction parameter WP.

[0056] According to this embodiment, the error detection circuit 150 calculates an error code value CDQ from the reference coordinates RCRD output based on the correction parameters WP, and compares the error code value CDQ with the expected value CDEX associated with the correction parameters WP, thereby checking whether the reference coordinates RCRD output based on the correction parameters WP are correct.

[0057] 3.Third configuration example 6 shows a third configuration example of the circuit device 100 according to this embodiment. Note that the description of components similar to those already described will be omitted where appropriate.

[0058] The error detection circuit 150 detects an error in the read address RADD output by the coordinate address conversion circuit 160, thereby detecting abnormalities in the image conversion circuit 130 and the coordinate address conversion circuit 160. The error detection circuit 150 includes an arithmetic circuit 151 that calculates an error code value CDQ from the read address RADD, and a comparison circuit 152 that compares the error code value CDQ with an expected value CDEX of the error code value.

[0059] 7 is a diagram illustrating error detection in the third configuration example. As in FIG. 2, the image conversion circuit 130 outputs reference coordinates (sa1, ta1), (sa2, ta2), (sa3, ta3), . . . , (sa3072, ta3072) based on the correction parameters. The coordinate address conversion circuit 160 converts the reference coordinates (sa1, ta1) into a read address RADD1. The read address RADD1 is, for example, an address at which pixel data located at coordinates closest to the reference coordinates (sa1, ta1) in the first image data IMA is stored. Similarly, the coordinate address conversion circuit 160 converts the reference coordinates (sa2, ta2), (sa3, ta3), . . . , (sa3072, ta3072) into read addresses RADD2, RADD3, . . . , RADD3072.

[0060] The calculation circuit 151 calculates an error code value CDQ from the read addresses RADD1, RADD2, RADD3, ..., RADD3072 for one frame output by the coordinate address conversion circuit 160. If the reference coordinates and read addresses are calculated correctly, the same read address should be output for the same correction parameter WP, and therefore one expected value CDEX corresponds to one correction parameter WP. The comparison circuit 152 compares the error code value CDQ calculated by the calculation circuit 151 with the expected value CDEX to check whether the coordinate address conversion circuit 160 has output the correct read address.

[0061] In the above embodiment, the circuit device 100 includes a coordinate address conversion circuit 160. The coordinate address conversion circuit 160 converts the reference coordinate RCRD output by the image conversion circuit 130 into a read address RADD of the memory circuit 120. The error detection circuit 150 performs error detection by comparing an error code value CDQ calculated from the read address RADD output by the coordinate address conversion circuit 160 with an expected value CDEX of the error code value.

[0062] According to this embodiment, the error code value CDQ calculated from the read address RADD is compared with its expected value CDEX to check whether the reference coordinate RCRD output by the image conversion circuit 130 is correct. Since error detection is performed at a stage subsequent to the coordinate address conversion circuit 160, it is possible to detect not only abnormalities in the image conversion circuit 130 but also abnormalities in the coordinate address conversion circuit 160, compared to when error detection is performed on the reference coordinate RCRD.

[0063] 4. Fourth Configuration Example The fourth configuration example is an example in which interpolation processing is performed in image conversion. The configuration of the circuit device 100 is the same as that in FIG.

[0064] Fig. 8 is a diagram for explaining error detection in the fourth configuration example. The basic operation is the same as in Fig. 7, but in the fourth configuration example, the coordinate address conversion circuit 160 outputs multiple read addresses from one reference coordinate. Fig. 8 shows an example of converting reference coordinates (sa1, ta1) into 4 x 4 read addresses.

[0065] P1, P2, ..., P16 are 4 x 4 pixels existing around the reference coordinates (sa1, ta1) in the first image data IMA. The coordinate address conversion circuit 160 outputs read addresses RADD1_1, RADD1_2, ..., RADD1_16 for reading the pixel data of these pixels P1, P2, ..., P16 from the memory circuit 120. The image conversion circuit 130 performs interpolation processing based on the pixel data of pixels P1, P2, ..., P16 read from the memory circuit 120, to obtain pixel data of the output coordinates (xa1, ya1).

[0066] Similarly, the coordinate address conversion circuit 160 outputs 4 × 4 read addresses for each of the reference coordinates (sa2, ta2), (sa3, ta3), ..., (sa3072, ta3072). The image conversion circuit 130 obtains pixel data for each of the output coordinates (sa2, ta2), (sa3, ta3), ..., (sa3072, ta3072) by interpolation.

[0067] The arithmetic circuit 151 obtains the error code value CDQ from all read addresses output by the coordinate address conversion circuit 160 in one frame. Alternatively, the arithmetic circuit 151 may obtain the error code value CDQ from a representative read address for one frame. Fig. 8 shows an example in which RADD1_1 is used as the representative read address among the read addresses RADD1_1 to RADD1_16.

[0068] In the above embodiment, the coordinate address conversion circuit 160 outputs a plurality of read addresses RADD1_1 to RADD1_16 corresponding to a plurality of pixel data used for interpolation calculation in image conversion. The error detection circuit 150 performs error detection by comparing an error code value CDQ calculated from the plurality of read addresses RADD1_1 to RADD1_16 with an expected value CDEX.

[0069] According to this embodiment, errors in a plurality of read addresses RADD1_1 to RADD1_16 corresponding to a plurality of pixel data used in interpolation calculation can be detected collectively by comparing the error code value CDQ with the expected value CDEX.

[0070] In this embodiment, the error detection circuit 150 may perform error detection by comparing the error code value CDQ obtained from a representative read address among the plurality of read addresses RADD1_1 to RADD1_16 with the expected value CDEX.

[0071] According to this embodiment, the error code value CDQ is calculated only from the representative read address, so the calculation load of the error code value CDQ is reduced. Note that errors may be detected separately for read addresses other than the representative read address. Specifically, since the relative positional relationship between the plurality of pixel data used in the interpolation process is known, the read addresses of the plurality of pixel data can be calculated based on the representative read address. By comparing this read address as an expected value with the read address output by the image conversion circuit 130, errors can also be detected for read addresses other than the representative read address.

[0072] 5. Fifth Configuration Example 9 shows a fifth configuration example of the circuit device 100 according to this embodiment. The fifth configuration example is an example in which distortion correction is performed by forward warping. Note that the description of components similar to those already described will be omitted where appropriate.

[0073] Forward warping is a warp process that moves each pixel data of the first image data IMA to the corresponding destination coordinates, thereby obtaining the pixel data of the second image data IMB at those destination coordinates. Specifically, the image conversion circuit 130 outputs destination coordinates WCRD on the second image data IMB corresponding to each pixel data on the first image data IMA based on a correction parameter WP, which is a warp parameter. The coordinate address conversion circuit 160 converts the destination coordinates WCRD into a write address WADD of the memory circuit 120. The write address WADD is an address corresponding to the destination coordinates WCRD. The memory circuit 120 writes the pixel data of the first image data IMA to the write address WADD. The image conversion circuit 130 performs interpolation based on the pixel data PXDT read from the memory circuit 120, thereby outputting the second image data IMB.

[0074] FIG. 10 is a diagram illustrating error detection in the fifth configuration example. Here, an example is described in which a lookup table is used as the correction parameter WP. Here, the number of pixels in the first image data IMA is assumed to be 64 x 48. Note that distortion correction may be performed using a polynomial that indicates the relationship between coordinates on the first image data IMA and coordinates on the second image data IMB. In this case, the correction parameter WP is the coefficient of the polynomial.

[0075] The correction parameter WP is a lookup table that associates input-side coordinates with the amount of movement from the input-side coordinates to destination coordinates on the output side. The input-side coordinates refer to coordinates on the first image data IMA, and the output-side destination coordinates refer to coordinates on the second image data IMB. xb1, xb2, . . . xb10 are coordinates in the horizontal scanning direction on the input side, and yb1, yb2, . . . , yb10 are coordinates in the vertical scanning direction on the input side. ub1, ub2, . . . , ub10 are coordinate movement amounts in the horizontal scanning direction, and vb1, vb2, . . . , vb10 are coordinate movement amounts in the vertical scanning direction. For example, the destination coordinates on the output side corresponding to (xb1, yb1) on the input side are (xb1 + ub1, yb1 + vb1).

[0076] The image conversion circuit 130 uses the above correction parameters WP to determine destination coordinates (sb1,tb1), (sb2,tb2), (sb3,tb3), . . . , (sb3072,tb3072) on the second image data IMB corresponding to the coordinates (1,1), (2,1), (3,1), . . . , (64,48) of each pixel in the first image data IMA. For pixel positions not included in the lookup table of the correction parameters WP, the image conversion circuit 130 determines the destination coordinates by, for example, interpolation processing.

[0077] The coordinate address conversion circuit 160 converts the destination coordinates (sb1, tb1) into a write address WADD1. The write address WADD1 is, for example, an address at which pixel data located at coordinates closest to the destination coordinates (sb1, tb1) in the second image data IMB is stored. Similarly, the coordinate address conversion circuit 160 converts the reference coordinates (sb2, tb2), (sb3, tb3), ..., (sb3072, tb3072) into write addresses WADD2, WADD3, ..., WADD3072.

[0078] The calculation circuit 151 calculates an error code value CDQ from the write addresses WADD1, WADD2, WADD3, ..., WADD3072 for one frame output by the coordinate address conversion circuit 160. If the destination coordinates and write addresses are calculated correctly, the same write address should be output for the same correction parameter WP, and therefore one expected value CDEX corresponds to one correction parameter WP. The comparison circuit 152 compares the error code value CDQ calculated by the calculation circuit 151 with the expected value CDEX to check whether the coordinate address conversion circuit 160 has output the correct write address.

[0079] Although the above describes an example in which the arithmetic circuit 151 obtains the error code value from the write address, the arithmetic circuit 151 may obtain the error code value from the destination coordinates. Also, as in the second configuration example, the image conversion circuit 130 may switch the correction parameters during the vertical blanking period, and the error detection circuit 150 may perform error detection using an expected value corresponding to the correction parameters.

[0080] The circuit device of the present embodiment described above includes a memory circuit, an image conversion circuit, and an error detection circuit. The memory circuit stores input first image data. The image conversion circuit outputs reference coordinates indicating pixel positions on the first image data, and outputs second image data based on pixel data read from the memory circuit based on the output reference coordinates, thereby performing image conversion on the first image data through coordinate transformation. The error detection circuit detects errors in the reference coordinates output by the image conversion circuit.

[0081] According to this embodiment, error detection is performed on the reference coordinates output by the image conversion circuit, and it is possible to check with high accuracy whether the reference coordinates output by the image conversion circuit are correct, thereby making it possible to detect abnormalities in the image conversion circuit with high accuracy.

[0082] In this embodiment, the error detection circuit may perform error detection by comparing an error code value calculated from the reference coordinates output by the image conversion circuit with an expected value of the error code value.

[0083] According to this embodiment, the error code value calculated from the reference coordinates is compared with the expected value to check whether the reference coordinates output by the image conversion circuit are correct. Because the reference coordinates are real values, error detection of the reference coordinates can be expected to be more accurate than when error detection is performed after converting the reference coordinates into read addresses, which are integer values.

[0084] In this embodiment, the circuit device may also include a coordinate address conversion circuit. The coordinate address conversion circuit may convert the reference coordinates output by the image conversion circuit into a read address of the memory circuit. The error detection circuit may perform error detection by comparing an error code value calculated from the read address output by the coordinate address conversion circuit with an expected value of the error code value.

[0085] According to this embodiment, the error code value calculated from the read address is compared with its expected value to check whether the reference coordinates output by the image conversion circuit are correct. Because error detection is performed after the coordinate address conversion circuit, it is possible to detect not only abnormalities in the image conversion circuit but also abnormalities in the coordinate address conversion circuit, compared to when error detection is performed on the reference coordinates.

[0086] In this embodiment, the coordinate address conversion circuit may output a plurality of read addresses corresponding to a plurality of pixel data used in the interpolation calculation in the image conversion, and the error detection circuit may perform error detection by comparing an error code value calculated from the plurality of read addresses with an expected value.

[0087] According to this embodiment, errors at a plurality of read addresses corresponding to a plurality of pixel data used in interpolation calculations can be detected collectively by comparing the error code value with the expected value.

[0088] In this embodiment, the coordinate address conversion circuit may output a plurality of read addresses corresponding to a plurality of pixel data used for interpolation calculation in image conversion. The error detection circuit may perform error detection by comparing an error code value obtained from a representative read address among the plurality of read addresses with an expected value.

[0089] According to this embodiment, the error code value is calculated from only the representative read address, so the calculation load for the error code value is reduced.

[0090] In this embodiment, the circuit device may also include an interface circuit that acquires the expected value.

[0091] According to this embodiment, an expected value corresponding to the correction parameter can be input to the circuit device from outside the circuit device. The correction parameter differs depending on the type of coordinate transformation to be performed, but the expected value corresponding to the correction parameter can be set from outside the circuit device.

[0092] In this embodiment, the interface circuit may acquire an expected value associated with a correction parameter representing the coordinate transformation. The image transformation circuit may output reference coordinates based on the correction parameter. The error detection circuit may perform error detection using the expected value associated with the correction parameter.

[0093] According to this embodiment, the error detection circuit calculates an error code value from the reference coordinates output based on the correction parameters, and compares the error code value with an expected value associated with the correction parameters, thereby checking whether the reference coordinates output based on the correction parameters are correct.

[0094] In this embodiment, the coordinate transformation may be a coordinate transformation for image distortion correction or image scaling.

[0095] Distortion correction and scaling are image transformations that involve coordinate transformation. By detecting errors in the reference coordinates output by the image transformation circuit during this coordinate transformation, it is possible to detect abnormalities in the image transformation circuit.

[0096] In this embodiment, the error detection circuit may perform error detection using CRC.

[0097] According to this embodiment, the error detection circuit can obtain a CRC code by sequentially performing an encoding operation on the reference coordinates output by the image conversion circuit. Furthermore, the use of CRC enables relatively high-precision error detection.

[0098] The error detection method of this embodiment also includes storing first image data in a memory circuit. The error detection method also includes performing image transformation on the first image data using coordinate transformation and outputting second image data after the image transformation. The error detection method also includes outputting reference coordinates indicating pixel positions on the first image data during the image transformation, and outputting the second image data based on pixel data read from the memory circuit based on the output reference coordinates. The error detection method also includes performing error detection on the output reference coordinates.

[0099] Although the present embodiment has been described in detail above, it will be readily apparent to those skilled in the art that many modifications are possible without substantially departing from the novel features and advantages of the present disclosure. Therefore, all such modifications are intended to be included within the scope of the present disclosure. For example, a term described at least once in the specification or drawings together with a different term having a broader or equivalent meaning may be replaced with that different term anywhere in the specification or drawings. Furthermore, all combinations of the present embodiment and modifications are also included within the scope of the present disclosure. Furthermore, the configurations and operations of the error detection circuit, circuit device, processing device, etc. are not limited to those described in the present embodiment, and various modifications are possible. [Explanation of symbols]

[0100] 100...circuit device, 110...input circuit, 120...memory circuit, 130...image conversion circuit, 140...output circuit, 150...error detection circuit, 151...arithmetic circuit, 152...comparison circuit, 160...coordinate address conversion circuit, 190...interface circuit, 200...processing device, CDEX...expected value, CDQ...error code value, IMA...first image data, IMB...second image data, RADD...read address, RCRD...reference coordinate, WADD...write address, WCRD...destination coordinate, WP...correction parameter

Claims

1. a storage circuit for storing the input first image data; an image conversion circuit that performs image conversion on the first image data by coordinate conversion, by using correction parameters that indicate correspondence between reference coordinates that indicate pixel positions on the first image data and output-side coordinates that indicate pixel positions on the second image data to output the reference coordinates that correspond to the output-side coordinates, reading pixel data of the first image data that correspond to the output reference coordinates from the storage circuit, and outputting pixel data of the second image data at the output-side coordinates based on the read pixel data; an error detection circuit that calculates an error code value from the reference coordinates output by the image conversion circuit or the read address obtained by converting the reference coordinates into a read address of the storage circuit, and compares the error code value with an expected value of the error code value calculated in advance from the correction parameters, thereby detecting an error in the reference coordinates; A circuit device comprising:

2. 2. The circuit device according to claim 1, a coordinate address conversion circuit for converting the reference coordinates into the read address; The error detection circuit a circuit device that performs the error detection by comparing the error code value obtained from the read address output by the coordinate address conversion circuit with the expected value;

3. 3. The circuit device according to claim 2, The coordinate address conversion circuit outputting a plurality of read addresses corresponding to a plurality of pixel data used in an interpolation operation in the image conversion; The error detection circuit a circuit device that performs the error detection by comparing the error code value obtained from the plurality of read addresses with the expected value;

4. 3. The circuit device according to claim 2, The coordinate address conversion circuit outputting a plurality of read addresses corresponding to a plurality of pixel data used in an interpolation operation in the image conversion; The error detection circuit A circuit device characterized in that the error detection is performed by comparing the error code value obtained from a representative read address of the plurality of read addresses with the expected value.

5. 5. The circuit device according to claim 1, A circuit device comprising an interface circuit for acquiring the expected value.

6. 6. The circuit device according to claim 5, The interface circuit obtaining the expected value associated with the correction parameter; The error detection circuit a circuit device that performs the error detection using the expected value associated with the correction parameter;

7. 7. The circuit arrangement according to claim 1, The coordinate transformation is A circuit device characterized by being used for coordinate transformation in image distortion correction or image scaling.

8. A circuit device according to any one of claims 1 to 7, The error code value is A circuit device characterized in that the code is a CRC (Cyclic Redundancy Check) code, a checksum, a Hamming code, or an ECC (Error Correcting Code).

9. 8. The circuit arrangement according to claim 1, The error detection circuit A circuit device characterized in that the error detection is performed by CRC (Cyclic Redundancy Check).

10. storing the first image data in a storage circuit; performing image transformation on the first image data by coordinate transformation, and outputting second image data after the image transformation; In the image conversion, using a correction parameter indicating a correspondence between reference coordinates indicating pixel positions on the first image data and output-side coordinates indicating pixel positions on the second image data, outputting the reference coordinates corresponding to the output-side coordinates, reading pixel data of the first image data corresponding to the output reference coordinates from the storage circuit, and outputting pixel data of the second image data at the output-side coordinates based on the read pixel data; determining an error code value from the outputted reference coordinates or the read address obtained by converting the reference coordinates into a read address of the memory circuit, and comparing the error code value with an expected value of the error code value calculated in advance from the correction parameters, thereby detecting an error in the reference coordinates; 10. An error detection method comprising:

Images