Semiconductor device and ignition system

Abstract

To prevent generation of noise to realize stable operation of a device.SOLUTION: A semiconductor device 1 has a semiconductor switch 1a and a control circuit 1b. The control circuit 1b is driven by a voltage of a signal ct for instructing ON / OFF of the semiconductor switch 1a as a power source. The semiconductor switch 1a is, for example, an IGBT. The control circuit 1b also comprises an extraction circuit 1b1 (first extraction circuit), and an extraction circuit 1b2 (second extraction circuit). The extraction circuit 1b1 extracts a gate charge from a gate of the semiconductor switch 1a with a first sink capability when an instruction to turn off the semiconductor switch 1a is detected from the signal ct. The extraction circuit 1b2 extracts the gate charge with a second sink capability higher than the first sink capability when a voltage generated from a collector voltage of the semiconductor switch 1a is equal to or higher than a predetermined voltage.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device that controls the switching of a semiconductor switch and an ignition system that controls the ignition of an engine. [Background technology]

[0002] In recent years, the automotive industry has seen progress in the development of highly functional ignition systems. In ignition systems, a semiconductor device called an igniter, which controls the ignition of an automotive engine, discharges (ignites) the spark plug via an ignition coil under the control of an ECU (Electronic Control Unit).

[0003] 13 is a diagram showing the configuration of a conventional ignition system. The ignition system 100 includes an igniter 110, an ignition coil 2, a spark plug 3, and a capacitor C. VB The ignition coil 2 includes a primary coil L1, a secondary coil L2, and a diode Da.

[0004] The primary coil L1 of the ignition coil 2 is connected to a terminal a1 of an igniter 110 which serves as a switch for turning on and off a current, and the secondary coil L2 is connected to a spark plug 3.

[0005] A terminal a2 of the igniter 110 is connected to the ground (GND), and a terminal a3 of the igniter 110 is connected to the ECU 4. A capacitor C is provided between the power supplies of the ignition system 100 to suppress the propagation of noise and surges from the ignition coil 2 to the battery Ba. VB is connected.

[0006] The ECU 4, the ignition coil 2, and the spark plug 3 are supplied with power through a battery Ba, and the ignition system 100 operates when a signal from the ECU 4 is input to a terminal a3 of the igniter 110. The ignition system 100 and the battery Ba are connected via a harness h1 (wiring cable).

[0007] Fig. 14 shows the circuit configuration of a conventional igniter. Igniter 110 includes an IGBT (Insulated Gate Bipolar Transistor) as a power semiconductor switch, and a gate terminal (Gate), collector terminal (Collector), and emitter terminal (Emitter) are connected to the IGBT via resistor Rg as input / output terminals. The collector terminal, emitter terminal, and gate terminal correspond to terminals a1, a2, and a3 shown in Fig. 13, respectively.

[0008] Between the gate terminal to which a signal from the ECU 4 is input and the resistor Rg, a Zener diode GEZD (gate-emitter Zener diode) for surge removal and a pull-down resistor Rpull for drawing out the voltage Vg applied to the gate terminal to the emitter terminal when the signal is off are connected. In addition, a signal recognition circuit 11a is connected between the gate terminal and the emitter terminal, operates using the voltage Vg as a power source, and recognizes the signal sent from the ECU 4 instructing the IGBT to be on / off.

[0009] The output of the signal recognition circuit 11a is input to the gate of the pull-down MOS 13 via an inverter IN1. The pull-down MOS 13 is, for example, an NMOS transistor such as an N-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The pull-down MOS 13 is used as a pull-down MOS that discharges the gate voltage Vge applied to the gate of the IGBT and pulls out the gate charge.

[0010] The drain of the pull-out MOS 13 is connected to the gate of the IGBT via a resistor Rp, and the source of the pull-out MOS 13 is connected to the emitter terminal. A group of Zener diodes CGZD (multiple collector-gate Zener diodes) is connected between the collector terminal and the gate of the IGBT to perform clamping operation when high voltage is generated.

[0011] In a normal configuration, a fixed voltage supplied from the battery Ba is used as the driving voltage, but as described above, the igniter 110 uses the voltage of the signal input to the gate terminal from the ECU 4 (gate terminal voltage Vg) as the driving voltage. Therefore, when the signal level input to the gate terminal becomes equal to or lower than the operating power supply voltage of the signal recognition circuit 11a, the igniter 110 is put into a non-driving state, and the operation of the entire ignition system 100 stops.

[0012] Here, when an on signal to turn on the IGBT is input from the ECU 4 to the gate terminal, the signal recognition circuit 11a outputs an H level, and the inverter IN1 outputs an L level to the gate of the pull-out MOS 13, turning off the pull-out MOS 13.

[0013] Furthermore, when the IGBT is in the ON state and an OFF signal is received from the ECU 4, the signal recognition circuit 11a switches the output signal from H level to L level. At this time, the output logic of the inverter IN1 is inverted (from L level to H level), so that the pull-out MOS 13 is turned on and starts conducting, pulls out the gate charge from the gate of the IGBT, and discharges the gate voltage Vge.

[0014] However, if the gate terminal voltage Vg falls below the operating power supply voltage of the signal recognition circuit 11a, this function is lost. On the other hand, the gate voltage Vge of the IGBT is also discharged via the resistor Rg and the pull-down resistor Rpull. This discharge of the gate voltage Vge causes the IGBT to transition to the off state.

[0015] FIG. 15 is a time chart showing the operating waveforms of a conventional igniter. [Period from time t0 to time t1] Assume that the IGBT transitions to the off state from time t0. The gate terminal voltage Vg drops because it is discharged by the pull-down resistor Rpull. The gate voltage Vge is also discharged by the pull-down MOS 13 and the pull-down resistor Rpull, and the gate voltage Vge drops to the mirror voltage.

[0016] It should be noted that the igniter 110 has a circuit configuration that turns the IGBT off by gradually discharging the gate terminal voltage Vg and the gate voltage Vge, so that the gate terminal voltage Vg and the gate voltage Vge do not drop suddenly.

[0017] [Period from time t1 to time t2] The residual charge at the gate terminal is discharged through the pull-down resistor Rpull, causing the gate terminal voltage Vg to gradually decrease. Meanwhile, the IGBT collector voltage Vce increases, but the Miller capacitance feeds back from the IGBT collector to the gate.

[0018] Therefore, even if the gate voltage Vge is discharged by the pull-down resistor Rpull, the increased collector voltage Vce is fed back to the gate, so the decrease and increase cancel each other out, and the gate voltage Vge becomes close to a flat state. The period in which this phenomenon occurs (the period from time t1 to time t2) is called the mirror region.

[0019] [Period from time t2 to time t3] The period from time t2 onwards is the period after the end of the mirror region, and from time t2 onwards the IGBT approaches a fully off state (complete shutdown of the IGBT). As the gate voltage Vge decreases, the collector current Ice decreases. In addition, the collector voltage Vce rises to a clamp voltage determined by the breakdown voltage of the Zener diode group CGZD.

[0020] [Period from time t3 to time t4] When the Zener diode group CGZD breaks down, charge is supplied from the collector terminal to the gate voltage Vge, and the rate at which the gate voltage Vge falls decreases.

[0021] As the rate of decrease of the gate voltage Vge decreases, the rate of decrease of the collector current Ice also decreases, and the collector current Ice continues to decrease until the energy stored in the ignition coil 2 connected to the collector terminal is released.

[0022] [Period from time t4 to time t5] The supply of charge from the collector terminal to the IGBT gate ceases, and the gate voltage Vge accelerates its decline. The collector current Ice also becomes zero. However, because the gate terminal voltage Vg has fallen to a voltage at which the signal recognition circuit 11a cannot operate, no current is drawn by the pull-down MOS 13, and the current is gradually drawn only by the pull-down resistor Rpull. The gate voltage Vge at time t4 is the operating threshold voltage of the IGBT.

[0023] A related technology that has been proposed is, for example, a technology in which, when an IGBT transitions from an on to an off state, the first switch and the second switch are closed simultaneously to extract gate charge from the gate of the IGBT, and when the rate of rise of the collector voltage is high, the second switch is opened to mitigate the extraction of gate charge. [Prior art documents] [Patent documents]

[0024] [Patent Document 1] Patent Publication No. 2021-103849 Summary of the Invention [Problem to be solved by the invention]

[0025] In the above-described configuration of the igniter 110, the IGBT collector current Ice also drops sharply as the gate voltage Vge drops sharply after the mirror region ends, and this causes a large current change rate dI / dt (change in current over time), which corresponds to the IGBT switching speed. From the perspective of IGBT switching loss, it is considered that the larger the dI / dt, the smaller the switching loss.

[0026] However, since the collector current Ice flows from the emitter terminal to GND via the harness h1, if dI / dt is too large, an induced voltage will be generated at the emitter terminal due to the parasitic inductance of the harness h1 connecting the ignition system 100 and the battery Ba.

[0027] The emitter terminal is connected to a capacitor C to prevent noise and surges from propagating to the battery Ba. VB is connected, when an induced voltage occurs, the parasitic inductance component of harness h1 and capacitor C VB This causes a problem that resonance occurs between the capacitance component and the IGBT, generating resonance noise, which may cause the ignition system 100 to malfunction due to erroneous turning on of the IGBT or the like.

[0028] The above describes the generation of resonance noise when the IGBT is turned off in the ignition system 100. However, in general, a sudden drop in the collector current Ice when the IGBT is turned off increases the possibility of generating noise in the periphery of the IGBT. For this reason, there is a demand for technology that can effectively prevent noise that may be generated when the IGBT is turned off while maintaining the switching time of the IGBT.

[0029] In one aspect, the present invention aims to provide a semiconductor device and an ignition system that prevent noise generation and ensure stable operation of the device. [Means for solving the problem]

[0030] To solve the above problems, a semiconductor device is provided. The semiconductor device includes a semiconductor switch and a control circuit. The control circuit is driven by a voltage of a signal that instructs the semiconductor switch to be on or off, as a power source. The control circuit also includes a first extraction circuit and a second extraction circuit. The first extraction circuit extracts gate charge from the gate of the semiconductor switch with a first sink capability when it detects an instruction to turn the semiconductor switch off. The second extraction circuit extracts gate charge with a second sink capability higher than the first sink capability when a voltage generated from the collector voltage of the semiconductor switch is equal to or higher than a predetermined voltage.

[0031] To solve the above problem, an ignition system is provided. The ignition system includes an igniter, an ignition coil, a spark plug, and a capacitor. The igniter includes a semiconductor switch, a first extraction circuit that extracts gate charge from the gate of the semiconductor switch with a first sink capacity when an instruction to turn the semiconductor switch off is detected, and a second extraction circuit that extracts gate charge with a second sink capacity higher than the first sink capacity when a voltage generated from the collector voltage of the semiconductor switch is equal to or higher than a predetermined voltage. The ignition system is powered by a signal voltage output from an electronic control unit that instructs the semiconductor switch to turn on or off. The ignition coil is connected to an external power supply via a harness and amplifies the voltage generated by the semiconductor switch. The spark plug discharges based on the negative voltage output from the ignition coil. The capacitor is connected to a power supply and ground within the system and to the emitter of the semiconductor switch via the harness. [Effects of the Invention]

[0032] According to one aspect, it is possible to prevent noise generation and ensure stable operation of the device. [Brief explanation of the drawings]

[0033] [Figure 1] 1A and 1B are diagrams illustrating a semiconductor device according to the present invention; [Figure 2]FIG. 1 is a diagram illustrating an example of the overall configuration of an ignition system. [Figure 3] FIG. 2 is a diagram illustrating an example of the configuration of an ECU. [Figure 4] 3 is a time chart showing the overall operation of the ignition system. [Figure 5] FIG. 2 is a diagram illustrating an example of a circuit configuration of an igniter. [Figure 6] FIG. 2 is a diagram illustrating an example of a configuration of a logic circuit. [Figure 7] FIG. 2 is a diagram illustrating the operation logic of a logic circuit. [Figure 8] FIG. 2 is a diagram for explaining generation of a power supply voltage supplied to a logic circuit. [Figure 9] 4 is a time chart showing the operation of an igniter. [Figure 10] 10A and 10B are diagrams illustrating waveform comparison between the operation of the present invention and the conventional operation. [Figure 11] FIG. 10 is a diagram showing a modified example of the igniter. [Figure 12] FIG. 10 is a diagram illustrating a modified example of a logic circuit. [Figure 13] FIG. 1 is a diagram showing the configuration of a conventional ignition system. [Figure 14] FIG. 1 is a diagram showing a circuit configuration of a conventional igniter. [Figure 15] 10 is a time chart showing the operating waveforms of a conventional igniter. DETAILED DESCRIPTION OF THE INVENTION

[0034] The present embodiment will be described below with reference to the drawings. FIG. 1 is a diagram illustrating a semiconductor device of the present invention. The semiconductor device 1 includes a semiconductor switch 1a and a control circuit 1b. The control circuit 1b is driven by a voltage signal ct that instructs the semiconductor switch 1a to be on or off. The semiconductor switch 1a is, for example, an IGBT.

[0035] The control circuit 1b includes an extraction circuit 1b1 (first extraction circuit) and an extraction circuit 1b2 (second extraction circuit). When an instruction to turn off the semiconductor switch 1a is detected from the signal ct, the extraction circuit 1b1 extracts gate charge from the gate of the semiconductor switch 1a with a first sink capability. When the voltage generated from the collector voltage of the semiconductor switch 1a is equal to or higher than a predetermined voltage, the extraction circuit 1b2 extracts gate charge with a second sink capability higher than the first sink capability. The semiconductor switch 1a and the control circuit 1b including the extraction circuits 1b1 and 1b2 are integrated on the same chip.

[0036] In semiconductor device 1, extraction circuits 1b1 and 1b2 are used to extract the gate charge of semiconductor switch 1a in two stages. In the first stage, a first period t11, extraction circuit 1b1 slowly extracts the gate charge from the gate of semiconductor switch 1a with a first sink capability, thereby gradualing the decline of collector current Ice so that the collector current Ice has a current change rate that does not trigger noise generation.

[0037] On the other hand, since maintaining the switching time ts is also important in terms of switching loss, in the second period t12 of the second stage, the extraction circuit 1b2 extracts the gate charge with a second sink capability higher than that in the first period t11, thereby maintaining the specified switching time ts.

[0038] This configuration of the semiconductor device 1 makes it possible to prevent noise caused by the sudden switching operation of the semiconductor switch 1a when the semiconductor switch 1a is turned off, thereby realizing stable operation. In addition, the switching time of the semiconductor switch 1a is kept within a predetermined time, making it possible to suppress switching loss.

[0039] Next, a detailed description will be given of a case where the semiconductor device 1 is applied to an ignition system as an example of an application in which the semiconductor device 1 is used. Note that, in the following description, the same reference numerals will be used to designate components that have already been described, and descriptions of the same components may be omitted.

[0040] <Overall configuration of ignition system> 2 is a diagram showing an example of the overall configuration of an ignition system. The ignition system 1-1 includes an igniter 10 having the function of the semiconductor device 1, an ignition coil 2, a spark plug 3, and a capacitor C VB Equipped with.

[0041] The igniter 10 includes an IGBT, an IC 10a having the function of a control circuit 1b, a resistor R10, a resistor Rg, a pull-down resistor Rpull, and a diode D B3 , a Zener diode group CGZD, and a Zener diode GEZD. A gate terminal (Gate), a collector terminal (Collector), and an emitter terminal (Emitter) are connected to the IGBT as input / output terminals, respectively.

[0042] The igniter 10 generates a high voltage using the IGBT, and further amplifies this high voltage to several tens of kV using the ignition coil 2. When the IGBT switches from on to off, the spark plug 3 sparks and ignites the spark. The igniter 10 also uses the voltage of a signal input from the ECU 4 to its gate terminal as a driving voltage.

[0043] The ECU 4, the ignition coil 2, and the spark plug 3 are supplied with power through a battery Ba, and the ignition system 1-1 operates when a signal from the ECU 4 is input to the gate terminal of the igniter 10. The ignition system 1-1 and the battery Ba are connected via a harness h1.

[0044] As described above, the igniter 10 uses, as a driving voltage, the voltage of the signal input to the gate terminal from the ECU 4 (gate terminal voltage Vg). Therefore, when the signal level input to the gate terminal becomes equal to or lower than the operating power supply voltage of the IC 10a, the igniter 10 is put into a non-driving state, and the operation of the entire ignition system 1-1 stops.

[0045] The connection relationship of the peripheral components of the igniter 10 will be described. The positive power supply terminal of the battery Ba is connected to the power supply terminal of the ECU 4, one end of the capacitor C VB , one end of the primary coil L1, and the cathode of the diode Da. The other end of the primary coil L1 is connected to the collector terminal of the igniter 10. The anode of the diode Da is connected to one end of the secondary coil L2, the other end of the secondary coil L2 is connected to one end of the spark plug 3, and the other end of the spark plug 3 is connected to GND.

[0046] The negative power supply terminal of the battery Ba is connected to the reference power supply terminal of the ECU 4, the other end of the capacitor C VB , the emitter terminal of the igniter 10, and GND. The signal output terminal of the ECU 4 is connected to the gate terminal of the igniter 10. Details of the internal circuit configuration of the igniter 10 will be described later in FIG. 5.

[0047] <Configuration of ECU> FIG. 3 is a diagram showing an example of the configuration of the ECU. The ECU 4 includes a regulator 40, a PNP transistor 41, a resistor R41, and a capacitor C41. A PMOS transistor, which is a P-channel MOSFET, may be used instead of the PNP transistor 41.

[0048] The power supply terminal of the regulator 40 is connected to the positive power supply terminal of the battery Ba, and the battery voltage Vb is applied. The output terminal of the regulator 40 is connected to the emitter of the PNP transistor 41, and the collector of the PNP transistor 41 is connected to one end of the resistor R41.

[0049] The other end of the resistor R41 is connected to one end of the capacitor C41 and the gate terminal of the igniter 10, and the other end of the capacitor C41 and the reference power supply terminal of the regulator 40 are connected to GND. A signal for controlling the on / off of the IGBT transmitted from a processor or the like (not shown) is input to the base of the PNP transistor 41.

[0050] Here, regulator 40 outputs a voltage of 5 V from battery voltage Vb (approximately 12 V to 14 V) input from battery Ba. PNP transistor 41 is turned on when turning on the IGBT inside igniter 10, and gate terminal voltage Vg is applied to the gate terminal of igniter 10.

[0051] Furthermore, when the IGBT is turned off, the PNP transistor 41 is turned off. In this case, when the PNP transistor 41 is turned off, the charge stored in the capacitor C41 flows to GND via the pull-down resistor Rpull inside the igniter 10. Therefore, the pull-down resistor Rpull shown in FIG. 2 has both the function of consuming the charge stored in the capacitor C41 of the ECU 4 and the function of drawing out the gate charge when the IGBT is turned off.

[0052] <Overall operation of the ignition system> 4 is a time chart showing the overall operation of the ignition system, illustrating the operation when the IGBT is switched in the igniter 10.

[0053] [Period from time T0 to time T1] When the gate terminal voltage Vg becomes high due to an ON signal from the ECU 4, the gate voltage Vge of the IGBT inside the igniter 10 becomes high, and the IGBT starts to conduct electricity and causes the collector current Ice to flow.

[0054] The reason why the collector current Ice does not rise sharply is that the load of the IGBT is the ignition coil 2, and the collector current Ice rises at a gentle slope due to the influence of the inductance of the L load of the ignition coil 2.

[0055] Furthermore, the collector voltage Vce is approximately equal to the battery voltage Vb before the gate terminal voltage Vg reaches the level of the ON signal. When the ON signal from the ECU 4 is input to the gate terminal and the IGBT begins to conduct, the collector voltage Vce drops from a voltage approximately equal to the battery voltage Vb to the ON voltage of the IGBT. Furthermore, the secondary voltage V2 applied to the secondary coil L2 of the ignition coil 2 outputs a voltage proportional to the change in the collector current Ice over time.

[0056] During the period from time T0 to time T1, the collector current Ice rises gradually at first and then rises sharply. This steep rise in the collector current Ice is due to magnetic saturation of the ignition coil 2, which reduces the impedance of the coil and makes it easier for the collector current Ice to flow.

[0057] [Period from time T1 to time T2] The current limiting function built into the igniter 10 controls (reduced) the gate voltage Vge to limit the collector current Ice, and the current value of the collector current Ice is kept at a constant value (I CL ) is maintained. Also, since the collector current Ice is constant, the collector voltage Vce is also constant.

[0058] [Period from time T2 to time T3] In response to an OFF signal from the ECU 4, the gate terminal voltage Vg begins to transition to the L level, and the gate voltage Vge also begins to decrease. At time T2, the IGBT begins to cut off, causing the collector current Ice to decrease. The collector voltage Vce increases in proportion to the change in the collector current Ice over time (proportional to the cut-off speed of the IGBT), but is clamped by the Zener diode group CGZD inside the igniter 10, so the increase level is limited by the clamp voltage V CL It will stop at .

[0059] For example, if the breakdown voltage of the Zener diode group CGZD is 400V, the Zener diode group CGZD will break down when the collector voltage Vce rises to 400V. CLThereafter, the IGBT consumes the inductive energy stored in the primary coil L1 of the ignition coil 2 through this active clamp operation.

[0060] [Period after time T3] Once the collector current Ice has run out, the collector voltage Vce begins to return to the battery voltage Vb. Note that time period T3a corresponds to the discharge duration specific to the ignition coil 2. During time period T3a, the coil energy is fed back to the igniter 10, causing the collector voltage Vce to rise slightly for a few milliseconds. After time period T3a, the collector voltage Vce settles down to the level of the battery voltage Vb.

[0061] On the other hand, the secondary voltage V2 of the ignition coil 2 generates a voltage proportional to the winding ratio with the primary coil L1. However, when the IGBT is cut off at time T2, the energy stored in the secondary coil L2 is released, generating a negative voltage of, for example, several tens of kV. This negative voltage is the spark voltage V spark When this voltage is reached, the dielectric breakdown between the spark plug 3 and GND is broken, causing a discharge (ignition).

[0062] The above series of operations is an ideal state, and in reality, as described above, there is a possibility that resonant noise will occur due to the steep switching operation of the IGBT caused by the parasitic inductance component of the harness h1.

[0063] Therefore, the present invention suppresses the sudden change in the collector current Ice when the IGBT is in off-state, thereby preventing the occurrence of resonance noise, maintaining the ignition performance of the spark plug 3 and enabling stable operation of the ignition system 1-1.

[0064] <Igniter configuration> 5 is a diagram showing an example of the circuit configuration of an igniter. The igniter 10 includes an IGBT that turns the current on and off, an IC 10a that controls the IGBT, a group of Zener diodes CGZD that clamp the device to protect it from the high collector voltage that occurs when the current is off, a Zener diode GEZD that is used to remove surges, a pull-down resistor Rpull that pulls out the gate voltage Vge when the IGBT is off, a resistor R10, and a diode D B3 In the following description, the Zener diode group CGZD may be represented by the Zener diodes CGZD1 and CGZD2.

[0065] The IC 10a includes a first extraction circuit 11, a second extraction circuit 12, and a diode D B1 , D B2 The extraction circuit 11 includes a detection circuit 11-1, an extraction MOS 11b (first extraction transistor), and a resistor Rp1 (first resistive element), and the detection circuit 11-1 includes a signal recognition circuit 11a and an inverter IN1.

[0066] The pull-out circuit 12 includes a logic circuit 12a, a pull-out MOS 12b (second pull-out transistor), a resistor Rp2 (second resistive element), and a capacitor C2. NMOS transistors are used for the pull-out MOSs 11b and 12b.

[0067] In the extraction circuit 11, the detection circuit 11-1 operates using the gate terminal voltage Vg as a power supply, and the signal recognition circuit 11a recognizes a signal instructing the IGBT to be on / off, which is transmitted from the ECU 4. The output voltage V1 of the signal recognition circuit 11a is inverted via an inverter IN1, and the output voltage Mg1 (first drive signal) of the inverter IN1 is input to the gate of the extraction MOS 11b.

[0068] In the extraction circuit 12, the logic circuit 12a operates using the voltage Vs as a power supply, compares a voltage generated from the collector voltage of the IGBT with a predetermined voltage, generates an output voltage Mg2 (second drive signal) based on the comparison result, and inputs it to the gate of the extraction MOS 12b.

[0069] The connection relationship of each component will be explained. The gate terminal is connected to the cathode of the Zener diode GEZD, one end of the pull-down resistor Rpull, one end of the resistor Rg, and the diode D B1 and the power supply terminal of the signal recognition circuit 11a.

[0070] The collector terminal of the resistor Rg is connected to the collector of the IGBT, the cathode of the Zener diode CGZD1, one end of the resistor R10, and one input terminal of the logic circuit 12a, and the anode of the Zener diode CGZD1 is connected to the anode of the Zener diode CGZD2. The other end of the resistor Rg is connected to one end of the resistor Rp1, one end of the resistor Rp2, the cathode of the Zener diode CGZD2, and the diode D B2 and the gate of the IGBT.

[0071] The other end of resistor R10 is connected to diode D B3 The anode of the diode D B3 The cathode of the diode D B1 Cathode of diode D B2 The cathode of this is connected to the power supply terminal of the logic circuit 12a and one end of the capacitor C2.

[0072] The output terminal of the signal recognition circuit 11a is connected to the input terminal of the inverter IN1 and the other input terminal of the logic circuit 12a. The output terminal of the inverter IN1 is connected to the gate of the pull-out MOS 11b, and the other end of the resistor Rp1 is connected to the drain of the pull-out MOS 11b. The output terminal of the logic circuit 12a is connected to the gate of the pull-out MOS 12b, and the other end of the resistor Rp2 is connected to the drain of the pull-out MOS 12b.

[0073] The emitter terminal is connected to the anode of the Zener diode GEZD, the other end of the pull-down resistor Rpull, the reference power supply terminal of the signal recognition circuit 11a, the source of the pull-down MOS 11b, the other end of the capacitor C2, the reference power supply terminal of the logic circuit 12a, the source of the pull-down MOS 12b, and the emitter of the IGBT.

[0074] <Sink capacity of the extraction circuit> As described above, the steep switching operation of the IGBT when it is turned off in a conventional configuration generates resonant noise, so the igniter 10 of the present invention uses an IC 10a including extraction circuits 11 and 12 to extract the gate charge of the IGBT in two stages, thereby suppressing the generation of resonant noise.

[0075] When the dI / dt (rate of change of current) of the collector current falling when the IGBT is off is equal to or greater than a predetermined value, an induced voltage is generated in the emitter of the IGBT, generating noise. Therefore, the extraction circuit 11, which has a first sink capability, extracts gate charge from the gate of the IGBT at a first extraction speed at which dI / dt is less than a predetermined value (a change in the extraction speed does not trigger noise). Furthermore, the extraction circuit 12, which has a second sink capability, extracts gate charge at a second extraction speed at which the IGBT is turned off within a predetermined switching time of the IGBT (a change from the first extraction speed to the second extraction speed in this case also does not trigger resonant noise).

[0076] That is, in the first period of the first stage, the extraction circuit 11 gently extracts gate charge from the gate of the IGBT to make the collector current Ice fall gradually so that the collector current Ice has a dI / dt that does not trigger the generation of resonant noise. On the other hand, in the second period of the second stage, the extraction circuit 12 extracts gate charge more strongly than in the first period to maintain a predetermined switching time.

[0077] In this way, the gate charge is extracted in the first period by the extraction circuit 11 including the resistor Rp1 and extraction MOS 11b, etc., and the gate charge is extracted in the second period by the extraction circuit 12 including the resistor Rp2 and extraction MOS 12b, etc. The extraction operation will be described in more detail below.

[0078] Assume that the pull-out MOSs 11b and 12b are the same size. In this case, in the pull-out circuit 11, it is desired to pull out the gate charge so that the fall of the collector current Ice in the first period is more gradual than that of the igniter 110 of the conventional configuration shown in Fig. 13, so the resistor Rp1 is set to have a higher impedance (higher resistance value) than the resistor Rp shown in Fig. 13.

[0079] Furthermore, in the extraction circuit 12, it is desired to extract the gate charge so that the fall of the collector current Ice in the second period is steeper than that of the igniter 110 of the conventional configuration shown in FIG. 13, so the resistor Rp2 is set to a lower impedance (lower resistance value) than the resistor Rp shown in FIG. 13. The magnitude relationship of the resistance values ​​of the resistors Rp, Rp1, and Rp2 is as follows: <Rp<Rp1となる。

[0080] In this way, when the pull-out MOSs 11b and 12b are the same size, the resistor Rp1 in the pull-out circuit 11 is set to have a high impedance relative to the resistor Rp, and the resistor Rp2 in the pull-out circuit 12 is set to have a low impedance. This makes it possible to set the first sink capability of the pull-out circuit 11 lower than the sink capability of the igniter 110 of the conventional configuration, and the second sink capability of the pull-out circuit 12 higher than the first sink capability of the pull-out circuit 11.

[0081] On the other hand, the resistors Rp1 and Rp2 are not provided. In this configuration, the drains of the pull-out MOS 11b and 12b are connected to the gates of the IGBTs.

[0082] In this case, in the extraction circuit 11, it is desired to extract the gate charge so that the fall of the collector current Ice in the first period is more gradual than that of the igniter 110 of the conventional configuration shown in FIG. 13. Therefore, the size of the extraction MOS 11b is set smaller than the size of the extraction MOS 13 shown in FIG. 13, and the on-resistance value of the extraction MOS 11b is set larger than the on-resistance value of the extraction MOS 13.

[0083] 13, the pull-out circuit 12 is designed to pull out the gate charge so that the fall of the collector current Ice in the second period is steeper than that of the igniter 110 of the conventional configuration shown in FIG. 13, so the size of the pull-out MOS 12b is set larger than the size of the pull-out MOS 13, and the on-resistance of the pull-out MOS 12b is set smaller than the on-resistance of the pull-out MOS 13. The size relationship among the pull-out MOSs 13, 11b, and 12b is (size of pull-out MOS 11b)<(size of pull-out MOS 13)<(size of pull-out MOS 12b).

[0084] In this way, when the resistors Rp1 and Rp2 are not provided (or the resistors Rp1 and Rp2 may have the same resistance value), the size of the pull-out MOS 11b is made smaller and the size of the pull-out MOS 12b is made larger relative to the size of the pull-out MOS 13. This makes it possible to set the first sink capability of the pull-out circuit 11 lower than the sink capability of the igniter 110 of the conventional configuration, and the second sink capability of the pull-out circuit 12 higher than the first sink capability of the pull-out circuit 11.

[0085] As described above, by adjusting the resistance values ​​of the resistors Rp1 and Rp2 or adjusting the sizes of the pull-out MOSs 11b and 12b, the sink capabilities of both the pull-out circuits 11 and 12 can be flexibly adjusted.

[0086] <Logic circuit configuration and operation> 6 is a diagram showing an example of the configuration of a logic circuit 12a. The logic circuit 12a includes a logic element group 12a-1 including a two-input, one-output AND element ad and an inverter in0, a comparator cmp, resistors R0, R1, and R2, a diode D0, and a reference power supply unit Vref.

[0087] One end of resistor R0 is connected to the collector terminal, and the other end of resistor R0 is connected to one end of resistor R1 and the cathode of diode D0. The non-inverting input terminal of comparator cmp is connected to the other end of resistor R1 and one end of resistor R2 to generate voltage V Dis input, and the inverting input terminal of the comparator cmp is connected to the positive power supply terminal of the reference power supply unit Vref, and a predetermined voltage V R The anode of the diode D0 is connected to the other end of the resistor R2, the negative power supply terminal of the reference power supply unit Vref, and the emitter terminal.

[0088] The input terminal of the inverter in0 is connected to the output terminal of the signal recognition circuit 11a, and receives the voltage V1 The output terminal of the inverter in0 is connected to one input terminal of the AND element ad.

[0089] The output terminal of the comparator cmp is connected to the other input terminal of the AND element ad, and the output terminal of the AND element ad is connected to the gate of the extraction MOS 12b to output a voltage Mg2. Note that the voltage Vs shown in FIG. 5 is input to the power supplies of the components in the logic circuit 12a (AND element ad, inverter in0, and comparator cmp).

[0090] As shown above, the comparator cmp detects the voltage V across the resistors between the collector and emitter terminals. D and the reference power supply Vref outputs a predetermined voltage V R Then, a voltage Mg2, which is an output signal of the logic element group 12a-1 determined based on the logic of the output of the comparator cmp and the output (voltage V1) of the signal recognition circuit 11a, is input to the gate of the extraction MOS 12b.

[0091] 7 is a diagram showing the operation logic of the logic circuit. In logic table 5, when the output voltage of comparator cmp is at L level and the output voltage V1 of signal recognition circuit 11a (corresponding to the level indicating the on / off of the signal from ECU 4) is at L level, the output of AND element ad (output voltage Mg2 of logic circuit 12a) becomes L level and pull-out MOS 12b turns off. Also, when the output voltage of comparator cmp is at L level and the output voltage V1 of signal recognition circuit 11a is at H level, the output voltage Mg2 of logic circuit 12a becomes L level and pull-out MOS 12b turns off.

[0092] When the output voltage of the comparator cmp is at the H level and the output voltage V1 of the signal recognition circuit 11a is at the L level, the output voltage Mg2 of the logic circuit 12a becomes the H level, and the pull-out MOS 12b turns on (at this time, the gate charge is pulled out). Also, when the output voltage of the comparator cmp is at the H level and the output voltage V1 of the signal recognition circuit 11a is at the H level, the output voltage Mg2 of the logic circuit 12a becomes the L level, and the pull-out MOS 12b turns off.

[0093] <Power supply voltage of the logic circuit> FIG. 8 is a diagram for explaining the generation of the power supply voltage supplied to the logic circuit. The voltage Vs is supplied to the logic circuit 12a while ensuring a constant potential regardless of the on / off of the IGBT. The igniter 10 is configured to ensure the voltage Vs from a location that becomes a high potential even in states st1, st2, and st3 and perform stable power supply to the logic circuit 12a. Hereinafter, the fact that the voltage Vs is ensured at a constant value will be described.

[0094] [State st1] This is the case where the signal potential Vg of the gate terminal is off. At this time, the gate terminal voltage Vg and the gate voltage Vge are approximately equal to 0 V (Vg ≒ Vge ≒ 0 V). On the other hand, the voltage Vc (collector terminal voltage) of the collector terminal is approximately equal to the battery voltage Vb (Vc ≒ Vb). Therefore, a predetermined voltage Vs (a voltage at which the logic circuit 12a can operate normally) is generated and ensured through the resistor R10 and the diode D B3 and supplied to the logic circuit 12a.

[0095] [State st2] This is the case where the signal potential Vg of the gate terminal is on. At this time, since an H-level signal is input from the ECU 4, the gate terminal voltage Vg is 5 V, and the gate voltage Vge becomes a potential within the range from 0 V to the gate terminal voltage Vg (Vg ≒ 5 V, 0 V < < Vge < Vg). Also, since the IGBT turns on, the collector terminal voltage Vc is the collector-emitter saturation voltage Vcesat in the on state, and for example, it becomes as low as 1 V (Vc = Vcesat ≒ 1 V). Therefore, a predetermined voltage Vs is generated and ensured through the diode D B1 and supplied to the logic circuit 12a.

[0096] [State st3] This is the case immediately after the gate terminal signal potential Vg has transitioned from on to off (when the IGBT starts to cut off). At this time, the signal potential from ECU 4 is in the off state, but the IGBT is still maintained in the on state. In other words, the gate terminal voltage Vg is decreasing, but the gate voltage Vge has not yet dropped completely, and the IGBT is on. For this reason, the gate terminal voltage Vg is smaller than or equal to the gate voltage Vge, and the collector terminal voltage Vc is equal to the collector-emitter saturation voltage Vcesat (Vg≦Vge, Vc=Vcesat). Therefore, the diode D B2 A predetermined voltage Vs is generated and secured via the resistor 12a and supplied to the logic circuit 12a.

[0097] As described above, the power supply voltage of the logic circuit 12a is supplied to the B1 , D B2 , D B3 are supplied from the gate terminal side (gate terminal voltage Vg), the gate voltage Vge side, and the collector terminal side (collector terminal voltage Vc) via the respective

[0098] Therefore, the voltage Vs at which the logic circuit 12a can operate can be secured and stably supplied to the logic circuit 12a regardless of the switching operation of the IGBT of the igniter 10. Note that, although a capacitor C2 is connected in close proximity to the logic circuit 12a to reduce transient voltage fluctuations in the voltage Vs, a configuration may be adopted in which an additional protective diode is connected in parallel with the capacitor C2 in case the voltage Vs rises too much.

[0099] <Igniter operation> 9 is a time chart showing the operation of the igniter. In the following, we will explain the case where the sizes of the pull-out MOSs 11b and 12b are adjusted to provide different sink capabilities.

[0100] [Period from time t0 to time t1] The signal recognition circuit 11a recognizes the IGBT off signal from the ECU 4, and the signal recognition circuit 11a inputs a high-level voltage Mg1 to the gate of the pull-out MOS 11b. The pull-out MOS 11b then turns on and pulls out the gate charge from the IGBT gate. Note that since the first sink capability of the pull-out MOS 11b is reduced compared to the sink capability of the pull-out MOS 13 of the conventional configuration, the period (period from time t0 to time t1) until the gate voltage Vge reaches the mirror voltage is extended accordingly.

[0101] [Period from time t1 to time t2] The period from time t1 to time t2, which corresponds to the mirror region, is extended by the amount corresponding to the fact that the first sink capability of the pull-out MOS 11b is lower than that of the pull-out MOS 13. Also, the rate of increase in dV / dt of the collector voltage Vce is gentler than in FIG.

[0102] [Period from time t2 to time ta] The mirror region ends and the collector current Ice begins to fall, but because the first sink capability of the pull-out MOS 11b is lower than that of the pull-out MOS 13 shown in Figure 13, dI / dt changes more gradually than in Figure 14. Also, the collector voltage Vce begins to rise more rapidly from time t2, but dV / dt is gradually suppressed by the amount that the first sink capability of the pull-out MOS 11b has been reduced.

[0103] [Period from time ta to time t3] In the logic circuit 12a, the collector voltage Vce is divided by resistors, and the divided voltage V D The rise in the collector voltage Vce is detected through the D Since V is a voltage obtained by dividing the collector voltage Vce by resistors, it shows the same behavior as the time change of the collector voltage Vce. That is, Vce={(R0+R1+R2) / R2}×V D is.

[0104] In the logic circuit 12a, the divided voltage V D is a given voltage V RWhen this voltage exceeds , the output of the comparator cmp is inverted from L level to H level, and the output voltage Mg2 of the logic circuit 12a changes from L level to H level. At this timing (time ta), the extraction MOS 12b turns on and starts extracting the gate charge from the IGBT.

[0105] On the other hand, the second sink capability of the pull-out MOS 12b is set higher than the first sink capability of the pull-out MOS 11b. Therefore, the collector voltage Vce rises sharply at the transition point p1 with a dV / dt greater than the dV / dt during the gradual rise from time t2 to time ta. Vcep1, which is the collector voltage Vce at this transition point p1, is equal to the predetermined voltage V R 6, Vcep1 is a value determined by the resistance division ratio of the logic circuit 12a. That is, in the case of the logic circuit 12a of FIG. 6, Vcep1={(R0+R1+R2) / R2}×V R Furthermore, Vcep1 is ideally a voltage value lower than the battery voltage Vb, but it may be set to manipulate the operation timing of the pull-out MOS 12b and adjust the cut-off time of the collector current. In this case, Vcep1 may be higher than the battery voltage Vb.

[0106] Furthermore, the collector current Ice drops sharply from change point p2 with a larger dI / dt than the dI / dt during the gradual drop from time t2 to time ta. However, the drop in collector current Ice at this time is not as large as the dI / dt immediately after the mirror region as shown in Figure 14, so it is possible to suppress resonance noise caused by the steep dI / dt.

[0107] In the logic circuit 12a, clamp control is performed by the diode D0. However, without such clamp control, the divided voltage V D may rise until it reaches the voltage division ratio of the collector voltage Vce and exceed the upper input level of the comparator cmp.

[0108] For this reason, the logic circuit 12a is provided with a clamping diode D0 to protect the input of the comparator cmp. CL is the breakdown voltage of diode D0 × R2 / (R1+R2).

[0109] [Period from time t3 to time t4] When the Zener diode group CGZD breaks down, charge is supplied from the collector terminal to the gate voltage Vge, slowing down the rate at which the gate voltage Vge falls. As the rate at which the gate voltage Vge falls slows down, the rate at which the collector current Ice falls also slows down, and the collector current Ice continues to fall until the energy stored in the coil of the load connected to the collector terminal is released.

[0110] [Period from time t4 to time tb] The supply of charge from the collector terminal is cut off, and the decrease in gate voltage Vge accelerates. As described above, voltage Vs can be maintained as the internal circuit power supply, so the pull-out MOS 12b is in a driven state and the increase in gate voltage Vge is suppressed, so the IGBT can be prevented from turning on again even if external noise such as discharge noise from the spark plug 3 occurs.

[0111] [Period from time tb to time t5] The collector voltage Vce stops decreasing and becomes constant, the gate terminal voltage Vg and the gate voltage Vge become 0 V, and the IGBT is completely shut off. Here, when the signal from the ECU 4 is off, the signal recognition circuit 11a does not operate. In such a case, if the gate voltage of the IGBT is only pulled down by the pull-down resistor Rpull, the gate voltage Vge may rise momentarily due to noise or surges, causing the IGBT to malfunction and turn back on.

[0112] Therefore, in order to prevent such re-on of the IGBT, the divided voltage V D is a given voltage V RThe collector voltage Vce=Vcep1 when Vce is equal to Vcep1 is set to be lower than the battery voltage Vb, which is the voltage of the external power supply. As a result, even if the signal recognition circuit 11a is not operating and the pull-out MOS 11b is off when the signal is off, the pull-out MOS 12b can be turned on and operated, so the IGBT can be turned off reliably and the IGBT can be prevented from being turned on again due to noise or surges.

[0113] In addition, the predetermined voltage V R If is set to a value higher than the battery voltage Vb, the pull-out MOS 12b operates only at the high collector terminal voltage when the L load of the ignition coil 2 is off. In this case, the effect of preventing re-on may be weakened, but it is possible to vary the position of the change point of the collector current Ice (change point p2 at time ta shown in FIG. 9).

[0114] <Comparison of the present invention and the prior art> Figure 10 is a diagram comparing the waveforms of the operation of the present invention and the conventional operation. The dotted waveform is the conventional operation waveform shown in Figure 14, and the solid waveform is the operation waveform of the present invention shown in Figure 9. In the conventional operation waveform, during period T11, the collector current Ice drops sharply as the gate terminal voltage Vg drops.

[0115] On the other hand, in the operating waveform of the present invention, in the first half of the period T11a, the gate charge is extracted by the extraction circuit 11, which has low sinking capability, so the gate voltage Vge falls slowly, the mirror region becomes longer, and the collector current Ice also falls slowly, thereby suppressing the generation of resonant noise.

[0116] Furthermore, in the latter half of the period T11a, the gate charge is extracted by the extraction circuit 12 with high sinking capability with a strength that is not enough to trigger the generation of resonant noise, so the gate voltage Vge drops sharply and the collector current Ice also drops sharply.

[0117] Since the periods T11 and T11a have the same switching time interval, the present invention achieves two-stage gate charge extraction while suppressing the generation of resonance noise and maintaining the switching time.

[0118] <Modified Igniter> In the igniter 10 shown in FIG. 5, the collector terminal and the backflow prevention diode D B3 A resistor R10, which is a high-impedance resistive element, is connected between the igniter 10 and the collector terminal 12. By connecting such a high-resistance resistor R10, it is possible to prevent a large current from flowing into the igniter 10 even if the collector terminal voltage rises for some reason. On the other hand, a depletion-type power semiconductor switch can also be used instead of the high-resistance resistor R10.

[0119] 11 is a diagram showing a modified example of an igniter. An igniter 10-1 uses a dep-IGBT 14, which is a depletion-type power semiconductor switch, instead of the resistor R10.

[0120] The collector of the dep-IGBT 14 is connected to the collector terminal, the cathode of the Zener diode CGZD1, and one input terminal of the logic circuit 12a. The gate of the dep-IGBT 14 is connected to the emitter of the dep-IGBT 14 and the diode D B3 The other configurations are the same as in Figure 5.

[0121] The dep-IGBT 14 is a depression type IGBT with a breakdown voltage approximately equal to that of the main IGBT in the igniter 10, and has a high pinch-off voltage that is higher than the battery voltage Vb by shorting the gate and emitter, so that it can play a role similar to that of the high resistance resistor R10.

[0122] <Modification of logic circuit> Fig. 12 is a diagram showing a modified example of the logic circuit. In Fig. 6, the resistor R0 to which the collector voltage is supplied from one end is a high-impedance resistive element, but in the logic circuit 12a1, similar to Fig. 11, a dep-IGBT15, which is a depletion-type power semiconductor switch, is used instead of the resistor R0 with a high resistance value.

[0123] As described above, according to the present invention, when a command to turn off the semiconductor switch is detected, the first extraction circuit extracts gate charge from the gate of the semiconductor switch with a first sink capability, and when a voltage generated from the collector voltage of the semiconductor switch is equal to or higher than a predetermined voltage, the second extraction circuit extracts gate charge with a second sink capability higher than the first sink capability.

[0124] This configuration prevents noise generation and enables stable device operation. Furthermore, in the two-stage gate charge extraction, the delay in storage time caused by lowering the sink capacity of the first extraction circuit is eliminated by extracting the gate charge with the second extraction circuit, which has a higher sink capacity, thereby shortening the fall time and eliminating the delay. This allows the IGBT to be turned off within the desired switching time, thereby suppressing switching losses.

[0125] Furthermore, even if the operation of the first extraction circuit stops when the signal from the ECU is turned off, the second extraction circuit continues to operate, making it possible to prevent the IGBT from being erroneously turned on again due to external noise.

[0126] Although the embodiments have been described above, the configuration of each part shown in the embodiments can be replaced with other parts having similar functions. Also, any other components or processes may be added. Furthermore, any two or more configurations (features) of the above-described embodiments may be combined. [Explanation of symbols]

[0127] 1. Semiconductor device 1a semiconductor switch 1b Control circuit 1b1 Extraction circuit (first extraction circuit) 1b2 Extraction circuit (second extraction circuit) ct Signal that indicates whether a semiconductor switch is on or off Ice collector current t11 Time required for the first sink to extract the gate charge t12 Time required for the second sink to draw the gate charge ts Switching time

Claims

1. A semiconductor switch; a control circuit including: a first extraction circuit that extracts gate charge from the gate of the semiconductor switch with a first sink capacity when an instruction to turn off the semiconductor switch is detected; and a second extraction circuit that extracts the gate charge with a second sink capacity higher than the first sink capacity when a voltage generated from a collector voltage of the semiconductor switch is equal to or higher than a predetermined voltage, and that is driven by a voltage of a signal that instructs the semiconductor switch to be turned on or off; A semiconductor device having:

2. When the rate of change of the collector current falling when the semiconductor switch is turned off is equal to or greater than a predetermined value, an induced voltage is generated in the semiconductor switch, causing noise. the first extraction circuit having the first sink capability extracts the gate charge at a first extraction speed at which the current change rate is less than the predetermined value; the second extraction circuit having the second sink capability extracts the gate charge at a second extraction rate at which the semiconductor switch is turned off within a predetermined switching time of the semiconductor switch; The semiconductor device according to claim 1.

3. the first extraction circuit includes a detection circuit that detects whether the signal is on or off, a first resistance element, and a first extraction transistor, one end of the first resistance element is connected to the gate of the semiconductor switch, the other end of the first resistance element is connected to the drain of the first extraction transistor, a first drive signal from the detection circuit is input to the gate of the first extraction transistor, and a source of the first extraction transistor is connected to the emitter of the semiconductor switch and a reference power supply; the second pull-out circuit includes a logic circuit that compares a voltage generated from the collector voltage with the predetermined voltage when the signal is off, a second resistance element, and a second pull-out transistor, one end of the second resistance element is connected to the gate of the semiconductor switch, the other end of the second resistance element is connected to the drain of the second pull-out transistor, a second drive signal from the logic circuit is input to the gate of the second pull-out transistor, and a source of the second pull-out transistor is connected to the emitter of the semiconductor switch and the reference power supply. The semiconductor device according to claim 1.

4. a size of the first pull-out transistor and a size of the second pull-out transistor are made the same, an impedance of the second resistive element is made lower than an impedance of the first resistive element, and the second sink capability is set higher than the first sink capability; 4. The semiconductor device according to claim 3.

5. a resistance value of the first resistance element and a resistance value of the second resistance element are set to be the same, and a size of the second pull-out transistor is set to be larger than a size of the first pull-out transistor, so that the second sink capability is set to be higher than the first sink capability; 4. The semiconductor device according to claim 3.

6. the first pull-out circuit includes a detection circuit that detects whether the signal is on or off, and a first pull-out transistor, the drain of the first pull-out transistor is connected to the gate of the semiconductor switch, a first drive signal from the detection circuit is input to the gate of the first pull-out transistor, and the source of the first pull-out transistor is connected to the emitter of the semiconductor switch and a reference power supply; the second pull-out circuit includes a logic circuit that compares a voltage generated from the collector voltage with the predetermined voltage when the signal is off, and a second pull-out transistor, the drain of the second pull-out transistor is connected to the gate of the semiconductor switch, a second drive signal from the logic circuit is input to the gate of the second pull-out transistor, and the source of the second pull-out transistor is connected to the emitter of the semiconductor switch and the reference power supply, a size of the second pull-out transistor is set larger than a size of the first pull-out transistor, and the second sink capability is set higher than the first sink capability; The semiconductor device according to claim 1.

7. the second extraction circuit includes a logic circuit that compares a voltage generated from the collector voltage with the predetermined voltage when the signal is off, The power supply for the logic circuit is When the input potential of the signal is off, a predetermined power supply voltage is supplied from the voltage of the collector terminal of the semiconductor switch, When the input potential of the signal is on, a predetermined power supply voltage is supplied from the voltage of the signal, When the input potential of the signal transitions from on to off, a predetermined power supply voltage is supplied from the gate voltage of the semiconductor switch. The semiconductor device according to claim 1.

8. 8. The semiconductor device according to claim 7, further comprising a resistor provided between the power supply input terminal of said logic circuit and said collector terminal for suppressing a current flowing through said logic circuit when a voltage of said collector terminal exceeds a predetermined value.

9. 9. The semiconductor device according to claim 8, wherein said resistance portion is a high-impedance resistance element or a depletion-type power semiconductor switch.

10. 7. The semiconductor device according to claim 3, wherein the logic circuit comprises: a group of resistors that generates a divided voltage of the collector voltage; a reference power supply unit; a comparator; and a group of logic elements that generate the second drive signal by taking a logic between an output result of the comparator and a level indicating on / off of the signal, and wherein the collector voltage when the divided voltage becomes the predetermined voltage output by the reference power supply unit is set lower than the voltage of an external power supply that supplies a voltage to the collector terminal of the semiconductor switch.

11. 11. The semiconductor device according to claim 10, wherein one of the resistors that generates the divided voltage of the collector voltage and has one end to which the collector voltage is supplied is a high-impedance resistor or a depletion-type power semiconductor switch.

12. 2. The semiconductor device according to claim 1, wherein said semiconductor switch and said control circuit including said first pull-out circuit and said second pull-out circuit are integrated on the same chip.

13. an igniter comprising: a semiconductor switch; a first extraction circuit that extracts gate charge from the gate of the semiconductor switch with a first sink capacity when an instruction to turn off the semiconductor switch is detected; and a second extraction circuit that extracts the gate charge with a second sink capacity higher than the first sink capacity when a voltage generated from a collector voltage of the semiconductor switch is equal to or higher than a predetermined voltage, the igniter being driven by a voltage of a signal that is output from an electronic control unit and instructs the semiconductor switch to be turned on or off; an ignition coil connected to an external power source via a harness and amplifying the voltage generated by the semiconductor switch; a spark plug that discharges based on the negative voltage output from the ignition coil; a capacitor connected to a power supply and a ground in the system and to the emitter of the semiconductor switch via the harness; An ignition system having:

14. When the rate of change of the collector current falling when the semiconductor switch is turned off is equal to or greater than a predetermined value, an induced voltage is generated in the emitter of the semiconductor switch, and the induced voltage generates resonance noise due to the parasitic inductance of the harness and the capacitance of the capacitor. the first extraction circuit having the first sink capability extracts the gate charge at a first extraction speed at which the current change rate is less than the predetermined value; the second extraction circuit having the second sink capability extracts the gate charge at a second extraction rate at which the semiconductor switch is turned off within a predetermined switching time of the semiconductor switch; 14. The ignition system of claim 13.

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