Electronic Devices
By integrating filters and inductors within a dielectric substrate, the electronic device minimizes insertion loss and maintains performance, addressing miniaturization challenges in triplexers.
Patent Information
- Application Number
- JP2022127904
- Authority / Receiving Office
- JP · JP
- Patent Type
- Patents
- Current Assignee / Owner
- Filing Date
- 2022-08-10
- Publication Date
- 2025-10-07
- Estimated Expiration
- 2042-08-10
AI Technical Summary
Existing electronic devices that separate input signals into multiple frequency bands, such as triplexers, face challenges in minimizing insertion loss and maintaining filter characteristics while meeting miniaturization demands.
An electronic device comprising a dielectric substrate with integrated filters and an inductor, where the higher-frequency filter is coupled to a common terminal via a partial inductor, bypassing a second partial inductor, and capacitors are strategically placed to manage parasitic capacitance, ensuring appropriate inductance and reduced insertion loss.
The solution effectively suppresses insertion loss and maintains filter characteristics, enabling a compact and high-performance electronic device.
Smart Images
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Abstract
Description
[Technical Field]
[0001] The present invention relates to electronic devices. [Background technology]
[0002] Electronic devices that can separate an input signal into multiple signals with different frequency bands have attracted attention. Such electronic devices are called branching filters. Electronic devices that can separate an input signal into three frequency bands are called triplexers (Patent Document 1). [Prior art documents] [Patent documents]
[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2013-243600 Summary of the Invention [Problem to be solved by the invention]
[0004] There is a need for better electronic devices.
[0005] The present invention aims to solve the above-mentioned problems. [Means for solving the problem]
[0006] An electronic device according to one embodiment of the present invention comprises a dielectric substrate, a common terminal provided on the dielectric substrate for inputting or outputting a signal, an inductor formed in the dielectric substrate, a first filter formed in the dielectric substrate, and a second filter formed in the dielectric substrate, wherein the passband frequency of the second filter is higher than the passband frequency of the first filter, the first filter is electrically coupled to the common terminal via the inductor, the inductor includes a first partial inductor and a second partial inductor connected in series to the first partial inductor, and the second filter is electrically coupled to the common terminal via the first partial inductor without going through the second partial inductor. [Effects of the Invention]
[0007] According to the present invention, a better electronic device can be provided. [Brief explanation of the drawings]
[0008] [Figure 1] FIG. 1 is a circuit diagram illustrating an electronic device according to one embodiment. [Figure 2] FIG. 2 is a perspective view illustrating an electronic device according to one embodiment. [Figure 3] FIG. 3 is a perspective view illustrating a portion of an electronic device according to one embodiment. [Figure 4] FIG. 4 is a side view of a portion of an electronic device according to one embodiment. [Figure 5] FIG. 5 is a perspective view illustrating an electronic device according to one embodiment. [Figure 6] FIG. 6 is a graph showing the evaluation results of the electronic device according to one embodiment. [Figure 7] FIG. 7 is a circuit diagram showing an electronic device according to a reference example. DETAILED DESCRIPTION OF THE INVENTION
[0009] [One embodiment] An electronic device according to an embodiment will be described with reference to the drawings, in which: Figure 1 is a circuit diagram showing an electronic device according to the present embodiment.
[0010] 1, an electronic device 10 according to this embodiment includes a plurality of filters 12L, 12M, and 12H. Here, the electronic device 10 will be described as a duplexer, but is not limited to this.
[0011] The pass band (pass frequency band) of filter 12L has a relatively low frequency (pass band frequency). The pass band of filter 12H has a relatively high frequency. The pass band of filter 12M has a higher frequency than the pass band of filter 12L but a lower frequency than the pass band of filter 12H.
[0012] The electronic device 10 further includes an inductor 14. The inductor 14 includes a partial inductor (first partial inductor) 14A and a partial inductor (second partial inductor) 14B. The partial inductor 14B is connected in series to the partial inductor 14A.
[0013] One end (input node, input end) of the filter (low-band filter) 12L is electrically coupled to a common terminal (common input terminal) 16A via an inductor 14. The other end (output node, output end) of the filter 12L is electrically connected to a terminal (output terminal) 16B.
[0014] One end (input node, input end) of filter (middle band filter) 12M is electrically coupled to common terminal 16A via inductor 14. More specifically, one end of filter 12M is electrically coupled to common terminal 16A via capacitor 20A and inductor 14. The other end (output node) of filter 12M is electrically connected to terminal (output terminal) 16C.
[0015] One end (input node) of the filter (high-band filter) 12H is electrically coupled to the common terminal 16A via the partial inductor 14A. More specifically, one end of the filter 12H is electrically coupled to the common terminal 16A via the capacitor 20B and the partial inductor 14A, but not via the partial inductor 14B. One end of the filter 12H is electrically coupled to a portion where the partial inductor 14A and the partial inductor 14B are connected to each other via the capacitor 20B. That is, one end of the filter 12H is electrically coupled to the connection node 14a via the capacitor 20B. The other end (output node) of the filter 12H is electrically connected to the terminal (output terminal) 16D.
[0016] One end of the partial inductor 14A is connected to the common terminal 16A. The other end of the partial inductor 14A is connected to one end of the partial inductor 14B at the connection node 14a. The other end of the partial inductor 14B is connected to one end of the filter 12L and to one end of the capacitor 20A. The other end of the capacitor 20A is connected to one end of the filter 12M. One end of the capacitor 20B is connected to the partial inductor 14A at the connection node 14a. The other end of the capacitor 20B is connected to one end of the filter 12H.
[0017] Note that, although a case where the filter 12M is electrically coupled to the common terminal 16A via the inductor 14 will be described here as an example, the present invention is not limited to this. The filter 12M may be electrically coupled to the common terminal 16A via the partial inductor 14A without via the partial inductor 14B. In other words, the filter 12M may be electrically coupled to the common terminal 16A via a part of the inductor 14.
[0018] FIG. 2 is a perspective view showing the electronic device according to this embodiment.
[0019] 2, the electronic device 10 includes a dielectric substrate 24. The dielectric substrate 24 is formed, for example, in a rectangular parallelepiped shape, but is not limited to this. The dielectric substrate 24 is formed by laminating a plurality of ceramic sheets (dielectric ceramic sheets).
[0020] The dielectric substrate 24 has a main surface (first main surface, upper surface) 24a and a main surface (second main surface, lower surface) 24b (see FIG. 4). The main surface 24a and the main surface 24b are located on opposite sides to each other.
[0021] Filters 12L, 12M, and 12H are formed within the dielectric substrate 24. Within the dielectric substrate 24, an inductor (inductor coil) 14 is further formed.
[0022] A shielding layer 54 is formed on the main surface 24a of the dielectric substrate 24. The shielding layer 54 may be formed inside the dielectric substrate 24.
[0023] Fig. 3 is a perspective view showing a portion of the electronic device according to this embodiment. Fig. 3 shows an inductor 14. Fig. 4 is a side view showing a portion of the electronic device according to this embodiment. Fig. 4 shows the inductor 14 and capacitors 20A and 20B. For ease of explanation, Figs. 3 and 4 show only some of the components.
[0024] As shown in Fig. 3, the inductor 14 is configured by combining a plurality of winding patterns 26a to 26d and a plurality of via electrodes 28a to 28c. When describing the individual winding patterns without distinction, the reference numeral 26 is used, and when describing the individual winding patterns with distinction, the reference numerals 26a to 26d are used. When describing the individual via electrodes without distinction, the reference numeral 28 is used, and when describing the individual via electrodes with distinction, the reference numerals 28a to 28c are used. The inductor 14 is also called a spiral inductor. The inductor 14 is formed three-dimensionally.
[0025] As shown in FIG. 3, one end of the winding pattern 26a is connected to the upper end of the via electrode 30. The lower end of the via electrode 30 is electrically connected to the common terminal 16A via the conductive pattern 36 (see FIG. 4) and the via electrode 38 (see FIG. 4). That is, one end of the winding pattern 26a is electrically connected to the common terminal 16A via the via electrode 30. In other words, one end of the inductor 14 is electrically connected to the common terminal 16A via the via electrode 30. The via electrode 30 penetrates a dielectric layer 24B (see FIG. 4), which will be described later. The other end of the winding pattern 26a is connected to the upper end of the via electrode 28a. The lower end of the via electrode 28a is connected to one end of the winding pattern 26b. The other end of the winding pattern 26b is connected to the upper end of the via electrode 28b. The lower end of the via electrode 28b is connected to one end of the winding pattern 26c. The other end of the winding pattern 26c is connected to the upper end of the via electrode 28c. The lower end of the via electrode 28c is connected to one end of the winding pattern 26d. The other end of the winding pattern 26d is connected to the upper end of the via electrode 29. The lower end of the via electrode 29 is electrically connected to the filter 12L (see FIG. 2) via the conductive pattern 32.
[0026] As shown in Fig. 4, the inductor 14 is connected to the capacitor 20A through a via electrode 42. The capacitor 20A includes a pair of capacitor electrodes 20Aa and 20Ab. A capacitor dielectric layer 20Ac is provided between the capacitor electrode 20Aa and the capacitor electrode 20Ab. The inductor 14 is connected to the capacitor electrode 20Aa through the via electrode 42. The capacitor electrode 20Ab is electrically connected to the filter 12M through a via electrode 44.
[0027] The partial inductor 14A (see FIG. 1) described above is configured by the winding pattern 26a. The partial inductor 14B (see FIG. 1) described above is configured by the winding patterns 26b to 26d and via electrodes 28b and 28c. The partial inductors 14A and 14B are connected to each other by the via electrode 28a. That is, the partial inductors 14A and 14B are connected to each other at the connection node 14a. The via electrode 28a forms part of the connection node 14a (see FIG. 1) described above. In the example shown in FIG. 3, the conductive pattern 34 is connected to one end of the winding pattern 26b, but this is not limiting. A portion of the winding pattern 26 other than the end may be connected to the conductive pattern 34. Furthermore, a portion of the via electrode 28 other than its upper and lower portions may be connected to the conductive pattern 34.
[0028] As shown in FIG. 4, the connection node 14a is electrically connected to the capacitor 20B via the conductive pattern 34, the via electrode 40, the conductive pattern 46, and the via electrode 48. The capacitor 20B includes a pair of capacitor electrodes 20Ba and 20Bb. The connection node 14a is electrically connected to the capacitor electrode 20Ba via the conductive pattern 34, the via electrode 40, the conductive pattern 46, and the via electrode 48. A capacitor dielectric layer 20Bc is provided between the capacitor electrode 20Ba and the capacitor electrode 20Bb. The capacitor electrode 20Bb is electrically connected to the filter 12H (see FIG. 2) via the via electrode 50.
[0029] As shown in Figure 4, the dielectric substrate 24 includes a dielectric layer (first dielectric layer) 24A, a dielectric layer (second dielectric layer) 24B, and a dielectric layer (third dielectric layer) 24C. The dielectric layer 24B is located on the dielectric layer 24A. The dielectric constant of the dielectric layer 24B is higher than that of the dielectric layer 24A. The dielectric layer 24C is located on the dielectric layer 24B. The dielectric constant of the dielectric layer 24C is lower than that of the dielectric layer 24B.
[0030] The inductor 14 is formed in the dielectric layer 24C. The dielectric constant of the dielectric layer 24C is relatively low, so that the inductor 14 has good characteristics.
[0031] A ground layer 52 is provided within the dielectric substrate 24. The ground layer 52 is provided at the boundary between the dielectric layer 24A and the dielectric layer 24B.
[0032] The capacitor 20A is located above the ground layer 52. The capacitor electrode 20Ab of the capacitor 20A is located within the dielectric layer 24B. The capacitor electrode 20Aa of the capacitor 20A is formed on the dielectric layer 24A. More specifically, the capacitor electrode 20Aa of the capacitor 20A is located at the boundary between the dielectric layer 24B and the dielectric layer 24C.
[0033] The capacitor dielectric layer 20Ac of the capacitor 20A is formed of a part of the dielectric layer 24B. The reason why the capacitor dielectric layer 20Ac is formed of a part of the dielectric layer 24B is to obtain a capacitor 20A with sufficient capacitance. That is, since the dielectric constant of the dielectric layer 24B is relatively high, a capacitor 20A with sufficient capacitance can be obtained.
[0034] The capacitor 20B is located above the ground layer 52. The capacitor electrode 20Bb of the capacitor 20B is located within the dielectric layer 24B. The capacitor electrode 20Ba of the capacitor 20B is located on the dielectric layer 24B. More specifically, the capacitor electrode 20Ba of the capacitor 20B is located at the boundary between the dielectric layer 24B and the dielectric layer 24C.
[0035] The capacitor dielectric layer 20Bc of the capacitor 20B is formed of a part of the dielectric layer 24B. The reason why the capacitor dielectric layer 20Bc is formed of a part of the dielectric layer 24B is to obtain a capacitor 20B with sufficient capacitance. In other words, since the dielectric constant of the dielectric layer 24B is relatively high, a capacitor 20B with sufficient capacitance can be obtained.
[0036] 5 is a perspective view showing a part of the electronic device according to this embodiment, showing the electronic device 10 as seen obliquely from below.
[0037] 5, a common terminal 16A and terminals 16B to 16D are provided on the lower surface of the dielectric layer 24A (see FIG. 4). Terminals (ground electrodes) 16E to 16H are further provided on the lower surface of the dielectric layer 24A. The terminals 16E to 16H are electrically connected to the ground layer 52.
[0038] As described above, the common terminal 16A is electrically connected to the via electrode 30. The dielectric layer 24B exists between the portion of the via electrode 30 that penetrates the dielectric layer 24B and the ground layer 52. The dielectric constant of the dielectric layer 24B is relatively high. Therefore, a certain amount of parasitic capacitance 22 (see FIG. 1) occurs in the common terminal 16A.
[0039] The evaluation results of the electronic device according to this embodiment will be described with reference to FIG.
[0040] FIG. 6 is a graph showing evaluation results of the electronic device according to this embodiment. The horizontal axis in FIG. 6 represents frequency. The vertical axis in FIG. 6 represents insertion loss. The solid line in FIG. 6 represents the characteristics of this embodiment. The dashed line in FIG. 6 represents the characteristics of a reference example. FIG. 7 is a circuit diagram showing an electronic device according to a reference example. As shown in FIG. 7, in the reference example, filter 12M is electrically coupled to common terminal 16A without via inductor 14. Also, as shown in FIG. 7, in the reference example, filter 12H is electrically coupled to common terminal 16A without via partial inductor 14A.
[0041] 6, in the reference example, the insertion loss in the path including filter 12H is relatively large. That is, in the reference example, the insertion loss in the path from common terminal 16A to terminal 16D is relatively large. Also, in the reference example, the insertion loss in the path including filter 12M is relatively large. That is, in the reference example, the insertion loss in the path from common terminal 16A to terminal 16C is relatively large.
[0042] In contrast, in this embodiment, insertion loss in the path including filter 12H can be suppressed. That is, in this embodiment, insertion loss in the path from common terminal 16A to terminal 16D can be suppressed. Also, in this embodiment, insertion loss in the path including filter 12M can be suppressed. That is, in this embodiment, insertion loss in the path from common terminal 16A to terminal 16C can be suppressed.
[0043] As described above, according to this embodiment, the filter 12H is electrically coupled to the common terminal 16A via the partial inductor 14A. Therefore, according to this embodiment, the influence of the parasitic capacitance 22 generated at the common terminal 16A on the filter 12H can be suppressed. Moreover, according to this embodiment, the filter 12H is electrically coupled to the common terminal 16A via the partial inductor 14A, not via the partial inductor 14B. Therefore, according to this embodiment, an appropriate inductance is obtained between the filter 12H and the common terminal 16A. Because the inductance between the filter 12H and the common terminal 16A is appropriate, the characteristics of the filter 12H do not deteriorate. Moreover, according to this embodiment, the partial inductor 14A is part of the inductor 14, so there is no need to form an inductor separate from the inductor 14. According to this embodiment, an electronic device with excellent characteristics can be provided while satisfying the demand for miniaturization. Thus, according to this embodiment, it is possible to provide a better electronic device.
[0044] [Modified embodiment] The present invention is not limited to the above-described embodiment, and various configurations can be adopted without departing from the gist of the present invention.
[0045] For example, in the above embodiment, the electronic device 10 is described as a demultiplexer, but is not limited to this. The electronic device 10 may be a multiplexer. In this case, signals are input to the terminals (input terminals) 16B to 16D, and are output from the common terminal (common output terminal) 16A.
[0046] The following additional notes are further disclosed regarding the above embodiment.
[0047] (Appendix 1) The electronic device (10) comprises a dielectric substrate (24), a common terminal (16A) provided on the dielectric substrate for inputting or outputting a signal, an inductor (14) formed in the dielectric substrate, a first filter (12L) formed in the dielectric substrate, and a second filter (12H) formed in the dielectric substrate, wherein the passband frequency of the second filter is higher than the passband frequency of the first filter, the first filter is electrically coupled to the common terminal via the inductor, the inductor includes a first partial inductor (14A) and a second partial inductor (14B) connected in series to the first partial inductor, and the second filter is electrically coupled to the common terminal via the first partial inductor without via the second partial inductor. With this configuration, the second filter is electrically coupled to the common terminal via the first partial inductor. Therefore, with this configuration, the influence of parasitic capacitance occurring in the common terminal on the second filter can be suppressed. Moreover, with this configuration, the second filter is electrically coupled to the common terminal via the first partial inductor, not via the second partial inductor, so that an appropriate inductance is obtained between the second filter and the common terminal. Since the inductance between the second filter and the common terminal is appropriate, the characteristics of the second filter do not deteriorate. Furthermore, with this configuration, the first partial inductor is part of the inductor, so there is no need to form an inductor separate from the inductor. This configuration makes it possible to provide an electronic device with good characteristics while satisfying the demand for miniaturization. This configuration makes it possible to provide an even better electronic device.
[0048] (Appendix 2) In the electronic device described in Appendix 1, the dielectric substrate may include a first dielectric layer (24A), a second dielectric layer (24B) formed on the first dielectric layer and having a higher dielectric constant than the first dielectric layer, and a third dielectric layer (24C) formed on the second dielectric layer and having a lower dielectric constant than the second dielectric layer, the common terminal may be provided on a lower surface of the first dielectric layer, the inductor may be formed in the third dielectric layer, and a ground plane (52) may be provided at a boundary between the first dielectric layer and the second dielectric layer, and the second filter may be electrically coupled to the common terminal via a first capacitor (20B) including a first capacitor dielectric layer (20Bc) made of a part of the second dielectric layer, the first partial inductor, and a via electrode (30) penetrating the second dielectric layer. In this configuration, a relatively large parasitic capacitance may occur between the via electrode and the ground plane, but because the second filter is electrically coupled to the common terminal via the first partial inductor, the influence of the parasitic capacitance on the second filter may be sufficiently suppressed.
[0049] (Appendix 3) The electronic device described in Appendix 2 may further include a third filter (12M) formed in the dielectric substrate, wherein the frequency of the pass band of the third filter is higher than the frequency of the pass band of the first filter and lower than the frequency of the pass band of the second filter, and the third filter may be electrically coupled to the common terminal via a second capacitor (20A) including a second capacitor dielectric layer (20Ac) consisting of another part of the second dielectric layer, at least a part of the inductor, and the via electrode.
[0050] The present invention is not limited to the above disclosure, and various configurations can be adopted without departing from the gist of the present invention. [Explanation of symbols]
[0051] 10: Electronic Devices 12H, 12L, 12M: Filters 14: Inductor 14A, 14B: Partial inductors 14a: Connection node 16A~16H: Common terminal 20A, 20B: Capacitor 20Aa, 20Ab, 20Ba, 20Bb: capacitor electrodes 20Ac, 20Bc: Capacitor dielectric layer 22: Parasitic capacitance 24: Dielectric substrate 24A to 24C: Dielectric layers 24a, 24b: Main surfaces 26a, 26b, 26c, 26d: Winding patterns 28a to 28c, 29, 30, 38, 40, 42, 44, 48, 50: Via electrodes 32, 34, 36, 46: Conductive patterns 52: Ground layer 54: Shielding layer
Claims
1. a dielectric substrate; a common terminal provided on the dielectric substrate for inputting or outputting a signal; an inductor formed within the dielectric substrate; a first filter formed within the dielectric substrate; a second filter formed within the dielectric substrate; Equipped with the frequency of the pass band of the second filter is higher than the frequency of the pass band of the first filter; the first filter is electrically coupled to the common terminal via the inductor; the inductor includes a first partial inductor and a second partial inductor connected in series to the first partial inductor; the second filter is electrically coupled to the common terminal via the first partial inductor without via the second partial inductor; the inductor is provided separately from both the first filter and the second filter, the first partial inductor is a part of one of the inductors, the second partial inductor is another part of the one inductor, The electronic device, wherein the first partial inductor and the second partial inductor overlap each other in a plan view.
2. 10. The electronic device according to claim 1, the dielectric substrate includes a first dielectric layer, a second dielectric layer formed on the first dielectric layer and having a higher dielectric constant than the first dielectric layer, and a third dielectric layer formed on the second dielectric layer and having a lower dielectric constant than the second dielectric layer, the common terminal is provided on a lower surface of the first dielectric layer; the inductor is formed in the third dielectric layer; a ground plane is provided at the boundary between the first dielectric layer and the second dielectric layer; the second filter is electrically coupled to the common terminal via a first capacitor including a first capacitor dielectric layer made of a portion of the second dielectric layer, the first partial inductor, and a via electrode that penetrates the second dielectric layer.
3. 3. The electronic device according to claim 2, further comprising a third filter formed within the dielectric substrate; a frequency of the pass band of the third filter is higher than a frequency of the pass band of the first filter and lower than a frequency of the pass band of the second filter; the third filter is electrically coupled to the common terminal via a second capacitor including a second capacitor dielectric layer consisting of another portion of the second dielectric layer, at least a portion of the inductor, and the via electrode.
Citation Information
Patent Citations
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