Data access method, device and non-transitory computer-readable storage medium

Abstract

The present disclosure provides a data access method, apparatus, and non-transitory computer-readable storage medium, in which the method includes: obtaining a plurality of processing-to-be-processed instructions, each of the processing-to-be-processed instructions including an access-to-be address; determining a merge-to-be instruction in the plurality of processing-to-be-processed instructions; merging-processing the merge-to-be instructions to obtain a merge instruction; and performing data access based on the access-to-be address corresponding to the merge instruction, thereby reducing instruction overhead, improving instruction processing efficiency, and effectively improving the performance of an electronic device.

Description

[Technical Field]

[0001] (Cross-reference of related applications) This application is filed based on and claims priority to a Chinese patent application bearing application number 202111543913.4 and filing date 2021 / 12 / 16, the entire contents of which are hereby incorporated by reference into this application.

[0002] The present disclosure relates to the field of electronic devices, and in particular to a data access method, apparatus and non-transitory computer-readable storage medium. [Background technology]

[0003] With the development of technology, memories based on the Joint Electron Device Engineering Council (JEDEC) protocol (e.g., Nand flash) have been widely applied in electronic devices such as mobile terminals.

[0004] Currently, after a processing instruction is generated in a process on an electronic device, the processing instruction is sent to a memory based on the JEDEC protocol, and the memory processes the processing instruction, i.e., accesses the access address of the processing instruction, i.e., reads or writes data.

[0005] However, if there are multiple instructions to be processed, the instructions to be processed need to be sent to the memory one by one, which increases instruction overhead and allows the memory to only process the instructions one by one, reducing the efficiency of instruction processing and affecting the performance of the electronic device. Summary of the Invention

[0006] In response to this, the present disclosure provides a data access method, an apparatus, and a non-transitory computer-readable storage medium that can efficiently improve the performance of electronic devices.

[0007] A first aspect of an embodiment of the present disclosure provides a data access method applied to an electronic device, the method comprising: obtaining a plurality of instructions to be processed, each of the instructions to be processed including an address to be accessed; determining a merge-to-be-executed command among the plurality of process-to-be-executed commands, and performing a merge process on the merge-to-be-executed command to obtain a merge command; and performing data access based on the address to be accessed corresponding to the merge instruction.

[0008] Optionally, determining a merge-to-be-done instruction in said plurality of processing-to-be instructions comprises: obtaining a first command, the first command being one of the commands to be processed; a second instruction is acquired by traversing instructions to be processed other than the first instruction, and an access planned address of the second instruction and an access planned address of the first instruction are indirectly consecutive, and the access planned address of the second instruction is not consecutive to the access planned address of the first instruction via an access planned address of another instruction to be processed; and determining the second instruction and the first instruction as the instructions to be merged in response to the second instruction and the first instruction satisfying a first predetermined merge condition.

[0009] Optionally, determining the second instruction and the first instruction as the to-be-merged instructions in response to the second instruction and the first instruction satisfying a first predetermined merging condition comprises: Obtaining a storage interval and / or a current total access data amount, the storage interval indicating a distance between the access destination address of the first instruction and the access destination address of the second instruction, and the current total access data amount indicating a sum of the access destination data amounts corresponding to all merge destination instructions; If the storage interval is smaller than a first predetermined threshold and / or the current total amount of accessed data is smaller than a second predetermined threshold, determining the second instruction and the first instruction as the instructions to be merged.

[0010] Optionally, the method further comprises: When the total amount of currently accessed data is equal to or greater than the second predetermined threshold, traversal of instructions to be processed other than the first instruction is stopped.

[0011] Optionally, the method further comprises: Obtaining a first length of time and obtaining a first time threshold corresponding to the first command, the first length of time indicating a length of time from a determination of obtaining the first command to a current time; responsive to the first length of time being less than a first time threshold, continuing traversal of instructions to be processed other than the first instruction; and in response to the first length of time being equal to or greater than the first time threshold, stopping traversal of instructions to be processed other than the first instruction.

[0012] Optionally, the method further comprises: obtaining a difference between the access address of the second instruction and the access address of the first instruction, and determining that the access address is a logical address; Obtaining a predetermined storage unit size; The method includes obtaining the storage interval based on the difference value and the size of the predetermined storage unit.

[0013] Optionally, the method further comprises: obtaining a first command, the first command being one of the commands to be processed; traversing instructions to be processed other than the first instruction; and determining, in response to the currently traversed instruction to be processed and the first instruction satisfying a second predetermined merge condition, the currently traversed instruction to be processed and the first instruction as the instructions to be merged.

[0014] Optionally, the method further comprises: storing the command to be processed in a predetermined command queue; In the predetermined instruction queue, a second time length corresponding to the instruction to be processed is greater than a second time threshold, the second time length indicating a storage time length for the instruction to be processed in the predetermined instruction queue; The instruction to be processed is located at a set position in a predetermined instruction queue, and the set position satisfies at least one of the conditions of being the first position in the queue or the last position in the queue, and the instruction to be processed is set as the first instruction.

[0015] Optionally, merging the plurality of to-be-merged instructions to obtain a merge instruction comprises: The method includes generating a merge processing result based on the access destination address of each merge-destination instruction, and encapsulating the merge processing result in a set instruction format to obtain the merge instruction.

[0016] Optionally, the method further comprises: acquiring a data amount to be accessed corresponding to each of the merge-planned commands; and adding the amount of data to be accessed corresponding to each of the merge-planned commands to the merge processing result.

[0017] A second aspect of an embodiment of the present disclosure provides a data access apparatus applied to an electronic device, the apparatus including: an instruction acquisition module, an instruction merging module, and an instruction sending module; the instruction acquisition module is configured to acquire a plurality of instructions to be processed, each of the instructions to be processed including an address to be accessed; an instruction merging module configured to determine a to-be-merged instruction in the plurality of to-be-processed instructions, and to merge the to-be-merged instructions to obtain a merged instruction; The command sending module is configured to perform data access based on the address to be accessed corresponding to the merge command.

[0018] Optionally, said instruction merge module specifically: obtaining a first instruction, the first instruction being one of the instructions to be processed; a second instruction is acquired by traversing instructions to be processed other than the first instruction, and an access planned address of the second instruction and an access planned address of the first instruction are indirectly consecutive, and the access planned address of the second instruction is not consecutive to the access planned address of the first instruction via an access planned address of another instruction to be processed; The processor is configured to determine the second instruction and the first instruction as the to-be-merged instructions in response to the second instruction and the first instruction satisfying a first predetermined merging condition.

[0019] Optionally, said instruction merge module further comprises: Obtain a storage interval and / or obtain a current total access data amount, wherein the storage interval indicates a distance between the access planned address of the first instruction and the access planned address of the second instruction, and wherein the current total access data amount indicates a sum of the access planned data amounts corresponding to all merge planned instructions; When the storage interval is smaller than a first predetermined threshold and / or the total amount of currently accessed data is smaller than a second predetermined threshold, the second instruction and the first instruction are determined to be the instructions to be merged.

[0020] Optionally, said instruction merge module further comprises: When the total amount of currently accessed data is equal to or greater than the second predetermined threshold, the traversal of instructions to be processed other than the first instruction is stopped.

[0021] Optionally, said instruction merge module further comprises: Obtain a first time length; obtain a first time threshold corresponding to the first command, the first time length indicating a time length from a determination of obtaining the first command to a current time; responsive to the first length of time being less than a first time threshold, continuing to traverse instructions to be processed other than the first instruction; The method is configured to stop traversal of instructions to be processed other than the first instruction in response to the first length of time being equal to or greater than the first time threshold.

[0022] Optionally, said instruction merge module further comprises: obtaining a difference between the access address of the second instruction and the access address of the first instruction, the access address being a logical address; Obtain the size of a given storage unit; The storage interval is acquired based on the difference value and the size of the predetermined storage unit.

[0023] Optionally, said instruction merge module specifically: obtaining a first instruction, the first instruction being one of the instructions to be processed; traversing instructions to be processed other than the first instruction; In response to the currently traversed instruction to be processed and the first instruction satisfying a second predetermined merging condition, the currently traversed instruction to be processed and the first instruction are configured to determine the currently traversed instruction to be processed and the first instruction as the instructions to be merged.

[0024] Optionally, said instruction merge module further comprises: storing the command to be processed in a predetermined command queue; In the predetermined instruction queue, a second time length corresponding to the instruction to be processed is greater than a second time threshold, the second time length indicating a storage time length for the instruction to be processed in the predetermined instruction queue; The instruction to be processed is positioned at a set position in a predetermined instruction queue, and the instruction to be processed that satisfies at least one of the conditions that the set position is the first position in the queue or the last position in the queue is configured to be the first instruction.

[0025] Optionally, said instruction merge module specifically: The merge processing result is generated based on the access destination address of each merge destination instruction, and the merge processing result is encapsulated in a set instruction format to obtain the merge instruction.

[0026] Optionally, said instruction merge module further comprises: Obtaining a data amount to be accessed corresponding to each of the merge-planned commands; The amount of data to be accessed corresponding to each of the merge instructions is added to the merge processing result.

[0027] A third aspect of an embodiment of the present disclosure provides a temporary computer-readable storage medium having stored thereon a computer program that, when executed by a processor, implements the steps of the data access method described in any one of the first aspects above.

[0028] A fourth aspect of an embodiment of the present disclosure provides a data access device including a processor and a memory for storing instructions executable by the processor, The processor: Acquire a plurality of instructions to be processed, each of the instructions to be processed including an address to be accessed; determining a merge command among the plurality of process commands, and performing a merge process on the merge command to obtain a merge command; Data access is performed based on the address to be accessed corresponding to the merge instruction.

[0029] A fifth aspect of an embodiment of the present disclosure provides a computer program product including a computer program that, when executed by a processor, implements the steps of the data access method according to any one of the first aspects.

[0030] The technical solutions provided by the embodiments of the present disclosure achieve the following beneficial effects: when obtaining multiple to-be-processed instructions, a to-be-merged instruction among the multiple to-be-processed instructions is determined, i.e., at least two to-be-processed instructions that can be merged are determined, and the determined to-be-merged instructions are merged to obtain a merge instruction, thereby reducing the number of instructions and thereby reducing instruction overhead; by performing data access based on the to-be-accessed address corresponding to the merge instruction, multiple to-be-accessed addresses can be accessed based on one instruction, i.e., multiple to-be-processed instructions can be processed simultaneously, improving the efficiency of instruction processing and thereby effectively improving the performance of electronic devices.

[0031] It should be noted that the above general description and the following detailed description are merely exemplary and explanatory and are not intended to limit the present disclosure. [Brief explanation of the drawings]

[0032] The drawings herein are incorporated into the specification, illustrate embodiments consistent with the present disclosure, and together with the specification serve to explain the principles of the present disclosure. [Figure 1] FIG. 1 is a schematic diagram illustrating a location layout of a file in an embodiment of the present disclosure. [Figure 2] 1 is a flowchart of a data access method according to an embodiment of the present disclosure. [Figure 3] FIG. 1 is a schematic diagram of an ordered read / write process in an embodiment of the present disclosure. [Figure 4] 10 is a flowchart of another data access method according to an embodiment of the present disclosure. [Figure 5] FIG. 2 is a schematic diagram of a random read / write process in an embodiment of the present disclosure. [Figure 6]FIG. 10 is a schematic diagram of another random read / write process in an embodiment of the present disclosure. [Figure 7] FIG. 1 is a block diagram of a data access device according to an embodiment of the present disclosure. [Figure 8] FIG. 1 is a configuration diagram of a data access device according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0033] Reference will now be made in detail to exemplary embodiments illustrated in the drawings. When the following description refers to the drawings, identical numerals in different drawings represent identical or similar elements unless otherwise stated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present disclosure. To the contrary, they are merely examples of apparatus and methods consistent with certain aspects of the present disclosure, as detailed in the appended claims.

[0034] The terms used in this disclosure are for the purpose of describing particular embodiments only and are not intended to limit the disclosure. As used in this disclosure and the appended claims, the singular forms "a," "the," and "the" are also intended to include the plural form unless the context clearly dictates otherwise. The term "and / or," as used herein, should also be understood to mean and include any and all possible combinations of one or more of the associated listed items.

[0035] In this disclosure, terms such as first, second, and third may be used to describe various pieces of information, but it should be understood that such information should not be limited to these terms. These terms are used only to distinguish between the same types of information. For example, first information may be referred to as second information, and similarly, second information may be referred to as first information, without departing from the scope of this disclosure. Depending on the context, the word "when" as used herein may be interpreted as "when" or "when" or "responsive to a determination."

[0036] In the prior art, after obtaining a processing instruction generated by a process on an electronic device, the processing instruction is sent to a memory based on the JEDEC protocol, and the processing instruction is processed in the memory, that is, the access address of the processing instruction is accessed.

[0037] Here, a memory based on the JEDEC protocol, i.e., a memory chip, is accessed in units of blocks. As shown in Figure 1, the data storage unit in the file system of an electronic device (for example, F2FS (Flash Friendly File System)) is 4 KB, the size of file 1 is 24 KB, and the data of file 1 can be stored at locations LBA1 to LBA6, addresses 1 to 6, respectively.

[0038] Optionally, the Nand flash memory based on the JEDEC protocol includes an EMMC (Embedded Multi Media Card) storage chip, a UFS (Universal Flash Storage) storage chip.

[0039] However, when there are multiple instructions to be processed, the instructions to be processed must be sent one by one to the memory based on the JEDEC protocol, which increases instruction overhead, i.e., increases the resources required to send related instructions to the memory. The memory based on the JEDEC protocol can only process the instructions to be processed one by one, which reduces the efficiency of instruction processing and affects the performance of the electronic device.

[0040] To address the above-mentioned problems, an embodiment of the present disclosure proposes a data access method that acquires multiple processing instructions, merges the processing instructions, and obtains a merged instruction containing the access addresses of the multiple processing instructions. The merged instruction is sent to a JEDEC protocol-based memory to reduce instruction overhead. The JEDEC protocol-based memory accesses the multiple access addresses in the merged instruction, enabling simultaneous processing of the processing instructions and improving instruction processing efficiency, thereby improving the performance of the electronic device, i.e., improving the IO (Input / Output) performance of the entire system.

[0041] As shown in FIG. 2, FIG. 2 is a flowchart of a data access method in an exemplary embodiment of the present disclosure, which is applied to an electronic device, specifically, which is applied to a processor of the electronic device, and which includes the following steps:

[0042] In S201, a plurality of processing-scheduled instructions are obtained, where each processing-scheduled instruction includes an access-scheduled address.

[0043] In S202, a merge-scheduled command is determined from the plurality of process-scheduled commands, and the merge-scheduled command is subjected to a merge process to obtain a merge command.

[0044] In an embodiment of the present disclosure, an electronic device supports multitasking parallel processing, and during execution, each process of the electronic device simultaneously generates various data read / write operation requests, i.e., instructions to be processed. After obtaining the instructions to be processed generated by the processes, i.e., a plurality of instructions to be processed, a mergeable instruction is determined from the plurality of instructions to be processed, i.e., at least two instructions to be processed are defined as an instruction to be merged, and the instructions to be merged are merged, i.e., the plurality of instructions are merged into one instruction, and the merged instruction is defined as a merge instruction, and the merge instruction includes a plurality of addresses to be accessed, and the plurality of addresses to be accessed includes the addresses to be accessed of each of the instructions to be merged.

[0045] Here, the processing command includes a target access address, i.e., each processing command has a corresponding target access address, which indicates the data address to be accessed, i.e., the address where data needs to be read or written.

[0046] Optionally, the address to be accessed is a logical address.

[0047] In S203, data access is performed based on the access destination address corresponding to the merge command.

[0048] In this embodiment, data access is performed based on the access destination address of each merge instruction in the merge instruction, that is, by accessing the access destination address of each merge instruction in the merge instruction and performing the corresponding data read / write operation, it is possible to access the access destination addresses of multiple processing destination instructions using a single instruction, and there is no need to access multiple access destination addresses based on multiple instructions, which can realize simultaneous processing of instructions and improve the efficiency of data access.

[0049] Optionally, when data access is performed based on a merge instruction, the memory can be used to perform the data access, i.e., by sending the merge instruction to the target memory, the target memory can perform the data access based on the access address to be accessed of each merge instruction in the merge instruction.

[0050] Specifically, after obtaining the merge command, the merge command is sent to the target memory, which executes the merge command, i.e., analyzes the merge command, obtains the addresses to be accessed in the merge command, accesses the addresses to be accessed in the merge command, and performs the corresponding data read / write operations, thereby improving the efficiency of command processing, fully utilizing the concurrent processing capability of the target memory, and enhancing the concurrency of the target memory.

[0051] Here, the target memory includes a memory based on the JEDEC protocol, such as a Nand flash. Specifically, the target memory is an EMMC (Embedded Multi Media Card) memory chip, a UFS (Universal Flash Storage) memory chip, etc.

[0052] Optionally, the electronic device includes a product including the target memory, such as a mobile terminal (e.g., a mobile phone, a tablet, etc.), a terminal device (e.g., a computer, a server), etc.

[0053] The target memory access method includes random access (i.e., random read / write), which refers to discrete random address access to the memory. If the target memory is a NAND flash memory, the process generates instructions to be processed and then caches the instructions. If the cached instructions to be processed do not have consecutive addresses, it indicates that a random access method is required. This requires sending the instructions to be processed separately to the NAND flash memory, i.e., accessing the NAND flash memory separately. This increases instruction overhead, and the NAND flash memory can only process one instruction each time. This undermines the concurrent processing capability of the NAND flash memory and impacts the system's random access throughput. For example, as shown in Figure 3, process A generates instruction 1, whose address to be accessed is address 1 (i.e., address 1 in Figure 1). process B generates instruction 2, whose address to be accessed is address 3 (i.e., address 3 in Figure 1). process C generates instruction 3, whose address to be accessed is address 5 (i.e., address 5 in Figure 1). Processes A, B, and C access data at logical addresses 1, 3, and 5 in file 1 in Figure 1. Address 1, address 3, and address 5 are not consecutive, so they cannot be merged and instructions 1, 2, and 3 must be sent to the NAND flash memory, respectively. In this disclosure, by performing a merge process on instructions to be processed that have non-consecutive access addresses, multiple instructions to be processed are merged to obtain a single instruction, i.e., a merge instruction, which reduces instruction overhead. The merge instruction is sent to the NAND flash memory, allowing the NAND flash memory to access multiple addresses to be accessed at once, thereby improving instruction processing efficiency.

[0054] From the above description, when multiple instructions to be processed are obtained, a merge instruction from the multiple instructions to be processed is determined, i.e., at least two instructions to be processed that can be merged are determined, and the determined merge instruction is merged to obtain a merge instruction, thereby reducing the number of instructions and reducing instruction overhead. Data access is performed based on the access address corresponding to the merge instruction, and one instruction can be used to access the access addresses of multiple instructions to be processed, thereby improving the efficiency of simultaneous instruction processing and instruction processing, and thereby effectively improving the performance of the electronic device.

[0055] As shown in Figure 4, Figure 4 is a flowchart showing another data access method in an embodiment of the present disclosure. In addition to the embodiment of Figure 2, when performing random access, non-contiguous instructions of access addresses can be merged as shown in Figure 4. This process will be described below in relation to a specific embodiment, and the method includes the following steps:

[0056] In S401, a plurality of processing-scheduled instructions are obtained, where each processing-scheduled instruction includes an access-scheduled address.

[0057] In S402, a first command is obtained, where the first command is one of the commands to be processed.

[0058] In the embodiment of the present disclosure, one processing-scheduled instruction is selected from the acquired processing-scheduled instructions, and the selected processing-scheduled instruction is set as the first instruction.

[0059] Optionally, to improve data access efficiency, after obtaining the instructions to be processed, the instructions to be processed can be stored in a predetermined instruction queue to perform instruction caching, and to facilitate merging of instructions to be processed. One instruction to be processed is selected as a first instruction from the predetermined instruction queue that stores the instructions to be processed, i.e., the first instruction is determined. Here, the process of determining the first instruction specifically involves storing the instructions to be processed in the predetermined instruction queue. An instruction to be processed in the predetermined instruction queue that satisfies at least one of the following conditions is determined as the first instruction: A second time length corresponding to the instruction to be processed is greater than a second time threshold. Here, the second time length indicates the storage time of the instruction to be processed in the predetermined instruction queue. The instruction to be processed is located at a set position in the predetermined instruction queue. Here, the set position is the first position of the queue or the last position of the queue.

[0060] The instructions to be processed in the predetermined instruction queue may be arranged based on a predetermined address sorting rule, which may include a rule in which addresses are ordered from large to small (i.e., the access destination addresses of the access instructions in the predetermined instruction queue are ordered from large to small), a rule in which addresses are ordered from small to large (i.e., the access destination addresses of the access instructions in the predetermined instruction queue are ordered from small to large), etc.

[0061] Optionally, when there are a plurality of instructions to be processed that satisfy the condition, the instruction to be processed that has the longest second time length can be determined as the first instruction, and the second time length indicates the length of time for which the instructions to be processed are stored in a predetermined instruction queue. Here, the logical addresses are named sequentially, for example, there are 1000 memory blocks in the target memory, and the 1000 memory blocks are named 1 to 1000, and the corresponding logical addresses are 1 to 1000. Since the addresses to be accessed are logical addresses, the addresses to be accessed can be sorted based on the size of the addresses to be accessed, and the instructions to be processed can be sorted based on the order of the addresses to be accessed.

[0062] Optionally, the set position may be other positions, which are not limited here.

[0063] Optionally, the condition for determining the first instruction from the predetermined instruction queue may be other conditions, such as the second length of time corresponding to the instruction to be processed being the longest, i.e., the instruction to be processed that has the longest storage time in the predetermined instruction queue may be the first instruction.

[0064] Optionally, after obtaining the command to be processed, correlation processing is performed on the command to be processed (for example, determining whether the command format is in accordance with specifications, whether memory is available, etc.), and the processed command to be processed is stored in a predetermined command queue.

[0065] In S403, a second instruction is obtained by traversing instructions to be processed other than the first instruction, where the access address of the second instruction and the access address of the first instruction are indirectly consecutive, and the access address of the second instruction is not consecutive to the access address of the first instruction via the access address of the other instructions to be processed.

[0066] In an embodiment of the present disclosure, instructions to be processed other than the first instruction in a predetermined instruction queue are traversed to determine whether a second instruction whose address is not consecutive to that of the first instruction exists among the other instructions to be processed. If it is determined that a second instruction exists, instructions to be merged are determined based on the second instruction, i.e., the first instruction and the second instruction are determined as instructions to be merged. For example, the first instruction is an instruction located at the first position in the predetermined instruction queue, and instructions located at other positions in the predetermined instruction queue are traversed to determine whether a second instruction exists among the instructions located at other positions in the predetermined instruction queue.

[0067] Here, the access planned address of the second instruction and the access planned address of the first instruction are indirectly consecutive, and the access planned address of the second instruction is not consecutive to the access planned address of the first instruction via the access planned address of another processing planned instruction.

[0068] Here, "indirectly consecutive" indicates that the access address of the second instruction is consecutive to the access address of the first instruction via another logical address, i.e., the access address of the second instruction is not consecutive to the access address of the first instruction. For example, if the access address of the currently traversed instruction to be processed is 4 and the access address of the first instruction is 1, and the access address of the currently traversed instruction to be processed needs to be consecutive to the access address of the first instruction via another logical address (i.e., logical addresses 2 and 3), it is determined that the access address of the currently traversed instruction to be processed and the access address of the first instruction are indirectly consecutive.

[0069] Here, if the access planned address of the currently traversed instruction to be processed is 2 and the access planned address of the first instruction is 1, it is determined that the access planned address of the currently traversed instruction to be processed and the access planned address of the first instruction are consecutive.

[0070] In an embodiment of the present disclosure, in the process of traversing instructions to be processed other than the first instruction, it is determined whether the access address of the currently traversed instruction to be processed and the access address of the first instruction are indirectly consecutive. If the access address of the currently traversed instruction to be processed and the access address of the first instruction are not indirectly consecutive, it indicates that the access address of the currently traversed instruction to be processed and the access address of the first instruction are consecutive, and the currently traversed instruction to be processed is a sequential access instruction corresponding to the first instruction, i.e., not the second instruction. If the scheduled access address of the currently traversed instruction to be processed and the scheduled access address of the first instruction are indirectly consecutive, determine whether the scheduled access address of the currently traversed instruction to be processed is consecutive to the scheduled access address of the first instruction via the scheduled access addresses of the other instructions to be processed. If the scheduled access address of the currently traversed instruction to be processed is consecutive to the scheduled access address of the first instruction via the scheduled access addresses of the other instructions to be processed, determine that the currently traversed instruction to be processed is not the second instruction. If the scheduled access address of the currently traversed instruction to be processed is not consecutive to the scheduled access address of the first instruction via the scheduled access addresses of the other instructions to be processed, determine that the currently traversed instruction to be processed is the second instruction. For example, the currently traversed instructions include instruction 1, instruction 2, and instruction 3. The scheduled access address of instruction 1 is 1, the scheduled access address of instruction 2 is 2, and the scheduled access address of instruction 3 is 3. Instruction 3 is the currently traversed instruction to be processed, and instruction 1 is the first instruction. It is determined that the access address of instruction 3 and the access address of instruction 1 are not consecutive, i.e., they are indirectly consecutive, and then it is determined whether the access address of instruction 3 is consecutive to the access address of instruction 1 via the access address of another instruction to be processed. Since the access address of instruction 3 is consecutive to the access address of instruction 1 via the access address of instruction 2, it is determined that instruction 3 is not the second instruction.

[0071] Optionally, when the to-be-processed instructions are arranged according to a predetermined address sorting rule, in the process of traversing the to-be-processed instructions other than the first instruction, determine whether the to-be-accessed address of the currently traversed to-be-processed instruction and the to-be-accessed address of the first instruction are consecutive; if the to-be-accessed address of the currently traversed to-be-processed instruction and the to-be-accessed address of the first instruction are consecutive, it determines that the currently traversed to-be-processed instruction is a sequential access instruction corresponding to the first instruction and not the second instruction; if the to-be-accessed address of the currently traversed to-be-processed instruction and the to-be-accessed address of the first instruction are not consecutive, it continues to determine whether the to-be-accessed address corresponding to the currently traversed to-be-processed instruction and the to-be-accessed address of the to-be-processed instruction traversed immediately before are consecutive. If the access planned address corresponding to the currently traversed processing instruction is continuous with the access planned address of the immediately preceding processing instruction, if the access planned address of the immediately preceding processing instruction is continuous with the access planned address of the first instruction, or if the access planned address of the first instruction is continuous via the access planned address of the traversed processing instruction, it is determined that the currently traversed processing instruction is a sequential access data instruction corresponding to the first instruction and not the second instruction, and if the access planned address corresponding to the currently traversed processing instruction is not continuous with the access planned address of the immediately preceding processing instruction, it is determined that the currently traversed processing instruction is the second instruction.

[0072] Optionally, the access method corresponding to the target memory also includes ordered access (i.e., sequential read / write). Here, ordered access refers to consecutive address access to the memory, and random read / write refers to discrete and random address access to the memory. If it is determined that none of the instructions to be processed other than the first instruction in the predetermined instruction queue is the second instruction, it is declared that all of the other instructions to be processed are ordered access instructions of the first instruction, that is, it is declared that the access addresses of the other instructions to be processed and the access addresses of the first instruction are sequentially accessible. According to the ordered access rule, the first instruction and the instructions to be processed whose access addresses are consecutive to the access addresses of the first instruction are determined as merged instructions, and the merged instructions are merged to obtain a merged instruction. Data access is performed based on the access addresses of each merged instruction in the merged instructions.

[0073] Here, the order access rule can be defined based on actual needs, for example, all or some of the processing-to-be instructions other than the first instruction can be the merge-to-be instructions.

[0074] Specifically, to improve data read and write efficiency, instructions to be processed generated by each process can be cached. For example, if the target memory is a NAND flash memory, if the addresses to be accessed in the cached instructions are consecutive addresses, the cached instructions can be declared sequentially accessible. The consecutive addresses, i.e., the instructions to be processed, can be merged, and the NAND flash memory can access the addresses in order based on the merged instructions to be processed, i.e., the merged addresses. This maximizes the use of a small number of instructions, ensures that the addresses accessed by each instruction and the preceding and following instructions are consecutive, improves memory processing concurrency, and reduces instruction overhead. For example, as shown in Figure 5, process A generates instruction 1, and the address to be accessed in instruction 1 is address 1 (i.e., address 1 in Figure 1); process B generates instruction 2, and the address to be accessed in instruction 2 is address 2 (i.e., address 2 in Figure 1); and process C generates instruction 3, and the address to be accessed in instruction 3 is address 3 (i.e., address 3 in Figure 1). Processes A, B, and C access data at logical addresses 1, 2, and 3 of file 1 in Figure 1. Address 1, address 2, and address 3 are adjacent and consecutive, so instructions 1, 2, and 3 are merged to obtain an instruction including addresses 1, 2, and 3, i.e., request A, and this request A is sent to the NAND flash memory, which can then access the data in order based on request A.

[0075] In S404, in response to the second instruction and the first instruction satisfying a first predetermined merging condition, the second instruction and the first instruction are determined as instructions to be merged.

[0076] In the embodiment of the present disclosure, if it is determined that the currently traversed processing instruction is the second instruction, it continues to determine whether the second instruction is a to-be-merged instruction, i.e., whether the second instruction and the first instruction satisfy a first predetermined merging condition. If the second instruction and the first instruction satisfy the first predetermined merging condition, it indicates that the second instruction, i.e., the currently traversed processing instruction, and the first instruction can be merged, i.e., can be accessed simultaneously, and the second instruction and the first instruction are to-be-merged instructions. It continues to traverse processing instructions other than the first instruction, i.e., the next processing instruction other than the first instruction, and determines whether the next processing instruction is the second instruction.

[0077] In response to the second instruction and the first instruction not satisfying the first predetermined merging condition, continuing to traverse instructions to be processed other than the first instruction to determine whether the next instruction to be processed is the second instruction.

[0078] Optionally, when continuing to traverse instructions to be processed other than the first instruction, it is necessary to determine whether the cache time of the first instruction exceeds the time available to wait for execution of the first instruction, i.e., obtain a first time length, and obtain a first time threshold corresponding to the first instruction. Here, the first time length indicates the time length from the determination of retrieval of the first instruction to the current time. In response to the first time length being less than the first time threshold, indicating that the time available to wait for execution of the instruction, i.e., the time available for the instruction to be cached, has not yet been exceeded, and to continue traversing instructions to be processed other than the first instruction. In response to the first time length being equal to or greater than the first time threshold, indicating that the time available to wait for execution of the instruction, i.e., the time available for the instruction to be cached, has been exceeded, and to stop traversing instructions to be processed other than the first instruction, and to merge the traversed and determined instructions to be merged.

[0079] Here, the first time threshold indicates an upper limit of the latency of instruction execution, which can be set based on the real-time requirements of an application associated with the process, and represents the upper limit of the latency of instruction execution, i.e., the maximum time that an instruction can be cached.

[0080] Specifically, since different processes have different real-time requirements, the first time threshold can be determined based on the process corresponding to the first command. That is, when the first time threshold corresponding to the first command is obtained, the target process corresponding to the first command, i.e., the process that generates the first command, can be obtained, and the process type corresponding to the target process (e.g., video application type, notepad application type) can be determined. The time threshold corresponding to the process type is set as the first time threshold corresponding to the first command.

[0081] Optionally, determining the second instruction and the first instruction as instructions to be merged in response to the second instruction and the first instruction satisfying a first predetermined merging condition comprises: The method includes obtaining a storage interval and / or a current total access data amount, where the storage interval indicates a distance between a scheduled access address of the first instruction and a scheduled access address of the second instruction, and the current total access data amount indicates a sum of scheduled access data amounts corresponding to all determined instructions to be merged.

[0082] If the storage interval is smaller than a first predetermined threshold and / or the total amount of currently accessed data is smaller than a second predetermined threshold, it is determined that the second instruction and the first instruction are to-be-merged instructions.

[0083] For example, the first predetermined merging condition includes a storage interval that is less than a first predetermined threshold. The storage interval is obtained. It is determined whether the storage interval is less than the first predetermined threshold. In response to the storage interval being less than the first predetermined threshold, it indicates that the currently traversed instructions to be processed are accessed simultaneously, i.e., it is determined that the second instruction and the first instruction are instructions to be merged. In response to the storage interval being equal to or greater than the first predetermined threshold, it indicates that the currently traversed instructions to be processed cannot be accessed simultaneously, and it is determined that the second instruction is not an instruction to be merged and cannot be merged with the first instruction.

[0084] For example, the first predetermined merge condition is that the total amount of currently accessed data is less than a second predetermined threshold, and the current total amount of accessed data is obtained. Whether the current total amount of accessed data is less than the second predetermined threshold is determined. In response to the current total amount of accessed data being less than the second predetermined threshold, it indicates that the currently traversed instructions to be processed can be accessed simultaneously, and the second instruction and the first instruction are determined to be instructions to be merged. In response to the current total amount of accessed data being equal to or greater than the second predetermined threshold, it indicates that the currently traversed instructions to be processed cannot be accessed simultaneously, and the second instruction is determined not to be an instruction to be merged.

[0085] For example, if the first predetermined merge condition includes that the storage interval is smaller than a first predetermined threshold and the total amount of currently accessed data is smaller than a second predetermined threshold, the storage interval and the total amount of currently accessed data are obtained. It is determined whether the storage interval is smaller than the first predetermined threshold and whether the total amount of currently accessed data is smaller than a second predetermined threshold. In response to the storage interval being smaller than the first predetermined threshold and the total amount of currently accessed data being smaller than the second predetermined threshold, it indicates that the currently traversed processing-to-be instructions can be accessed simultaneously, and a second instruction is obtained, and the second instruction and the first instruction are determined to be instructions to be merged. In response to the storage interval being equal to or greater than the first predetermined threshold and / or the total amount of currently accessed data being equal to or greater than the second predetermined threshold, it indicates that the currently traversed processing-to-be instructions cannot be accessed simultaneously, and the second instruction is determined to be not an instruction to be merged.

[0086] Here, the first predetermined threshold indicates the upper limit of the distance of the merged address, and the merged address represents the difference between the two merged logical addresses. The first predetermined threshold is determined based on the cache size in the memory, so that data for each access can be processed simultaneously by the target memory at one time. Specifically, the first predetermined threshold can be provided by the corresponding vendor of the target memory. For example, the first predetermined threshold may be 300M, indicating that the target memory can cache 300M of data at one time, thereby allowing the corresponding address to be accessed from the cached data.

[0087] Here, the second predetermined threshold indicates the upper limit of the amount of data that can be accessed at one time, i.e., the maximum amount of data that can be accessed simultaneously at one time. The second predetermined threshold should refer to the hardware support of the target memory and is provided by the vendor corresponding to the target memory. The second predetermined threshold is, for example, 128K.

[0088] Optionally, before obtaining the storage interval, it is necessary to calculate the storage interval, which is calculated by obtaining a difference between the access address of the second instruction and the access address of the first instruction. Here, the access address is a logical address. The size of the predetermined storage unit is obtained. The difference value and the size of the predetermined storage unit are multiplied to obtain the storage interval. For example, if the access address of the second instruction is 3, the access address of the first instruction is 1, and the size of the predetermined storage unit is 4KB, the storage interval is (3-1)*4KB=8KB.

[0089] Here, the target memory is accessed in units of blocks, that is, storage blocks, so the size of this predetermined storage unit, that is, the size of a storage block, is, for example, 4 KB.

[0090] Optionally, before obtaining the current total access data amount, it is necessary to calculate the current total access data amount, which is calculated by adding up the access-planned data amounts corresponding to the determined merge-planned instructions (i.e., the first instruction and the second instruction) to obtain the current total access data amount.

[0091] Here, the amount of data to be accessed represents the address length corresponding to the address to be accessed, which can represent the size of the data that needs to be accessed. For example, 24 KB of data can be written from the address to be accessed, and this 24 KB can be the amount of data to be accessed. Of course, the amount of data to be accessed can also represent an address offset, and it is only necessary to determine the amount of data that needs to be accessed through this amount of data to be accessed.

[0092] Here, the amount of data to be accessed may be obtained from the processing schedule command, i.e., the processing schedule command may include the amount of data to be accessed, or may be obtained independently, and this is not limited here.

[0093] For example, the first instruction is instruction 1, and the instructions to be processed other than the first instruction include instruction 2 and instruction 3. After determining that instruction 2 is the instruction to be merged, it is determined whether instruction 3 is the second instruction. If instruction 3 is the second instruction, the storage interval is calculated, and the current total amount of data to be accessed is calculated. When calculating the current total amount of data to be accessed, the sum of the amounts of data to be accessed corresponding to the determined instructions to be merged, i.e., the sum of the amount of data to be accessed corresponding to instruction 2 and the amount of data to be accessed corresponding to instruction 1, is calculated to obtain the current total amount of data to be accessed.

[0094] Optionally, when merging the first instruction and the second instruction that satisfy the first predetermined merge condition, only the first instruction and the second instruction that satisfy the first predetermined merge condition may be merged, or an in-order access instruction between the first instruction and the second instruction that satisfy the first predetermined merge condition may be merged. Thus, the determined instructions to be merged also include the merged in-order access instruction.

[0095] For example, the first instruction is instruction 1, and the other to-be-processed instructions include instruction 2 and instruction 3, where the address to be accessed in instruction 1 is address 1 in FIG. 1, the address to be accessed in instruction 2 is address 2 in FIG. 1, and the address to be accessed in instruction 3 is address 4 in FIG. 1. By traversing the other to-be-processed instructions, the currently traversed to-be-processed instruction is instruction 2, and it is determined that instruction 2 is the sequential access instruction corresponding to instruction 1, i.e., the address to be accessed in instruction 2 is consecutive to instruction 1, and the next to-be-processed instruction, i.e., instruction 3, is traversed and it is determined that instruction 3 is the second instruction. In the process of calculating the current total access data amount, the address to be accessed in instruction 2 is between the address to be accessed in instruction 1 and the address to be accessed in instruction 3, so the determined merge-to-be-processed instructions include instruction 2 and instruction 1, and the current total access data amount is the sum of the amount of data to be accessed corresponding to instruction 2 and the amount of data to be accessed corresponding to instruction 1.

[0096] Optionally, if the current total access data amount is equal to or greater than a second predetermined threshold, this indicates that the amount of access data required to perform one access to the target memory based on the determined merge-scheduled instructions has reached an upper limit, so instructions are merged, i.e., there is no need to determine merge-scheduled instructions, and traversal of processing-scheduled instructions other than the first instruction is stopped.

[0097] Optionally, when determining instructions to be merged from the instructions to be processed, a first instruction can be obtained, where the first instruction is any instruction of the instructions to be processed, and instructions to be processed other than the first instruction are traversed. It is determined whether the currently traversed instruction to be processed and the first instruction satisfy a second predetermined merge condition, and in response to the currently traversed instruction to be processed and the first instruction satisfying the second predetermined merge condition, the first instruction and the currently traversed instruction to be processed are determined as instructions to be merged.

[0098] Here, the process of determining whether the first command and the currently traversed command to be processed satisfy the second predetermined merge condition is similar to the process of determining whether the first command and the second command satisfy the first predetermined merge condition described above, and therefore, the description thereof will be omitted here.

[0099] In S405, the commands to be merged are subjected to a merge process to obtain a merge command. In the embodiment of the present disclosure, a merge processing result is generated based on the access destination address of each merge destination instruction, and the merge processing result is encapsulated in a set instruction format to obtain a merge instruction.

[0100] In the embodiment of the present disclosure, after determining the instructions to be merged, a merge processing result is generated based on the access addresses of each instruction to be merged, the merge processing result including the access addresses of each instruction to be merged, and the merge processing result is encapsulated based on a set instruction format to obtain a merge instruction, thereby realizing the merging of instructions. Here, in the process of generating the merge processing result based on the access planned addresses of each merge-to-be instruction, the merge processing result including the access planned addresses of each merge-to-be instruction can be generated based on a predetermined structure type.

[0101] Here, the predetermined structure type includes a chain table structure type, a tree structure type, an array structure type, etc., which can be set by the user according to actual needs and are not limited here.

[0102] Optionally, the instruction format is a format that is recognizable by the target memory, for example a customized Write Buffer instruction format as specified in JDECE.

[0103] Optionally, the amount of data to be accessed corresponding to the instructions to be merged can be stored in the merge processing result, that is, the amount of data to be accessed corresponding to each instruction to be merged can be obtained separately, and the amount of data to be accessed corresponding to each instruction to be merged can be added to the merge processing result, that is, the merge processing result includes the amount of data to be accessed and the address to be accessed corresponding to the instructions to be merged.

[0104] Taking a specific application scenario as an example, as shown in Figure 6, when processes A, B, and C need to access data at logical addresses 1, 3, and 5 of a file, instructions 1, 2, and 3 are generated. The address to be accessed for instruction 1 is address 1, the amount of data to be accessed corresponding to instruction 1 is the length of address 1, the address to be accessed for instruction 2 is address 3, the amount of data to be accessed corresponding to instruction 2 is the length of address 3, the address to be accessed for instruction 3 is address 5, and the amount of data to be accessed corresponding to instruction 3 is the length of address 5. It is determined that instruction 1 is the first instruction, instructions 2 and 3 are both second instructions, and instructions 2 and 3 are both instructions to be merged. Address 1 and the length of address 1 corresponding to instruction 1, address 3 and the length of address 3 corresponding to instruction 2, and address 5 and the length of address 5 corresponding to instruction 3 are added to list A to realize the merging of the instructions.

[0105] In S406, data access is performed based on the access destination address corresponding to the merge command.

[0106] In this embodiment, after the merge instructions are obtained, the merge instructions are sent to the target memory so that the target memory accesses data based on the access destination addresses of each merge instruction in the merge instructions.

[0107] In the embodiments of the present disclosure, in a random read / write scenario, that is, when it is determined that a second instruction exists in a processing instruction other than a first instruction, the first instruction and the second instruction related to discrete access are merged to obtain a merge instruction, and the merge instruction is stored in the target memory, thereby reducing the number of instructions to be sent to the target memory and reducing the instruction overhead of random read / write; the target memory can then be accessed based on multiple access addresses in the merge instruction, thereby increasing the concurrency of the target memory and further increasing the random read / write throughput of the system, that is, improving the IO performance of the entire system.

[0108] In the embodiment of the present disclosure, when it is determined that there is no second instruction in the processing instructions other than the first instruction, that is, in the sequential read / write scenario, the sequential readable / writable instructions, that is, the processing instructions, are merged to obtain a merge instruction, and this merge instruction is sent to the target memory, reducing the number of instructions sent to the target memory and reducing the instruction overhead of sequential read / write, and the target memory can be accessed sequentially according to the multiple access addresses in this merge instruction, which can increase the concurrency of memory processing data and reduce the instruction overhead of the system, effectively improving the IO performance of the entire system.

[0109] In an embodiment of the present disclosure, after obtaining a target access instruction, the target access instruction is stored in a predetermined instruction queue, and the target access instruction at the first position of the target access instruction queue is designated as the first instruction. The remaining target access instructions in the target access queue are traversed backward. It is determined whether the remaining target access instructions include a second instruction whose target access address is not consecutive. If so, it indicates that a random access is required. The second instruction and the first instruction are merged to obtain a corresponding merge instruction, thereby reducing the number of instructions and the instruction overhead. The merge instruction is stored in the NAND flash memory, allowing the NAND flash memory to perform a single access to each target access address in the merge instruction, thereby realizing simultaneous instruction processing and improving instruction processing efficiency, thereby effectively increasing random access throughput and thus improving the overall system IO performance.

[0110] Although the above-described method embodiments are described as a series of combinations of actions for ease of explanation, the present disclosure is not limited by the order of actions described, as some steps may be performed in other orders or simultaneously, in accordance with the present disclosure.

[0111] Next, those skilled in the art should recognize that the embodiments described herein all belong to alternative embodiments, and the associated operations and modules are not necessarily required for the present disclosure.

[0112] Corresponding to the embodiment of the application function realization method, the present disclosure further provides an embodiment of an application function realization device and a corresponding terminal.

[0113] Referring to the block diagram of the data access device in the exemplary embodiment of FIG. 7, the device includes: an instruction acquisition module 710, an instruction merge module 720, and an instruction transmission module 730; The instruction fetch module 710 is configured to fetch a plurality of instructions to be processed, where each instruction to be processed includes an address to be accessed.

[0114] The instruction merging module 720 is configured to determine a to-be-merged instruction in the plurality of to-be-processed instructions, and merge the to-be-merged instructions to obtain a merge instruction.

[0115] The instruction sending module 730 is configured to perform data access based on the address to be accessed corresponding to the merge instruction.

[0116] Optionally, the instruction merge module 720 specifically: The method is configured to obtain a first instruction, where the first instruction is one of the instructions to be processed.

[0117] A second instruction is obtained by traversing instructions to be processed other than the first instruction, where the access address of the second instruction and the access address of the first instruction are indirectly consecutive, and the access address of the second instruction is not consecutive to the access address of the first instruction via the access address of the other instructions to be processed.

[0118] In response to the second instruction and the first instruction satisfying a first predetermined merge condition, the second instruction and the first instruction are determined as instructions to be merged.

[0119] Optionally, the instruction merge module 720 specifically: The memory interval is configured to acquire a storage interval and / or a total current access data amount, where the storage interval indicates a distance between a scheduled access address of the first instruction and a scheduled access address of the second instruction, and the total current access data amount indicates a sum of the scheduled access data amounts corresponding to all instructions to be merged.

[0120] If the storage interval is smaller than a first predetermined threshold and / or the total amount of currently accessed data is smaller than a second predetermined threshold, the second instruction and the first instruction are determined as instructions to be merged.

[0121] Optionally, the instruction merge module 720 further comprises: Obtain a first length of time and obtain a first time threshold corresponding to the first command, where the first length of time indicates a length of time from a decision to obtain the first command to a current time.

[0122] In response to the first length of time being less than the first time threshold, continuing to traverse instructions to be processed other than the first instruction.

[0123] In response to the first length of time being equal to or greater than a first time threshold, traversal of instructions to be processed other than the first instruction is stopped.

[0124] Optionally, the instruction merge module 720 further comprises: If the total amount of currently accessed data is equal to or greater than a second predetermined threshold, traversal of instructions to be processed other than the first instruction is stopped.

[0125] Optionally, the instruction merge module 720 further comprises: A difference value between the access address of the second instruction and the access address of the first instruction is obtained, where the access address is a logical address.

[0126] Obtain the size of a given storage unit.

[0127] The storage interval is obtained based on the difference value and the size of a predetermined storage unit.

[0128] Optionally, the instruction merge module 720 specifically: A first command is obtained, where the first command is one of the commands to be processed.

[0129] Traverse the instructions to be processed other than the first instruction.

[0130] In response to the currently traversed instruction to be processed and the first instruction satisfying a second predetermined merge condition, the first instruction and the currently traversed instruction to be processed are determined as instructions to be merged.

[0131] Optionally, the instruction merge module 720 further comprises: The instructions to be processed are stored in a predetermined instruction queue.

[0132] In a given instruction queue, a second length of time corresponding to the instruction to be processed is greater than a second time threshold, where the second length of time indicates a storage length in the predetermined instruction queue for the instruction to be processed; An instruction to be processed is located at a set position in a predetermined instruction queue, and the set position satisfies at least one of the conditions of being the first position in the queue or the last position in the queue, and the instruction to be processed is defined as a first instruction.

[0133] Optionally, the instruction merge module 720 specifically: A merge processing result is generated based on the access destination address of each merge destination instruction, and the merge processing result is encapsulated in a set instruction format to obtain a merge instruction.

[0134] Optionally, the instruction merge module 720 further comprises: The amount of data to be accessed corresponding to each command to be merged is acquired.

[0135] The amount of data to be accessed corresponding to each command to be merged is added to the result of the merge process.

[0136] The device embodiments basically correspond to the method embodiments, so please refer to the description of some of the method embodiments for relevant points. The above-mentioned device embodiments are merely examples, and the units described as the above separation means may or may not be physically separated, and the components displayed as units may not be physical units, i.e., may be located in one place or distributed across multiple network units. The objectives of the present disclosure can be achieved by selecting some or all of the modules according to actual needs. Those skilled in the art can understand and implement the present disclosure without any creative effort.

[0137] Accordingly, in one aspect, an embodiment of the present disclosure provides a data access apparatus including a processor and a memory for storing processor-executable instructions, the processor comprising: A plurality of instructions to be processed are obtained, where each instruction to be processed includes an address to be accessed.

[0138] A merge command is determined from the plurality of processing commands, and the merge command is merged to obtain a merge command.

[0139] Data access is performed based on the address to be accessed corresponding to the merge command.

[0140] 8 is a schematic diagram of a data access apparatus 1500 according to an embodiment. For example, the device 800 may be an electronic device, specifically, a mobile phone, a computer, a digital broadcast terminal, a messaging device, a game console, a tablet device, a medical device, a fitness device, a personal digital assistant, a wearable device such as a smart watch, smart glasses, smart handheld devices, or smart running shoes.

[0141] Referring to FIG. 8 , device 800 may include one or more components: a processing component 802, a memory 804, a power component 806, a multimedia component 808, an audio component 810, an input / output (I / O) interface 812, a sensor component 814, and a communication component 816.

[0142] The processing component 802 typically controls the overall operation of the device 800, such as the display, telephone calls, data communications, camera operation, recording operations, etc. The processing component 802 may include one or more processors 820 that execute instructions to complete all or some of the steps of the methods described above. Additionally, the processing component 802 may include one or more modules that facilitate interaction between the processing component 802 and other components. For example, the processing component 802 may include a multimedia module to facilitate interaction between the multimedia component 808 and the processing component 802.

[0143] Memory 804 is configured to store various types of data to support operation on device 800. Examples of this data include instructions for any applications or methods to operate on device 800, contact data, phone book data, messages, images, videos, etc. Memory 804 can be implemented by any type of volatile or non-volatile storage device, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk, optical disk, or a combination thereof.

[0144] The power supply component 806 provides power to the various components of the device 800. The power supply component 806 may include a power management system, one or more power sources, and other components associated with the generation, management, and distribution of power for the device 800.

[0145] The multimedia component 808 includes a screen that provides an output interface between the device 800 and a user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). When the screen includes a touch panel, the screen is implemented as a touchscreen and can receive input signals from a user. The touch panel includes one or more touch sensors for detecting touches, slides, and gestures on the touch panel. The touch sensors can detect not only the boundaries of a touch or slide operation but also the duration and pressure associated with the touch or slide operation. In some embodiments, the multimedia component 808 includes a front camera and / or a rear camera. When the device 800 is in an operating mode, such as a photo mode or a video mode, the front camera and / or the rear camera can receive external multimedia data. Each front camera and rear camera may have a fixed optical lens system or may have a focal length and optical zoom capability.

[0146] The audio component 810 is configured to output and / or input audio signals. For example, the audio component 810 includes a microphone (MIC) configured to receive external audio signals when the device 800 is in an operational mode such as a call mode, a recording mode, a voice recognition mode, etc. The received audio signals may be further stored in the memory 804 or transmitted via the communication component 816. In some embodiments, the audio component 810 further includes a speaker for outputting audio signals.

[0147] The I / O interface 812 provides an interface between the processing component 802 and a peripheral interface module, which can be a keyboard, click wheel, buttons, etc. These buttons include, but are not limited to, a home page button, volume buttons, start button, and lock button.

[0148] The sensor assembly 814 includes one or more sensors for providing status assessment of various aspects of the device 800. For example, the sensor assembly 814 may detect the on / off state of the device 800, the relative position of an assembly, e.g., the display and keypad of the device 800. The sensor assembly 814 may also detect positional changes of the device 800 or one assembly of the device 800, the presence or absence of a user touching the device 800, the orientation or acceleration / deceleration of the device 800, and temperature changes of the device 800. The sensor assembly 814 may include a proximity sensor configured to detect the presence of a nearby object in the absence of physical contact. The sensor component 814 may also include an optical sensor, such as a CMOS or CCD image sensor for use in imaging applications. In some embodiments, the sensor assembly 814 may also include an acceleration sensor, a gyro sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.

[0149] The communication component 816 is configured to facilitate wired or wireless communication between the device 800 and other devices. The device 800 may access a wireless network based on a communication standard such as WiFi, 2G or 3G, 4G LTE, 5G NR, or a combination thereof. In an exemplary embodiment, the communication component 816 receives a broadcast signal or broadcast-related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 816 further includes a near-field communication (NFC) module for facilitating short-range communication. For example, the NFC module may be implemented based on radio frequency identification (RFID) technology, infrared data association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology, and other technologies.

[0150] In an exemplary embodiment, device 800 may be implemented by one or more application specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processors (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to perform the methods described above.

[0151] In an exemplary embodiment, a non-transitory computer-readable storage medium, e.g., memory 804, containing instructions is provided, such that the instructions in the storage medium, when executed by a processor 820 of the device 800, enable the device 800 to perform a data access method, the method comprising: obtaining a plurality of instructions to be processed, each of which includes an address to be accessed; determining a merge-to-be-executed instruction among the plurality of processing-to-be-executed instructions, and performing a merge process on the merge-to-be-executed instructions to obtain a merge instruction; and performing data access based on the address to be accessed corresponding to the merge instruction.

[0152] The non-transitory computer-readable storage medium may be a ROM, a random access memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, and the like.

[0153] In an exemplary embodiment, a computer program product is also provided that includes a computer program that, when executed by a processor, implements the steps of the above-described method.

[0154] Other embodiments of the present disclosure will readily occur to those skilled in the art after considering the specification and practicing the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of the present disclosure in accordance with the general principles of the present disclosure, including common knowledge or customary technical means known in the art but not disclosed herein. The specification and examples are to be considered exemplary only, with the true scope and spirit of the present disclosure being indicated by the following claims.

[0155] It should be understood that the present disclosure is not limited to the exact construction described above and shown in the drawings, but that various modifications and variations are possible without departing from the scope thereof, which is limited only by the appended claims.

Claims

1. A data access method applied to an electronic device, comprising: obtaining a plurality of instructions to be processed, each of the instructions to be processed including an address to be accessed; determining a merge-to-be-executed command among the plurality of process-to-be-executed commands, and performing a merge process on the merge-to-be-executed command to obtain a merge command; performing data access based on an access destination address corresponding to the merge instruction; Determining a merge-to-be-done instruction in the plurality of processing-to-be-done instructions includes: obtaining a first command, the first command being one of the commands to be processed; a second instruction is acquired by traversing instructions to be processed other than the first instruction, and an access planned address of the second instruction and an access planned address of the first instruction are indirectly consecutive, and the access planned address of the second instruction is not consecutive to the access planned address of the first instruction via an access planned address of another instruction to be processed; determining the second instruction and the first instruction as the instructions to be merged in response to the second instruction and the first instruction satisfying a first predetermined merge condition. A data access method comprising:

2. determining the second instruction and the first instruction as the instructions to be merged in response to the second instruction and the first instruction satisfying a first predetermined merge condition; Obtaining a storage interval and / or a current total access data amount, the storage interval indicating a distance between the access planned address of the first instruction and the access planned address of the second instruction, and the current total access data amount indicating a sum of the access planned data amounts corresponding to all merge planned instructions; determining the second instruction and the first instruction as the instructions to be merged when the storage interval is smaller than a first predetermined threshold and / or the total amount of currently accessed data is smaller than a second predetermined threshold.

2. The data access method according to claim 1.

3. The method further comprises: and stopping traversal of instructions to be processed other than the first instruction when the total amount of currently accessed data is equal to or greater than the second predetermined threshold.

3. The data access method according to claim 2.

4. The method further comprises: obtaining a difference between the access address of the second instruction and the access address of the first instruction, and determining that the access address is a logical address; Obtaining a predetermined storage unit size; and acquiring the storage interval based on the difference value and the size of the predetermined storage unit.

3. The data access method according to claim 2.

5. The method further comprises: Obtaining a first length of time and obtaining a first time threshold corresponding to the first command, the first length of time indicating a length of time from a determination of obtaining the first command to a current time; responsive to the first length of time being less than a first time threshold, continuing traversal of instructions to be processed other than the first instruction; and in response to the first length of time being equal to or greater than the first time threshold, stopping traversal of instructions to be processed other than the first instruction.

2. The data access method according to claim 1.

6. The method further comprises: obtaining a first command, the first command being one of the commands to be processed; traversing instructions to be processed other than the first instruction; determining the currently traversed instruction to be processed and the first instruction as the instructions to be merged in response to the currently traversed instruction to be processed and the first instruction satisfying a second predetermined merge condition.

2. The data access method according to claim 1.

7. The method further comprises: storing the command to be processed in a predetermined command queue; In the predetermined instruction queue, and determining, as the first instruction, an instruction to be processed that satisfies at least one of the following conditions: a condition in which a second time length corresponding to the instruction to be processed is greater than a second time threshold, the second time length indicating a storage time length of the instruction to be processed in the predetermined instruction queue; and a condition in which the instruction to be processed is located at a set position in the predetermined instruction queue, the set position being either the first position or the last position of the queue.

7. The data access method according to claim 1, wherein the data access method is a data access method for accessing data from a plurality of storage areas.

8. merging the plurality of instructions to be merged to obtain a merge instruction, generating a merge processing result based on the access destination address of each merge destination instruction, and encapsulating the merge processing result in a set instruction format to obtain the merge instruction; 2. The data access method according to claim 1.

9. The method further comprises: obtaining a data amount to be accessed corresponding to each of the merge-planned commands; and adding the amount of data to be accessed corresponding to each of the merge-planned commands to the merge processing result.

9. The data access method according to claim 8.

10. A data access device including a command acquisition module, a command merge module, and a command transmission module, The instruction acquisition module is configured to acquire a plurality of instructions to be processed, each of the instructions to be processed including an address to be accessed; the instruction merging module is configured to determine a to-be-merged instruction in the plurality of to-be-processed instructions, and to merge the to-be-merged instructions to obtain a merge instruction; the instruction sending module is configured to perform data access based on an access destination address corresponding to the merge instruction; The instruction merge module obtaining a first instruction, the first instruction being any one of the instructions to be processed; a second instruction is acquired by traversing instructions to be processed other than the first instruction, and an access planned address of the second instruction and an access planned address of the first instruction are indirectly consecutive, and the access planned address of the second instruction is not consecutive to the access planned address of the first instruction via an access planned address of another instruction to be processed; configured to determine the second instruction and the first instruction as the to-be-merged instructions in response to the second instruction and the first instruction satisfying a first predetermined merging condition. A data access device comprising:

11. The instruction merge module further comprises: acquiring a storage interval and / or a current total access data amount, the storage interval indicating a distance between the access planned address of the first instruction and the access planned address of the second instruction, and the current total access data amount indicating a sum of the access planned data amounts corresponding to all the merge planned instructions; When the storage interval is smaller than a first predetermined threshold and / or the total amount of currently accessed data is smaller than a second predetermined threshold, the second instruction and the first instruction are determined to be the instructions to be merged.

11. The data access device according to claim 10.

12. A computer program is stored which, when executed by a processor, implements the steps of the data access method according to any one of claims 1 to 6 and 8 to 9. A non-transitory computer-readable storage medium comprising:

13. 1. A data access device including a processor and a memory for storing instructions executable by the processor, The processor: Acquire a plurality of instructions to be processed, each of the instructions to be processed including an address to be accessed; determining a merge command among the plurality of process commands, and performing a merge process on the merge command to obtain a merge command; performing data access based on the access destination address corresponding to the merge instruction; The processor: obtaining a first instruction, the first instruction being any one of the instructions to be processed; a second instruction is acquired by traversing instructions to be processed other than the first instruction, and an access planned address of the second instruction and an access planned address of the first instruction are indirectly consecutive, and the access planned address of the second instruction is not consecutive to the access planned address of the first instruction via an access planned address of another instruction to be processed; configured to determine the second instruction and the first instruction as the to-be-merged instructions in response to the second instruction and the first instruction satisfying a first predetermined merging condition. A data access device comprising:

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