Method for manufacturing a piezoelectric structure that can be used to transfer a piezoelectric layer for a high frequency device, and method for transferring such a piezoelectric layer

Abstract

A method for manufacturing a piezoelectric structure (10, 10'), characterized in that the method comprises the steps of: preparing a substrate (20) made of piezoelectric material; preparing a carrier substrate (100); depositing a dielectric bonding layer (1001) on only one side of the substrate (20) made of piezoelectric material at a temperature of 300°C or less; bonding (1') the substrate (20) made of piezoelectric material to the carrier substrate (100) via the dielectric bonding layer (1001); and a thinning step (2') to form a piezoelectric structure (10, 10') comprising a layer (200) made of piezoelectric material bonded to the carrier substrate (100).

Description

[Technical Field]

[0001] The present invention relates to a method for fabricating a piezoelectric structure that can be used to transfer a piezoelectric layer for a high frequency device, and to a method for transferring such a piezoelectric layer. [Background technology]

[0002] It is a known technique to fabricate radio frequency (RF) devices, such as resonators or filters, on a substrate that includes, successively from its base to its surface, a carrier substrate, typically made of a material such as silicon or sapphire, an intermediate bonding layer, and a piezoelectric layer.

[0003] A surface acoustic wave (SAW) filter typically comprises a piezoelectric layer and two electrodes in the form of two interdigitated metal combs deposited on the surface of the piezoelectric layer. Depending on the operation of the SAW filter, the thickness of the piezoelectric layer can be on the order of tens of nanometers to tens of micrometers. In the latter case, parasitic modes propagate through the thickness of the piezoelectric layer and tend to be reflected at the interface with the underlying carrier substrate. This phenomenon is called "backlash." To avoid these parasitic modes, a known technique is to make the surface of the piezoelectric layer at the interface with the intermediate bonding layer sufficiently rough to reflect the parasitic waves in all directions. Considering the intended operating wavelength of the resonator, the roughness of the rough surface of the piezoelectric layer is very large, on the order of magnitude of the operating wavelength (several micrometers).

[0004] The piezoelectric layer is typically obtained by transferring a thick substrate of piezoelectric material (eg obtained by slicing an ingot) onto a carrier substrate, for example a silicon substrate.

[0005] Transferring the piezoelectric layer entails bonding a thick piezoelectric substrate to a carrier substrate and then thinning the thick piezoelectric substrate so that only a thin piezoelectric layer of the desired thickness for fabricating RF devices remains on the carrier substrate.

[0006] To obtain good adhesion between the piezoelectric substrate and the carrier substrate, a layer of oxide (e.g., silicon oxide SiO2) is generally deposited on each of the two substrates, and the substrates are bonded together via the oxide layer.

[0007] However, since the piezoelectric material and the material of the carrier substrate have very different thermal expansion coefficients, such annealing would result in significant deformation of the assembly.

[0008] On the other hand, depositing an oxide film on a thick piezoelectric substrate causes the substrate to flex significantly, which is incompatible with subsequent processing steps that are designed for flat substrates.

[0009] Finally, as mentioned above, heterostructures cannot be subjected to strengthening annealing due to the different thermal expansion coefficients of the thick piezoelectric substrate and the handle substrate. However, without strengthening annealing, the bond energy between the oxide layers of the two substrates remains so low that the mechanical strength of the donor virtual substrate is insufficient. As a result, fracture of the bonded interface can occur during the thinning step of the thick piezoelectric substrate.

[0010] To ensure good adhesion between the thick piezoelectric substrate and the carrier substrate, especially when the thick piezoelectric substrate has a high level of roughness, current methods require multiple steps, such as depositing multiple oxide layers followed by chemical mechanical polishing (CMP) of the oxide layers, which are deposited alternately on both sides of the thick piezoelectric substrate to avoid significant deflection that would make bonding impossible. Summary of the Invention

[0011] The present invention aims to overcome these limitations of the prior art by proposing a method for manufacturing a piezoelectric structure that can also be used to transfer piezoelectric layers for high frequency devices, and a method for transferring such piezoelectric layers.

[0012] The present invention relates to a method for manufacturing a piezoelectric structure, characterized in that the method includes the steps of providing a substrate made of piezoelectric material, providing a carrier substrate, depositing a dielectric bonding layer on only one side of the substrate made of piezoelectric material at a temperature of 300°C or less, bonding the substrate made of piezoelectric material to the carrier substrate via the dielectric bonding layer, and a thinning step to form a piezoelectric structure comprising a layer made of piezoelectric material bonded to the carrier substrate.

[0013] Therefore, the low stresses induced by depositing the dielectric bonding layer at these low temperatures (below 300°C) ensure sufficient mechanical stability to allow the thinning steps described elsewhere in this specification, as well as sufficient mechanical stability during subsequent packaging steps used during component fabrication.

[0014] In some embodiments, the dielectric bonding layer comprises a layer of silicon oxide deposited by plasma-assisted chemical vapor deposition on a substrate of piezoelectric material.

[0015] In an advantageous embodiment, the bonding step comprises molecular bonding between the dielectric bonding layer and the carrier substrate, or between the dielectric bonding layer and a dielectric bonding layer formed on the carrier substrate.

[0016] In an advantageous embodiment, there is a bond interface strengthening anneal at a temperature below the deposition temperature of said dielectric bonding layer.

[0017] In an advantageous embodiment, the thinning step is carried out at a temperature below the deposition temperature of said dielectric bonding layer.

[0018] In an advantageous embodiment, the substrate made of piezoelectric material has a rough surface designed to reflect high frequencies.

[0019] In an advantageous embodiment, the thickness of the dielectric bonding layer is between 200 nm and 500 nm.

[0020] In an advantageous embodiment, a dielectric bonding layer is provided on the carrier substrate.

[0021] In an advantageous embodiment, the thinning step comprises etching and / or chemical mechanical polishing.

[0022] The present invention also relates to a method for transferring a piezoelectric layer to a final substrate, the method comprising the steps of: preparing a piezoelectric structure obtained by carrying out a manufacturing method according to any one of the previous claims; forming a weakened zone in the layer of piezoelectric material so as to define the extent of the piezoelectric layer to be transferred; preparing a final substrate; forming a preferably dielectric bonding layer on a main surface of the final substrate and / or on the layer of piezoelectric material; bonding the layer of piezoelectric material to the final substrate; and fracturing and separating the piezoelectric structure along the weakened zone at a temperature below the deposition temperature of the dielectric bonding layer.

[0023] In an advantageous embodiment, the weakened zone is formed by implanting atomic species into the layer of piezoelectric material.

[0024] In an advantageous embodiment, the final substrate and the carrier substrate have the same coefficient of expansion.

[0025] Other features and advantages of the present invention will be better understood from the following detailed description when read in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0026] [Figure 1] 1A-1D illustrate a manufacturing process according to one embodiment of the present invention and a substrate according to this embodiment of the present invention. [Figure 2] 5A-5C illustrate a manufacturing process according to another embodiment of the invention and a substrate according to this another embodiment of the invention. [Figure 3] FIG. 1 illustrates a transfer process according to one embodiment of the present invention. [Figure 4] 10A to 10C are diagrams illustrating a transfer process according to another embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0027] To improve clarity of the figures, the layers are not necessarily drawn to scale.

[0028] 1 shows a carrier substrate 100, preferably made of silicon material, onto which a layer 200 of piezoelectric material, preferably made of single-crystal piezoelectric material, more particularly made of lithium tantalate or lithium niobate material, is to be transferred. Other materials may be envisaged for the layer of piezoelectric material 200. The transferred active layer 200 may also comprise a ferroelectric material, for example LiTaO3, LiNbO3, LiAlO3, BaTiO3, PbZrTiO3, KNbO3, BaZrO3, CaTiO3, PbTiO3 or KTaO3.

[0029] The donor substrate containing this active layer can take the form of a standard-sized circular wafer, e.g., 150 mm or 200 mm in diameter. However, the present invention is not limited to these dimensions or shapes. The donor substrate may be obtained from an ingot of ferroelectric material so that the donor substrate has a predetermined crystal orientation, or the donor substrate may comprise a layer of ferroelectric material bonded to a carrier substrate. The crystal orientation of the transferred active layer of ferroelectric material is selected depending on the intended application. For the material LiTaO3, it is customary to select an XY orientation of 30° to 60°, or even 40° to 50°, especially when it is desired to utilize the properties of thin layers for forming SAW filters. For the material LiNbO3, it is customary to select an XY orientation of approximately 128°. However, the present invention is in no way limited to a specific crystal orientation.

[0030] Whatever the crystal orientation of the ferroelectric material of the donor substrate, this step involves, for example, introducing hydrogen and / or helium species (ions and / or atoms) into said donor substrate. This introduction can correspond, for example, to hydrogen implantation, i.e., hydrogen ion bombardment of the plane of the donor substrate. As is known per se, the purpose of the implanted ions is to create a weakened plane that defines, on the face side, a first layer of ferroelectric material to be transferred, and another that forms the remainder of the substrate. The nature, amount and type of implanted species, as well as the implanted ion type, as well as the implantation energy, are chosen depending on the thickness of the layer desired to be transferred and the physicochemical properties of the donor substrate. Thus, in the case of a donor substrate made of LiTaO3, a 1×10 ion beam is used to define a first layer of approximately 10-2000 nm. 16 ~5×10 17 atoms / cm 2 It becomes possible to select the amount of hydrogen to be implanted at an energy of 30 to 300 keV.

[0031] The carrier substrate 100 made of silicon material may also be replaced by a carrier substrate 100 made of sapphire, polycrystalline aluminum nitride (AlN), glass, or any other material having a thermal expansion coefficient less than or opposite to that of the piezoelectric material of the piezoelectric layer 200 (for the purposes of the present invention, the thermal expansion coefficient is the thermal expansion coefficient in a plane parallel to the main surface of the substrate in question). In this way, the carrier substrate 100 acts as a stiffener that limits the expansion of the piezoelectric structure 10 during temperature changes to which it is subjected, thereby reducing the thermal frequency coefficient of the piezoelectric layer 200, i.e., the degree to which the frequency of waves propagating in the piezoelectric layer 200 changes with temperature. Silicon is particularly preferred because it allows the addition of a surface trap layer to provide additional functionality that allows electrical isolation with respect to RF applications, which occurs.

[0032] The use of silicon has the advantage that it not only opens up the field of application of piezoelectric material films to large-scale equipment of the 300 mm type, but also makes them compatible with the microelectronics industry, which has high requirements for the acceptance of foreign materials other than silicon, in particular lithium tantalate or lithium niobate, in its production lines. It is therefore also possible to foresee integrating components obtained or manufactured with layers made of ferroelectrics and also with layers made of piezoelectric material, such as SAW filters and / or BAW filters, with parts obtained or formed on silicon substrates, such as transistors, power amplifiers, and even network switches, thereby reducing the losses in the interconnections between different types of components and making such systems integrating multiple components more compact.

[0033] 1 shows a schematic representation of a bonding step 1' for bonding a substrate 20 made of a piezoelectric material to a carrier substrate 100, preferably made of a silicon material. The bonding step 1' for bonding a substrate 20 made of a piezoelectric material to a carrier substrate 100, preferably made of a silicon material, is preferably carried out by a molecular bonding step, which comprises a bonding step, preferably at room temperature, optionally followed by a strengthening annealing of the bonded interface.

[0034] Also shown schematically is the deposition of a dielectric bonding layer 1001 on one side of the piezoelectric substrate 20 prior to the bonding step 1′ for bonding the piezoelectric substrate 20 to the carrier substrate 100 via the dielectric bonding layer 1001. The dielectric bonding layer 1001 is deposited at a temperature of 300°C or less. Typically, the deposition temperature of the dielectric bonding layer 1001 is selected so that deflections caused by the different thermal expansion coefficients of the piezoelectric substrate 20 and the dielectric bonding layer 1001 remain compatible with the molecular bonding step, and the assembly formed by the piezoelectric substrate 20 and the dielectric bonding layer 1001 has a deflection of 100 μm or less. The thickness of the dielectric bonding layer 1001 must be taken into consideration. Good results have been shown for deposition temperatures of 300°C or less across a range of anticipated thicknesses from 200 nm to 500 nm. It was found that not only did the deflection (80-90 μm for a 500 nm dielectric bonding layer 1001) remain below the threshold compatible with molecular bonding (approximately 100 μm), but the properties of the dielectric bonding layer 1001 were also such that the bond energy obtained between the dielectric bonding layer 1001 and the carrier substrate 100 was improved. Thus, the bond energy was reduced to 1 J / m 2 These energies are high enough to provide stable mechanical strength during subsequent steps such as thinning or toughening annealing steps.

[0035] The molecular bonding step is preferably carried out at room temperature, i.e., about 20°C. However, it is also possible to carry out this direct thermal bonding at temperatures between 20°C and 50°C. In addition, the bonding step is advantageously carried out at low pressure, i.e., at a pressure of 5 mTorr or less (to be precise, 1 Torr is 101325 / 760 Pascals, i.e., about 133.322 Pa), which allows water to desorb from the surfaces forming the bonding interface. Carrying out the bonding step under vacuum can further improve water desorption at the bonding interface.

[0036] In an advantageous embodiment, the substrate 20 made of piezoelectric material has a roughened surface designed to reflect high frequencies. As used herein, a "roughened surface" refers to a surface whose roughness is on the same order of magnitude as the wavelength of the RF waves intended to propagate through the piezoelectric layer of the resonator or filter, allowing the parasitic waves to be reflected in all directions, thereby no longer contributing to the output signal of the resonator or filter. In the context of the present invention, the roughness of such a surface is between 1.0 and 1.8 μm, measured peak to valley. To fill this roughness, the dielectric bonding layer 1001 is thicker than the roughness, and planarity is achieved by chemical and / or mechanical etching steps.

[0037] Preferably, the dielectric bonding layer 1001 comprises a layer of silicon oxide deposited, preferably by plasma-assisted chemical vapor deposition, on a substrate 20 made of a piezoelectric material.

[0038] According to another embodiment, the dielectric bonding layer 1001 is a layer made of silicon oxide, or a layer made of silicon nitride, or a layer comprising a combination of silicon nitride and silicon oxide, or a superposition of at least one layer made of silicon oxide and one layer made of silicon nitride, preferably obtained by plasma-assisted chemical vapor deposition.

[0039] In one advantageous embodiment, a bond interface strengthening anneal is performed to strengthen the mechanical strength of the piezoelectric structure. This anneal is performed at a temperature below the deposition temperature of the dielectric bonding layer 1001, thus increasing the bond energy without creating defects at the bond interface due to the presence of any impurities (such as hydrogen) during such annealing and their outgassing and migration towards the bond interface. The strengthening anneal is typically performed at a temperature of 300° C. or less for a period of time varying from a few minutes to a few hours.

[0040] As shown schematically in FIG. 1, a thinning step 2′ of thinning the substrate 20 made of piezoelectric material follows after this substrate has been bonded to the carrier substrate 100. FIG. 1 shows a schematic representation of the thinning step 2′, which may be carried out, for example, by chemical and / or mechanical etching (polishing, grinding, milling, etc.). In this way, a layer 200 made of piezoelectric material is obtained. The thinning step may also consist of applying the SmartCut™ method. This method is shown schematically in FIGS. 3 and 4 and comprises the formation of weakened zones in the layer to be transferred so as to delimit the layer to be transferred from the remaining layers of the substrate chosen for the transfer, the preparation of a receiving substrate onto which the layer to be transferred will be transferred, generally by molecular bonding (a step of bonding the layer to be transferred to the receiving substrate), and then a release step which comprises breaking and separating along the weakened zones, thereby forming a heterostructure comprising the layer to be transferred to the receiving substrate. The thinning step is generally carried out at a temperature below the deposition temperature of the dielectric bonding layer 1001, which makes it possible to prevent the aforementioned defects at the bonding interface due to the presence of any impurities (such as hydrogen) during such a thinning step and their outgassing and migration towards the bonding interface.

[0041] 1 in that, prior to the bonding step 1', a dielectric bonding layer 1002 is formed on the carrier substrate 100, and this layer is therefore present in the piezoelectric structure 10' obtained by the manufacturing process according to the invention. Depending on the material chosen for the carrier substrate 100, this dielectric bonding layer 1002 is formed in such a way as to allow molecular bonding between the assembly consisting of the substrate 20 made of piezoelectric material and the dielectric bonding layer 1001, and the assembly 100' consisting of the carrier substrate 100 and the dielectric bonding layer 1002. The deflection of the assembly 200' therefore remains below 100 μm.

[0042] Preferably, the dielectric bonding layer 1002 comprises a layer of silicon oxide. In the case of a carrier substrate 100 made of silicon material, the layer may be a thermal oxide, although the invention is not limited to thermal oxide. Without limitation, the layer may also be obtained by plasma-assisted chemical vapor deposition.

[0043] FIG. 3 shows a schematic representation of one embodiment of a process for transferring a piezoelectric layer 200′ to a final substrate 300′, comprising: providing a piezoelectric structure 10′ (obtained using the process shown schematically in FIG. 2 , with the understanding that the invention is not limited to this embodiment); forming weakened zones 0″ in the layer of piezoelectric material 200 to define the piezoelectric layer 200′ to be transferred from the remaining layer 201 of the layer of piezoelectric material 200; providing a final substrate 300′; step 2″ bonding the layer of piezoelectric material 200 to the final substrate 300′; and a debonding step 2″ comprising fracturing and separating the piezoelectric structure 10′ along the weakened zones, thereby forming a heterostructure 30′ comprising the piezoelectric layer 200′ on the final substrate 300′. The debonding step is preferably performed at a temperature below the deposition temperature of the dielectric bonding layer 1001, preferably below 300° C.

[0044] The transfer process shown schematically in FIG. 4 differs from the transfer process shown schematically in FIG. 3 in that, prior to bonding step 1'', a dielectric bonding layer 2001 is formed on the piezoelectric structure 10' and a dielectric bonding layer 2002 is formed on the final substrate 300', and therefore these two dielectric bonding layers 2001 and 2002 are present in the heterostructure 30'' obtained by the transfer process according to the invention.

[0045] Therefore, the thickness of the dielectric layer of the final structure is the sum of the thicknesses of the two dielectric bonding layers. If the thickness of the dielectric layer of the final structure needs to fit within a certain range of values, certain flexibility in fabricating these layers can be achieved either on the piezoelectric structure or on the final substrate. For example, the final substrate may already contain the above-mentioned components and therefore cannot exceed a certain thermal budget to avoid damaging these components. Therefore, it is possible to form a thicker dielectric layer on the piezoelectric structure than on the final substrate.

[0046] The invention is not so limited, and it may be the case that only one of the dielectric bonding layers is formed either on the piezoelectric structure 10' or on the final substrate 300'.

[0047] The bonding step 1'' for bonding the piezoelectric structure 10' to a final substrate 300', preferably made of silicon material, is preferably performed by a molecular bonding step. This molecular bonding step preferably comprises a bonding step at room temperature, which may be followed by a strengthening anneal of the bonded interface.

[0048] In the transfer process shown diagrammatically in Figures 3 and 4, the weakened zone 0" is formed by implanting atomic species into the layer 200 of piezoelectric material. Typically, the implantation step 0" is performed using hydrogen ions. One interesting alternative, well known to those skilled in the art, involves replacing all or some of the hydrogen ions with helium ions.

[0049] For a layer 200 of lithium tantalate piezoelectric material, the hydrogen implantation dose is typically 6×10 16 cm -2 ~1×10 17 cm -2 The implantation energy is typically 50 to 170 keV. Therefore, desorption is typically carried out at a temperature of 150° C. to 300° C. In this way, a piezoelectric layer 200′ having a thickness of about 10 nm to 500 nm is obtained.

[0050] The final substrate 300' and the carrier substrate 100 can advantageously have the same, or at least very similar, coefficients of thermal expansion, which allows for improved mechanical strength and reduced deformation during bond interface strengthening annealing. The two substrates may be of identical nature, made essentially of silicon, apart from any dielectric bonding or trapping layers that may be present. The latter does not have a sufficient thickness to significantly affect the benefits of a "sandwich" structure with the final substrate 300' and the carrier substrate 100 made of the same material.

[0051] Immediately after the desorption operation, additional technological steps are advantageously added with the aim of strengthening the bonding interface, or restoring an appropriate level of roughness, or correcting any defects that occurred during the implantation step (or otherwise preparing the surface for the resumption of other process steps, such as, for example, the formation of electrodes of a SAW-type device). These steps are, for example, polishing, chemical etching (wet or dry), annealing, chemical cleaning steps. These steps can be used alone or in combination, which can be adjusted by a person skilled in the art.

[0052] In an advantageous embodiment, the carrier substrate 100 and / or the final substrate 300′ may be a silicon substrate having an electrical resistivity greater than 1 kΩcm. The carrier substrate 100 and / or the final substrate 300′ may also include a charge trapping layer disposed on the surface of the silicon substrate intended to be bonded. The trapping layer may comprise undoped polysilicon. Under some circumstances, the silicon-based substrate may have a standard resistivity less than 1 kΩcm, especially if the trapping layer is sufficiently thick, e.g., greater than 30 μm. Generally, it is the amorphous layer that contains structural defects such as dislocations, grain boundaries, amorphous zones, gaps, inclusions, and pores. These structural defects form traps for charges that tend to flow through the material, for example, at the sites of incomplete or dangling chemical bonds. In this way, conduction is hindered in the trapping layer, resulting in a high resistivity. Advantageously, for reasons of simplicity of implementation, the trapping layer is formed by a layer of polysilicon. Its thickness can be between 0.3 μm and 3 μm, especially when the layer is formed on an electrically resistive silicon-based substrate. However, other thicknesses below or above this range are entirely feasible, depending on the expected level of RF performance. To preserve the polycrystalline nature of this layer during heat treatments that may be performed on the carrier substrate 100 or the final substrate 300′, an amorphous layer, for example made of silicon dioxide, can be advantageously provided on this substrate prior to the deposition of the charge trapping layer. Alternatively, the trapping layer can be formed by implanting a surface thickness of the substrate with heavy chemical species, such as argon, in order to create structural defects in the substrate that constitute electrical traps. This layer can also be formed by porosifying a surface thickness of the substrate.

Claims

1. A method for manufacturing a piezoelectric structure (10, 10') for a high frequency device, the method comprising the steps of: providing a substrate (20) made of piezoelectric material; providing a carrier substrate (100); depositing a dielectric bonding layer (1001) on only one side of the substrate (20) made of piezoelectric material at a temperature of 300°C or less; bonding (1') the substrate (20) made of piezoelectric material to the carrier substrate (100) via the dielectric bonding layer (1001); and a thinning step (2') to form the piezoelectric structure (10, 10') comprising a layer (200) made of piezoelectric material bonded to the carrier substrate (100). a bonding interface strengthening anneal at a temperature below the deposition temperature of the dielectric bonding layer (1001); A method comprising:

2. 2. The method of claim 1, wherein the dielectric bonding layer (1001) comprises a layer of silicon oxide deposited by plasma-assisted chemical vapor deposition on the substrate (20) of piezoelectric material.

3. 3. The method according to claim 1 or 2, wherein the bonding step (1') comprises a molecular bonding step between the dielectric bonding layer (1001) and the carrier substrate (100) or between the dielectric bonding layer (1001) and a dielectric bonding layer (1002) formed on the carrier substrate (100).

4. 1. A method for manufacturing a piezoelectric structure (10, 10') for a high frequency device, the method comprising the steps of: providing a substrate (20) made of piezoelectric material; providing a carrier substrate (100); depositing a dielectric bonding layer (1001) on only one side of the substrate (20) made of piezoelectric material at a deposition temperature of 300°C or less; bonding (1') the substrate (20) made of piezoelectric material to the carrier substrate (100) via the dielectric bonding layer (1001); and a thinning step (2') to form the piezoelectric structure (10, 10') comprising a layer (200) made of piezoelectric material bonded to the carrier substrate (100), A method wherein the thinning step (2') is performed at a temperature below the deposition temperature of the dielectric bonding layer (1001).

5. The method according to any one of claims 1 to 4, wherein the substrate (20) made of piezoelectric material has a rough surface designed to reflect high frequencies.

6. 1. A method for manufacturing a piezoelectric structure (10, 10') for a high frequency device, the method comprising the steps of: providing a substrate (20) made of piezoelectric material; providing a carrier substrate (100); depositing a dielectric bonding layer (1001) on only one side of the substrate (20) made of piezoelectric material at a temperature of 300°C or less; bonding (1') the substrate (20) made of piezoelectric material to the carrier substrate (100) via the dielectric bonding layer (1001); and a thinning step (2') to form the piezoelectric structure (10, 10') comprising a layer (200) made of piezoelectric material bonded to the carrier substrate (100), The method, wherein the thickness of said dielectric bonding layer (1001) is between 200 nm and 500 nm.

7. The method of any one of claims 1 to 6, further comprising providing a dielectric bonding layer (1002) on the carrier substrate (100).

8. The method according to any one of the preceding claims, wherein said thinning step (2') comprises etching and / or chemical mechanical polishing.

9. 10. A method for transferring a piezoelectric layer (200') to a final substrate (300'), comprising the steps of: preparing a piezoelectric structure (10, 10') obtained by carrying out a method according to any one of claims 1 to 8; forming a weakened zone (0'') in said layer (200) of piezoelectric material so as to define the extent of the piezoelectric layer (200') to be transferred; preparing a final substrate (300'); bonding (1'') said layer (200) of piezoelectric material and said final substrate (300'); and a detachment step (2'') comprising breaking and separating the piezoelectric structure (10, 10') along the weakened zone at a temperature below the deposition temperature of the dielectric bonding layer (1001).

10. The method of claim 9, further comprising the step of forming a dielectric bonding layer (2001, 2002) on the main surface of the final substrate (300') and / or on the layer (200) made of piezoelectric material.

11. 11. The method according to claim 9 or 10, wherein the weakened zone is formed by implanting atomic species into the layer (200) of piezoelectric material.

12. The method according to any one of claims 9 to 11, wherein the final substrate (300') and the carrier substrate (100) have the same coefficient of expansion.

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