Memory System

Abstract

To improve the processing capacity of a memory system.SOLUTION: A memory system 3 includes a nonvolatile memory 10 including a plurality of memory areas PLN each having a memory cell array 111, and a memory controller 20. A data read-out operation includes a first operation for reading data from the memory cell array, and a second operation for transmitting at least a portion of the read data to the memory controller. The memory controller determines a priority between the second operation in a first memory area PLN0 and the second operation in a second memory area PLN1 on the basis of a result of comparing a first total time of the first operation and the second operation in the first memory area with a second total time of the first operation and the second operation in a second memory area in the case of executing reading operations in the first memory area and in the second memory area in parallel.SELECTED DRAWING: Figure 10

Description

[Technical Field]

[0001] FIELD OF THE INVENTION Embodiments of the present invention relate to a memory system. [Background technology]

[0002] 2. Description of the Related Art As a memory system, a solid state drive (SSD) equipped with a nonvolatile semiconductor memory such as a NAND flash memory is known. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 6266019 [Patent Document 2] Patent No. 5183662 [Patent Document 3] U.S. Patent No. 10,503,412 Summary of the Invention [Problem to be solved by the invention]

[0004] One embodiment of the present invention provides a memory system with increased processing power. [Means for solving the problem]

[0005] According to an embodiment, the memory system includes a nonvolatile memory including multiple memory regions, each having a memory cell array, including at least a first memory region and a second memory region different from the first memory region, and a memory controller that controls the nonvolatile memory. A data read operation from the nonvolatile memory includes a first operation that reads data from the memory cell array and a second operation that transmits at least a portion of the read data to the memory controller. When the memory controller executes read operations in the first memory region and the second memory region in parallel, the memory controller determines a priority of the second operation in the first memory region and the second operation in the second memory region based on a result of comparing a first total time required for the first operation and the second operation in the first memory region with a second total time required for the first operation and the second operation in the second memory region. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a block diagram showing an example of the overall configuration of a data processing device including a memory system according to the first embodiment. [Figure 2] FIG. 2 is a block diagram showing the basic configuration of a memory chip included in the memory system according to the first embodiment. [Figure 3] FIG. 3 is a circuit diagram showing an example of a circuit configuration of a memory cell array included in the memory system according to the first embodiment. [Figure 4] FIG. 4 is a diagram showing an example of a page configuration in the memory cell array included in the memory system according to the first embodiment. [Figure 5] FIG. 5 is a diagram showing an example of a user log in the memory system according to the first embodiment. [Figure 6] FIG. 6 is a diagram showing an example of a lookup table in the memory system according to the first embodiment. [Figure 7] FIG. 7 is a diagram illustrating an example of an available cluster pool in the memory system according to the first embodiment. [Figure 8]FIG. 8 is a diagram showing a specific example of generation of an available cluster pool in the memory system according to the first embodiment. [Figure 9] FIG. 9 is a diagram showing a specific example of how priorities are determined in the memory system according to the first embodiment. [Figure 10] FIG. 10 is a timing chart showing a specific example of a read operation based on priority in the memory system according to the first embodiment. [Figure 11] FIG. 11 is a flowchart showing an example of a garbage collection read operation in the memory system according to the first embodiment. [Figure 12] FIG. 12 is a diagram showing a specific example of how priorities are determined in the memory system according to the second embodiment. [Figure 13] FIG. 13 is a timing chart showing a specific example of a read operation based on priority in the memory system according to the second embodiment. [Figure 14] FIG. 14 is a block diagram showing an example of the overall configuration of a data processing device including a memory system according to the third embodiment. [Figure 15] FIG. 15 is a diagram showing a specific example of a command queue in the memory system according to the third embodiment. [Figure 16] FIG. 16 is a diagram showing a specific example of priority determination and scheduling in the NAND controller included in the memory system according to the third embodiment. [Figure 17] FIG. 17 is a flowchart showing an example of a garbage collection read operation in the memory system according to the third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments will be described with reference to the drawings. The drawings are schematic. In the following description, components having substantially the same functions and configurations are designated by the same reference numerals. The numbers following the letters constituting the reference numerals are used to distinguish between elements having similar configurations.

[0008] A memory system according to an embodiment will be described below.

[0009] 1 Configuration 1.1 Configuration of information processing device 1.1.1 Data Processing Device Configuration First, an example of the configuration of a data processing device 1 will be described with reference to Fig. 1. Fig. 1 is a block diagram showing an example of the overall configuration of the data processing device 1.

[0010] 1, a data processing device 1 includes a host device 2 and a memory system 3. A plurality of memory systems 3 may be connected to the host device 2. A plurality of host devices 2 may be connected to the memory system 3.

[0011] The host device 2 is an information processing device (computing device) that accesses the memory system 3. The host device 2 controls the memory system 3. More specifically, for example, the host device 2 requests (commands) the memory system 3 to write or read data (hereinafter referred to as "user data").

[0012] The memory system 3 is, for example, a solid state drive (SSD). The memory system 3 is connected to the host device 2.

[0013] 1.1.2 Memory System Configuration Next, an example of the configuration of the memory system 3 will be described.

[0014] As shown in FIG. 1, the memory system 3 includes a nonvolatile memory 10 and a memory controller 20.

[0015] The nonvolatile memory 10 is a nonvolatile storage medium. The nonvolatile memory 10 stores data received from the memory controller 20 in a nonvolatile manner. The following describes a case where the nonvolatile memory 10 is a NAND flash memory. However, the nonvolatile memory 10 may be a nonvolatile storage medium other than a NAND flash memory.

[0016] The memory controller 20 is, for example, a SoC (System On a Chip). In response to a request (command) from the host device 2, the memory controller 20 commands the nonvolatile memory 10 to perform a read operation, a write operation, an erase operation, etc. The memory controller 20 also manages the memory space of the nonvolatile memory 10.

[0017] Next, the internal configuration of the nonvolatile memory 10 will be described. The nonvolatile memory 10 includes multiple memory chips 11. In the example shown in FIG. 1, the nonvolatile memory 10 includes eight memory chips 11_0 to 11_7. Hereinafter, when there is no limitation on any one of the memory chips 11_0 to 11_7, it will be simply referred to as "memory chip 11." Note that the number of memory chips 11 included in the nonvolatile memory 10 is arbitrary.

[0018] The memory chip 11 is, for example, a semiconductor chip equipped with a NAND flash memory. The memory chip 11 stores data in a nonvolatile manner. The multiple memory chips 11 can operate independently of each other. The memory chips 11 are connected to the memory controller 20 via NAND buses. In the example shown in FIG. 1, two NAND buses are provided. Four memory chips 11_0 to 11_3 are connected to the NAND bus corresponding to channel CH0. Four memory chips 11_4 to 11_7 are connected to the NAND bus corresponding to channel CH1. The number of NAND buses and the number of memory chips 11 connected to one NAND bus are arbitrary.

[0019] Next, the internal configuration of the memory controller 20 will be described. The memory controller 20 includes a host interface circuit (host I / F) 21, a CPU (Central Processing Unit) 22, a ROM (Read Only Memory) 23, a RAM (Random Access Memory) 24, a buffer memory 25, a block management unit 26, a valid cluster search circuit 27, a scheduler 28, and one or more NAND controllers 29. These circuits are connected to each other, for example, by a bus. Note that the functions of the host interface circuit 21, the block management unit 26, the valid cluster search circuit 27, the scheduler 28, and the NAND controller 29 may be realized by dedicated circuits or by the CPU 22 executing firmware.

[0020] The host interface circuit 21 is an interface circuit connected to the host device 2. The host interface circuit 21 performs communication in accordance with an interface standard between the host device 2 and the memory controller 20. The host interface circuit 21 transmits requests and user data received from the host device 2 to the CPU 22 and the buffer memory 25, respectively. In addition, the host interface circuit 21 transmits user data in the buffer memory 25 to the host device 2 in response to an instruction from the CPU 22.

[0021] The CPU 22 is a processor that controls the overall operation of the memory controller 20. For example, the CPU 22 commands the nonvolatile memory 10 to perform write, read, and erase operations based on requests from the host device 2.

[0022] The CPU 22 also performs various processes for managing the nonvolatile memory 10, such as garbage collection, refreshing, and wear leveling.

[0023] Garbage collection is also called compaction. Garbage collection is a process of reading (collecting) valid data from multiple blocks and rewriting (copying) it to another block. A block from which all valid data has been copied becomes erasable. For example, data erasure operations in the nonvolatile memory 10 are performed for each data area called a "block." In contrast, data write and read operations are performed in data units called "pages." A block includes multiple pages. Therefore, the data erasure unit differs from the data write and read unit. When data is rewritten in the nonvolatile memory 10, the new data is written to a different memory element (page). Therefore, as data rewriting progresses, the amount of invalid data increases within a block. If even one valid data remains in a block even after the amount of invalid data increases, the block erase operation cannot be performed. For example, if the number of erasable blocks decreases, the CPU 22 performs garbage collection.

[0024] Refresh is a process in which, when data degradation in a block is detected, the data in that block is rewritten to another block or to the block itself. For example, data degradation refers to a state in which the number of corrected bits in a data error correction process has increased.

[0025] Wear leveling is a process of leveling the number of erase operations for each of the multiple blocks in non-volatile memory 10, for example, by swapping data stored in a block that has been erased relatively frequently with data stored in a block that has been erased relatively rarely.

[0026] The ROM 23 is a non-volatile memory. For example, the ROM 23 is an EEPROM. TM The ROM 23 is a non-transitory storage medium that stores firmware, programs, etc. For example, the CPU 22 loads firmware from the ROM 23 into the RAM 24.

[0027] The RAM 24 is a volatile memory. The RAM 24 is a dynamic random access memory (DRAM) or a static random access memory (SRAM). The RAM 24 is used as a work area for the CPU 22. For example, the RAM 24 stores firmware for managing the nonvolatile memory 10 and various management tables.

[0028] For example, the RAM 24 stores a user log, a look-up table (LUT), and an available cluster pool as management tables.

[0029] The user log is a log that indicates the status of writing user data in the nonvolatile memory 10. For example, the user log indicates the relationship between the physical address and the logical address of the nonvolatile memory 10 for each physical address. A physical address is an address that identifies a memory element of the nonvolatile memory 10. Hereinafter, a physical address will also be referred to as a NAND address. A logical address is an address used by the host device 2 to address user data. In the following, an example will be given in which a logical block address (LBA) is used as the logical address.

[0030] The lookup table is a table that indicates the relationship between a logical block address and a corresponding NAND address for each logical block address. For example, the memory controller 20 uses the lookup table to manage the mapping between the logical block addresses and the NAND addresses. For example, the CPU 22 loads a portion of the lookup table from the nonvolatile memory 10 to the RAM 24. The lookup table in the RAM 24 is updated when a write operation is performed. The CPU 22 then updates the lookup table in the nonvolatile memory 10 at any timing based on the lookup table in the RAM 24.

[0031] The valid cluster pool is a table that shows a collection of NAND addresses corresponding to valid clusters. For example, one page can be divided into multiple clusters. That is, a cluster is a data unit with a data length shorter than that of a page. Each cluster contains user data associated with a different logical block address. A valid cluster is a cluster that contains valid data. For example, during garbage collection, the valid cluster pool stores NAND addresses corresponding to valid clusters in the block to be read.

[0032] The buffer memory 25 is a volatile memory. The buffer memory 25 is a DRAM, an SRAM, or the like. The buffer memory 25 temporarily stores user data that the memory controller 20 reads from the nonvolatile memory 10, user data that the memory controller 20 receives from the host device 2, and the like.

[0033] The block management unit 26 manages the memory space of the nonvolatile memory 10 for each block. For example, the block management unit 26 manages the user log of each block. For example, when performing garbage collection, the block management unit 26 reads the user log of the block to be read from the nonvolatile memory 10. Then, the block management unit 26 stores the read user log in the RAM 24. In addition, for example, the block management unit 26 manages information on the block to be written to during garbage collection (hereinafter also referred to as "write destination information"). For example, the write destination information includes information on the storage capacity available for writing to the block to be written to.

[0034] The valid cluster search circuit 27 is a circuit that searches for valid clusters from the information stored in the user log. For example, the user log stores the corresponding logical block address for each cluster. However, the user data corresponding to the logical block address may become invalid due to data rewriting or the like. In other words, the user log can be used to determine whether the corresponding cluster is valid or invalid. A valid cluster is a cluster that contains valid data. An invalid cluster is a cluster that does not contain valid data. The valid cluster search circuit 27 compares the user log with the lookup table to extract information about valid clusters.

[0035] The scheduler 28 adjusts the schedules of various operations executed in the memory system 3. For example, the scheduler 28 schedules write operations or read operations, erase operations, garbage collection, and the like based on requests from the host. The scheduler 28 selects a NAND controller 29 connected to the memory chip 11 that is the target of the operation. Then, the scheduler 28 transmits instructions (commands) to the NAND controller 29 in an order based on the scheduling results. The commands include a NAND address or write data.

[0036] The NAND controller 29 controls the memory chip 11. One NAND controller 29 corresponds to one channel CH. In the example shown in FIG. 1, the memory controller 20 includes two NAND controllers 29_0 and 29_1. The NAND controller 29_0 corresponds to channel CH0. The NAND controller 29_1 corresponds to channel CH1. Hereinafter, when there is no need to specify either the NAND controller 29_0 or 29_1, it will be simply referred to as the "NAND controller 29."

[0037] The NAND controller 29 transmits commands corresponding to write operations, read operations, erase operations, etc. to the memory chip 11. Furthermore, the NAND controller 29 receives read data from the memory chip 11 during a read operation.

[0038] 1.1.3 Memory Chip Configuration Next, an example of the configuration of the memory chip 11 will be described with reference to Fig. 2. Fig. 2 is a block diagram showing the basic configuration of the memory chip 11. In the example shown in Fig. 2, some of the connections between the components are indicated by arrows. However, the connections between the components are not limited to this.

[0039] 2, the memory chip 11 transmits and receives a signal DQ and timing signals DQS and DQSn to and from a memory controller 20 (more specifically, a NAND controller 29) via a NAND bus. The signal DQ is, for example, data DAT, an address ADD (NAND address ADD), or a command CMD. The timing signals DQS and DQSn are timing signals used when inputting and outputting data DAT. The timing signal DQSn is an inverted signal of the timing signal DQS.

[0040] The memory chip 11 also receives various control signals from the memory controller 20 via the NAND bus. The memory chip 11 also transmits a ready / busy signal RBn to the memory controller 20 via the NAND bus. The ready / busy signal RBn is a signal that indicates whether the memory chip 11 is in a state where it can or cannot receive a command CMD from the memory controller 20. The busy state is a state where the memory chip 11 cannot receive a command CMD from the memory controller 20. The ready state is a state where the memory chip 11 can receive a command CMD from the memory controller 20.

[0041] Next, a description will be given of the internal configuration of the memory chip 11. The memory chip 11 includes an input / output circuit 101, a logic control circuit 102, an address register 103, a command register 104, a sequencer 105, a ready / busy circuit 106, and a plurality of planes PLN.

[0042] The input / output circuit 101 is a circuit that inputs and outputs a signal DQ. The input / output circuit 101 is connected to the memory controller 20. The input / output circuit 101 is also connected to a logic control circuit 102, an address register 103, a command register 104, and a data register 114 of each plane PLN.

[0043] When the input signal DQ is an address ADD, the input / output circuit 101 transmits the address ADD to the address register 103. When the input signal DQ is a command CMD, the input / output circuit 101 transmits the command CMD to the command register 104.

[0044] When the input signal DQ is data DAT, the input / output circuit 101 receives the input signal DQ based on the timing signals DQS and DQSn. Then, the input / output circuit 101 transmits the data DAT to the data register 114 of the corresponding plane PLN based on the address ADD stored in the address register 103. The input / output circuit 101 also outputs the data DAT to the memory controller 20 together with the timing signals DQS and DQSn.

[0045] The logic control circuit 102 is a circuit that performs logic control based on control signals. The logic control circuit 102 is connected to the memory controller 20. The logic control circuit 102 is also connected to the input / output circuit 101 and the sequencer 105. The logic control circuit 102 receives various control signals from the memory controller 20. The logic control circuit 102 controls the input / output circuit 101 and the sequencer 105 based on the received control signals.

[0046] The address register 103 is a register that temporarily stores an address ADD. The address register 103 is connected to the input / output circuit 101, and the row decoder 112 and column decoder 115 of each plane PLN. The address ADD includes a row address RA and a column address CA. The address register 103 transfers the row address RA to the row decoder 112. The address register 103 also transfers the column address CA to the column decoder 115.

[0047] The command register 104 is a register that temporarily stores the command CMD. The command register 104 is connected to the input / output circuit 101 and the sequencer 105. The command register 104 transfers the command CMD to the sequencer 105.

[0048] The sequencer 105 is a circuit that controls the memory chip 11. The sequencer 105 controls the operation of the entire memory chip 11. More specifically, for example, the sequencer 105 controls the ready / busy circuit 106, as well as the row decoder 112, sense amplifier 113, data register 114, and column decoder 115 of each plane PLN. The sequencer 105 executes a write operation, a read operation, an erase operation, etc. based on a command CMD.

[0049] The ready / busy circuit 106 is a circuit that transmits a ready / busy signal RBn. The ready / busy circuit 106 transmits the ready / busy signal RBn to the controller in accordance with the operating status of the sequencer 105.

[0050] A plane PLN is a unit (memory area) that performs data write and read operations. In the example shown in FIG. 2, the memory chip 11 includes four planes PLN0, PLN1, PLN2, and PLN3. The number of planes PLN included in the memory chip 11 is not limited to four. The planes PLN0 to PLN3 can operate independently of each other. The planes PLN0 to PLN3 can also operate in parallel. In other words, the memory chip 11 has multiple memory areas that can be controlled independently of each other. Hereinafter, when there is no limitation on any of the planes PLN0 to PLN3, they will be referred to as "plane PLN."

[0051] Next, the internal configuration of the plane PLN will be described. Below, a case will be described where the planes PLN0 to PLN3 have the same configuration. Note that the configuration of each plane PLN may be different. The plane PLN includes a memory cell array 111, a row decoder 112, a sense amplifier 113, a data register 114, and a column decoder 115.

[0052] The memory cell array 111 is a set of multiple memory cell transistors arranged in a matrix. The memory cell array 111 includes, for example, four blocks BLK0, BLK1, BLK2, and BLK3. The number of blocks BLK in the memory cell array 111 is arbitrary. A block BLK is, for example, a set of multiple memory cell transistors from which data is erased collectively. In other words, a block BLK is a unit for erasing data. The configuration of a block BLK will be described in detail later.

[0053] The row decoder 112 is a decoding circuit for the row address RA. Based on the decoding result, the row decoder 112 selects one of the blocks BLK in the memory cell array 111. The row decoder 112 applies a voltage to the row-direction wiring (word lines and select gate lines, which will be described later) of the selected block BLK.

[0054] The sense amplifier 113 is a circuit that writes and reads data DAT. The sense amplifier 113 is connected to the memory cell array 111 and the data register 114. During a read operation, the sense amplifier 113 reads the data DAT from the memory cell array 111. During a write operation, the sense amplifier 113 supplies a voltage corresponding to the write data DAT to the memory cell array 111.

[0055] The data register 114 is a register that temporarily stores data DAT. The data register 114 is connected to the sense amplifier 113 and the column decoder 115. The data register 114 includes a plurality of latch circuits. Each latch circuit temporarily stores write data or read data.

[0056] The column decoder 115 is a circuit that decodes the column address CA. The column decoder 115 receives the column address CA from the address register 103. The column decoder 115 selects a latch circuit in the data register 114 based on the result of decoding the column address CA.

[0057] 1.1.4 Memory cell array circuit configuration Next, an example of the circuit configuration of the memory cell array 111 will be described with reference to Fig. 3. Fig. 3 is a circuit diagram showing an example of the circuit configuration of the memory cell array 111.

[0058] The block BLK includes, for example, four string units SU0 to SU3. The number of string units SU included in the block BLK is arbitrary. The string unit SU is, for example, a set of multiple NAND strings NS that are collectively selected in a write operation or a read operation.

[0059] Next, the internal configuration of the string unit SU will be described. The string unit SU includes a plurality of NAND strings NS. The NAND string NS is a collection of a plurality of memory cell transistors connected in series. Each of the plurality of NAND strings NS in the string unit SU is connected to one of bit lines BL0 to BLn (n is an integer equal to or greater than 1).

[0060] Next, the internal configuration of the NAND strings NS will be described. Each NAND string NS includes a plurality of memory cell transistors MC and select transistors ST1 and ST2. In the example shown in Figure 3, the NAND string NS includes eight memory cell transistors MC0 to MC7.

[0061] The memory cell transistor MC is a memory element that stores data in a nonvolatile manner. The memory cell transistor MC includes a control gate and a charge storage layer. The memory cell transistor MC may be a MONOS (Metal-Oxide-Nitride-Oxide-Silicon) type or an FG (Floating Gate) type.

[0062] The selection transistors ST1 and ST2 are switching elements and are used to select the string units SU during various operations.

[0063] The current paths of the select transistor ST2, memory cell transistors MC0 to MC7, and select transistor ST1 in the NAND string NS are connected in series. The drain of the select transistor ST1 is connected to a bit line BL. The source of the select transistor ST2 is connected to a source line SL.

[0064] The control gates of the memory cell transistors MC0 to MC7 in the same block BLK are commonly connected to word lines WL0 to WL7, respectively. More specifically, for example, the block BLK includes four string units SU0 to SU3. Each string unit SU includes a plurality of memory cell transistors MC0. The control gates of the plurality of memory cell transistors MC0 in the block BLK are commonly connected to one word line WL0. The same is true for the memory cell transistors MC1 to MC7.

[0065] The gates of the multiple select transistors ST1 in the string unit SU are commonly connected to one select gate line SGD. More specifically, the gates of the multiple select transistors ST1 in the string unit SU0 are commonly connected to a select gate line SGD0. The gates of the multiple select transistors ST1 in the string unit SU1 are commonly connected to a select gate line SGD1. The gates of the multiple select transistors ST1 in the string unit SU2 are commonly connected to a select gate line SGD2. The gates of the multiple select transistors ST1 in the string unit SU3 are commonly connected to a select gate line SGD3.

[0066] The gates of the multiple select transistors ST2 in the block BLK are commonly connected to a select gate line SGS.

[0067] The word lines WL0 to WL7, the select gate lines SGD0 to SGD3, and the select gate line SGS are each connected to a row decoder 112 in the plane PLN.

[0068] The bit line BL is commonly connected to one NAND string NS of each of the plurality of string units SU in each block BLK. Each bit line BL is connected to a sense amplifier 113 in the plane PLN.

[0069] The source line SL is shared among, for example, a plurality of blocks BLK.

[0070] A set of memory cell transistors MC connected to a common word line WL within one string unit SU is referred to as, for example, a "cell unit CU." In other words, a cell unit CU is a set of memory cell transistors MC selected collectively in a write or read operation. A page is a unit of data that is collectively written (or collectively read) to a cell unit CU. For example, when a memory cell transistor MC stores one bit of data, the memory capacity of the cell unit CU is one page. Note that a cell unit CU may have a memory capacity of two or more pages depending on the number of bits of data stored in the memory cell transistor MC.

[0071] One page PG includes a plurality of clusters CT. An example of the configuration of one page PG is shown in Fig. 4. In the example shown in Fig. 4, one page PG includes four clusters CT.

[0072] For example, in a read operation of the memory chip 11, one of the cell units CU is selected, and data is read from the memory cell array 111 to the sense amplifier 113 in page units. The read data is stored in the data register 114. The data stored in the data register 114 can be transmitted to the memory controller 20 for each cluster CT. For example, the memory controller 20 requests the memory chip 11 to transmit data of valid clusters CT.

[0073] 1.2 Example of a user log Next, a specific example of a user log will be described with reference to Fig. 5. Fig. 5 is a diagram showing an example of a user log.

[0074] As shown in FIG. 5, the user log includes, for each NAND address that identifies a cluster CT, information on the logical block address LBA corresponding to the user data written to the cluster CT. For example, the user log may be managed on a block-by-block basis. The example shown in FIG. 5 shows the user log for block BLK100. For example, the NAND address includes items for block BLK, page PG, and cluster CT. The NAND address may also include information on the plane PLN, string unit SU, or word line WL. In the example shown in FIG. 5, a corresponding logical block address LBA is stored for each cluster CT.

[0075] More specifically, user log #0 stores "0x1000" as the logical block address LBA corresponding to cluster CT0 of page PG0. User log #1 stores "0x1008" as the logical block address LBA corresponding to cluster CT1 of page PG0. User log #2 stores "0x1010" as the logical block address LBA corresponding to cluster CT2 of page PG0. User log #3 stores "0x1018" as the logical block address LBA corresponding to cluster CT3 of page PG0. User log #4 stores "0x1008" as the logical block address LBA corresponding to cluster CT0 of page PG1. The user data corresponding to the logical block addresses LBA stored in the user logs may be valid data or invalid data. For example, the same logical block address "0x1008" is stored in user log #1 (cluster CT1 of page PG0) and user log #4 (cluster CT0 of page PG1). In this case, valid data is stored in one of the clusters CT, and invalid data is stored in the other cluster CT. The amount of data in one cluster CT may be different from the amount of user data corresponding to one logical block address LBA. For example, one cluster CT may store user data corresponding to eight consecutive logical block addresses LBA. In this case, for example, the first address of the eight logical block addresses LBA corresponding to one cluster CT may be stored as information on the logical block address LBA.

[0076] 1.3 Example of a lookup table Next, a specific example of a lookup table will be described with reference to Fig. 6. Fig. 6 is a diagram showing an example of a lookup table.

[0077] As shown in Fig. 6, the lookup table includes information on the corresponding NAND address for each logical block address LBA. The example shown in Fig. 6 shows a case where user data corresponding to eight logical block addresses LBA is stored in one cluster CT. In this case, for example, the lookup table records the corresponding NAND address for each of the first addresses of the eight logical block addresses LBA.

[0078] More specifically, logical block address LBA "0x1000" corresponds to cluster CT0 of page PG0 of block BLK100. Logical block address LBA "0x1008" corresponds to cluster CT0 of page PG1 of block BLK100. Logical block address LBA "0x1010" corresponds to cluster CT2 of page PG0 of block BLK100. Logical block address LBA "0x1018" corresponds to cluster CT3 of page PG0 of block BLK100.

[0079] 1.4 Example of an effective cluster pool Next, a specific example of an available cluster pool will be described with reference to Fig. 7. Fig. 7 is a diagram showing an example of an available cluster pool.

[0080] As shown in Fig. 7, the valid cluster pool is a collection of information on NAND addresses corresponding to valid clusters CT. In the example shown in Fig. 7, cluster CT0 of page PG0 of block BLK100, cluster CT0 of page PG1 of block BLK100, cluster CT2 of page PG0 of block BLK100, and cluster CT3 of page PG0 of block BLK100 are stored as NAND addresses corresponding to valid clusters CT.

[0081] Next, a specific example of generating an available cluster pool will be described with reference to Fig. 8. Fig. 8 is a diagram showing a specific example of generating an available cluster pool.

[0082] As shown in FIG. 8, for example, the valid cluster search circuit 27 compares the user log with the lookup table. More specifically, the valid cluster search circuit 27 compares the NAND addresses corresponding to the same logical block address between the user log and the lookup table. If the NAND addresses in the lookup table and the user log match, the valid cluster search circuit 27 determines that the cluster CT in the user log contains valid data, i.e., is a valid cluster CT. On the other hand, if the NAND addresses do not match, the valid cluster search circuit 27 determines that the cluster CT in the user log does not contain valid data, i.e., is an invalid cluster CT. The valid cluster search circuit 27 performs a search for a valid cluster for each cluster CT in the user log. As a result of the search, the NAND address of the valid cluster CT is stored in the RAM 24, and a valid cluster pool is generated.

[0083] More specifically, the available cluster pool shown in FIG. 8 is an example of an available cluster pool based on the example of the user log shown in FIG. 5 and the example of the lookup table shown in FIG.

[0084] The LBA "0x1000" corresponding to the NAND address "BLK100, PG0, CT0" of user log #0 is associated with the NAND address "BLK100, PG0, CT0" in the lookup table. In other words, the two NAND addresses match. Therefore, the cluster CT corresponding to user log #0 is a valid cluster CT.

[0085] The LBA "0x1008" corresponding to the NAND address "BLK100, PG0, CT1" of user log #1 is associated with the NAND address "BLK100, PG1, CT0" in the lookup table. In other words, the two NAND addresses do not match. Therefore, the cluster CT corresponding to user log #1 is an invalid cluster CT.

[0086] The LBA "0x1010" corresponding to the NAND address "BLK100, PG0, CT2" of user log #2 is associated with the NAND address "BLK100, PG0, CT2" in the lookup table. In other words, the two NAND addresses match. Therefore, the cluster CT corresponding to user log #2 is a valid cluster CT.

[0087] The LBA "0x1018" corresponding to the NAND address "BLK100, PG0, CT3" of user log #3 is associated with the NAND address "BLK100, PG0, CT3" in the lookup table. In other words, the two NAND addresses match. Therefore, the cluster CT corresponding to user log #3 is a valid cluster CT.

[0088] The LBA "0x1008" corresponding to the NAND address "BLK100, PG1, CT0" of user log #4 is associated with the NAND address "BLK100, PG1, CT0" in the lookup table. In other words, the two NAND addresses match. Therefore, the cluster CT corresponding to user log #4 is a valid cluster CT.

[0089] 1.5 Read Behavior in Garbage Collection Next, a read operation in garbage collection will be described. Below, a case will be described in which data of valid clusters CT is read from one block BLK of each of four planes PLN0 to PLN3 of the memory chip 11. The number of planes PLN from which data of valid clusters CT is read is arbitrary. Furthermore, the planes PLN to be read may be distributed among multiple memory chips 11 connected to one channel CH. Note that the read operation described below is not limited to garbage collection, and can be applied to a case in which data of multiple planes PLN is read in parallel via one channel CH (NAND bus).

[0090] A read operation roughly includes a cell read operation and a data output operation. The cell read operation is an operation of reading data from the memory cell array 111 to the data register 114. The cell read operation is performed in units of a page. The data output operation is an operation of outputting data from the data register 114 to the memory controller 20. The data output operation is performed in units of a cluster. For example, of one page of data read by the cell read operation, data of a valid cluster is output to the memory controller 20 by the data output operation.

[0091] A cell read operation can be performed in parallel in multiple plane PLNs. A data output operation cannot be performed in parallel in multiple plane PLNs because the channel CH (NAND bus) is shared among multiple plane PLNs. For example, when two plane PLNs are ready to output data, the data output operation of one plane PLN is completed before the data output operation of the other plane PLN is performed. In such a case, the other plane PLN is placed in a standby state from the end of the cell read operation until the start of the data output operation.

[0092] In this embodiment, the priority of the data output operation for each plane PLN is determined based on the status of each plane PLN.

[0093] 1.5.1 Example of determining the priority of data output operations First, a specific example of priority determination for data output operations will be described with reference to Fig. 9. Fig. 9 is a diagram showing a specific example of priority determination. The example shown in Fig. 9 shows cluster maps for each of four planes PLN0 to PLN3. The cluster maps indicate whether each cluster CT is a valid cluster or an invalid cluster. Furthermore, the example shown in Fig. 9 shows a case where the read target block BLK of each plane PLN includes eight pages PG, and one page PG includes four clusters CT.

[0094] As shown in Figure 9, for example, in the case of garbage collection, the number of pages PG to be read and the number of valid clusters CT differ for each plane PLN. That is, the valid cluster ratio for each block BLK differs. The valid cluster ratio is the ratio of the number of valid clusters to the total number of clusters CT in the block BLK. In other words, the number of cell read operations and the number of data output operations differ for each plane PLN.

[0095] In the example shown in FIG. 9, for plane PLN0, page PG0 includes one valid cluster. Page PG1 includes two valid clusters. Page PG2 includes three valid clusters. Page PG3 includes two valid clusters. Page PG4 includes three valid clusters. Pages PG5 to PG7 do not include any valid clusters. Plane PLN0 includes a total of 11 valid clusters. Five cell read operations and 11 data output operations are executed in plane PLN0.

[0096] In plane PLN1, page PG0 includes one valid cluster. Page PG1 includes no valid clusters. Page PG2 includes three valid clusters. Page PG3 includes three valid clusters. Page PG4 includes three valid clusters. Page PG5 includes two valid clusters. Page PG6 includes one valid cluster. Page PG7 includes three valid clusters. Plane PLN1 includes a total of 16 valid clusters. Seven cell read operations and 16 data output operations are performed in plane PLN1.

[0097] In the case of plane PLN2, page PG0 includes two valid clusters. Page PG1 includes two valid clusters. Page PG2 includes two valid clusters. Page PG3 includes one valid cluster. Page PG4 includes one valid cluster. Page PG5 includes two valid clusters. Pages PG6 to PG7 do not include any valid clusters. Plane PLN2 includes a total of 10 valid clusters. In plane PLN2, six cell read operations and ten data output operations are executed.

[0098] In the case of plane PLN3, page PG0 includes one valid cluster. Page PG1 includes three valid clusters. Page PG2 includes two valid clusters. Page PG3 includes one valid cluster. Page PG4 includes one valid cluster. Pages PG5 to PG7 do not include any valid clusters. Plane PLN3 includes a total of eight valid clusters. Five cell read operations and eight data output operations are executed in plane PLN3.

[0099] The period of one cell read operation is defined as tR. The period of one data output operation is defined as tDout. The total time (hereinafter referred to as "tR+tDout total time") of multiple cell read operations and multiple data output operations executed for each plane PLN is calculated. For example, in this embodiment, the valid cluster search circuit 27 calculates the tR+tDout total time for each plane PLN based on the search results for valid clusters. In other words, the valid cluster search circuit 27 calculates the tR+tDout total time for each plane PLN based on the valid cluster ratio of the plane PLN (target block BLK). The valid cluster search circuit 27 then determines the priority in descending order of the tR+tDout total time. For example, in the example shown in FIG. 9, the order of the lengths of the tR+tDout total time is PLN1>PLN2>PLN0>PLN3. Based on this result, the valid cluster search circuit 27 assigns the priority of each plane PLN as follows: plane PLN1=1st place, PLN2=2nd place, PLN0=3rd place, and PLN3=4th place.

[0100] A method for determining a plane PLN from the NAND address of a valid cluster pool will be described. For example, multiple blocks BLK included in multiple planes PLN connected to one channel CH are assigned different block BLK numbers (BLK addresses) so that they can be distinguished from one another. More specifically, for example, the memory chip 11 shown in FIG. 2 includes four planes PLN0 to PLN3. Each plane PLN includes four blocks BLK. In this case, for example, BLK0 to BLK3 are assigned as the numbers of the four blocks BLK included in plane PLN0. For example, BLK4 to BLK7 are assigned as the numbers of the four blocks BLK included in plane PLN1. For example, BLK8 to BLK11 are assigned as the numbers of the four blocks BLK included in plane PLN2. For example, BLK12 to BLK15 are assigned as the numbers of the four blocks BLK included in plane PLN3. The valid cluster search circuit 27 performs a calculation of (block BLK number) / 4 from the number of the block BLK in the valid cluster pool, and determines the plane PLN from the integer part of the calculation result.

[0101] 1.5.2 Timing chart of a specific example of a priority-based read operation Next, a timing chart of a specific example of a priority-based read operation will be described with reference to FIG. 10. FIG. 10 is a timing chart showing a specific example of a priority-based read operation. Note that the example shown in FIG. 10 illustrates a case where a cell read operation and a data output operation are performed based on the cluster map and priority described with reference to FIG. 9. For simplicity, the period during which a command is sent from the memory controller 20 to the memory chip 11 is omitted. For simplicity, the example illustrates a case where the period tR of each cell read operation is the same. Note that the period tR of the cell read operation may vary depending on the conditions of the read operation. For example, if a memory cell transistor MC can store 3-bit data including a lower bit, a middle bit, and an upper bit, a cell unit CU can store 3-page data including a lower page, a middle page, and an upper page. In such a case, the period tR of the cell read operation of each page differs depending on the data allocation.

[0102] As shown in FIG. 10, the data output operation of the plane PLN1 with a higher priority is executed preferentially. As a result, there is almost no waiting state in the plane PLN1. In this way, by increasing the priority of the plane PLN with a long total time of tR+tDout, the increase in the processing time of the entire read operation is suppressed. Note that in the example shown in FIG. 10, the read operation of the plane PLN2 with the second priority is completed after the read operation of the plane PLN0 with the third priority is completed. As such, a situation may occur in which the order of completion of the read operations does not match the priority. However, since the length of the processing time of the entire read operation is determined by the read operation of the plane PLN1, there is almost no impact on the processing time of the entire read operation.

[0103] The timing of each read operation will be specifically described below. Multiple planes PLN can execute cell read operations in parallel. Therefore, regardless of priority, planes PLN0 to PLN3 each execute the first cell read operation R1 for page PG0 in parallel. After completing the first cell read operation R1, plane PLN1 (priority: 1st) executes a data output operation D1 for one valid cluster CT included in page PG0. After completing the first cell read operation R1, planes PLN0, PLN2, and PLN3 enter a standby state until a data output operation can be executed. After completing the data output operation D1, plane PLN1 executes the second cell read operation R2 for page PG2. Furthermore, after completing the data output operation D1 for plane PLN1, plane PLN2 (priority: 2nd) executes data output operations D1 and D2 consecutively for two valid clusters CT included in page PG0. After completing the data output operation D2, plane PLN2 executes the second cell read operation R2 for page PG1. Furthermore, when the data output operation D2 of plane PLN2 is completed, plane PLN0 (priority: third) executes a data output operation D1 for one valid cluster CT included in page PG0. After the data output operation D1 is completed, plane PLN0 executes a second cell read operation R2 for page PG1. Furthermore, when the data output operation D1 of plane PLN0 is completed, plane PLN3 (priority: fourth) executes a data output operation D1 for one valid cluster CT included in page PG0.

[0104] After completing the second cell read operation R2, plane PLN1 sequentially executes data output operations D2, D3, and D4 for the three valid clusters CT included in page PG2. After completing data output operation D4, plane PLN1 executes the third cell read operation R3 for page PG3. After completing the second cell read operation R2, planes PLN0, PLN2, and PLN3 enter a standby state until a data output operation can be executed. After completing data output operation D4 for plane PLN1, plane PLN2 sequentially executes data output operations D3 and D4 for the two valid clusters CT included in page PG1. After completing data output operation D4 for plane PLN2, plane PLN0 executes the third cell read operation R3 for page PG2. After completing data output operation D4 for plane PLN2, plane PLN0 sequentially executes data output operations D2 and D3 for the two valid clusters CT included in page PG1. After the data output operation D3 is completed, the plane PLN0 executes the third cell read operation R3 for the page PG2. Also, after the data output operation D3 of the plane PLN0 is completed, the plane PLN3 executes the data output operations D2, D3, and D4 consecutively for the three valid clusters CT included in the page PG1.

[0105] After completing the third cell read operation R3, plane PLN1 sequentially executes data output operations D5, D6, and D7 for the three valid clusters CT included in page PG3. After completing data output operation D7, plane PLN1 executes the fourth cell read operation R4 for page PG4. After completing data output operation D7 of plane PLN1, plane PLN2, which had been in a standby state, sequentially executes data output operations D5 and D6 for the two valid clusters CT included in page PG2. After completing data output operation D6, plane PLN2 executes the fourth cell read operation R4 for page PG3. After completing data output operation D6 of plane PLN2, plane PLN0, which had been in a standby state, sequentially executes data output operations D4, D5, and D6 for the three valid clusters CT included in page PG2. After completing data output operation D6, plane PLN0 executes the fourth cell read operation R4 for page PG3. When the data output operation D6 of the plane PLN0 is completed, the plane PLN3, which has been in a standby state, successively executes data output operations D5 and D6 for the two valid clusters CT included in the page PG2. After completing the data output operation D6, the plane PLN3 executes the fourth cell read operation R4 for the page PG3.

[0106] After completing the fourth cell read operation R4, plane PLN1 sequentially executes data output operations D8, D9, and D10 for the three valid clusters CT included in page PG4. After completing data output operation D10, plane PLN1 executes the fifth cell read operation R5 for page PG5. After completing data output operation D10 for plane PLN1, plane PLN2, which was in a standby state, executes data output operation D7 for one valid cluster CT included in page PG3. After completing data output operation D7, plane PLN2 executes the fifth cell read operation R5 for page PG4. After completing the fourth cell read operation R4, plane PLN0 executes data output operations D7 and D8 for the two valid clusters CT included in page PG3. After completing data output operation D8, plane PLN0 executes the fifth cell read operation R5 for page PG4. When the data output operation D8 of the plane PLN0 is completed, the plane PLN3 executes a data output operation D7 for one valid cluster CT included in the page PG3. After the data output operation D7 is completed, the plane PLN3 executes a fifth cell read operation R5 for the page PG4.

[0107] After completing the fifth cell read operation R5, plane PLN1 sequentially executes data output operations D11 and D12 for two valid clusters CT included in page PG5. After completing data output operation D12, plane PLN1 executes the sixth cell read operation R6 for page PG6. After completing data output operation D12 for plane PLN1, plane PLN2, which was in a standby state, executes data output operation D8 for one valid cluster CT included in page PG4. After completing data output operation D8, plane PLN2 executes the sixth cell read operation R6 for page PG5. After completing the fifth cell read operation R5, plane PLN0 sequentially executes data output operations D9, D10, and D11 for three valid clusters CT included in page PG4. After completing data output operation D11, plane PLN0 completes the read operation. When the data output operation D11 of the plane PLN0 is completed, the plane PLN3, which has been in a standby state, executes the data output operation D8 for one valid cluster CT included in the page PG4. When the plane PLN3 completes the data output operation D8, it completes the read operation.

[0108] After the sixth cell read operation R6 is completed, the plane PLN1 executes a data output operation D13 for one valid cluster CT included in page PG6. After the data output operation D13 is completed, the plane PLN1 executes a seventh cell read operation R7 for page PG7. After the sixth cell read operation R6 is completed, the plane PLN2 executes data output operations D9 and D10 for two valid clusters CT included in page PG5. For example, the data output operations for two valid clusters CT are executed consecutively. After the data output operation D10 is completed, the plane PLN2 completes the read operation.

[0109] After completing the seventh cell read operation R7, the plane PLN1 executes data output operations D14, D15, and D16 for the three valid clusters CT included in page PG7. For example, the data output operations for the three valid clusters CT are executed consecutively. After completing the data output operation D16, the plane PLN1 completes the read operation.

[0110] 1.5.3 Garbage Collection Read Operation Flow Next, an example of the flow of a read operation in garbage collection will be described with reference to Fig. 11. Fig. 11 is a flowchart showing an example of a read operation in garbage collection.

[0111] 11, first, the block management unit 26 reads the user log of the block BLK to be read from the target memory chip 11 (S10). The block management unit 26 transmits the user log to the valid cluster search circuit 27.

[0112] The block management unit 26 transmits write destination information of the block BLK to which the valid cluster CT is to be written to the valid cluster search circuit 27 (S11). Note that the order of S10 and S11 may be reversed, or they may be executed in parallel.

[0113] The valid cluster search circuit 27 reads the lookup table from the RAM 24 (S12).

[0114] The valid cluster search circuit 27 compares the user log with the lookup table to search for valid clusters (S13). The valid cluster search circuit 27 determines whether each cluster CT in the user log is invalid or valid.

[0115] The search results are sent to the RAM 24, and an available cluster pool is generated (S14).

[0116] Based on the search results, the valid cluster search circuit 27 determines the priority of the data output operation of the multiple planes PLNs (blocks BLK) to be read (S15). The valid cluster search circuit 27 determines the priority of each plane in a set of multiple planes PLNs for which a write operation is executed collectively (for example, in parallel). More specifically, the valid cluster search circuit 27 calculates the total time tR+tDout for each plane PLN. Then, the valid cluster search circuit 27 determines the priority based on the calculation result. The valid cluster search circuit 27 transmits the determined priority to the scheduler 28.

[0117] The scheduler 28 schedules read operations in each plane PLN based on the available cluster pool and the priority (S16). More specifically, the scheduler 28 receives commands for various operations, such as write operations, read operations, erase operations, and garbage collection, from the CPU 22. The scheduler 28 adjusts the schedules of these operations to determine the timing of garbage collection. When performing garbage collection, the scheduler 28 then determines the schedules for cell read operations and data output operations in each plane PLN based on the available cluster pool and priority.

[0118] Based on the instruction of the scheduler, the NAND controller 29 transmits a command requesting a cell read operation to the target memory chip 11 (S17).

[0119] Upon receiving the command, the sequencer 105 executes a cell read operation (S18).

[0120] The NAND controller 29 transmits a command requesting a data output operation to the target memory chip 11 in accordance with the priority (S19).

[0121] Upon receiving the command, the sequencer 105 executes the data output operation (S20). When the data output operation for all valid clusters CT is completed, the read operation is completed.

[0122] 1.6 Effects of this embodiment The configuration according to this embodiment can provide a memory system with improved processing capabilities. The effects of this embodiment will be described in detail below.

[0123] For example, in garbage collection, when data is read from multiple plane PLNs via a single NAND bus, the data output operation may be performed using a round-robin method. That is, plane PLNs that are ready to output data output data one by one in turn, one by one, of the valid clusters CT. For example, in garbage collection, the number of valid clusters CT to be read varies for each plane PLN. Furthermore, the total time for the cell read operation and the data output operation also varies. For this reason, when the round-robin method is applied, even the plane PLN with the longest total time will experience a wait state, just like the other plane PLNs. This increases the overall processing time for the read operation.

[0124] In contrast, with the configuration according to this embodiment, the memory controller 20 can calculate the total tR+tDout time for each plane PLN. The memory controller 20 can determine the priority of the data output operation for each plane PLN in descending order of the total tR+tDout time. The memory controller 20 can then request the data output operation based on the priority. By giving priority to the data output operation for the plane PLN with the longest total tR+tDout time, the memory controller 20 can suppress the occurrence of a wait state in that plane PLN and suppress an increase in the overall processing time for the read operation of the valid cluster CT. This can improve the processing capacity of the memory system 3.

[0125] 2. Second embodiment Next, a second embodiment will be described. In the second embodiment, a method of determining priority different from that of the first embodiment will be described. The following description will focus on the differences from the first embodiment.

[0126] 2.1 Example of determining the priority of data output operations First, a specific example of priority determination for data output operations will be described with reference to Fig. 12. Fig. 12 is a diagram showing a specific example of priority determination. The example shown in Fig. 12 shows cluster maps of four planes PLN0 to PLN3. The example shown in Fig. 12 also shows a case where a block BLK of each plane PLN includes eight pages PG, and one page PG includes four clusters CT.

[0127] 12, similarly to the diagram shown in FIG. 9, the order of the lengths of the tR+tDout total time is PLN1>PLN2>PLN0>PLN3. As shown in FIG. 12, in this embodiment, the valid cluster search circuit 27 assigns the first priority to the plane PLN1 having the longest tR+tDout total time, and assigns the second priority to the other planes PLN0, PLN2, and PLN3. That is, the valid cluster search circuit 27 preferentially executes the data output operation of the plane PLN having the longest tR+tDout total time. Note that in the example shown in FIG. 12, the valid cluster search circuit 27 calculates all of the tR+tDout total times of the planes PLN0 to PLN3 and compares the lengths of the tR+tDout total times of each plane PLN, but this is not limiting. Since it is sufficient to determine the plane PLN with the longest total tR+tDout time, calculation of the total tR+tDout time may be omitted for planes PLNs with a relatively small number of valid clusters CT (for example, planes PLN0 and PLN3).

[0128] 2.2 Timing chart of a specific example of a priority-based read operation Next, a timing chart of a specific example of a read operation based on priority will be described with reference to Fig. 13. Fig. 13 is a timing chart showing a specific example of a read operation based on priority. Note that the example shown in Fig. 13 shows a case where a cell read operation and a data output operation are performed based on the cluster map and priority explained using Fig. 12. Also, to simplify the explanation, the period during which a command is sent from the memory controller 20 to the memory chip 11 is omitted. Furthermore, to simplify the explanation, a case where the period tR of each cell read operation is the same is shown.

[0129] 13, in this embodiment, the data output operation of the plane PLN1, which has the highest priority, is executed preferentially, and the data output operations of the planes PLN0, PLN2, and PLN3, which have the second highest priority, are executed in a round-robin manner.

[0130] The timing of each read operation will be specifically described below. First, regardless of priority, the planes PLN0 to PLN3 each execute a first cell read operation R1 for page PG0 in parallel. After the first cell read operation R1 is completed, the plane PLN1 (priority: 1st) executes a data output operation D1 for one valid cluster CT included in page PG0. After the first cell read operation R1 is completed, the planes PLN0, PLN2, and PLN3 enter a standby state until they are able to execute a data output operation. After the data output operation D1 is completed, the plane PLN1 executes a second cell read operation R2 for page PG2. After the data output operation D1 of the plane PLN1 is completed, the standby planes PLN0, PLN2, and PLN3 execute data output operations based on the round-robin method. First, the plane PLN2 executes a data output operation D1 for the first valid cluster CT of the two valid clusters CT included in page PG0. When the data output operation D1 of plane PLN2 is completed, plane PLN3 executes a data output operation D1 for one valid cluster CT included in page PG0. After the data output operation D1 is completed, plane PLN3 executes a second cell read operation R2 for page PG1. Also, when the data output operation D1 of plane PLN3 is completed, plane PLN0 executes a data output operation D1 for one valid cluster CT included in page PG0. After the data output operation D1 of plane PLN0 is completed, plane PLN0 executes a second cell read operation R2 for page PG1. Also, when the data output operation D1 of plane PLN0 is completed, plane PLN2 executes a data output operation D2 for the second valid cluster CT of the two valid clusters CT included in page PG0. After the data output operation D2 is completed, plane PLN2 executes a second cell read operation R2 for page PG1.

[0131] After completing the second cell read operation R2, plane PLN1 sequentially executes data output operations D2, D3, and D4 for the three valid clusters CT included in page PG2. After completing data output operation D4, plane PLN1 executes the third cell read operation R3 for page PG3. After completing data output operation D4 for plane PLN1, data output operations for planes PLN0, PLN2, and PLN3 are executed in a round-robin fashion. First, plane PLN3, which is in a standby state, executes data output operation D2 for the first valid cluster CT of the three valid clusters CT included in page PG1. After completing data output operation D2 for plane PLN3, plane PLN0 executes data output operation D2 for the first valid cluster CT of the two valid clusters CT included in page PG1. After completing data output operation D2 for plane PLN0, plane PLN2 executes data output operation D3 for the first valid cluster CT of the two valid clusters CT included in page PG1. When the data output operation D3 of the plane PLN2 is completed, the plane PLN3 executes a data output operation D3 for the second valid cluster CT of the three valid clusters CT included in the page PG1. When the data output operation D3 of the plane PLN3 is completed, the plane PLN0 executes a data output operation D3 for the second valid cluster CT of the two valid clusters CT included in the page PG1. After the data output operation D3 is completed, the plane PLN0 executes a third cell read operation R3 for the page PG2. Furthermore, when the data output operation D3 of the plane PLN0 is completed, the plane PLN2 executes a data output operation D4 for the second valid cluster CT of the two valid clusters CT included in the page PG1. After the data output operation D4 of the plane PLN2 is completed, the plane PLN3 executes a data output operation D4 for the third valid cluster CT of the three valid clusters CT included in the page PG1.After the data output operation D4 is completed, the plane PLN3 executes the third cell read operation R3 for the page PG2.

[0132] After completing the third cell read operation R3, the plane PLN1 sequentially executes data output operations D5, D6, and D7 for the three valid clusters CT included in page PG3. After completing the data output operation D7, the plane PLN1 executes the fourth cell read operation R4 for page PG4. For example, while the plane PLN1 is executing the cell read operation R4, the cell read operation R3 of the plane PLN0 is completed. Then, the plane PLN0 executes the data output operation D4 for the first valid cluster CT of the three valid clusters CT included in page PG2. After completing the data output operation D4 of the plane PLN0, the plane PLN2 executes the data output operation D5 for the first valid cluster CT of the two valid clusters CT included in page PG2. After completing the data output operation D5 of the plane PLN2, the plane PLN3 executes the data output operation D5 for the first valid cluster CT of the two valid clusters CT included in page PG2. When the data output operation D5 of plane PLN3 is completed, plane PLN0 executes a data output operation D5 for the second valid cluster CT of the three valid clusters CT included in page PG2. When the data output operation D5 of plane PLN0 is completed, plane PLN2 executes a data output operation D6 for the second valid cluster CT of the two valid clusters CT included in page PG2. After the data output operation D6 is completed, plane PLN2 executes a fourth cell read operation R4 for page PG3. Furthermore, when the data output operation D6 of plane PLN2 is completed, plane PLN3 executes a data output operation D6 for the second valid cluster CT of the two valid clusters CT included in page PG2. After the data output operation D6 is completed, plane PLN3 executes a fourth cell read operation R4 for page PG3. For example, by the time plane PLN3 completes the data output operation D6, the fourth cell read operation R4 of plane PLN1 is completed. Then, even if plane PLN0 is in a standby state, the data output operation of plane PLN1 is executed preferentially.

[0133] After completing the fourth cell read operation R4, plane PLN1 successively executes data output operations D8, D9, and D10 for the three valid clusters CT included in page PG4. After completing data output operation D10, plane PLN1 executes the fifth cell read operation R5 for page PG5. After completing data output operation D10 for plane PLN1, plane PLN0 executes data output operation D6 for the third valid cluster CT of the three valid clusters CT included in page PG2. After completing data output operation D6, plane PLN0 executes the fourth cell read operation R4 for page PG3. After completing the fourth cell read operation R4, plane PLN2 executes data output operation D7 for one valid cluster CT included in page PG3. After completing data output operation D7, plane PLN2 executes the fifth cell read operation R5 for page PG4. After completing data output operation D7 for plane PLN2, plane PLN3 executes data output operation D7 for one valid cluster CT included in page PG3. After the data output operation D7 is completed, the plane PLN3 executes the fifth cell read operation R5 for the page PG4.

[0134] After completing the fifth cell read operation R5, plane PLN1 successively executes data output operations D11 and D12 for two valid clusters CT included in page PG5. After completing data output operation D12, plane PLN1 executes the sixth cell read operation R6 for page PG6. For example, after completing data output operation D12 for plane PLN1, plane PLN0, which was in a standby state, executes data output operation D7 for the first valid cluster CT of two valid clusters CT included in page PG3. Because planes PLN2 and PLN3 were executing cell read operation R5 when plane PLN0 completed data output operation D7, plane PLN0 successively executes data output operation D8 for the second valid cluster CT of two valid clusters CT included in page PG3. After completing data output operation D8, plane PLN0 executes the fifth cell read operation R5 for page PG4. Furthermore, after completing data output operation D8 for plane PLN0, plane PLN2 executes data output operation D8 for one valid cluster CT included in page PG4. After completing the data output operation D8, plane PLN2 executes the sixth cell read operation R6 for page PG5. Also, when the data output operation D8 of plane PLN2 is completed, plane PLN3 executes the data output operation D8 for one valid cluster CT included in page PG4. When plane PLN3 completes the data output operation D8, it completes the read operation.

[0135] After completing the sixth cell read operation R6, the plane PLN1 executes a data output operation D13 for one valid cluster CT included in page PG6. After completing the data output operation D13, the plane PLN1 executes a seventh cell read operation R7 for page PG7. After that, for example, after completing the fifth cell read operation R5, the plane PLN0 executes a data output operation D9 for the first valid cluster CT of the three valid clusters CT included in page PG4. Because the plane PLN2 was executing the cell read operation R6 when the plane PLN0 completed the data output operation D9, the plane PLN0 subsequently executes a data output operation D10 for the second valid cluster CT of the three valid clusters CT included in page PG4. After completing the data output operation D10 for the plane PLN0, the plane PLN2, which had been in a standby state, executes a data output operation D9 for the first valid cluster CT of the two valid clusters CT included in page PG5. When the data output operation D9 of plane PLN2 is completed, plane PLN0 executes a data output operation D11 for the third valid cluster CT of the three valid clusters CT included in page PG4. When plane PLN0 completes the data output operation D11, it completes the read operation. When plane PLN0 completes the data output operation D11, plane PLN2 executes a data output operation D10 for the second valid cluster CT of the two valid clusters CT included in page PG5. When plane PLN2 completes the data output operation D10, it completes the read operation.

[0136] After completing the seventh cell read operation R7, the plane PLN1 executes data output operations D14, D15, and D16 for the three valid clusters CT included in page PG7. After completing the data output operation D16, the plane PLN1 completes the read operation.

[0137] 2.3 Effects of this embodiment The configuration according to this embodiment provides the same effects as those of the first embodiment.

[0138] Furthermore, with the configuration according to this embodiment, it is sufficient to select one plane PLN with the highest priority. Therefore, for example, for a plane PLN with a relatively small number of valid clusters CT, the calculation of the total time tR+tDout can be omitted. In other words, the determination of priority can be simplified.

[0139] 3. Third embodiment Next, a third embodiment will be described. In the third embodiment, a case where the NAND controller 29 executes priority determination and scheduling will be described. The following mainly describes the differences from the first and second embodiments.

[0140] 3.1 Memory System Configuration First, an example of the configuration of the memory system 3 will be described with reference to Fig. 14. Fig. 14 is a block diagram showing an example of the overall configuration of the data processing device 1.

[0141] As shown in Fig. 14, the overall configuration of the data processing device 1 of this embodiment is the same as the overall configuration of the data processing device 1 of the first embodiment described using Fig. 1. In this embodiment, the internal configuration of the memory controller 20 is different from that of the first embodiment. The following describes the configuration that is different from that of the first embodiment.

[0142] The RAM 24 includes one or more command queues CQ. Each of the one or more command queues CQ corresponds to one or more NAND controllers 29. The command queues CQ are used when the CPU 22 issues commands to the memory chips 11 to perform various operations. The command queues CQ store commands to be sent to the corresponding NAND controllers 29. For example, the command queues CQ have multiple entries corresponding to multiple commands. The command queues CQ may be provided within the NAND controllers 29.

[0143] The scheduler 28 stores a plurality of commands, such as a write operation, a read operation, and an erase operation, received from the CPU 22 in a command queue CQ corresponding to the NAND controller 29 in question.

[0144] The NAND controller 29 includes a channel scheduler 201. The channel scheduler 201 is a circuit that adjusts the schedule of operations executed by the memory chips 11 connected to the corresponding channels CH. In the example shown in FIG. 14, the NAND controller 29_0 includes a channel scheduler 201_0. The NAND controller 29_1 includes a channel scheduler 201_1. Hereinafter, when there is no need to specify either the channel scheduler 201_0 or 201_1, it will be simply referred to as the "channel scheduler 201." For example, the channel scheduler 201 schedules commands to be executed by the corresponding memory chips 11 based on commands received from the command queue CQ. The NAND controller 29 transmits commands to the memory chips 11 based on the adjustment by the channel scheduler 201.

[0145] The NAND controller 29 controls the timing of commands sent from the command queue CQ to the channel scheduler 201 so as to prevent multiple commands from conflicting with each other (hereinafter also referred to as "exclusive control"). More specifically, for example, if a command for a read operation and a command for a write operation to be executed in one plane PLN are stored in the command queue CQ, the read operation and the write operation cannot be executed simultaneously, so it can be said that the two commands are in a conflicting state. For example, the NAND controller 29 first sends the read operation command to the channel scheduler 201. Then, after the read operation in the memory chip 11 is completed, the NAND controller 29 sends the write operation command from the command queue CQ to the channel scheduler 201.

[0146] In this embodiment, the NAND controller 29 determines the priority of the data output operation.

[0147] 3.2 Example of a command queue Next, a specific example of the command queue CQ will be described with reference to Fig. 15. Fig. 15 is a diagram showing a specific example of the command queue CQ.

[0148] As shown in Fig. 15, the command queue CQ stores a plurality of instructions (commands) and corresponding NAND addresses. For example, the commands are assigned identification numbers ((A) to (J) in the example shown in Fig. 15) in the order they are input to the command queue CQ, so that the same instructions can be distinguished from one another. In the example shown in Fig. 15, the items of the NAND address include the number of the memory chip 11, the plane PLN, and the page PG. Note that information such as the block BLK or the cluster CT may also be stored as information on the NAND address.

[0149] More specifically, for example, the command "Read(A)" is a read command for page PG0 of plane PLN0 of memory chip 11_0. The command "Read(B)" is a read command for page PG1 of plane PLN1 of memory chip 11_1. The command "Read(C)" is a read command for page PG0 of plane PLN0 of memory chip 11_1. The command "Read(D)" is a read command for page PG0 of plane PLN0 of memory chip 11_0. The command "Write(E)" is a write command for page PG0 of plane PLN0 of memory chip 11_1. The command "Read(F)" is a read command for page PG0 of plane PLN1 of memory chip 11_1. The command "Read(G)" is a read command for page PG0 of plane PLN0 of memory chip 11_1. The command "Read(H)" is a read command for page PG1 of plane PLN0 of memory chip 11_0. The command "Read(I)" is a read command for page PG0 of plane PLN0 of memory chip 11_1. The command "Read(J)" is a read command for page PG0 of plane PLN1 of memory chip 11_0.

[0150] 3.3 Example of Prioritization and Scheduling Next, a specific example of priority determination and scheduling will be described with reference to Fig. 16. Fig. 16 is a diagram showing a specific example of priority determination and scheduling in the NAND controller 29.

[0151] In the first embodiment, the case where the valid cluster search circuit 27 determines the priority has been described. In the first embodiment, the scheduler 28 performs scheduling for the entire nonvolatile memory 10 based on the priority. In contrast, in the present embodiment, the NAND controller 29 determines the priority based on the command queue CQ. Then, the channel scheduler 201 adjusts the schedule of commands to be sent to the memory chip 11 based on the priority.

[0152] As shown in FIG. 16, the NAND controller 29 calculates the total tR+tDout time for each plane PLN based on, for example, the commands in the command queue CQ shown in FIG. 15. Then, the NAND controller 29 determines the priority based on the calculation result. In the example shown in FIG. 16, planes PLN0 and PLN1 of the memory chip 11_0 and planes PLN0 and PLN1 of the memory chip 11_1 are selected as read targets for garbage collection. The NAND controller 29 calculates the total tR+tDout time for each plane PLN by referring to the command queue CQ. Here, it is assumed that the total tR+tDout time for the plane PLN0 of the memory chip 11_0 is 80, the total tR+tDout time for the plane PLN1 of the memory chip 11_0 is 60, the total tR+tDout time for the plane PLN0 of the memory chip 11_1 is 100, and the total tR+tDout time for the plane PLN1 of the memory chip 11_1 is 70. Then, based on the calculation results, the NAND controller 29 sets the priority of plane PLN0 of memory chip 11_1 to first, the priority of plane PLN0 of memory chip 11_0 to second, the priority of plane PLN1 of memory chip 11_1 to third, and the priority of plane PLN1 of memory chip 11_0 to fourth.

[0153] The NAND controller 29 transmits the commands in the command queue CQ to the channel scheduler 201. At this time, if the plane PLN targeted by the commands is the same and there is a conflict between the processes, the NAND controller 29 does not transmit the next command until the previously executed process is completed. Note that if the target page of the previously executed read operation and the target page of the later executed read operation are the same (for example, if the target clusters CT are different), the data read into the data register 114 in one cell read operation can be shared between these read operations, so there is no conflict between these read operations.

[0154] Furthermore, the NAND controller 29 subdivides and transmits a command when transmitting the command from the command queue CQ to the channel scheduler 201. Specifically, for example, the NAND controller 29 subdivides a read operation command "Read" into a cell read operation command "Sense" and a data output operation command "Dataout."

[0155] Furthermore, the NAND controller 29 may consolidate commands sent to the channel scheduler 201. For example, if there are multiple read operation commands “Read” in the command queue CQ that target the same page PG but different clusters CT, the NAND controller 29 transmits the consolidated single command “Sense” and multiple commands “Dataout” to the channel scheduler 201.

[0156] More specifically, for example, in response to the command “Read(A)” and the command “Read(D)” of the same target page PG, the NAND controller 29 transmits the command “Sense(A)”, the command “Dataout(A)”, and the command “Dataout(D)” to the channel scheduler 201. The NAND controller 29 transmits the command “Sense(B)” and the command “Dataout(B)”, which are obtained by subdividing the command “Read(B)”, to the channel scheduler 201. In response to the command “Read(C)”, the command “Read(G)”, and the command “Read(I)” of the same target page PG, the NAND controller 29 transmits the command “Sense(C)”, the command “Dataout(C)”, the command “Dataout(G)”, and the command “Dataout(I)” to the channel scheduler 201. Furthermore, the NAND controller 29 transmits to the channel scheduler 201 a command “Sense(J)” and a command “Dataout(J)” that are obtained by subdividing the command “Read(J)”.

[0157] Since other commands conflict with previously transmitted commands, they are not transmitted to the channel scheduler 201 until the processing of the previously transmitted command is completed. For example, the target plane PLN of the command "Write(E)" is the same as that of the command "Read(C)". Therefore, the command "Write(E)" is not transmitted to the channel scheduler 201 until the processing of the command "Read(C)" is completed. The target page PG of the command "Read(F)" is different from that of the command "Read(B)", but the target plane PLN is the same as that of the command "Read(B)". Therefore, the command "Read(F)" is not transmitted to the channel scheduler 201 until the processing of the command "Read(B)" is completed. The target page PG of the command "Read(H)" is different from that of the command "Read(A)", but the target plane PLN is the same as that of the command "Read(A)". Therefore, the command "Read(H)" is not transmitted to the channel scheduler 201 until the processing of the command "Read(A)" is completed.

[0158] The channel scheduler 201 determines the transmission order of commands based on priority. First, since cell read operations can be executed in parallel between planes PLN, the channel scheduler 201 assigns the commands "Sense(A)", "Sense(B)", "Sense(C)", and "Sense(J)" as first to fourth in the transmission order. Note that the order of these four may be interchanged. Next, the channel scheduler 201 assigns the commands "Dataout(C)", "Dataout(G)", and "Dataout(I)" corresponding to the plane PLN0 of the memory chip 11_1, which has the first priority, as fifth to seventh in the transmission order. Note that the order of these three may be interchanged. Next, the channel scheduler 201 assigns the commands "Dataout(A)" and "Dataout(D)" corresponding to the plane PLN0 of the memory chip 11_0, which has the second priority, as eighth and ninth in the transmission order. Note that these two orders may be interchanged. Next, the channel scheduler 201 assigns the command "Dataout(B)" corresponding to the plane PLN1 of the memory chip 11_1, which has the third highest priority, as the tenth command in the transmission order. Then, the channel scheduler 201 assigns the command "Dataout(J)" corresponding to the plane PLN1 of the memory chip 11_0, which has the fourth highest priority, as the eleventh command in the transmission order.

[0159] 3.4 Garbage Collection Read Operation Flow Next, an example of the flow of a read operation in garbage collection will be described with reference to Fig. 17. Fig. 17 is a flowchart showing an example of a read operation in garbage collection.

[0160] The procedures from S10 to S14 are the same as those in the first embodiment described with reference to FIG.

[0161] After S14, the scheduler 28 performs overall scheduling (S30). More specifically, the scheduler 28 receives commands for various operations such as write operations, read operations, erase operations, and garbage collection from the CPU 22. The scheduler 28 determines the schedule for these operations for each channel CH.

[0162] Based on the scheduling result, commands are stored in the command queue CQ corresponding to each channel CH (S31).

[0163] The NAND controller 29 determines the priority of the data output operation for each plane PLN by referring to the corresponding command queue CQ (S32). The NAND controller 29 transmits the determined priority to the channel scheduler 201.

[0164] The NAND controller 29 transmits commands obtained by dividing the command in the command queue CQ to the channel scheduler 201 based on the exclusive control (S33).

[0165] The channel scheduler 201 schedules the received commands based on the priority (S34).

[0166] The procedures from S17 to S20 are the same as those in the first embodiment described with reference to FIG.

[0167] 3.5 Effects of this embodiment The effects according to this embodiment are similar to those of the first embodiment.

[0168] In this embodiment, as in the first embodiment, the priorities of four plane PLNs are determined from 1st to 4th, but the present invention is not limited to this. For example, as in the second embodiment, one plane PLN may be determined as having a high priority, and the other plane PLNs may be assigned the same priority.

[0169] 4. Modifications, etc. The memory system according to the embodiment includes a nonvolatile memory (10) including a plurality of memory areas (planes PLN), each having a memory cell array (111), including at least a first memory area (plane PLN0) and a second memory area (plane PLN1) different from the first memory area, and a memory controller (20) that controls the nonvolatile memory. A data read operation from the nonvolatile memory includes a first operation (cell read operation) that reads data from the memory cell array and a second operation (data output operation) that transmits at least a portion of the read data to the memory controller. When the memory controller executes read operations in the first memory area and the second memory area in parallel, the memory controller determines the priority of the second operation in the first memory area and the second operation in the second memory area based on a result of comparing a first total time of the time required for the first operation and the time required for the second operation in the second memory area and a second total time of the time required for the first operation and the time required for the second operation in the second memory area.

[0170] The above embodiment can provide a memory system with improved processing capabilities.

[0171] The embodiment is not limited to the above-described embodiment, and various modifications are possible.

[0172] For example, in the first embodiment, the four planes PLN0 to PLN3 of one memory chip 11 execute the read operation of the valid cluster CT, but the present invention is not limited to this. For example, each plane PLN of the four memory chips C11_0 to C11_3 connected to the channel CH0 may execute the read operation of the valid cluster CT.

[0173] For example, in the above embodiment, the read operation in garbage collection has been described, but the present invention is not limited to this. The above embodiment can be applied to a case where read operations are performed in parallel in multiple planes PLN connected to one channel CH.

[0174] Furthermore, the term "connected" in the above embodiments also includes a state in which something else, such as a transistor or a resistor, is interposed between them and indirectly connected.

[0175] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0176] 1...Data processing device 2...Host device 3. Memory system 10...Non-volatile memory 11...Memory chip 20...Memory controller 21...Host interface circuit 22...CPU 23...ROM 24...RAM 25...Buffer memory 26...Block Management Department 27...Valid cluster search circuit 28...Scheduler 29...NAND controller 101...input / output circuit 102...Logic control circuit 103...Address register 104...Command register 105...Sequencer 106...Ready / Busy circuit 111...Memory cell array 112...Row decoder 113...Sense amplifier 114...Data register 115...Column decoder 201...Channel Scheduler

Claims

1. a non-volatile memory including a plurality of memory regions, each having a memory cell array, including at least a first memory region and a second memory region different from the first memory region; a memory controller that controls the nonvolatile memory; Equipped with the operation of reading data from the nonvolatile memory includes a first operation of reading data from the memory cell array and a second operation of transmitting at least a portion of the read data to the memory controller; The memory controller when the read operations in the first memory area and the second memory area are executed in parallel, determining priorities of the second operation in the first memory area and the second operation in the second memory area based on a result of comparing a first total time of a time required for the first operation and a time required for the second operation in the first memory area with a second total time of a time required for the first operation and a time required for the second operation in the second memory area; Memory system.

2. The memory controller calculating the first total time based on a first search result of valid clusters to be read by the read operation from the first memory area, and calculating the second total time based on a second search result of valid clusters to be read by the read operation from the second memory area; 10. The memory system of claim 1.

3. The memory controller adjusting a schedule so that the second operation in the first memory region is executed with priority over the second operation in the second memory region when the first total time is longer than the second total time; 3. The memory system according to claim 1.

4. the plurality of memory areas further includes a third memory area different from the first memory area and the second memory area; The memory controller when the read operations in the first memory area, the second memory area, and the third memory area are executed in parallel, based on a result of comparing the first total time, the second total time, and a third total time of the time required for the first operation and the time required for the second operation in the third memory area, the priority of any one of the second operation in the first memory area, the second operation in the second memory area, and the second operation in the third memory area is set higher than the other two; 10. The memory system of claim 1.

5. the memory controller includes a command queue configured to store a plurality of first commands to be executed in the first memory region and a plurality of second commands to be executed in the second memory region; the memory controller establishes the priority based on the plurality of first commands and the plurality of second commands; 10. The memory system of claim 1.

6. The memory controller calculating the first total time based on the plurality of first commands stored in the command queue, and calculating the second total time based on the plurality of second commands stored in the command queue; adjusting a schedule so that the first commands are sent from the command queue to the nonvolatile memory before the second commands are sent when the first total time is longer than the second total time; 6. The memory system of claim 5.

7. Each of the plurality of memory areas further includes a data register; the first operation is an operation in which data read from the memory cell array is stored in the data register; the second operation is an operation of transmitting data read from the data register to the memory controller; 7. The memory system according to claim 1.

8. the data read from the memory cell array in the first operation has a first size; the data read from the data register in the second operation has a second size smaller than the first size; 8. The memory system of claim 7.

9. The memory controller When data to be read to the memory controller is stored in the data register of the first memory area and the data register of the second memory area, and the priority of the second operation in the first memory area is determined to be higher than the priority of the second operation in the second memory area, causing the second memory area to wait until the execution of the second operation in the first memory area is completed, and executing the second operation in the second memory area after the execution of the second operation in the first memory area is completed.

8. The memory system of claim 7.

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