semiconductor memory device

Abstract

To provide a semiconductor storage device that improves reliability.SOLUTION: According to an embodiment, a semiconductor storage device includes: a memory cell array 17 including a plurality of memory cells MC; a word line WL connected to the plurality of memory cells; a plurality of bit lines BL each connected to the plurality of memory cells; a sense amplifier 19 connected to the plurality of bit lines; and a controller 14 capable of executing a write operation including repeating a program loop including a program operation and a verify operation. While the program voltage VPGM is applied to the word line in the program operation, the sense amplifier applies each of the plurality bit lines with a first voltage VSS, a second voltage VQPW1 higher than the first voltage, a third voltage VQPW2 higher than the second voltage, and a fourth voltage VHSA higher than the third voltage.SELECTED DRAWING: Figure 14

Description

[Technical Field]

[0001] FIELD Embodiments of the present invention relate to a semiconductor memory device. [Background technology]

[0002] NAND flash memory is known as a semiconductor memory device. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2021-47953 [Patent Document 2] Japanese Patent Publication No. 2020-102291 Summary of the Invention [Problem to be solved by the invention]

[0004] One embodiment of the present invention provides a semiconductor memory device with improved reliability. [Means for solving the problem]

[0005] A semiconductor memory device according to an embodiment includes a memory cell array including a plurality of memory cells, word lines connected to the plurality of memory cells, a plurality of bit lines each connected to the plurality of memory cells, a sense amplifier connected to the plurality of bit lines, and a controller capable of performing a write operation including a repetition of a program loop including a program operation and a verify operation. During the program operation, while a program voltage is applied to the word lines, the sense amplifier applies one of a first voltage, a second voltage higher than the first voltage, a third voltage higher than the second voltage, or a fourth voltage higher than the third voltage to each of the plurality of bit lines. The verify operation includes a first verify operation based on a first verify voltage, a second verify operation based on a second verify voltage higher than the first verify voltage, and a third verify operation based on a third verify voltage higher than the second verify voltage. The plurality of memory cells include a first memory cell whose threshold voltage is determined to be equal to or lower than the first verify voltage in the first verify operation, and a second memory cell whose threshold voltage is determined to exceed the first verify voltage. In a program operation, the sense amplifier applies a second voltage to a bit line connected to a first memory cell whose threshold voltage exceeds the second verify voltage and is equal to or lower than the third verify voltage, among the plurality of bit lines, and applies a third voltage to a bit line connected to a second memory cell whose threshold voltage exceeds the second verify voltage and is equal to or lower than the third verify voltage. [Brief explanation of the drawings]

[0006] [Figure 1]FIG. 1 is a block diagram showing the overall configuration of a semiconductor memory device according to the first embodiment. [Figure 2] FIG. 2 is a circuit diagram of a memory cell array included in the semiconductor memory device according to the first embodiment. [Figure 3] FIG. 3 is a block diagram of a data register and a sense amplifier included in the semiconductor memory device according to the first embodiment. [Figure 4] FIG. 4 is a circuit diagram of a sense amplifier unit included in the semiconductor memory device according to the first embodiment. [Figure 5] FIG. 5 is a circuit diagram of a voltage generating circuit and a sense circuit included in the semiconductor memory device according to the first embodiment. [Figure 6] FIG. 6 is a conceptual diagram showing an example of a data storage method in the semiconductor memory device according to the first embodiment. [Figure 7] FIG. 7 is a timing chart showing an outline of the write operation in the semiconductor memory device according to the first embodiment. [Figure 8] FIG. 8 is a table showing an example of program loop settings in the semiconductor memory device according to the first embodiment. [Figure 9] FIG. 9 is a threshold voltage distribution diagram showing the relationship between three types of verify voltages used for each write state and three types of program operations in the write operation in the semiconductor memory device according to the first embodiment. [Figure 10] FIG. 10 is a conceptual diagram showing the fluctuations in threshold voltage of fast and slow cells during a write operation in the semiconductor memory device according to the first embodiment. [Figure 11] FIG. 11 is a timing chart showing the voltage of the word line WLsel and the voltage of the bit line BL in the program operation in the semiconductor memory device according to the first embodiment. [Figure 12] FIG. 12 is a table showing an example of the setting of the verify voltage in the semiconductor memory device according to the first embodiment. [Figure 13]FIG. 13 is a diagram showing the relationship between the number of program loops in a write operation and the VL1 verify operation in the semiconductor memory device according to the first embodiment. [Figure 14] FIG. 14 is a timing chart showing various wirings and various signals in a program operation in the semiconductor memory device according to the first embodiment. [Figure 15] FIG. 15 is a diagram showing the operations of the voltage generating circuit and the sense amplifier unit in a program operation in the semiconductor memory device according to the first embodiment. [Figure 16] FIG. 16 is a diagram showing the operations of the voltage generating circuit and the sense amplifier unit in a program operation in the semiconductor memory device according to the first embodiment. [Figure 17] FIG. 17 is a diagram showing the operations of the voltage generating circuit and the sense amplifier unit in a program operation in the semiconductor memory device according to the first embodiment. [Figure 18] FIG. 18 is a diagram showing the operations of the voltage generating circuit and the sense amplifier unit in a program operation in the semiconductor memory device according to the first embodiment. [Figure 19] FIG. 19 is a diagram showing the operations of the voltage generating circuit and the sense amplifier unit in the program operation in the semiconductor memory device according to the first embodiment. [Figure 20] FIG. 20 is a flowchart of the write operation in the semiconductor memory device according to the first embodiment. [Figure 21] FIG. 21 is a table showing an example of the setting of the verify voltage in the semiconductor memory device according to the first example of the second embodiment. [Figure 22] FIG. 22 is a diagram showing the relationship between the number of program loops in a write operation and the VL1 verify operation in a semiconductor memory device according to a first example of the second embodiment. [Figure 23] FIG. 23 is a table showing an example of the setting of the verify voltage in a semiconductor memory device according to the second example of the second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments will be described with reference to the drawings. In this description, components having substantially the same functions and configurations will be designated by the same reference numerals. Furthermore, each embodiment shown below exemplifies an apparatus or method for embodying the technical concept of the embodiment, and the technical concept of the embodiment does not limit the material, shape, structure, arrangement, etc. of the components to those described below. The technical concept of the embodiment can be modified in various ways within the scope of the claims.

[0008] 1. First embodiment A semiconductor memory device 1 according to the first embodiment will be described. The semiconductor memory device 1 is a NAND flash memory capable of storing data in a nonvolatile manner. The semiconductor memory device 1 according to the first embodiment will be described below. Note that the semiconductor memory device 1 is not limited to a NAND flash memory. The semiconductor memory device 1 may be another nonvolatile memory.

[0009] 1.1 Configuration 1.1.1 Overall configuration of semiconductor memory device First, an example of the overall configuration of a semiconductor memory device will be described with reference to Fig. 1. Fig. 1 is a block diagram showing the basic overall configuration of a semiconductor memory device. Note that in Fig. 1, some of the connections between the components are indicated by arrows, but the connections between the components are not limited to this.

[0010] As shown in Fig. 1, a semiconductor memory device 1 is configured to be controllable by an external memory controller 2. For example, the semiconductor memory device 1 transmits and receives a signal DQ and timing signals DQS and DQSn to and from the memory controller 2. The signal DQ is, for example, data DAT, an address ADD, or a command CMD. The timing signals DQS and DQSn are timing signals used when inputting and outputting data DAT. The timing signal DQSn is an inverted signal of the timing signal DQS.

[0011] The semiconductor memory device 1 also receives various control signals from the memory controller 2. The semiconductor memory device 1 then transmits a ready / busy signal RBn to the memory controller 2. The ready / busy signal RBn is a signal that indicates whether the semiconductor memory device 1 is in a state where it cannot receive a command CMD from the memory controller 2 (busy state) or can receive a command CMD from the memory controller 2 (ready state).

[0012] The semiconductor memory device 1 includes an input / output circuit 10, a logic control circuit 11, an address register 12, a command register 13, a sequencer 14, a ready / busy circuit 15, a voltage generation circuit 16, a memory cell array 17, a row decoder 18, a sense amplifier 19, a data register 20, and a column decoder 21.

[0013] The input / output circuit 10 is a circuit that inputs and outputs a signal DQ. The input / output circuit 10 is connected to the memory controller 2. The input / output circuit 10 is also connected to a logic control circuit 11, an address register 12, a command register 13, and a data register 20.

[0014] When the input signal DQ is an address ADD, the input / output circuit 10 transmits the address ADD to the address register 12. When the input signal DQ is a command CMD, the input / output circuit 10 transmits the command CMD to the command register 13.

[0015] When the input signal DQ is data DAT, the input / output circuit 10 receives the input signal DQ based on the timing signals DQS and DQSn. Then, the input / output circuit 10 transmits the data DAT to the data register 20. The input / output circuit 10 also outputs the data DAT to the memory controller 2 together with the timing signals DQS and DQSn.

[0016] The logic control circuit 11 is a circuit that performs logic control based on control signals. The logic control circuit 11 is connected to the memory controller 2. The logic control circuit 11 is also connected to the input / output circuit 10 and the sequencer 14. The logic control circuit 11 receives a plurality of control signals from the memory controller 2. The logic control circuit 11 controls the input / output circuit 10 and the sequencer 14 based on the received control signals.

[0017] The address register 12 is a register that temporarily stores an address ADD. The address register 12 is connected to the input / output circuit 10, a row decoder 18, and a column decoder 21. The address ADD includes a row address RA and a column address CA. The address register 12 transfers the row address RA to the row decoder 18. The address register 12 also transfers the column address CA to the column decoder 21.

[0018] The command register 13 is a register that temporarily stores the command CMD. The command register 13 is connected to the input / output circuit 10 and the sequencer 14. The command register 13 transfers the command CMD to the sequencer 14.

[0019] The sequencer 14 is a circuit (controller) that controls the semiconductor memory device 1. The sequencer 14 controls the overall operation of the semiconductor memory device 1. The sequencer 14 can function as a controller for the semiconductor memory device 1. For example, the sequencer 14 controls a ready / busy circuit 15, a voltage generation circuit 16, a row decoder 18, a sense amplifier 19, a data register 20, and a column decoder 21. For example, the sequencer 14 executes a write operation, a read operation, an erase operation, etc. based on a command CMD.

[0020] The ready / busy circuit 15 is a circuit that transmits a ready / busy signal RBn to the memory controller 2.

[0021] The voltage generation circuit 16 generates voltages used for write, read, and erase operations under the control of the sequencer 14. The voltage generation circuit 16 supplies the generated voltages to the memory cell array 17, row decoder 18, sense amplifier 19, etc. The row decoder 18 and sense amplifier 19 can apply the voltages supplied by the voltage generation circuit 16 to the memory cell array 17.

[0022] The memory cell array 17 is a collection of multiple memory cell transistors (also simply referred to as "memory cells") arranged in a matrix. The memory cell array 17 includes multiple blocks BLK. In the example shown in FIG. 1, the memory cell array 17 includes four blocks BLK0, BLK1, BLK2, and BLK3. The number of blocks BLK in the memory cell array 17 is arbitrary. A block BLK is, for example, a collection of multiple memory cell transistors from which data is erased collectively. In other words, a block BLK is a unit for erasing data. The configuration of a block BLK will be described in detail later.

[0023] The row decoder 18 is a decoding circuit for the row address RA. Based on the decoding result, the row decoder 18 selects one of the blocks BLK in the memory cell array 17. The row decoder 18 applies a voltage to the row-direction wiring (word lines and select gate lines, which will be described later) of the selected block BLK.

[0024] The sense amplifier 19 is a circuit that writes and reads data DAT. The sense amplifier 19 is connected to the memory cell array 17 and the data register 20. During a read operation, the sense amplifier 19 reads data DAT from the memory cell array 17. During a write operation, the sense amplifier 19 supplies a voltage based on the write data DAT and the threshold voltage of the memory cell transistor to the memory cell array 17. For example, during a write operation, the sense amplifier 19 can generate four voltages based on the write data and the threshold voltage of the memory cell transistor. Then, the sense amplifier 19 can apply one of the four voltages to the wiring in the column direction (bit lines, described later).

[0025] The data register 20 is a register that temporarily stores data DAT. The data register 20 is connected to the sense amplifier 19 and the column decoder 21. The data register 20 includes a plurality of latch circuits. Each latch circuit temporarily stores write data or read data.

[0026] The column decoder 21 is a circuit that decodes the column address CA. The column decoder 21 receives the column address CA from the address register 12. The column decoder 21 selects a latch circuit in the data register 20 based on the result of decoding the column address CA.

[0027] 1.1.2 Memory cell array circuit configuration Next, an example of the circuit configuration of the memory cell array 17 will be described with reference to Fig. 2. Fig. 2 is a circuit diagram of the memory cell array 17.

[0028] The block BLK includes, for example, four string units SU0 to SU3. The number of string units SU included in the block BLK is arbitrary. The string unit SU is, for example, a set of multiple NAND strings NS that are collectively selected in a write operation or a read operation.

[0029] Next, the internal configuration of the string unit SU will be described. The string unit SU includes a plurality of NAND strings NS. The NAND string NS is a collection of a plurality of memory cell transistors connected in series. Each of the plurality of NAND strings NS in the string unit SU is connected to one of bit lines BL0 to BLm (m is an integer equal to or greater than 1).

[0030] Next, the internal configuration of the NAND strings NS will be described. Each NAND string NS includes a plurality of memory cell transistors MC and select transistors ST1 and ST2. In the example shown in Figure 2, the NAND string NS includes eight memory cell transistors MC0 to MC7.

[0031] The memory cell transistor MC is a memory element that stores data in a nonvolatile manner. The memory cell transistor MC includes a control gate and a charge storage layer. The memory cell transistor MC may be a MONOS (Metal-Oxide-Nitride-Oxide-Silicon) type that uses an insulator for the charge storage layer, or an FG (Floating Gate) type that uses a conductor for the charge storage layer.

[0032] The selection transistors ST1 and ST2 are switching elements and are used to select the string units SU during various operations.

[0033] The current paths of the select transistor ST2, memory cell transistors MC0 to MC7, and select transistor ST1 in the NAND string NS are connected in series. The drain of the select transistor ST1 is connected to a bit line BL. The source of the select transistor ST2 is connected to a source line SL.

[0034] The control gates of the memory cell transistors MC0 to MC7 in the same block BLK are commonly connected to word lines WL0 to WL7, respectively. More specifically, for example, the block BLK includes four string units SU0 to SU3. Each string unit SU includes a plurality of memory cell transistors MC0. The control gates of the plurality of memory cell transistors MC0 in the block BLK are commonly connected to one word line WL0. The same is true for the memory cell transistors MC1 to MC7.

[0035] The gates of the multiple select transistors ST1 in the string unit SU are commonly connected to one select gate line SGD. More specifically, the gates of the multiple select transistors ST1 in the string unit SU0 are commonly connected to a select gate line SGD0. The gates of the multiple select transistors ST1 in the string unit SU1 are commonly connected to a select gate line SGD1. The gates of the multiple select transistors ST1 in the string unit SU2 are commonly connected to a select gate line SGD2. The gates of the multiple select transistors ST1 in the string unit SU3 are commonly connected to a select gate line SGD3.

[0036] The gates of the select transistors ST2 in the block BLK are commonly connected to a select gate line SGS. Note that, like the select gate lines SGD, the select gate line SGS may be provided for each string unit SU.

[0037] The word lines WL0 to WL7, the select gate lines SGD0 to SGD3, and the select gate line SGS are connected to a row decoder 18, respectively.

[0038] The bit line BL is commonly connected to one NAND string NS of each of the plurality of string units SU in each block BLK. Each bit line BL is connected to a sense amplifier 19.

[0039] The source line SL is shared among, for example, a plurality of blocks BLK.

[0040] A set of memory cell transistors MC connected to a common word line WL in one string unit SU is referred to as a "cell unit CU," for example. In other words, a cell unit CU is a set of memory cell transistors MC selected collectively in a write or read operation. A page is a unit of data collectively written (or collectively read) to a cell unit CU. For example, when a memory cell transistor MC stores 1-bit data, the memory capacity of the cell unit CU is 1 page. Note that the cell unit CU may have a memory capacity of 2 or more pages depending on the number of bits of data stored in the memory cell transistor MC. The following describes the case where the memory cell transistor MC is a triple level cell (TLC) that stores 3-bit data.

[0041] 1.1.3 Data Register and Sense Amplifier Configuration Next, an example of the configuration of the data register 20 and the sense amplifier 19 will be described with reference to Fig. 3. Fig. 3 is a block diagram of the data register 20 and the sense amplifier 19.

[0042] As shown in FIG. 3, the sense amplifier 19 includes a plurality of sense amplifier units SAU provided for each bit line BL.

[0043] The data register 20 includes, for example, a plurality of latch circuits XDL provided for each sense amplifier unit SAU. The latch circuits XDL temporarily store read data and write data. The latch circuits XDL are used for inputting and outputting data between the sense amplifier units SAU and the input / output circuit 10. Each latch circuit XDL is connected to a corresponding sense amplifier unit SAU via a bus DBUS. Note that a plurality of sense amplifier units SAU may be connected to one latch circuit XDL.

[0044] Next, the internal configuration of the sense amplifier unit SAU will be described. The sense amplifier unit SAU includes, for example, a sense circuit SA and latch circuits SDL, ADL, BDL, CDL, DDL, and TDL. The sense circuit SA and the latch circuits SDL, ADL, BDL, CDL, DDL, and TDL are commonly connected to a bus LBUS. In other words, the latch circuit XDL, sense circuit SA, and the latch circuits SDL, ADL, BDL, CDL, DDL, and TDL are connected so as to be able to transmit and receive data to and from each other.

[0045] During a read operation, the sense circuit SA senses the data read onto the corresponding bit line BL and determines whether the read data is "0" data or "1" data. During a write operation, the sense circuit SA applies a voltage to the bit line BL based on the data stored in the latch circuit SDL.

[0046] The latch circuits SDL, ADL, BDL, CDL, DDL, and TDL temporarily store read data and write data. For example, during a read operation, data can be transferred from the sense circuit SA to any of the latch circuits SDL, ADL, BDL, CDL, DDL, and TDL. During a write operation, data can be transferred from the latch circuit XDL to any of the latch circuits SDL, ADL, BDL, CDL, DDL, and TDL.

[0047] The configuration of the sense amplifier unit SAU is not limited to this and can be modified in various ways. For example, the number of latch circuits included in the sense amplifier unit SAU can be designed based on the number of bits of data stored in one memory cell transistor MC.

[0048] 1.1.4 Circuit configuration of the sense amplifier unit Next, an example of the circuit configuration of the sense amplifier unit SAU will be described with reference to FIG. 4. FIG. 4 is a circuit diagram of the sense amplifier unit SAU. In the example shown in FIG. 4, for the sake of simplicity, the circuit diagrams of the latch circuits ADL, BDL, CDL, DDL, and TDL are omitted. The circuit configurations of the latch circuits ADL, BDL, CDL, DDL, and TDL are the same as that of the latch circuit SDL. In the following description, one of the source or drain of a transistor will be referred to as "one end of the transistor," and the other of the source or drain will be referred to as "the other end of the transistor."

[0049] As shown in FIG. 4, the sense amplifier unit SAU includes a sense circuit SA, latch circuits SDL, ADL, BDL, CDL, DDL, and TDL, a precharge circuit PPC, and a DBUS switch circuit DSC.

[0050] First, the internal configuration of the sense circuit SA will be described. The sense circuit SA includes a high-voltage n-channel MOS transistor 30, a low-voltage p-channel MOS transistor 31, low-voltage n-channel MOS transistors 32 to 45, and a capacitive element .

[0051] One end of the transistor 30 is connected to the bit line BL. The other end of the transistor 30 is connected to a node ND1. The gate of the transistor 30 is connected to a node BLS. When the bit line BL and the sense amplifier unit SAU are electrically connected, a high (“H”) level voltage is applied to the node BLS to turn on the transistor 30.

[0052] A voltage VHSA is applied to one end of the transistor 31. The voltage VHSA is the power supply voltage of the sense circuit SA. The other end of the transistor 31 is connected to a node ND2. The gate of the transistor 31 is connected to a node INV_S. The node INV_S is a node capable of holding data in the latch circuit SDL. When the node INV_S is at a low (“L”) level, the transistor 31 is turned on.

[0053] One end of the transistor 32 is connected to the node ND2. The other end of the transistor 32 is applied with the ground voltage VSS. The gate of the transistor 32 is connected to the node INV_S. When the node INV_S is at the "H" level, the transistor 32 is turned on. Therefore, based on the logic level of the node INV_S, one of the transistors 31 and 32 is turned on, and the other is turned off. In other words, based on the logic level of the node INV_S, either the voltage VHSA or the voltage VSS is applied to the node ND2.

[0054] One end of the transistor 33 is connected to the node ND2, the other end of the transistor 33 is connected to the node ND3, and the gate of the transistor 33 is connected to the node BLX.

[0055] One end of the transistor 34 is connected to the node ND1. The other end of the transistor 34 is connected to the node ND3. The gate of the transistor 33 is connected to the node BLC. The transistor 34 can function as a clamp transistor that clamps the voltage applied to the bit line BL based on the voltage applied to the node BLC.

[0056] One end of the transistor 35 is connected to the node ND3. The voltage VSS is applied to the other end of the transistor 35. The gate of the transistor 35 is connected to the node NLO.

[0057] One end of the transistor 36 is connected to the node ND3, the other end of the transistor 36 is connected to the node SEN1, and the gate of the transistor 36 is connected to the node XXL.

[0058] One end of the transistor 37 is connected to the node ND1. The gate of the transistor 37 is connected to the node APLS. The transistor 37 can function as a clamp transistor that clamps the voltage applied to the node ND1 based on the voltage applied to the node APLS.

[0059] One end of the transistor 38 is connected to the other end of the transistor 37. A voltage VHSA is applied to the other end of the transistor 38. A gate of the transistor 37 is connected to a node SEN1. When a high-level voltage is applied to the node SEN1, the transistor 38 is turned on. A voltage different from the voltage VHSA may be applied to the other end of the transistor 38. For example, a voltage used to control a signal CLKSA, which will be described later, may be applied.

[0060] One end of transistor 39 is connected to node SEN1. The other end of transistor 39 is connected to node SEN2. The gate of transistor 39 is connected to node S2S. For example, the sense circuit SA can perform an operation using transistors 40 to 45, which will be described later. For example, when performing an operation, the sense circuit SA can perform the operation while maintaining the voltage of node SEN1 by turning off transistor 39.

[0061] One end of the transistor 40 is connected to a node SEN2. The other end of the transistor 40 is connected to a node ND4. The gate of the transistor 40 is connected to a node BLQ. For example, the transistor 40 is turned on when a high-level voltage is applied from the precharge circuit PPC to the nodes SEN1 and SEN2.

[0062] One end of the transistor 41 is connected to a node ND4. The other end of the transistor 41 is connected to one end of the transistor 42. A signal STB is input to the gate of the transistor 41. When the signal STB is asserted, the sense circuit SA determines the data stored in the selected memory cell transistor MC. More specifically, when the signal STB of "H" level is input, the transistor 41 is turned on. During this time, if the transistor 42 is on, the bus LBUS is discharged via the transistors 41, 42, and 45. On the other hand, if the transistor 42 is off, the bus LBUS is not discharged via the transistors 41, 42, and 45. Data ("0" or "1") based on the voltage of the bus LBUS is stored in one of the latch circuits SDL, ADL, BDL, CDL, DDL, and TDL that share the bus LBUS.

[0063] The voltage VSS is applied to the other end of the transistor 42. The gate of the transistor 42 is connected to the node SEN2. The transistor 42 functions as a sense transistor that senses the voltage of the node SEN2. For example, when the voltage of the node SEN2 is equal to or greater than the threshold voltage of the transistor 42, the transistor 42 is turned on. On the other hand, when the voltage of the node SEN2 is less than the threshold voltage of the transistor 42, the transistor 42 is turned off.

[0064] One end of the transistor 43 is connected to the node SEN2. The other end of the transistor 43 is connected to one end of the transistor 44. The gate of the transistor 43 is connected to the node LSL.

[0065] The voltage VSS is applied to the other end of the transistor 44. The gate of the transistor 44 is connected to the bus LBUS via a node ND5.

[0066] One end of the transistor 45 is connected to a node ND4. The other end of the transistor 45 is connected to the bus LBUS via a node ND5. The gate of the transistor 45 is connected to a node LSW. For example, the transistor 45 is turned on while the signal STB is asserted.

[0067] One electrode of the capacitance element 46 is connected to the node SEN1, and the other electrode of the capacitance element 46 receives the clock signal CLKSA.

[0068] Next, the precharge circuit PPC will be described. The precharge circuit PPC is a precharge circuit for the bus LBUS, node SEN1, etc. The precharge circuit PPC includes a low-voltage n-channel MOS transistor 50. A voltage VHLB is applied to one end of the transistor 50. The voltage VHLB is a precharge voltage. The other end of the transistor 50 is connected to a node ND4. The gate of the transistor 50 is connected to a node LPC. For example, when the transistors 45 and 50 are on, the precharge circuit PCC charges the bus LBUS with a high-level voltage. When the transistors 39, 40, and 50 are on, the precharge circuit PCC charges the node SEN1 with a high-level voltage.

[0069] Next, the DBUS switch circuit DSC will be described. The DBUS switch circuit DSC is a circuit that connects the sense amplifier unit SAU and the bus DBUS. In other words, the DBUS switch circuit DSC connects the sense amplifier unit SAU and the latch circuit XDL. The DBUS switch circuit DSC includes a low-voltage n-channel MOS transistor 51. One end of the transistor 51 is connected to a node ND4. The other end of the transistor 51 is connected to the bus DBUS. The gate of the transistor 51 is connected to a node DSW.

[0070] Next, the internal configuration of the latch circuit SDL will be described. The latch circuit SDL includes inverters 60 and 61, and low-voltage n-channel MOS transistors 62 and 63.

[0071] The input node of the inverter 60 is connected to the node LAT_T, and the output node of the inverter 60 is connected to the node INV_S.

[0072] The input node of the inverter 61 is connected to the node INV_S, and the output node of the inverter 61 is connected to the node LAT_T.

[0073] One end of the transistor 62 is connected to the bus LBUS. The other end of the transistor 62 is connected to the node INV_S. The gate of the transistor 62 is connected to the node STI.

[0074] One end of the transistor 63 is connected to the bus LBUS. The other end of the transistor 63 is connected to the node LAT_T. The gate of the transistor 63 is connected to the node STL.

[0075] The latch circuit SDL stores data at the node LAT_T, while the latch circuit SDL stores the inverted data of the data stored at the node LAT_T at the node INV_S.

[0076] Each of the nodes BLS, BLX, BLC, NLO, XXL, APLS, S2S, BLQ, LSL, LSW, LPC, DSW, STI, and STL is shared, for example, among a plurality of sense amplifier units SAU. A signal is input (a voltage is applied) to each of the nodes BLS, BLX, BLC, NLO, XXL, APLS, S2S, BLQ, LSL, LSW, LPC, DSW, STI, and STL under the control of the sequencer 14.

[0077] 1.1.5 Circuit configuration of voltage generation circuit Next, an example of the circuit configuration of the voltage generating circuit 16 will be described with reference to FIG. 5. FIG. 5 is a circuit diagram of the voltage generating circuit 16 and the sense circuit SA. FIG. 5 shows a part of the voltage generating circuit 16 and a part of the sense circuit SA corresponding to the nodes XXL, BLX, BLC, and APLS. The sense circuit SA shown in FIG. 5 is an excerpt of a part of the sense circuit SA shown in FIG. 4. Therefore, in the following explanation, a description of the sense circuit SA will be omitted.

[0078] As shown in FIG. 5, the voltage generating circuit 16 includes a current source 70, variable resistance elements 71-73, n-channel MOS transistors 74 and 75, drivers 76-78, and selector circuits 80-83.

[0079] A voltage VX4 is applied to the input terminal of the current source 70. The current source 70 supplies a constant current IX4 from its output terminal. The output terminal of the current source 70 is connected to a node ND11.

[0080] One end of the variable resistance element 71 is connected to a node ND11, and the other end of the variable resistance element 71 is connected to a node ND12. For example, the resistance value of the variable resistance element 71 is set to r1.

[0081] One end of the variable resistance element 72 is connected to a node ND12, and the other end of the variable resistance element 72 is connected to a node ND13. For example, the resistance value of the variable resistance element 72 is set to r2.

[0082] One end and the gate of the transistor 74 are connected to the node ND13. The other end of the transistor 74 is connected to one end of the variable resistance element 73. The transistor 74 functions as a diode.

[0083] The other end of the variable resistance element 73 is connected to one end of the transistor 75. For example, the resistance value of the variable resistance element 73 is set to r3.

[0084] A voltage VSS is applied to the other end of the transistor 75. A signal SW1 is input to the gate of the transistor 75. For example, the signal SW1 is a signal that controls whether or not a voltage is applied to the nodes XXL, BLX, BLC, and APLS.

[0085] The driver 76 is a driver circuit for the voltage at the node ND11. For example, the driver 76 includes a unity-gain operational amplifier. The voltage at the node ND11 is applied to the input terminal of the driver 76. For example, the voltage Vnd11 at the node ND11 is Vnd11=IX4·(r1+r2+r3)+Vth74, ignoring the on-resistances of the transistors 74 and 75. Vth74 is the threshold voltage of the diode-connected transistor 74.

[0086] The driver 77 is a driver circuit for the voltage at the node ND12. For example, the driver 77 includes a unity-gain operational amplifier. The voltage at the node ND13 is applied to the input terminal of the driver 77. For example, the voltage Vnd12 at the node ND12 is Vnd12=IX4·(r2+r3)+Vth74, ignoring the on-resistances of the transistors 74 and 75. Therefore, the voltage Vnd12 applied to the input terminal of the driver 77 is lower than the voltage Vnd11 applied to the input terminal of the driver 76. In other words, the output voltage of the driver 77 is lower than the output voltage of the driver 76. The relationship is Vnd11-Vnd12=IX4·r1. Therefore, by controlling the resistance value r1 of the variable resistor 71, the voltage difference between the voltages Vnd11 and Vnd12 can be controlled.

[0087] The driver 78 is a driver circuit for the voltage at the node ND11. For example, the driver 78 includes a unity-gain operational amplifier. The voltage at the node ND13 is applied to the input terminal of the driver 77. For example, the voltage Vnd13 at the node ND13 is Vnd13=IX4·r3+Vth74, ignoring the on-resistances of the transistors 74 and 75. Therefore, the voltage Vnd13 applied to the input terminal of the driver 78 is lower than the voltage Vnd12 applied to the input terminal of the driver 77. In other words, the output voltage of the driver 78 is lower than the output voltage of the driver 77. The relationship is Vnd12-Vnd13=IX4·r2. Therefore, the voltage difference between the voltages Vnd12 and Vnd13 can be controlled by controlling the resistance value r2 of the variable resistor 72. The voltages Vnd11, Vnd12, and Vnd13 have the relationship Vnd11>Vnd12>Vnd13.

[0088] The selector circuit 80 has a 0th input terminal and a 1st input terminal. The selector circuit 80 electrically connects either the 0th input terminal or the 1st input terminal to an output terminal based on a signal SEL1. The 0th input terminal of the selector circuit 80 is connected to the output terminal of the driver 76. A voltage VSS is applied to the 1st input terminal of the selector circuit 80. The output terminal of the selector circuit 80 is connected to a node XXL.

[0089] The selector circuit 81 has a 0th input terminal, a first input terminal, and a second input terminal. The selector circuit 81 electrically connects one of the 0th input terminal, the first input terminal, and the second input terminal to the output terminal based on a signal SEL2. A voltage VHSA+Vth is applied to the 0th input terminal of the selector circuit 81. The voltage Vth is the threshold voltage of the low-withstand-voltage n-channel MOS transistors 32 to 45 of the sense circuit SA. A first input terminal of the selector circuit 81 is connected to the output terminal of the driver 77. A voltage VSS is applied to a second input terminal of the selector circuit 81. An output terminal of the selector circuit 81 is connected to a node BLX.

[0090] The selector circuit 82 has a 0th input terminal, a first input terminal, and a second input terminal. The selector circuit 82 electrically connects one of the 0th input terminal, the first input terminal, and the second input terminal to the output terminal based on a signal SEL3. A voltage VHSA+Vth is applied to the 0th input terminal of the selector circuit 82. The first input terminal of the selector circuit 82 is connected to the output terminal of the driver 78. A voltage VSS is applied to the second input terminal of the selector circuit 82. The output terminal of the selector circuit 82 is connected to a node BLC.

[0091] The selector circuit 83 has a 0th input terminal and a 1st input terminal. The selector circuit 83 electrically connects either the 0th input terminal or the 1st input terminal to the output terminal based on a signal SEL4. The 0th input terminal of the selector circuit 83 is connected to the output terminal of the driver 76. A voltage VSS is applied to the 1st input terminal of the selector circuit 83. The output terminal of the selector circuit 83 is connected to a node APLS.

[0092] The signals SEL1 to SEL4 are signals based on the control of the sequencer 14.

[0093] 1.2 Data storage method Next, an example of a data storage method will be described with reference to Fig. 6. Fig. 6 is a conceptual diagram showing an example of a data storage method. Fig. 6 shows an example of the threshold voltage distribution of memory cell transistors MC, data allocation, and voltages used to read data. In the threshold voltage distribution diagram referred to below, "NMCs" on the vertical axis indicates the number of memory cell transistors MC, and the voltage on the horizontal axis indicates the voltage applied to the gate of the memory cell transistor MC.

[0094] 6, when one memory cell transistor MC is a TLC that stores 3-bit data, the threshold voltage distribution formed by the multiple memory cell transistors MC included in the cell unit CU can have eight different states. Hereinafter, these eight states will be referred to as "S0" state, "S1" state, "S2" state, "S3" state, "S4" state, "S5" state, "S6" state, and "S7" state, in order from lowest to highest threshold voltage.

[0095] When the memory cell transistor MC is in an erased state, the threshold voltage of the memory cell transistor MC is included in the "S0" state. When data is written to the memory cell transistor MC, the threshold voltage of the memory cell transistor MC is included in one of the "S0" to "S7" states. Different 3-bit data is assigned to each of the "S0" to "S7" states. It is preferable that the data assignment in each of two adjacent states is set so that only one bit of data differs. Below, an example of data assignment for eight types of states is listed.

[0096] "S0" state: "111 (high-order bit / middle-order bit / low-order bit)" data “S1” state: “110” data “S2” state: “100” data “S3” state: “000” data “S4” state: “010” data “S5” state: “011” data “S6” state: “001” data “S7” state: “101” data A verify voltage used to verify data writing and a read voltage used to read data are set between adjacent states. Specifically, a verify voltage V1 and a read voltage R1 are set between the "S0" and "S1" states. A verify voltage V2 and a read voltage R2 are set between the "S1" and "S2" states. A verify voltage V3 and a read voltage R3 are set between the "S2" and "S3" states. A verify voltage V4 and a read voltage R4 are set between the "S3" and "S4" states. A verify voltage V5 and a read voltage R5 are set between the "S4" and "S5" states. A verify voltage V6 and a read voltage R6 are set between the "S5" and "S6" states. A verify voltage V7 and a read voltage R7 are set between the "S6" and "S7" states. The verify voltages V1 to V7 are preferably set higher than the read voltages R1 to R7, respectively.

[0097] Verify voltages V1 to V7 are associated with states "S1" to "S7," respectively. In a write operation, the semiconductor memory device 1 performs a read operation using the verify voltages (hereinafter referred to as a verify operation) to check whether the threshold voltage of a memory cell transistor MC in which certain data is to be stored has exceeded the verify voltage associated with that data. Then, when the sequencer 14 detects that the threshold voltage of the memory cell transistor MC has exceeded the verify voltage associated with that data, it completes writing of the data to that memory cell transistor MC.

[0098] The read voltage R1 is used to distinguish between the "S0" state and the "S1" state or higher. The read voltage R2 is used to distinguish between the "S1" state or lower and the "S2" state or higher. The read voltage R3 is used to distinguish between the "S2" state or lower and the "S3" state or higher. The read voltage R4 is used to distinguish between the "S3" state or lower and the "S4" state or higher. The read voltage R5 is used to distinguish between the "S4" state or lower and the "S5" state or higher. The read voltage R6 is used to distinguish between the "S5" state or lower and the "S6" state or higher. The read voltage R7 is used to distinguish between the "S6" state or lower and the "S7" state or higher. In addition, the read pass voltage VREAD is set to a voltage higher than the highest state. A memory cell transistor MC with the read pass voltage VREAD applied to its gate is turned on regardless of the data to be stored.

[0099] In a read operation, the semiconductor memory device 1 uses at least one read voltage to determine the state in which the memory cell transistor MC is distributed. For example, lower page data, which is a set of lower-order bit data, is determined by a read operation using each of read voltages R1 and R5. Middle page data, which is a set of middle-order bit data, is determined by a read operation using each of read voltages R2, R4, and R6. Upper page data, which is a set of upper-order bit data, is determined by a read operation using each of read voltages R3 and R7. In a page read operation using multiple read voltages, arithmetic processing is performed as appropriate.

[0100] Note that the semiconductor memory device 1 may use other data allocations when the memory cell transistors MC are TLC (hereinafter referred to as "TLC method"). Furthermore, the semiconductor memory device 1 may use a storage method other than the TLC method, and may use any data allocation. For example, one memory cell transistor MC may store 2-bit data, 4-bit data or more. The operations described in this specification can be performed regardless of the data storage method or type of data allocation.

[0101] In this specification, the previous state refers to the adjacent state with a lower threshold voltage. For example, the state immediately before the "S2" state is the "S1" state.

[0102] 1.3 Write Operation Next, the write operation will be described. In the following description, the word line WL selected in the write operation will be referred to as the "word line WLsel." The memory cell transistor MC connected to the word line WLsel will be referred to as the "memory cell transistor MCsel."

[0103] 1.3.1 Write Operation Overview First, an overview of the write operation will be described with reference to FIG. 7. FIG. 7 is a timing chart showing an overview of the write operation. As shown in FIG. 7, the semiconductor memory device 1 repeatedly executes a program loop during the write operation. FIG. 7 shows the number of times the program loop has been executed during the write operation (hereinafter referred to as the loop count) and the voltage change of the word line WLsel (WLsel voltage). Each program loop includes a program operation (Program) and a verify operation (Verify).

[0104] A program operation can increase the threshold voltage of the memory cell transistor MC. In the program operation, multiple memory cell transistors MCsel connected to a word line WLsel are set to be program-target or program-inhibit based on the write data stored in the associated sense amplifier unit SAU. Specifically, memory cell transistors MCsel that have not reached the threshold voltage of the write target state (hereinafter referred to as the "write state") are set to be program-target. On the other hand, memory cell transistors MCsel that have reached the threshold voltage of the write state are set to be program-inhibited.

[0105] In a program operation, a program voltage VPGM is applied to the word line WLsel. The program voltage VPGM is a high voltage capable of increasing the threshold voltage of the memory cell transistor MCsel. The program voltage VPGM is stepped up, for example, according to the repetition of a program loop. That is, the program voltage VPGM can increase according to the number of program loops executed. The step-up width DVPGM of the program voltage VPGM can be set to any value. When the program voltage VPGM is applied to the word line WLsel, the threshold voltage of the memory cell transistor MCsel connected to the word line WLsel and the bit line BL to be programmed increases. On the other hand, the increase in the threshold voltage of the memory cell transistor MCsel connected to the word line WLsel and the bit line BL to be programmed is suppressed by a self-boost technique or the like. After completing the program operation, the sequencer 14 executes a verify operation.

[0106] The verify operation is a read operation that checks whether the threshold voltage of the memory cell transistor MCsel has reached the threshold voltage of the write state. The sequencer 14 executes the verify operation on the memory cell transistor MCsel that is set as the program target and that is in the write state that matches the verify target within the same program loop.

[0107] During the verify operation, the sense amplifier units SAU determine whether the threshold voltage of the memory cell transistor MCsel exceeds the verify voltage applied to the word line WLsel based on the voltage of the bit line BL. Each sense amplifier unit SAU determines a memory cell transistor MCsel whose threshold voltage exceeds the verify voltage, i.e., whose threshold voltage is deemed to have reached the write state threshold voltage, as a "verify pass." On the other hand, each sense amplifier unit SAU determines a memory cell transistor MCsel whose threshold voltage is equal to or lower than the verify voltage, i.e., whose threshold voltage is deemed not to have reached the write state threshold voltage, as a "verify fail." Each sense amplifier unit SAU stores the write state verify result described above in one of its internal latch circuits. Upon completing the verify operation, the sequencer 14 sets each memory cell transistor MCsel as program target or program inhibit based on the verify result of the current program loop, and starts processing the next program loop.

[0108] The semiconductor memory device 1 may perform a detection operation ("Detection") as appropriate after each program loop. In the detection operation, the number of memory cell transistors MCsel that have passed verification is counted for each write state. Then, for each write state, the sequencer 14 determines whether or not the write for that write state has been completed based on the count value. In the repetition of the program loop, when the sequencer 14 detects that the number of memory cell transistors MCsel that have not passed verification for the "S1" to "S7" states has fallen below a predetermined number, for example, the program loop ends the write operation.

[0109] 1.3.2 Example of a program loop Next, a specific example of a program loop will be described with reference to Fig. 8. Fig. 8 is a table showing an example of setting a program loop in a write operation. The table shown in Fig. 8 shows the relationship between the number of loops and the write state to be verified that is assigned to the loop, and a white circle is written in the part where the verify operation is set.

[0110] 8, the type and number of write states to be verified can be changed as the program loop progresses. In this example, the sequencer 14 executes a maximum of 19 program loops. The sequencer 14 then executes a verify operation for at least one type of state in each of the 19 program loops.

[0111] Specifically, the "S1" state is set as the verify target in the first to sixth program loops. The "S2" state is set as the verify target in the second to eighth program loops. The "S3" state is set as the verify target in the fourth to tenth program loops. The "S4" state is set as the verify target in the sixth to twelfth program loops. The "S5" state is set as the verify target in the eighth to fourteenth program loops. The "S6" state is set as the verify target in the tenth to sixteenth program loops. The "S7" state is set as the verify target in the twelfth to nineteenth program loops.

[0112] Note that the number of program loops that the semiconductor memory device 1 can execute in one write operation may be any other number. Even when writing is not completed in all write states, the sequencer 14 can end the write operation in response to the execution of a predetermined number of program loops. The write states to be verified associated with the number of loops may be other settings. The sequencer 14 may omit the program operation and verification operation of the write state in the subsequent program loops based on the result of the detection operation.

[0113] 1.3.3 Details of the programming method Next, referring to FIG. 9, the details of the programming method will be described. FIG. 9 is a threshold voltage distribution diagram showing the relationship between three types of verification voltages that can be used for each write state and three types of program conditions in the write operation. In the example shown in FIG. 9, it shows the case where all memory cell transistors MCsel are written from the "S0" state to the "S1" state.

[0114] As shown in FIG. 9, for each write state, a first verification low voltage VL1, a second verification low voltage VL2, and a verification high voltage VH used for the verification operation are set. That is, the verification operation includes a verification operation using the first verification low voltage VL1 (hereinafter referred to as "VL1 verification operation"), a verification operation using the second verification low voltage VL2 (hereinafter referred to as "VL2 verification operation"), and a verification operation using the verification high voltage VH (hereinafter referred to as "VH verification operation"). The verification high voltage VH is the verification voltage described with reference to FIG. 6. In the example shown in FIG. 9, VH = V1. The first verification low voltage VL1, the second verification low voltage VL2, and the verification high voltage VH are in the relationship of VL1 < VL2 < VH.

[0115] The first verify low voltage VL1 is a voltage for distinguishing the multiple memory cell transistors MCsel of the cell unit CU into memory cell transistors MCsel with a relatively large increase in threshold voltage (hereinafter referred to as "fast cells") and memory cell transistors MCsel with a relatively small increase in threshold voltage (hereinafter referred to as "slow cells").

[0116] The sequencer 14 executes a VL1 verify operation once in a program loop that is executed multiple times for one write state. In the VL1 verify operation, the sequencer 14 determines that a memory cell transistor MCsel whose threshold voltage is equal to or lower than voltage VL1 is a slow cell. In other words, a memory cell transistor MCsel that fails the VL1 verify operation is determined to be a slow cell. On the other hand, in the VL1 verify operation, the sequencer 14 determines that a memory cell transistor MCsel whose threshold voltage exceeds voltage VL1 is a fast cell. In other words, a memory cell transistor MCsel that passes the VL1 verify operation is determined to be a fast cell. Hereinafter, the determination of distinguishing between fast and slow cells based on the VL1 verify operation will be referred to as "cell determination."

[0117] The second verify low voltage VL2 is a voltage for determining the magnitude of the difference between the threshold voltage of the memory cell transistor MCsel and the voltage VH.

[0118] The sequencer 14 executes a VL2 verify operation and a VH verify operation in each program loop, and determines the conditions for the program operation of the next program loop based on the results of the VL2 verify operation and the VH verify operation.

[0119] More specifically, the program operation includes three program conditions PG0 to PG2 and a program inhibit condition. For example, if the threshold voltage of memory cell transistor MCsel is equal to or lower than voltage VL2, the sequencer 14 applies program condition PG0 in the program operation of the next program loop. In other words, a program operation to which program condition PG0 is applied (hereinafter referred to as a "PG0 program operation") is executed on memory cell transistor MCsel that has failed VL2 verification.

[0120] Furthermore, if the threshold voltage of the memory cell transistor MCsel exceeds voltage VL2 and is equal to or lower than voltage VH, the sequencer 14 applies program condition PG1 to the slow cells and program condition PG2 to the fast cells in the program operation of the next program loop. In other words, a program operation to which program condition PG1 is applied (hereinafter referred to as PG1 program operation) is executed for the slow cells that pass VL2 verify but fail VH verify. On the other hand, a program operation to which program condition PG2 is applied (hereinafter referred to as "PG2 program operation") is executed for the fast cells that pass VL2 verify but fail VH verify.

[0121] Furthermore, when the threshold voltage of the memory cell transistor MCsel exceeds the voltage VH, the sequencer 14 sets the memory cell transistor MC to be program-inhibited in the program operation of the next program loop.

[0122] Program condition PG0 is a program condition that causes a relatively large amount of variation in the threshold voltage of memory cell transistor MC. Program condition PG1 is a program condition that causes a smaller amount of variation in the threshold voltage of memory cell transistor MC than program condition PG0. Program condition PG1 is applied to slow cells. Program condition PG2 is a program condition that causes a smaller amount of variation in the threshold voltage of memory cell transistor MC than program condition PG0. Program condition PG2 is applied to fast cells. For example, when program condition PG0, program condition PG1, program condition PG2, or a program inhibit condition is applied to a program operation of one memory cell transistor MC, the amount of variation in the threshold voltage of the memory cell transistor MC is in the following relationship: "program condition PG0" > "program condition PG1" > "program condition PG2" > "program inhibit." For example, if the threshold voltage of memory cell transistor MC exceeds voltage VL2 and is equal to or lower than voltage VH, performing the PG0 program operation may result in the threshold voltage of memory cell transistor MC exceeding voltage VH by a relatively large amount. Therefore, the PG1 program operation is performed on slow cells, and the PG2 program operation is performed on fast cells. It is preferable that the variation in the threshold voltage of the slow cell due to the PG1 program operation and the variation in the threshold voltage of the fast cell due to the PG2 program operation be small.

[0123] The sequencer 14 may apply the program condition PG1 or the program condition PG2 in the final program operation of multiple program operations executed for one write state. In other words, the memory cell transistor MCsel for which the PG1 program operation or the PG2 program operation has been executed is set to program inhibit in the next or subsequent program loop. The sequencer 14 applies the program condition PG1 to slow cells and the program condition PG2 to fast cells, thereby reducing variations in the threshold voltages of the multiple memory cell transistors MCsel.

[0124] Next, an example of the relationship between the threshold voltage of a memory cell transistor MC and program conditions will be described with reference to Fig. 10. Fig. 10 is a conceptual diagram showing fluctuations in the threshold voltage of fast and slow cells during a write operation.

[0125] As shown in FIG. 10, for example, when the same program conditions are applied to a fast cell and a slow cell during a program operation, the fast cell exhibits a larger threshold voltage fluctuation during a single program operation. In the example shown in FIG. 10, after a PG0 program operation is performed on the fast cell once, the threshold voltage of the fast cell rises above voltage VL2 and below voltage VH. Then, after a PG2 program operation is performed on the fast cell, the threshold voltage of the fast cell exceeds voltage VH. At this time, the increase in the threshold voltage of the fast cell is more suppressed than in the first PG0 program operation. In contrast, after a second PG0 program operation is performed on the slow cell, the threshold voltage of the slow cell rises above voltage VL2 and below voltage VH. In this state, for example, if program conditions PG2 are applied to the next program operation of the slow cell, the threshold voltage fluctuation of the slow cell will be smaller than the threshold voltage fluctuation of the fast cell after the PG2 program. This may result in the slow cell's threshold voltage not reaching voltage VH. For this reason, program condition PG1, which causes a larger amount of variation in threshold voltage than program condition PG2, is applied to the program operation of slow cells.

[0126] 1.3.4 Wordline and Bitline Voltages in Program Operations Next, an example of the voltages of the word line WL and the bit line BL in a program operation will be described with reference to FIG. 11. FIG. 11 is a timing chart showing the voltages of the word line WLsel and the bit line BL in a program operation. Hereinafter, the bit line BL connected to the memory cell transistor MCsel that is the target of the PG0 program operation will be referred to as "bit line BL_pg0." The bit line BL connected to the memory cell transistor MCsel that is the target of the PG1 program operation will be referred to as "bit line BL_pg1." The bit line BL connected to the memory cell transistor MCsel that is the target of the PG2 program operation will be referred to as "bit line BL_pg2." The bit line BL connected to the program-inhibited memory cell transistor MCsel will be referred to as "bit line BL_inh."

[0127] As shown in FIG. 11, at the start of a program operation, the voltages of the word line WLsel and the bit lines BL_pg0, BL_pg1, BL_pg2, and BL_inh are, for example, voltage VSS. While a program voltage VPGM is applied to the word line WLsel, voltage VSS is applied to the bit line BL_pg0. Voltage VQPW1 is applied to the bit line BL_pg1. Voltage VQPW2 is applied to the bit line BL_pg2. Voltage VINH is applied to the bit line BL_inh. Voltage VQPW1 is a voltage higher than voltage VSS. Voltage VQPW2 is a voltage higher than voltage VQPW1. Voltage VSGD is a voltage applied to the select gate line SGD corresponding to the target string unit SU while the program voltage VPGM is applied to the word line WLsel. Voltage VINH is a voltage higher than voltages VQPW2 and VSGD. In other words, while the program voltage VPGM is applied to the word line WLsel, the sense amplifier 19 applies the voltage VSS to the bit line BL_pg0, the voltage VQPW1 to the bit line BL_pg1, the voltage VQPW2 to the bit line BL_pg2, and the voltage VINH to the bit line BL_inh.

[0128] While the program voltage VPGM is applied to the word line WLsel, the select transistor ST1 is turned on in the NAND string NS connected to the bit line BL_pg0, BL_pg1, or BL_pg2. At this time, the voltage VSS is applied to the channel of the memory cell transistor MCsel corresponding to the bit line BL_pg0. The voltage VQPW1 is applied to the channel of the memory cell transistor MCsel corresponding to the bit line BL_pg1. The voltage VQPW2 is applied to the channel of the memory cell transistor MCsel corresponding to the bit line BL_pg2. On the other hand, in the NAND string NS connected to BL_inh, the select transistor ST1 is cut off. That is, the channel of the memory cell transistor MCsel corresponding to BL_inh is set to a floating state.

[0129] As a result, in the memory cell transistor MCsel corresponding to the bit line BL_pg0, electrons are injected into the charge storage layer based on the voltage difference between the voltage VPGM and the voltage VSS, and the threshold voltage rises. In the memory cell transistor MCsel corresponding to the bit line BL_pg1, electrons are injected into the charge storage layer based on the voltage difference between the voltage VPGM and the voltage VQPW1, and the threshold voltage rises. In the memory cell transistor MCsel corresponding to the bit line BL_pg2, electrons are injected into the charge storage layer based on the voltage difference between the voltage VPGM and the voltage VQPW2, and the threshold voltage rises. The voltage differences between the program voltage VPGM and the channel voltage have the relationship (VPGM-VSS)>(VPGM-VQPW1)>(VPGM-VQPW2). Therefore, the ease of threshold voltage rise is in the relationship of program condition PG0>program condition PG1>program condition PG2. Furthermore, in the memory cell transistor MCsel corresponding to the bit line BL_inh, the voltage of the channel in the floating state rises as the voltage VPGM applied to the word line WLsel rises, thereby suppressing the rise in the threshold voltage.

[0130] 1.3.5 Verify voltage setting Next, an example of verify voltage setting will be described with reference to Fig. 12. Fig. 12 is a table showing an example of verify voltage setting.

[0131] As shown in FIG. 12, the verify high voltage VH of each write state is the verify voltage described with reference to FIG. 6. Specifically, the verify high voltage VH of the "S1" state is voltage V1. The verify high voltage VH of the "S2" state is voltage V2. The verify high voltage VH of the "S3" state is voltage V3. The verify high voltage VH of the "S4" state is voltage V4. The verify high voltage VH of the "S5" state is voltage V5. The verify high voltage VH of the "S6" state is voltage V6. The verify high voltage VH of the "S7" state is voltage V7.

[0132] Next, the second verify low voltage VL2 of each write state will be described. The second verify low voltage VL2 of the "S1" state is voltage V1L2. Voltage V1L2 is lower than voltage V1. The second verify low voltage VL2 of the "S2" state is voltage V2L2. Voltage V2L2 is higher than voltage V1 and lower than voltage V2. The second verify low voltage VL2 of the "S3" state is voltage V3L2. Voltage V3L2 is higher than voltage V2 and lower than voltage V3. The second verify low voltage VL2 of the "S4" state is voltage V4L2. Voltage V4L2 is higher than voltage V3 and lower than voltage V4. The second verify low voltage VL2 of the "S5" state is voltage V5L2. Voltage V5L2 is higher than voltage V4 and lower than voltage V5. The second verify low voltage VL2 in the "S6" state is a voltage V6L2. The voltage V6L2 is higher than the voltage V5 and lower than the voltage V6. The second verify low voltage VL2 in the "S7" state is a voltage V7L2. The voltage V7L2 is higher than the voltage V6 and lower than the voltage V7.

[0133] Next, the first verify low voltage VL1 of each write state will be described. The first verify low voltage VL1 of the "S1" state is voltage V1L1. Voltage V1L1 is lower than voltage V1L2. The first verify low voltage VL1 of the "S2" to "S7" states is the verify high voltage VH of the "S(N-1)" state (N is an integer equal to or greater than 2 and is a number assigned to each write state), i.e., voltage V(N-1). More specifically, the first verify low voltage VL1 of the "S2" state is voltage V1, which is the same as the verify high voltage VH of the "S1" state. The first verify low voltage VL1 of the "S3" state is voltage V2, which is the same as the verify high voltage VH of the "S2" state. The first verify low voltage VL1 of the "S4" state is voltage V3, which is the same as the verify high voltage VH of the "S3" state. The first verify low voltage VL1 in the "S5" state is the same voltage V4 as the verify high voltage VH in the "S4" state. The first verify low voltage VL1 in the "S6" state is the same voltage V5 as the verify high voltage VH in the "S5" state. The first verify low voltage VL1 in the "S7" state is the same voltage V6 as the verify high voltage VH in the "S6" state.

[0134] 1.3.6 Specific examples of timing for executing VL1 verify operation Next, a specific example of the timing for executing the VL1 verify operation will be described with reference to FIG. 13. FIG. 13 illustrates the relationship between the number of program loops in a write operation and the VL1 verify operation. The upper table in FIG. 13 is the same as that in FIG. 8. In each write state, a white circle indicates a portion where a verify operation is set. A black circle indicates a program loop in which the sequencer 14 determines that the write operation in the write state has been completed. The lower table in FIG. 13 shows setting data for voltages VQPW1 and VQPW2 based on the results of VL1 verify. For example, in the lower table, a "H" level indicates voltage VQPW1, and a "L" level indicates voltage VQPW2. The setting data corresponding to the lower table is stored in one of the latch circuits ADL, BDL, CDL, DDL, or TDL of each sense amplifier unit SAU. The following describes the case where setting data is stored in the latch circuit TDL.

[0135] As shown in FIG. 13, first, in the first program loop, data at the "L" level is stored in the latch circuits TDL corresponding to each write state.

[0136] For example, in the “S1” state, the number of program loops for executing the VL1 verify operation is preset. In the example shown in FIG. 13, in the second program loop, the VL1 verify operation is executed using the voltage V1L1 corresponding to the “S1” state. More specifically, in the second program loop, the sequencer 14 executes a VL1 verify operation using the voltage V1L1, a VL2 verify operation using the voltage V1L2, and a VH verify operation using the voltage V1 corresponding to the “S1” state, as well as a VL2 verify operation using the voltage V2L2 and a VH verify operation using the voltage V2 corresponding to the “S2” state. The sequencer 14 updates the data in the latch circuit TDL corresponding to the “S1” state based on the result of the VL1 verify operation using the voltage V1L1 corresponding to the “S1” state. As a result, the data in the latch circuit TDL corresponding to the fast cell that passed the VL1 verify among the latch circuits TDL corresponding to the “S1” state is set to “L.” On the other hand, among the latch circuits TDL corresponding to the "S1" state, the data of the latch circuit TDL corresponding to the slow cell that failed the VL1 verify is set to "H".

[0137] In the fifth program loop, the sequencer 14 executes verify operations corresponding to the "S1" state, the "S2" state, and the "S3" state. For example, in the fifth program loop, the sequencer 14 determines that the write operation corresponding to the "S1" state has been completed. In this case, the write operation corresponding to the "S1" state in the sixth program loop may be omitted. The sequencer 14 considers the result of the VH verify operation using the voltage V1 corresponding to the "S1" state in the fifth program loop as the result of the VL1 verify operation corresponding to the "S2" state, and updates the data in the latch circuits TDL corresponding to the "S2" state. As a result, the data in the latch circuits TDL corresponding to the fast cells that passed the VH verify using the voltage V1 among the latch circuits TDL corresponding to the "S2" state is set to "L." On the other hand, the data in the latch circuits TDL corresponding to the slow cells that failed the VH verify using the voltage V1 among the latch circuits TDL corresponding to the "S2" state is set to "H."

[0138] In the seventh program loop, the sequencer 14 executes verify operations corresponding to the "S2" state, the "S3" state, and the "S4" state. For example, in the seventh program loop, the sequencer 14 determines that the write operation corresponding to the "S2" state has been completed. In this case, the write operation corresponding to the "S2" state in the eighth program loop may be omitted. The sequencer 14 considers the result of the VH verify operation using the voltage V2 corresponding to the "S2" state in the seventh program loop as the result of the VL1 verify operation corresponding to the "S3" state, and updates the data in the latch circuit TDL corresponding to the "S3" state. As a result, the data in the latch circuit TDL corresponding to the fast cell that passed the VH verify using the voltage V2 among the latch circuits TDL corresponding to the "S3" state is set to "L". On the other hand, the data in the latch circuit TDL corresponding to the slow cell that failed the VH verify using the voltage V2 among the latch circuits TDL corresponding to the "S3" state is set to "H".

[0139] In the ninth program loop, the sequencer 14 executes verify operations corresponding to the “S3” state, the “S4” state, and the “S5” state. For example, in the ninth program loop, the sequencer 14 determines that the write operation corresponding to the “S3” state has been completed. In this case, the write operation corresponding to the “S3” state in the tenth program loop may be omitted. The sequencer 14 considers the result of the VH verify operation using the voltage V3 corresponding to the “S3” state in the ninth program loop as the result of the VL1 verify operation corresponding to the “S4” state, and updates the data in the latch circuit TDL corresponding to the “S4” state. As a result, the data in the latch circuit TDL corresponding to the fast cell that passed the VH verify using the voltage V3 among the latch circuits TDL corresponding to the “S4” state is set to “L.” On the other hand, the data in the latch circuit TDL corresponding to the slow cell that failed the VH verify using the voltage V3 among the latch circuits TDL corresponding to the “S4” state is set to “H.”

[0140] In the 11th program loop, the sequencer 14 executes verify operations corresponding to the “S4” state, the “S5” state, and the “S6” state. For example, in the 11th program loop, the sequencer 14 determines that the write operation corresponding to the “S4” state has been completed. In this case, the write operation corresponding to the “S4” state in the 12th program loop may be omitted. The sequencer 14 considers the result of the VH verify operation using the voltage V4 corresponding to the “S4” state in the 11th program loop as the result of the VL1 verify operation corresponding to the “S5” state, and updates the data in the latch circuit TDL corresponding to the “S5” state. As a result, the data in the latch circuit TDL corresponding to the fast cell that passed the VH verify using the voltage V4 among the latch circuits TDL corresponding to the “S5” state is set to “L.” On the other hand, the data in the latch circuit TDL corresponding to the slow cell that failed the VH verify using the voltage V4 among the latch circuits TDL corresponding to the “S5” state is set to “H.”

[0141] In the 13th program loop, the sequencer 14 executes verify operations corresponding to the “S5” state, the “S6” state, and the “S7” state. For example, in the 13th program loop, the sequencer 14 determines that the write operation corresponding to the “S5” state has been completed. In this case, the write operation corresponding to the “S5” state in the 14th program loop may be omitted. The sequencer 14 considers the result of the VH verify operation using the voltage V5 corresponding to the “S5” state in the 13th program loop as the result of the VL1 verify operation corresponding to the “S6” state, and updates the data in the latch circuit TDL corresponding to the “S6” state. As a result, the data in the latch circuit TDL corresponding to the fast cell that passed the VH verify using the voltage V5 among the latch circuits TDL corresponding to the “S6” state is set to “L.” On the other hand, the data in the latch circuit TDL corresponding to the slow cell that failed the VH verify using the voltage V5 among the latch circuits TDL corresponding to the “S6” state is set to “H.”

[0142] In the 15th program loop, the sequencer 14 executes verify operations corresponding to the “S6” state and the “S7” state. For example, in the 15th program loop, the sequencer 14 determines that the write operation corresponding to the “S6” state has been completed. In this case, the write operation corresponding to the “S6” state in the 16th program loop may be omitted. The sequencer 14 considers the result of the VH verify operation using the voltage V6 corresponding to the “S6” state in the 15th program loop as the result of the VL1 verify operation corresponding to the “S7” state, and updates the data in the latch circuit TDL corresponding to the “S7” state. As a result, the data in the latch circuit TDL corresponding to the fast cell that passed the VH verify using the voltage V6 among the latch circuits TDL corresponding to the “S7” state is set to “L.” On the other hand, the data in the latch circuit TDL corresponding to the slow cell that failed the VH verify using the voltage V6 among the latch circuits TDL corresponding to the “S7” state is set to “H.”

[0143] 1.3.7 Program operation flow Next, an example of the flow of a program operation will be described with reference to Figures 14 to 19. Figure 14 is a timing chart showing various wirings and various signals in the program operation. Figures 15 to 19 are diagrams showing the operations of the voltage generating circuit 16 and the sense amplifier unit SAU in the program operation.

[0144] As shown in FIG. 14, first, at time t1, the row decoder 18 applies a voltage VSS to the word line WLsel. The sense amplifier unit SAU executes a first arithmetic operation to update the data in the latch circuit SDL. Hereinafter, the operation of updating the data in the latch circuit SDL by the arithmetic operation will also be referred to as "scan SCAN." In the first arithmetic operation, if programming is inhibited, "H" level data is stored in the corresponding latch circuit SDL, and if programming is to be performed, "L" level data is stored in the corresponding latch circuit SDL. That is, "H" level data is stored in the latch circuit SDL corresponding to the bit line BL_inh. Also, "L" level data is stored in the latch circuits SDL corresponding to the bit lines BL_pg0, BL_pg1, and BL_pg2.

[0145] Based on the "H" level data stored in the latch circuit SDL, the node SEN1 is charged to the "H" level. More specifically, for example, in the sense circuit SA, the transistors 39 and 40 are turned on, and a "H" level voltage VHLB is applied to the node SEN1 from the precharge circuit PCC. Next, the transistors 39 and 43 are turned on. In this state, for example, the transistor 62 of the latch circuit SDL is turned on. As a result, when the latch circuit SDL stores "L" level data, the voltage of the bus LBUS is set to the "H" level. On the other hand, when the latch circuit SDL stores "H" level data, the voltage of the bus LBUS is set to the "L" level. When the bus LBUS is at the "H" level, the transistor 44 is turned on, and the node SEN1 is discharged via the transistors 39, 43, and 44. On the other hand, when the bus LBUS is at the "L" level, the transistor 44 is turned off, and the node SEN1 is not discharged. That is, when "H" level data is stored in the latch circuit SDL, the node SEN1 is set to "H" level.

[0146] The sequencer 14 sets the signal SEL1 to "1." This causes the selector circuit 80 of the voltage generating circuit 16 to select the first input terminal. As a result, the voltage VSS is applied to the node XXL.

[0147] The sequencer 14 sets the signal SEL2 to "0." This causes the 0th input terminal to be selected in the selector circuit 81 of the voltage generating circuit 16. As a result, the voltage VHSA+Vth is applied to the node BLX.

[0148] The sequencer 14 sets the signal SEL3 to "0." This causes the 0th input terminal to be selected in the selector circuit 82 of the voltage generating circuit 16. As a result, the voltage VHSA+Vth is applied to the node BLC.

[0149] The sequencer 14 sets the signal SEL4 to "1." This causes the first input terminal to be selected in the selector circuit 82 of the voltage generating circuit 16. As a result, the voltage VSS is applied to the node APLS.

[0150] The voltages of the bit lines BL_inh, BL_pg0, BL_pg1, and BL_pg2 at time t1 will be described with reference to FIGS.

[0151] As shown in FIG. 15, in the sense amplifier unit SAU connected to the bit line BL_inh, data at the "H" level is stored in the latch circuit SDL. Therefore, the node INV_S is set to the "L" level. As a result, the transistor 31 is set to the ON state. VHSA+Vth is applied to the gates of the transistors 33 and 34. Therefore, the transistors 33 and 34 are set to the ON state, enabling the transfer of the voltage VHSA. Furthermore, the transistor 30 is set to the ON state. As a result, the sense amplifier unit SAU applies the voltage VHSA to the bit line BL_inh as the voltage VINH via the transistors 31, 33, 34, and 30.

[0152] 16, in the sense amplifier unit SAU connected to the bit lines BL_pg0, BL_pg1, and BL_pg2, data at the "L" level is stored in the latch circuit SDL. Therefore, the node INV_S is set to the "H" level. As a result, the transistor 32 is set to the ON state. The transistors 33, 34, and 30 are set to the ON state. Therefore, the sense amplifier unit SAU applies the voltage VSS to the bit lines BL_pg0, BL_pg1, and BL_pg2 via the transistors 32, 33, 34, and 30.

[0153] 14, the row decoder 18 applies a voltage VPASS to the word line WLsel. The voltage VPASS is a voltage that turns on the corresponding memory cell transistor MC regardless of the threshold voltage of the memory cell transistor MC.

[0154] The sequencer 14 sets the signal SEL2 to "2." This causes the second input terminal to be selected in the selector circuit 81 of the voltage generating circuit 16. As a result, the voltage VSS is applied to the node BLX.

[0155] The sequencer 14 sets the signal SEL3 to "2." This causes the second input terminal to be selected in the selector circuit 82 of the voltage generating circuit 16. As a result, the voltage VSS is applied to the node BLC.

[0156] 17, in the sense amplifier unit SAU, the transistors 33 and 34 are turned off, so that the bit line BL_inh is brought into a floating state.

[0157] Next, at time t3 shown in FIG. 14, the sense amplifier unit SAU executes a second arithmetic operation to update the data in the latch circuit SDL. In the second arithmetic operation, a logical OR operation is performed between the inverted data of the setting data VQPW1 and VQPW2 stored in the latch circuit TDL described with reference to FIG. 13 and the data stored in the latch circuit SDL. As a result, "H" level data is stored in the latch circuit SDL corresponding to the bit lines BL_inh and BL_pg2. Furthermore, "L" level data is stored in the latch circuit SDL corresponding to the bit lines BL_pg0 and BL_pg1. As at time t1, the node SEN1 is charged to "H" level based on the "H" level data stored in the latch circuit SDL.

[0158] 14, the voltage of the node SEN1 corresponding to the bit line BL_inh is set to the “L” level based on the second arithmetic operation, while the voltage of the node SEN1 corresponding to the bit line BL_pg2 is maintained at the “H” level.

[0159] 14, the sequencer 14 sets the signal SEL2 to "1." This causes the selector circuit 81 of the voltage generating circuit 16 to select the first input terminal. As a result, the voltage VBLX is applied to the node BLX.

[0160] The sequencer 14 sets the signal SEL3 to "1." This causes the first input terminal to be selected in the selector circuit 82 of the voltage generating circuit 16. As a result, the voltage VQPW1+Vth is applied to the node BLC.

[0161] The sequencer 14 sets the signal SEL4 to "0." This causes the 0th input terminal to be selected in the selector circuit 83 of the voltage generating circuit 16. As a result, the voltage VQPW2+Vth is applied to the node APLS.

[0162] 18, in the voltage generating circuit 16, the resistance values ​​r1 to r3 of the variable resistance elements 71 to 73 are adjusted so that the voltages Vnd11 to Vnd13 become the voltage VQPW2+Vth, the voltage VBLX, and the voltage VQPW1+Vth, respectively. The voltages VQPW2+Vth, the voltage VBLX, and the voltage VQPW1+Vth have the relationship "VQPW2+Vth" > "VBLX" > "VQPW1+Vth".

[0163] In the sense amplifier unit SAU connected to the bit line BL_pg2, the node INV_S is at the "L" level, so that the transistor 31 is turned on. Therefore, the voltage VHSA is applied to one end of the transistor 33. The voltage VBLX is applied to the gate of the transistor 33. Therefore, the voltage VBLX-Vth is applied to one end of the transistor 34. Furthermore, because the node SEN1 is at the "H" level, the transistor 38 is turned on. The voltage VQPW2+Vth is applied to the gate of the transistor 37. Therefore, the voltage VQPW2 is applied to the other end of the transistor 34. The voltage VQPW1+Vth is applied to the gate of the transistor 34. Because the voltage VQPW1+Vth is lower than the voltage VQPW2 and the voltage VBLX-Vth, the transistor 34 is cut off. Therefore, the sense amplifier unit SAU applies the voltage VQPW2 to the bit line BL_pg2.

[0164] 14, the sense amplifier unit SAU executes a third arithmetic operation to update the data in the latch circuit SDL. In the third arithmetic operation, a logical OR operation is performed on the setting data of VQPW1 and VQPW2 stored in the latch circuit TDL and the data stored in the latch circuit SDL. As a result, "H" level data is stored in the latch circuits SDL corresponding to the bit lines BL_inh, BL_pg1, and BL_pg2.

[0165] As shown in FIG. 19, in the sense amplifier unit SAU connected to the bit line BL_pg1, the node INV_S is at the "L" level, so that the transistor 31 is turned on. Therefore, the voltage VHSA is applied to one end of the transistor 33. The voltage VBLX is applied to the gate of the transistor 33. Therefore, the voltage VBLX-Vth is applied to one end of the transistor 34. Furthermore, the node SEN1 is at the "L" level, so that the transistor 38 is turned off. Therefore, the voltage VQPW2 is not applied to the other end of the transistor 34. The transistor 34 clamps the voltage of the bit line BL_pg1 to VQPW1 based on the voltage VQPW1+Vth applied to the gate. That is, the sense amplifier unit SAU applies the voltage VQPW1 to the bit line BL_pg1.

[0166] 14, the row decoder 18 applies a voltage VPGM to the word line WLsel. During the period from times t6 to t7, the program voltage VPGM is applied to the word line WLsel. During this period, the sense amplifier 19 applies a voltage VSS to the bit line BL_pg0, a voltage VPQW1 to the bit line BL_pg1, a voltage VQPW2 to the bit line BL_pg2, and a voltage VINH (=VHSA) to the bit line BL_inh. This causes charges based on the channel voltage to be injected into the charge storage layer of the memory cell transistor MCsel.

[0167] After that, at time t8, a recovery operation is performed and each wiring is reset. The sequencer 14 sets the signals SEL1 to SEL4 to "1", "2", "2", and "1", respectively.

[0168] 1.3.8 Write Operation Flow Next, an example of the flow of a write operation will be described with reference to FIG. 20. FIG. 20 is a flowchart of the write operation. In the following description, a variable j (j is an integer equal to or greater than 1) is used as the count number (number of times) of a program loop. A variable k (k is an integer equal to or greater than 1) is used as the count number of a program loop in which a VL1 verify operation in the "S1" state is set. The variable j is a variable controlled by, for example, a counter provided in the sequencer 14. The variable j is incremented with each repetition of the program loop. The variable k is a preset fixed value.

[0169] 20, first, the sequencer 14 sets a variable j to 1. The sequencer 14 also sets N to 1 as the number of the write state in which the cell determination is to be performed (step S10).

[0170] The sequencer 14 executes a program operation and a verify operation corresponding to the first program loop (step S11).

[0171] The sequencer 14 increments the variable j to j=j+1 (step S12).

[0172] The sequencer 14 checks whether the variable j has reached the variable k (step S13).

[0173] If j=k is not satisfied (No in step S13), that is, if the number of program loops j has not reached the preset variable k, the sequencer 14 proceeds to S11.

[0174] On the other hand, if j=k (step S13_Yes), that is, if the number of program loops j reaches the preset variable k, the sequencer 14 also performs a VL1 verify operation corresponding to the “S1” state in the verify operation in the next jth program loop (step S14).

[0175] The sequencer 14 performs cell determination in the "S(N)" state (step S15). More specifically, when N=1, the sequencer 14 performs cell determination in the "S1" state based on the result of the VL1 verify operation. Also, when N≧2, the sequencer 14 performs cell determination in the "S(N)" state based on the result of the VH verify operation in the "S(N-1)" state.

[0176] The sequencer 14 increments the variable j to j=j+1 (step S16).

[0177] The sequencer 14 executes the program operation and the verify operation corresponding to the j-th program loop (step S17).

[0178] The sequencer 14 executes a detection operation to determine whether the write operation of the "S(N)" state is completed (step S18).

[0179] If it is determined that the write operation of the "S(N)" state is not completed (step S18_No), the sequencer 14 proceeds to S16.

[0180] On the other hand, if it is determined that the write operation of the "S(N)" state is completed (step S18_Yes), the sequencer 14 checks whether N has reached the upper limit value (the highest write state) (step S19). That is, the sequencer 14 checks whether the write operations of all states are completed.

[0181] If N has not reached the upper limit (No in step S19), the sequencer 14 increments N to N+1 (step S20). After that, the sequencer 14 proceeds to S15.

[0182] On the other hand, if N has reached the upper limit (Yes in step S19), the sequencer 14 ends the write operation.

[0183] 1.4 Effects of this embodiment In the case of the semiconductor memory device according to the above embodiment, the reliability can be improved. Hereinafter, this effect will be described in detail.

[0184] In a semiconductor memory device, the threshold voltage of a memory cell transistor MC to be written is determined according to the threshold voltage before exceeding the verify voltage in the write state and the amount of increase in the threshold voltage due to the program operation executed thereafter. The threshold voltages of a plurality of memory cell transistors MC after the write operation have variations close to a normal distribution. Such variations in the threshold voltage of the memory cell transistor MC can occur according to variations in the write characteristics of the memory cell transistor MC and the step-up width of the program voltage. In order to speed up the write operation, it is preferable to increase the step-up width of the program voltage. However, increasing the step-up width of the program voltage can cause the spread of the threshold voltage distribution of the memory cell transistor MC. [[ID=:5]]

[0185] On the other hand, the semiconductor memory device 1 according to the present embodiment can set three types of verify voltages (first verify low voltage VL1, second verify low voltage VL2, and verify high voltage VH) for each write state. The voltages VL1, VL2, and VH are in the relationship of VL1 < VL2 < VH. In the first verify operation using the first verify low voltage VL1, it is possible to distinguish between a memory cell transistor MC (fast cell) with a relatively large amount of increase in the threshold voltage due to the program operation and a memory cell transistor MC (slow cell) with a relatively small amount. Then, different program conditions can be applied to the fast cells and the slow cells based on the VL2 verify operation using the second verify low voltage VL2 and the VH verify operation using the verify high voltage VH. Thereby, the variation in the amount of increase in the threshold voltage can be reduced between the fast cells and the slow cells.

[0186] For example, for memory cell transistors MC (including both slow cells and fast cells) that have failed the VL2 verification operation, the semiconductor memory device 1 applies program condition PG0 in the next programming operation. For slow cells that have passed the VL2 verification operation and failed the VH verification operation, the semiconductor memory device 1 applies program condition PG1 with the next programming operation being the last programming operation. For fast cells that have passed the VL2 verification operation and failed the VH verification operation, the semiconductor memory device 1 applies program condition PG2 with the next programming operation being the last programming operation. The semiconductor memory device 1 sets memory cell transistors MC (including both slow cells and fast cells) that have passed the VH verification operation to program prohibition. Then, in the next programming operation, the semiconductor memory device 1 applies a program prohibition condition. The program condition PG0, the program condition PG1, the program condition PG2, and the program prohibition condition have different voltages of bit line BL in the programming operation. The voltages of bit line BL are in the relationship of BL_pg0 < BL_pg1 < BL_pg2 < BL_inh. The semiconductor memory device 1 can control the amount of increase in the threshold voltage of the memory cell transistor MC based on the voltage of the bit line BL.

[0187] More specifically, the semiconductor memory device 1 can make the amount of increase in the threshold voltage of memory cell transistors MC (including both slow cells and fast cells) that have passed the VL2 verification operation and failed the VH verification operation smaller than the amount of increase in the threshold voltage of memory cell transistors MC that have failed the VL2 verification operation by making the voltages of bit lines BL_pg1 and BL_pg2 higher than the voltage of bit line L_pg0. Further, the semiconductor memory device 1 can reduce the variation between the amount of increase in the threshold voltage of slow cells and the amount of increase in the threshold voltage of fast cells in the programming operation of memory cell transistors MC that have passed the VL2 verification operation and failed the VH verification operation by making the voltage of bit line BL_pg1 lower than the voltage of bit line BL_pg2.

[0188] This can reduce the variation in the threshold voltages of the plurality of memory cell transistors MC included in the write state. Further, in the last program operation of the slow cells, the possibility that the threshold voltage becomes equal to or lower than the voltage VH (does not reach the voltage VH) can be reduced. Therefore, the reliability of the semiconductor memory device 1 can be improved.

[0189] Furthermore, in the configuration according to the present embodiment, as the first verify low voltage VL1 of the "S(N)" (N is an integer of 2 or more) state, the verify high voltage VH of the previous "S(N - 1)" state can be assigned. Thereby, the verify operation can be simplified. Therefore, a decrease in the processing ability of the semiconductor memory device 1 can be suppressed.

[0190] Furthermore, in the configuration according to the present embodiment, the sense amplifier 19 can apply different voltages to the bit lines BL_pg0, BL_pg1, BL_pg2, and BL_inh in the program operation. For example, the sense amplifier 19 can apply the voltage VSS to the bit line BL_pg0, the voltage VQPW1 to the bit line BL_pg1, the voltage VQPW2 to the bit line BL_pg2, and the voltage VHSA to the bit line BL_inh.

[0191] Furthermore, in the configuration according to the present embodiment, in the voltage generation circuit 16, the voltages VQPW1 + Vth and VQPW2 + Vth corresponding to the voltages VQPW1 and VQPW2 can be generated by voltage division based on the plurality of variable resistance elements 71 to 73 connected in series to one power supply. Therefore, regardless of variations in the process or the like, the relationship VQPW1 + Vth < VQPW2 + Vth can be maintained. Therefore, the reliability of the semiconductor memory device 1 can be improved.

[0192] 2. Second Embodiment Next, the second embodiment will be described. In the second embodiment, two examples of setting the first verify low voltage VL1 are shown. Hereinafter, the description will focus on the differences from the first embodiment.

[0193] 2.1 First Example First, a first example will be described. In the first example, a VL1 verify operation is not performed in one or more write states, i.e., cell determination to distinguish between slow and fast cells is not performed. For example, when the number of program loops is small, the variation between the threshold voltages of slow and fast cells is small. Therefore, cell determination can be omitted in write states with a low verify high voltage VH. In write states where cell determination is not performed, a PG2 program operation using voltage VQPW2 is performed on memory cell transistors MCsel whose threshold voltages exceed voltage VL2 but are equal to or less than voltage VH.

[0194] First, an example of verify voltage setting will be described with reference to Fig. 21. Fig. 21 is a table showing an example of verify voltage setting.

[0195] As shown in FIG. 21, for example, the first verify low voltage VL1 is not set in the "S1" to "S3" states. That is, the sequencer 14 does not perform the VL1 verify operation, i.e., cell determination, in the "S1" to "S3" states. The sequencer 14 performs cell determination in the "S4" to "S7" states. The settings of the other verify voltages are the same as those in FIG. 12 of the first embodiment. Note that there may be one or more write states in which the first verify low voltage VL1 is not set.

[0196] Next, a specific example of the timing for executing the VL1 verify operation will be described with reference to Fig. 22. Fig. 22 is a diagram showing the relationship between the number of program loops in a write operation and the VL1 verify operation. The example shown in Fig. 22 shows a case where the verify voltage setting described with reference to Fig. 21 is applied.

[0197] As shown in FIG. 22, first, in the first program loop, data at the “L” level is stored in the latch circuit TDL corresponding to each write state. In the “S1” to “S3” states, cell determination is not performed, so the data in the latch circuit TDL is maintained at “L”. Therefore, the PG1 program operation using the voltage VQPW1 is not performed. The “S4” to “S7” states are the same as those described with reference to FIG. 13 in the first embodiment.

[0198] 2.2 Second Example Next, a second example will be described. In the second example, a case will be described in which the verify high voltage VH of the "S(N-1)" state is not used as the first verify low voltage VL1. That is, a case will be described in which the voltage VL1 is set individually in each write state. For example, the sequencer 14 executes the VL1 verify operation of the "S2" to "S7" states in the verify operation of the next program loop after it is determined that the write operation of the "S(N-1)" state has been completed.

[0199] First, an example of verify voltage setting will be described with reference to Fig. 23. Fig. 23 is a table showing an example of verify voltage setting.

[0200] The first verify low voltage VL1 in each write state will be described below. Note that the other verify voltages are the same as those in FIG. 12 of the first embodiment.

[0201] 23, the first verify low voltage VL1 in the "S1" state is a voltage V1L1. The voltage V1L1 is lower than the voltage V1L2. The first verify low voltage VL1 in the "S2" state is a voltage V2L1. The voltage V2L1 is higher than the voltage V1L2 and lower than the voltage V2L2. The voltage V2L1 may be higher or lower than the voltage V1.

[0202] The first verify low voltage VL1 in the "S3" state is a voltage V3L1. The voltage V3L1 is higher than the voltage V2L2 and lower than the voltage V3L2. The voltage V3L1 may be higher or lower than the voltage V2.

[0203] The first verify low voltage VL1 in the "S4" state is a voltage V4L1. The voltage V4L1 is higher than the voltage V3L2 and lower than the voltage V4L2. The voltage V4L1 may be higher or lower than the voltage V3.

[0204] The first verify low voltage VL1 in the "S5" state is a voltage V5L1. The voltage V5L1 is higher than the voltage V4L2 and lower than the voltage V5L2. The voltage V5L1 may be higher or lower than the voltage V4.

[0205] The first verify low voltage VL1 in the "S6" state is a voltage V6L1. The voltage V6L1 is higher than the voltage V5L2 and lower than the voltage V6L2. The voltage V6L1 may be higher or lower than the voltage V5.

[0206] The first verify low voltage VL1 in the "S7" state is a voltage V7L1. The voltage V7L1 is higher than the voltage V6L2 and lower than the voltage V7L2. The voltage V7L1 may be higher or lower than the voltage V6.

[0207] 2.3 Effects of this embodiment The configuration according to this embodiment provides the same effects as those of the first embodiment.

[0208] 3. Modifications, etc. The semiconductor memory device according to the embodiment includes a memory cell array (17) including a plurality of memory cells (MC), word lines (WL) connected to the plurality of memory cells, a plurality of bit lines (BL) connected to the plurality of memory cells, a sense amplifier (19) connected to the plurality of bit lines, and a controller (14) capable of executing a write operation including a repetition of a program loop including a program operation and a verify operation. During the program operation, while a program voltage (VPGM) is applied to the word lines, the sense amplifier applies one of a first voltage (VSS), a second voltage (VQPW1) higher than the first voltage, a third voltage (VQPW2) higher than the second voltage, and a fourth voltage (VHSA) higher than the third voltage to each of the plurality of bit lines.

[0209] The above embodiment can provide a semiconductor memory device 1 that can improve reliability.

[0210] The embodiment is not limited to the above-described embodiment, and various modifications are possible.

[0211] Furthermore, the term "connected" in the above embodiments also includes a state in which something else, such as a transistor or a resistor, is interposed between them and indirectly connected.

[0212] The embodiments are merely examples, and the scope of the invention is not limited thereto. [Explanation of symbols]

[0213] 1...Semiconductor memory device 2...Memory controller 10...Input / output circuit 11...Logic control circuit 12...Address register 13...Command register 14...Sequencer 15...Ready / Busy circuit 16...Voltage generation circuit 17...Memory cell array 18...Row decoder 19...Sense amplifier 20...Data register 21...Column decoder 30~45, 50, 51, 62, 63, 74, 75...Transistors 46...Capacitor element 60, 61...Inverter 70…Current source 71 to 73: Variable resistance elements 76~78...Driver 80~83...Selector circuit

Claims

1. a memory cell array including a plurality of memory cells; a word line connected to the plurality of memory cells; a plurality of bit lines respectively connected to the plurality of memory cells; a sense amplifier connected to the plurality of bit lines; a controller capable of executing a write operation including a repetition of a program loop including a program operation and a verify operation; Equipped with the sense amplifier applies, to each of the plurality of bit lines, one of a first voltage, a second voltage higher than the first voltage, a third voltage higher than the second voltage, and a fourth voltage higher than the third voltage while a program voltage is being applied to the word line in the program operation; the verify operation includes a first verify operation based on a first verify voltage, a second verify operation based on a second verify voltage higher than the first verify voltage, and a third verify operation based on a third verify voltage higher than the second verify voltage; the plurality of memory cells include a first memory cell whose threshold voltage is determined to be equal to or lower than a first verify voltage in the first verify operation, and a second memory cell whose threshold voltage is determined to be higher than the first verify voltage; In the program operation, the sense amplifier applies the second voltage to a bit line connected to the first memory cell, whose threshold voltage exceeds the second verify voltage and is equal to or lower than the third verify voltage, among the plurality of bit lines, and applies the third voltage to a bit line connected to the second memory cell, whose threshold voltage exceeds the second verify voltage and is equal to or lower than the third verify voltage. Semiconductor memory device.

2. In the program operation, the sense amplifier applies the first voltage to one of the plurality of bit lines connected to one of the plurality of memory cells that is a write target and has a threshold voltage lower than the second verify voltage, and applies the fourth voltage to a bit line connected to one of the plurality of memory cells that is not a write target and one of the plurality of memory cells that has a threshold voltage higher than the third verify voltage.

2. The semiconductor memory device according to claim 1.

3. each of the plurality of memory cells is capable of storing multiple bits of data; the plurality of bits of data are determined by the threshold voltage of each of the plurality of memory cells being included in one of a plurality of states; the first verify voltage corresponding to an N-th state (N is an integer equal to or greater than 2) among the plurality of states is the same as the third verify voltage corresponding to an N-1-th state; 2. The semiconductor memory device according to claim 1.

4. the first verify operation corresponding to the Nth state is based on a result of the third verify operation corresponding to the N-1th state in the program loop in which the write operation of the N-1th state has been completed; 4. The semiconductor memory device according to claim 3.

5. the sense amplifier includes a sense amplifier unit connected to each of the plurality of bit lines; The sense amplifier unit a first transistor having one end connected to a corresponding bit line and the other end connected to a first node; a second transistor having one end connected to the first node and the other end connected to a second node; a third transistor having one end connected to the second node and the other end to which a fifth voltage based on write data is applied; a fourth transistor having one end connected to the second node and the other end connected to a third node; a fifth transistor having one end connected to the first node; a sixth transistor having one end to which a sixth voltage is applied, the other end connected to the other end of the fifth transistor, and a gate connected to the third node; Including, 5. The semiconductor memory device according to claim 1.

6. During the program operation, while the program voltage is being applied to the word line, the first transistor is turned on; a seventh voltage based on the second voltage is applied to a gate of the second transistor; an eighth voltage higher than the seventh voltage is applied to the gate of the third transistor; the fourth transistor is turned off, a ninth voltage higher than the seventh voltage is applied to the gate of the fifth transistor based on the third voltage; a tenth voltage of the third node is applied to the gate of the sixth transistor; 6. The semiconductor memory device according to claim 5.

7. In the program operation, when the sense amplifier unit applies the second voltage to the corresponding bit line, the second transistor is turned on; the third transistor is turned on, and the fourth voltage is applied to the other end of the third transistor as the fifth voltage; the sixth transistor is turned off, In the program operation, when the sense amplifier unit applies the third voltage to the corresponding bit line, the second transistor is turned off; the third transistor is turned on, and the fourth voltage is applied to the other end of the third transistor as the fifth voltage; the sixth transistor is turned on; 7. The semiconductor memory device according to claim 6.

8. In the program operation, when the sense amplifier unit applies the first voltage to the corresponding bit line, the second transistor is turned on; the third transistor is turned on, and the first voltage is applied as the fifth voltage to the other end of the third transistor; the sixth transistor is turned off, In the program operation, when the sense amplifier unit applies the fourth voltage to the corresponding bit line, the second transistor and the third transistor are turned on, and the fifth transistor is turned off; 8. The semiconductor memory device according to claim 6.

9. a voltage generating circuit for supplying a voltage to the sense amplifier; The voltage generating circuit includes: a current source having an output terminal connected to the fourth node; a first variable resistance element having one end connected to the fourth node and the other end connected to a fifth node; a second variable resistance element having one end connected to the fifth node and the other end connected to a sixth node; Including, the voltage generating circuit applies the voltage of the fourth node to the gate of the fifth transistor, applies the voltage of the fifth node to the gate of the third transistor, and applies the voltage of the sixth node to the gate of the second transistor while the program voltage is being applied to the word line in the program operation; 6. The semiconductor memory device according to claim 5.

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