Method and system for in-line ECC protection

Abstract

To provide a method, a system, and an integrated circuit for in-line error correction code (ECC) protection.SOLUTION: A memory system 100 has an ECC bridge 102 that receives commands from an interconnect, manages ECC data, and performs address translation between system addresses and physical memory device addresses. The address translation is performed by calculating a first ECC memory address for a first ECC data block that is after and adjacent to a first data block having a first data address, calculating a second ECC memory address that is after and adjacent to the first ECC block, and calculating a second data address that is after and adjacent to the second ECC block. The bridge checks and calculates ECC data for a complete burst of data, and / or caches ECC data for a complete burst of data that includes read and / or write data.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] In computing systems, data stored in memory (e.g., dynamic random access memory (DRAM) or double data rate (DDR) synchronous dynamic random access memory (SDRAM)) may suffer errors during write or read operations, in the controller, physical interface (PHY) or board, or in the memory itself while the data is stored therein. Additionally, external memory is often made by a third party and / or may not be rated for or sufficiently reliable for functional safety applications. Incorrect data or commands from memory may cause the system to operate incorrectly. Incorrect system operation is undesirable, especially in systems or applications where functional safety or reliability is important.

[0002] There are three general types of memory errors: permanent, transient, and systematic. Permanent errors are usually the result of physical damage or degradation of the memory or associated circuit elements, which could be silicon or wiring shorts. Transient errors are due to particle strikes and typically result in a bit flip state (e.g., in a flip-flop). Systematic errors are logic bugs; for example, the system may be working correctly as designed, but may simply have a hardware or software bug. Summary of the Invention

[0003] Examples described herein include an integrated circuit including an interconnect configured to receive commands from a system to read data from and / or write data to physical addresses of a memory device. The integrated circuit further includes a bridge configured to receive the commands from the interconnect and to perform address translation between system addresses and physical addresses. The address translation is performed by calculating a first error correcting code (ECC) memory address for a first data block after and adjacent to a first ECC data block having a first data address, calculating a second ECC memory address after and adjacent to the first ECC data block, and calculating a second command address after and adjacent to the second ECC system.

[0004] Another example integrated circuit described herein includes an interconnect configured to receive commands from a system to read and / or write a portion of data. The integrated circuit also includes a bridge configured to receive the commands from the interconnect and to check and calculate ECC data for bursts of data that include the portion of data.

[0005] Another example integrated circuit described herein includes an interconnect configured to receive commands from a system to read and / or write a portion of data. The integrated circuit further includes a bridge configured to receive the commands from the interconnect and to check and calculate ECC data. The bridge is further configured to cache the ECC data for a complete burst of data that includes the portion of data.

[0006] Examples described herein also include a memory system having a memory device, a processor, and an interconnect, where the interconnect is configured to receive commands from the processor to read data from and / or write data to physical addresses of the memory device. The memory device further includes a bridge configured to receive commands from the interconnect and to perform address translation between system addresses and physical addresses. The address translation is performed by calculating a first ECC memory address after and adjacent to a first data block having a first data address, calculating a second ECC memory address after and adjacent to the first ECC block, and calculating a second data address after and adjacent to the second ECC block.

[0007] Another example memory device described herein includes a memory system including a memory device, a processor, and an interconnect, and a bridge. The interconnect is configured to receive commands from the processor to read and / or write portions of data to the memory device. The bridge is configured to receive the commands from the interconnect and to check and calculate ECC data, the bridge being further configured to cache the ECC data for complete bursts of data that include the portions of data.

[0008] Examples described herein also include a method of writing data to or reading data from external memory, the method including receiving a command from a system to read and / or write a portion of the data, and caching ECC data for a complete burst of data that includes the portion of the data.

[0009] Also described herein is an exemplary method for writing data to or reading data from an external memory, the method including receiving a command from a system to read and / or write a portion of the data, and checking ECC data for a complete burst of data that includes the portion of the data.

[0010] Also described herein is an example method for converting a system memory address to a physical memory address, the method including providing a first ECC block associated with a first data block and providing a second ECC block associated with a second data block, the method also including calculating a first ECC memory address for a first ECC data block after and adjacent to the first data block having the first data address, calculating a second ECC memory address after and adjacent to the first ECC block, and calculating a second data address for a second data block after and adjacent to the second ECC block.

[0011] For a detailed description of various examples, reference will now be made to the accompanying drawings. [Brief explanation of the drawings]

[0012] [Figure 1] 1 illustrates a block diagram of an exemplary memory system.

[0013] [Figure 2] 1 illustrates a block diagram of an example ECC bridge.

[0014] [Figure 3] 1 illustrates a block diagram of an exemplary read-modify-write block.

[0015] [Figure 4] 1 illustrates a block diagram of an example inline ECC block.

[0016] [Figure 5] 1 illustrates an exemplary addressing pattern.

[0017] [Figure 6] 6 illustrates an example portion of the example addressing pattern of FIG. 5.

[0018] [Figure 7] 1 illustrates a block diagram of an exemplary state machine (SM) block.

[0019] [Figure 8] 1 illustrates an example device including an example memory system described herein. DETAILED DESCRIPTION OF THE INVENTION

[0020] The phrase "based on" means "based at least in part on." Thus, if X is based on Y, X can be a function of Y and any number of other factors.

[0021] The examples described herein calculate single error correcting, double error detecting (SECDED) ECC across each word of the burst. The size of the burst depends on the requirements of the memory device and is typically a power of two (e.g., 16, 32, 64, 128, 256). The ECC syndrome is stored intermixed with the regular data ("inline") so that the burst of data or ECC data does not extend across page boundaries. Generally, storage and retrieval consist of two separate commands: one for the data and one for the ECC syndrome. Address calculations for the data and ECC syndrome can be done automatically so that the host system still sees a flat, contiguous memory map. Address calculations can use a rolling system, ensuring that permanent defects at a single address are not masked by losing an entire chunk of data / ECC.

[0022] Additionally, some embodiments calculate and check the ECC over the entire burst, regardless of how much data is written or read, to further ensure there are no issues with bursts or aliasing of ECC syndromes that provide false matches. The example systems described herein automatically perform read-modify-write (RMW) operations when less than a full ECC quanta of data are written while maintaining full data consistency. The example systems described herein also implement an ECC cache where writes and reads are stored and merged to reduce RMW operations that can occur when receiving sub-burst writes and multiple reads that would be required when requesting sub-burst reads.

[0023] FIG. 1 illustrates a memory system 100 according to an example described herein. The memory system 100 includes an interconnect 101 that provides an interface for a master 107 to read from and / or write to memory. The master 107 may include, for example, a processor. The interconnect 101 performs the necessary translations and sends calls from the master 107 to an ECC bridge 102. The ECC bridge 102 serves as an interface between the computing system and the memory device. The ECC bridge 102 may handle, for example, error correcting code (ECC) checking, address translation between system addresses and physical addresses, and voltage translation between the computing system domain and the memory device domain (starting at the memory controller 102). The memory domain includes a memory controller 103, a physical layer (PHY) 104, board traces 105, and the memory device 106 itself. The memory controller 103, physical layer (PHY) 104, board traces 105, and memory device 106 may be, for example, SDRAM or external or internal RAM.

[0024] 2 shows a block diagram of ECC bridge 102. ECC bridge 102 interfaces with interconnect 101 operating at a computing system voltage using computing system voltage domain 201. ECC bridge 102 also includes memory voltage domain 203 for interfacing with memory devices 106 operating at a memory voltage (e.g., DDR voltage). ECC bridge 102 also includes voltage converter 202 for performing voltage conversion between computing system voltage domain 201 and memory voltage domain 203.

[0025] The memory voltage domain 203 includes a command arbiter 204 that receives voltage-converted read or write commands (and accompanying data) from the voltage converter 202 and queues the received commands. The read-modify-write (RMW) block 205 handles read-modify-write operations, e.g., read commands versus incomplete ECC quantum write commands. The ECC quantum is the size of data per ECC syndrome (e.g., 8 bytes of data). The inline ECC block 206 performs three main functions: ECC append / calculation, caching ECC data, and translating system addresses to physical addresses in the memory device.

[0026] The RMW block 205 is shown in more detail in FIG. 3. Commands and data from the command arbiter 204 are received by an arbitration scheduler 301, which consumes, routes incoming commands, and performs additional necessary tasks for the RMW block 205. The arbitration scheduler 301 may forward to the inline ECC block 206 any command that does not require additional processing by the RMW block 205 (as described below) and / or that is not an address collision (coherent) with any command in the RMW backlog holding queue 302, which may be a first-in, first-out (FIFO) queue. For example, the arbitration scheduler 301 may forward a write command to the inline ECC block 206 if any of the following conditions are met: (1) all write data byte enables are set to an ECC quantum; (2) the system address is not in an ECC-protected region; or (3) the data is not coherent with any command in the RMW backlog holding queue 302. The arbitration scheduler 301 may forward a read command to the inline ECC block 206 if the data is not coherent for any command in the RMW backlog holding queue 302. Commands forwarded by the arbitration scheduler 301 to the inline ECC block 206 may be forwarded via the multi-threaded FIFO queue 304.

[0027] For a command to write a partial ECC quantum of data, arbitration scheduler 301 issues a read command for the entire burst of data and places a write command in RMW backlog holding queue 302. When the read data is returned from state machine (SM) 207, it is placed in data merger block 303 where it is merged with the partial quantum write data placed in RMW backlog holding queue 302. Data merger block 303 routes the merged data to arbitration scheduler 301, which issues a write command for the merged data burst that is routed to inline ECC 206.

[0028] The arbitration scheduler 301 also processes commands in the RMW backlog holding queue 302 that are no longer coherent due to a change in conditions. In this case, the data may require a merger as described above, or the command may simply be passed to the inline ECC 206. As described above, the RMW backlog holding queue 302 holds commands and data that are either waiting for coherency resolution or for returned data due to a partial write.

[0029] The inline ECC block 206 is shown in more detail in FIG. 4. Commands and data sent to the inline ECC block 206 are received by a command arbitration and generation block 401 and an ECC encoding block 405. The ECC encoding block 405 calculates an ECC for the quantum of data to be written with a write command. The ECC encoding block 405 may also optionally encode the address of the data into each ECC. The encoded address may be the address of an ECC quantum, burst, or block, may be a system or virtual address, or may be a physical address within the memory device. One or more of these addresses may be encoded into each ECC syndrome.

[0030] For inbound commands, command arbitration and generation block 401 generates a sequence of commands based on ECC domain and ownership information. For example, a cache entry may be "owned" by a particular CPU and may be available only to that CPU. A small set of ECC cache lines in ECC cache buffer 402 may be reserved for all other system initiators.

[0031] When a read command is received by command arbitration and generation block 401, command arbitration and generation block 401 determines whether the ECC for the associated data is already in ECC cache buffer 402. If the ECC is in ECC cache buffer 402, command arbitration and generation block 401 routes the read command to SM 207 and uses the cached ECC. If the ECC for the associated data is not in ECC cache buffer 402, but ECC cache buffer 402 has space to cache the ECC block, command arbitration and generation block 401 routes the read command to SM 207 for both the data and the ECC block. When SM 207 returns the ECC blocks, they are stored in ECC cache buffer 402 (optionally via multi-threaded FIFO queue 404). If the ECC for the associated data is not in the ECC cache buffer 402 and there is no available space for an additional ECC block, the ECC cache buffer 402 removes the oldest read ECC data before sending a read command for both the data and the ECC block to the SM 207. If the removed ECC data is "dirty," i.e., the cached ECC data differs from the ECC data stored in physical memory, the ECC block may be written to external memory.

[0032] When a write command is received by the command arbitration and generation block 401, the command arbitration and generation block 401 determines whether the ECC for the associated data is already in the ECC cache buffer 402. If the ECC is in the ECC cache buffer 402, the ECC is merged with the cached ECC in the ECC cache buffer 402 and marked as "dirty." If the ECC for the associated data is not in the ECC cache buffer 402, but the ECC cache buffer 402 has space to cache the ECC block, the oldest owned entry in the ECC cache buffer 402 is allocated, and the ECC is stored in that space and marked as "dirty." The command arbitration and generation block 401 issues a write command to the SM 207 for the data block.

[0033] If the ECC for the associated data is not in the ECC cache buffer 402 and the space in the ECC cache buffer is not owned, the command arbitration and generation block 401 issues a write command to the SM 207 for the data block. If the ECC for the associated data is not in the ECC cache buffer 402 and all owned entries are dirty, the oldest entry in the ECC cache buffer 402 may be removed and, if dirty, written to external memory. This space may be reallocated, and the ECC for the write command may be written to the reallocated space in the ECC cache buffer 402.

[0034] Commands sent to the SM 207 by the command arbitration and generation block 401 may be sent via a multi-threaded FIFO queue 403 .

[0035] In the example inline ECC block 206 of Figure 4, an ECC cache buffer 402 holds previously read and written ECC blocks for future use. For each byte of ECC data, the ECC cache buffer 402 has a "dirty" flag that indicates whether the cached ECC byte differs from the ECC byte stored in physical memory. In the example described herein, each entry in the ECC cache buffer holds ECC syndrome data for eight bursts of data. In this case, the ECC cache buffer holds 64 bytes of ECC syndrome data for eight contiguous data blocks (512 bytes).

[0036] As mentioned above, the inline ECC block 206 also performs address translation between system addresses and physical memory addresses. The command arbitration and generation block 401 performs this address translation and inserts the translated addresses into read and write commands issued to the SM 207. In the example described herein, the system addresses are translated so that two 64-byte ECC blocks are placed between two 512-byte data blocks (each having eight 64-byte memory bursts). An example of this address translation is shown in FIG. 5. As can be seen from FIG. 5, ECC blocks 52 and 53 are placed consecutively between 512-byte data blocks 51 and 54.

[0037] This address translation provides protection against defects in command or addressing by staggering all address bits across data and ECC syndrome storage. This staggered pattern provides efficient use of memory space, reserving 8 / 9 of the space for normal data use while reserving only 1 / 9 for ECC syndrome, resulting in little, if any, wasted memory space. Also, because every eight bursts (e.g., 512 bytes) of data share one block used for ECC, address bit errors will not hit an aligned ECC block, protecting the memory address as well as the data. In particular, by using a burst count that is a power of two (e.g., 8 in this example) and a burst count that is a power of three plus the ECC syndrome (e.g., burst count (8) + 1 = 9 in this example), any address bit defect prevents the data and ECC from being aligned and resulting in an error. Also, the two 64-byte ECC blocks are placed back-to-back so that burst alignment does not cross any 128-byte page boundaries. Such an arrangement may, for example, support 128-byte bursts, with the 128 bytes starting on 128-byte memory-aligned boundaries. Depending on the burst alignment configuration of the memory device, and such that the number of data blocks + ECC blocks has a prime bias, different numbers and sizes of ECC blocks and data bursts / blocks may be used.

[0038] Figure 6 shows in more detail the relationship between data blocks 51 and 54 and ECC blocks 52 and 52 of Figure 5. Data block 51 has eight 64-byte bursts d0-d7. Data block 54 has eight 64-byte bursts d8-dF. 64-byte ECC block 52 contains ECC data e0 for data block 51, and 64-byte ECC block 53 contains ECC data e1 for ECC block 54. Using the address patterns of Figures 5 and 6, the first bursts of blocks 51 and 54 are always on 128-byte boundaries throughout the memory. Therefore, in this particular example, all read commands sent to the memory device should be 128-bit aligned, and all two-burst operations are always two-burst (128-byte) aligned.

[0039] Other alignment examples are also contemplated by the present system. For example, 256-byte alignment can be used with a 64-burst memory device. In such a case, four 64-byte ECC blocks are placed between 16 blocks of data. This ensures that all 256-byte aligned master requests are 256-byte aligned on the memory device.

[0040] 7 shows a block diagram of state machine (SM) 207. Arbiter 701 is responsible for arbitrating commands to memory controller 103 to ensure resources are available. Commands sent by arbiter 701 to memory controller 103 may be routed through multi-threaded FIFO queue 704. When read return FIFO 703 receives data and ECC from a memory device (such as memory device 106 of FIG. 1) in response to a read command, the read return FIFO holds the data and ownership for the data and returns the ECC data on line ECC 206. The read return FIFO 703 feeds the data to the ECC correction and detection (ECC COR / DET) block 702, which, in the case of a SECDED device, corrects single errors and / or detects double errors in the ECC-protected areas of the memory using the ECC data received from the inline ECC block 206, and returns the corrected read data to the RMW block 205 for merging. The ECC correction and detection block 702 performs this ECC check on the entire burst of data received from the memory device. Because eight ECC blocks are checked per burst, and because the ECC syndrome also includes the memory address, the chance of a false hit on the ECC syndrome in the event of an address bit error is small. The read return FIFO 703 can return the read ECC data directly to the inline ECC block 206.

[0041] Examples of ECC caches described herein (e.g., ECC cache buffer 402) provide efficient merging and caching of transactions to avoid less than optimal bursts on a memory device interface. Some embodiments check and calculate ECC over the entire burst to provide additional protection for commands and addresses, regardless of the data requested. Checking ECC over the entire data burst access (e.g., the entire 64-byte data burst for DDR memory) protects against command or address defects. Some examples also encode the address of a transaction into the ECC syndrome through a novel scheme that spreads the address across the burst, further protecting the transaction without additional bits. Some examples also protect functions (e.g., address translation, ECC generation, etc.) with additional diagnostics such as parity to enable higher error detection rates. Some examples can be further enhanced by adding obfuscation or encryption to protect data and enhance error detection.

[0042] The solution described herein is advantageous over existing solutions because it provides more efficient use of address space (potentially eliminating wasted memory), provides better protection against address defects (row, column, bank, and rank) by using a novel address translation scheme, provides more efficient use of the memory interface by minimizing RMW and sub-burst accesses, provides protection for the entire memory controller by generating two independent commands before entering the memory command queue, and provides additional protection by encoding addresses into ECC syndromes.

[0043] The inline ECC protection techniques described herein may be implemented in any type of electronics system or device and are particularly useful for systems and devices in applications where functional safety is important, such as automotive (e.g., ADAS or advanced driver assistance systems) or industrial applications. One example of such a device may include various internal and / or external components that contribute to the device's functionality, which may include hardware elements (including circuit elements), software elements (including computer code stored on a tangible computer-readable medium), or a combination of hardware and / or software elements. Such a device may include input / output (I / O) ports, input structures, one or more processors, memory, a power supply, etc.

[0044] FIG. 8 illustrates one such example device 80 having an example processor 81 and memory device 100 according to examples described herein.

[0045] The processor 81 may control the overall operation of the device 80. For example, the processor 81 may provide processing power for running the operating system, programs, user and application interfaces, and any other functions of the device. The processor 81 may include one or more microprocessors, such as one or more general-purpose microprocessors, application-specific microprocessors (ASICs), or a combination of such processing components. The processor 81 may include one or more processors based on x86 or RISC architectures, as well as dedicated graphics processors (GPUs), image signal processors, digital signal processors, video processors, audio, and / or related chipsets. The processor 81 may include multiple processing cores of the same or different types and may be implemented as a system-on-a-chip (SOC) device.

[0046] Instructions or data to be processed by processor 81 may be stored on a computer-readable medium such as memory device 100. Memory device 100 may include a memory device (e.g., DRAM, SDRAM, or internal memory) and an ECC bridge that implements the in-line ECC functionality described above.

[0047] Although ECC functionality and address translation are described herein as occurring in ECC bridge 102, this functionality may instead be implemented, in whole or in part, in another component (e.g., memory controller 103).

[0048] Modifications may be made to the exemplary embodiments described, and other embodiments are possible, within the scope of the claims of the invention.

Claims

1. 1. An integrated circuit comprising: an error correction code (ECC) circuit configured to be coupled to a memory, An arbitration circuit, receiving a memory command directed to the memory, the memory command relating to reading or writing a first unit of data; determining a first data address associated with the first unit of data and a first ECC address associated with first ECC data based on the memory command; The arbitration circuit is configured as follows: the ECC circuit, Including, the first ECC data is associated with a first plurality of units of data, the first plurality of units of data including the first unit of data and a second unit of data; In an address space of the memory, the first unit of data is followed by the second unit of data which is followed by the first ECC data, the first ECC data is adjacent to second ECC data associated with a second plurality of units of data including a third unit of data, and the second ECC data is followed by the third unit of data; the first unit of data is a burst of first data, and the second unit of data is a burst of second data; The integrated circuit, wherein the first ECC data is associated with a plurality of bursts of data, including the first burst of data and the second burst of data.

2. 10. The integrated circuit of claim 1, The integrated circuit, wherein the first plurality of units of data are adjacent to the first ECC data in the address space of the memory.

3. 3. An integrated circuit according to claim 2, The integrated circuit, wherein the second ECC data is adjacent to the second plurality of units of data in the address space of the memory.

4. 10. The integrated circuit of claim 1, 10. An integrated circuit, wherein the first unit of data has a size of 64 bytes and the plurality of bursts of data have a size of 512 bytes.

5. 1. An integrated circuit comprising: an error correction code (ECC) circuit configured to be coupled to a memory, An arbitration circuit, receiving a memory command directed to the memory, the memory command relating to reading or writing a first unit of data; determining a first data address associated with the first unit of data and a first ECC address associated with first ECC data based on the memory command; the arbitration circuit configured as follows: an ECC buffer coupled to the arbitration circuit, the ECC buffer configured to store the first ECC data associated with the first unit of data and the second unit of data; the ECC circuit including in an address space of the memory, the first unit of data is followed by the second unit of data which is followed by the first ECC data, the first ECC data is adjacent to second ECC data associated with a third unit of data, and the second ECC data is followed by the third unit of data; the arbitration circuit is further configured to determine, when the memory command relates to reading the unit of first data, whether to request the first ECC data from the memory based on whether the first ECC data is cached in the ECC buffer.

6. 6. An integrated circuit according to claim 5, The ECC circuit an ECC encoder circuit coupled to the arbitration circuit, when the memory command relates to writing the first unit of data; generating the first ECC data; storing the first ECC data in the ECC buffer; an integrated circuit further comprising the ECC encoder circuit configured to:

7. 7. An integrated circuit according to claim 6, The integrated circuit, wherein the ECC encoder circuit is further configured to encode at least one of the first data address and the first ECC address in the first ECC data.

8. 1. An integrated circuit comprising: an error correction code (ECC) circuit configured to be coupled to a memory, An arbitration circuit, receiving a memory command directed to the memory, the memory command relating to reading or writing a first unit of data; determining a first data address associated with the first unit of data and a first ECC address associated with first ECC data based on the memory command; The arbitration circuit is configured as follows: the ECC circuit, a read-modify-write (RMW) circuit coupled to the ECC circuit, the RMW circuit including a scheduler circuit and a data consolidation circuit coupled to the scheduler circuit; Including, the first ECC data is associated with the first unit of data and the second unit of data; in an address space of the memory, the first unit of data is followed by the second unit of data which is followed by the first ECC data, the first ECC data is adjacent to second ECC data associated with a third unit of data, and the second ECC data is followed by the third unit of data; The scheduler circuit determining whether the first unit of data is less than an ECC quantum; when the first unit of data is less than the ECC quantum and the memory command relates to writing the first unit of data, requesting a fourth unit of data from the memory, causing the data combining circuit to combine the fourth unit of data with the first unit of data to create a combined unit of data, and providing the combined unit of data to the ECC circuit; 1. An integrated circuit configured to:

9. 9. An integrated circuit according to claim 8, The integrated circuit further includes a memory controller coupled to the ECC circuit and the memory.

10. 1. An integrated circuit comprising: an error correction code (ECC) circuit configured to be coupled to a memory, An arbitration circuit, receiving a memory command directed to the memory, the memory command relating to reading or writing a first unit of data; determining a first data address associated with the first unit of data and a first ECC address associated with first ECC data based on the memory command; The arbitration circuit is configured as follows: the ECC circuit, a set of processors; an interconnect coupled between the ECC circuitry and the set of processors; Including, the first ECC data is associated with the first unit of data and the second unit of data; 1. An integrated circuit, wherein in the address space of the memory, a unit of first data is followed by a unit of second data which is followed by the first ECC data, the first ECC data is adjacent to second ECC data associated with a unit of third data, and the second ECC data is followed by the third unit of data.

11. 1. A method comprising: receiving a memory command directed to a memory associated with a first unit of data; determining a first data address for the first unit of data in an address space of the memory; determining a first ECC address for first ECC data associated with a first plurality of units of data in an address space of the memory, the first unit of data and a second unit of data; the first unit of data is followed in an address space of the memory by the second unit of data which is followed by the first ECC data; the first ECC data being adjacent in the address space of the memory to second ECC data associated with a second plurality of units of data including a third unit of data; the second ECC data follows the third unit of data in the address space of the memory; determining the first ECC address; accessing the memory using at least one of the first data address and the first ECC address; Including, the first unit of data is a burst of first data, and the second unit of data is a burst of second data; The method, wherein the first ECC data is associated with a plurality of bursts of data, including the first burst of data and the second burst of data.

12. 12. The method of claim 11, The method, wherein the first plurality of units of data are contiguous to the first ECC data in the address space of the memory.

13. 13. The method of claim 12, The method, wherein the second ECC data is adjacent to the second plurality of units of data in the memory address space.

14. 12. The method of claim 11, The method, wherein the first unit of data has a size of 64 bytes and the plurality of bursts of data have a size of 512 bytes.

15. 1. A method comprising: receiving a memory command directed to a memory associated with a first unit of data; determining a first data address for the first unit of data in an address space of the memory; determining a first ECC address for first ECC data associated with the first unit of data and the second unit of data in an address space of the memory; the first unit of data is followed in an address space of the memory by the second unit of data which is followed by the first ECC data; the first ECC data being adjacent in the address space of the memory to second ECC data associated with a third unit of data; the second ECC data follows the third unit of data in the address space of the memory; determining the first ECC address; accessing the memory using at least one of the first data address and the first ECC address; determining whether the first ECC data is present in an ECC buffer; determining whether to access the memory using the first ECC address based on whether the first ECC data exists in the ECC buffer; A method comprising:

16. 1. A method comprising: receiving a memory command directed to a memory associated with a first unit of data; determining a first data address for the first unit of data in an address space of the memory; determining a first ECC address for first ECC data associated with the first unit of data and the second unit of data in an address space of the memory; the first unit of data is followed in an address space of the memory by the second unit of data which is followed by the first ECC data; the first ECC data being adjacent in the address space of the memory to second ECC data associated with a third unit of data; the second ECC data follows the third unit of data in the address space of the memory; determining the first ECC address; accessing the memory using at least one of the first data address and the first ECC address; generating the first ECC data; storing the first ECC data in an ECC buffer before storing the first ECC data in the memory; The method further comprises:

17. 17. The method of claim 16, The method, wherein generating the first ECC data includes encoding at least one of the first data address and the first ECC address in the first ECC data.

18. 1. A method comprising: receiving a memory command directed to a memory associated with a first unit of data; determining a first data address for the first unit of data in an address space of the memory; determining a first ECC address for first ECC data associated with the first unit of data and the second unit of data in an address space of the memory; the first unit of data is followed in an address space of the memory by the second unit of data which is followed by the first ECC data; the first ECC data being adjacent in the address space of the memory to second ECC data associated with a third unit of data; the second ECC data follows the third unit of data in the address space of the memory; determining the first ECC address; accessing the memory using at least one of the first data address and the first ECC address; determining whether the first unit of data is less than an ECC quantum; when the first unit of data is less than the ECC quantum and the memory command is directed to write the first unit of data, requesting a fourth unit of data from the memory, aggregating the fourth unit of data and the first unit of data to create a consolidated unit of data, and writing the consolidated unit of data to the memory based on the first data address; The method further comprises:

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