Multilayer electronic components

Abstract

To achieve a laminated electronic component capable of lowering the height thereof.SOLUTION: An electronic component 1 includes a ground conductor layer 611, inductors L11, L12, capacitors C11, C12, and a laminate 50. The inductor L11 and the capacitor C11 and the inductor L12 and the capacitor C12 are used to configure LC resonators 11, 12, respectively. In a lamination direction T, the LC resonators 11, 12 each exist between a bottom face 50A of the laminate 50 and the ground conductor layer 611, but do not exist between a top face 50B of the laminate 50 and the ground conductor layer 611. In the lamination direction T, the inductors L11, L12 are disposed between the bottom face 50A and the capacitor C11 and between the bottom face 50A and the capacitor C12, respectively.SELECTED DRAWING: Figure 7

Description

[Technical Field]

[0001] The present invention relates to a multilayer electronic component having a ground conductor layer that covers an LC resonator. [Background technology]

[0002] In recent years, small mobile communication devices such as mobile phones and smartphones have become increasingly multifunctional and compact, and as a result, electronic components are being mounted at higher densities. As a result, the spacing between multiple electronic components mounted on a mounting board in small mobile communication devices is becoming smaller.

[0003] When the distance between multiple electronic components becomes small, electromagnetic interference between the multiple electronic components becomes more likely to occur. In response to this, for example, Patent Document 1 discloses a bandpass filter that blocks external noise by providing a ground electrode on the upper surface side. The bandpass filter disclosed in Patent Document 1 includes an LC resonator in which the line electrode of the inductor faces the ground electrode. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2013-128232 Summary of the Invention [Problem to be solved by the invention]

[0005] Electronic components used in small mobile communication devices are also required to be smaller and have a lower profile. Consider the case of reducing the profile of an electronic component, such as the bandpass filter disclosed in Patent Document 1, in which an inductor conductor layer constituting an inductor faces a ground conductor layer connected to ground. In this case, if the distance between the inductor conductor layer and the ground conductor layer is reduced, stray capacitance may occur between the inductor conductor layer and the ground conductor layer, potentially preventing desired characteristics from being achieved. Therefore, in electronic components with the above structure, it is difficult to reduce the distance between the inductor conductor layer and the ground conductor layer, and as a result, it has been difficult to reduce the profile of the electronic component.

[0006] The present invention has been made in view of the above problems, and an object of the present invention is to provide a multilayer electronic component that includes a ground conductor layer that covers an LC resonator, and that can be made low-profile. [Means for solving the problem]

[0007] The multilayer electronic component of the present invention includes a ground conductor layer connected to ground, at least one inductor, multiple capacitors, and a laminate. The laminate includes multiple dielectric layers stacked together and has a first surface facing a substrate and a second surface opposite the first surface. The laminate is for integrating the ground conductor layer, the at least one inductor, and the multiple capacitors. The at least one inductor and the multiple capacitors are used to form at least one LC resonator. The at least one LC resonator is located between the first surface and the ground conductor layer in the stacking direction of the multiple dielectric layers, but not between the second surface and the ground conductor layer. The at least one inductor is located between the first surface and the multiple capacitors in the stacking direction.

[0008] In the multilayer electronic component of the present invention, the ground conductor layer may be disposed in a position closer to the second surface than to the first surface within the multilayer body.

[0009] The multilayer electronic component of the present invention may further include a plurality of capacitor conductor layers each integrated into the laminate and facing a ground conductor layer. In this case, the plurality of dielectric layers may include at least one dielectric layer interposed between the ground conductor layer and the plurality of capacitor conductor layers. The plurality of capacitors may be composed of a ground conductor layer, the plurality of capacitor conductor layers, and at least one dielectric layer.

[0010] In the multilayer electronic component of the present invention, the at least one LC resonator may be a plurality of LC resonators. In this case, the at least one inductor may be a plurality of inductors. In this case, each of the plurality of LC resonators may be formed by at least one inductor of the plurality of inductors and at least one capacitor of the plurality of capacitors.

[0011] In the multilayer electronic component of the present invention, at least one inductor may include a first row of through holes, a second row of through holes, and an inductor conductor layer connecting the first row of through holes and the second row of through holes. Each of the first row of through holes and the second row of through holes may be formed by connecting two or more through holes in series. In this case, the inductor conductor layer may be disposed between the first surface and the first and second rows of through holes in the stacking direction. In this case, the inductor conductor layer may include a portion extending non-parallel to both the short-side direction and the long-side direction of each of the plurality of dielectric layers. The inductor conductor layer may also include a portion extending in a first direction perpendicular to the stacking direction and a portion extending in a second direction perpendicular to the stacking direction and intersecting the first direction.

[0012] The multilayer electronic component of the present invention may further include a ground terminal disposed on the first surface, and a plurality of through holes that connect the ground conductor layer to the ground within the multilayer body.

[0013] In the multilayer electronic component of the present invention, the capacitor connected to the at least one inductor does not have to be present between the first surface and the at least one inductor. [Effects of the Invention]

[0014] In the multilayer electronic component of the present invention, at least one LC resonator is located between the first surface and the ground conductor layer in the stacking direction of the multiple dielectric layers, but not between the second surface and the ground conductor layer. At least one inductor is located between the first surface and the multiple capacitors in the stacking direction. This makes it possible to realize a multilayer electronic component that can be made low-profile. [Brief explanation of the drawings]

[0015] [Figure 1] 1 is a circuit diagram showing a circuit configuration of a multilayer electronic component according to an embodiment of the present invention. [Figure 2] 1 is a perspective view showing the appearance of a multilayer electronic component according to an embodiment of the present invention; [Figure 3] FIG. 2 is an explanatory diagram showing the pattern-forming surfaces of the first to third dielectric layers in the laminate of the multilayer electronic component according to the embodiment of the present invention. [Figure 4] FIG. 2 is an explanatory diagram showing pattern-forming surfaces of fourth to sixth dielectric layers in a laminate of a multilayer electronic component according to one embodiment of the present invention. [Figure 5] FIG. 2 is an explanatory diagram showing pattern-forming surfaces of seventh to ninth dielectric layers in a laminate of a multilayer electronic component according to one embodiment of the present invention. [Figure 6] FIG. 2 is an explanatory diagram showing pattern-forming surfaces of the tenth to twelfth dielectric layers in the laminate of the multilayer electronic component according to the embodiment of the present invention. [Figure 7] 1 is a perspective view showing the inside of a laminate of a multilayer electronic component according to an embodiment of the present invention; [Figure 8]FIG. 10 is an explanatory diagram showing the pattern-formed surfaces of the first to third dielectric layers in the laminate of the multilayer electronic component of the comparative example. [Figure 9] FIG. 10 is an explanatory diagram showing the pattern-forming surfaces of the fourth to sixth dielectric layers in the laminate of the multilayer electronic component of the comparative example. [Figure 10] FIG. 10 is an explanatory diagram showing pattern-formed surfaces of the seventh to ninth dielectric layers in the laminate of the multilayer electronic component of the comparative example. [Figure 11] FIG. 10 is an explanatory diagram showing the pattern-forming surfaces of the 10th to 12th dielectric layers in the laminate of the multilayer electronic component of the comparative example. [Figure 12] FIG. 10 is a perspective view showing the inside of a laminate of a multilayer electronic component of a comparative example. [Figure 13] FIG. 10 is a characteristic diagram showing the pass loss characteristics and return loss characteristics of a model of a comparative example. [Figure 14] 10A and 10B are characteristic diagrams showing the transmission loss characteristics and the return loss characteristics of the model of the example. DETAILED DESCRIPTION OF THE INVENTION

[0016] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. First, with reference to FIG. 1, an outline of the configuration of a multilayer electronic component (hereinafter simply referred to as an electronic component) 1 according to an embodiment of the present invention will be described. FIG. 1 shows a bandpass filter as an example of the electronic component 1. The electronic component 1 includes at least one inductor and a plurality of capacitors. The at least one inductor and a plurality of capacitors are used to configure at least one LC resonator.

[0017] The at least one LC resonator may be a plurality of LC resonators. In this case, the at least one inductor is a plurality of inductors. Each of the plurality of LC resonators is configured by at least one inductor from the plurality of inductors and at least one capacitor from the plurality of capacitors.

[0018] In particular, in this embodiment, the electronic component 1 includes a first port 2, a second port 3, and two LC resonators 11 and 12 provided between the first port 2 and the second port 3 in a circuit configuration. The two LC resonators 11 and 12 are configured to be electromagnetically coupled. Each of the first port 2 and the second port 3 is a port for inputting or outputting a signal. Note that in this application, the expression "in a circuit configuration" is used to refer to an arrangement on a circuit diagram, not an arrangement in a physical configuration.

[0019] The electronic component 1 includes two inductors L11 and L12 as at least one inductor. The electronic component 1 also includes two capacitors C11 and C12 as multiple capacitors. The capacitors C11 and C12 are connected to the inductors L11 and L12, respectively. The LC resonator 11 is formed by the inductor L11 and the capacitor C11. The LC resonator 12 is formed by the inductor L12 and the capacitor C12.

[0020] The inductors L11 and L12 are magnetically coupled to each other. The electronic component 1 further includes a capacitor C10 that capacitively couples the inductors L11 and L12.

[0021] Another example of the circuit configuration of the electronic component 1 will be described below with reference to Fig. 1. The electronic component 1 further includes inductors L1, L2, L3, and L4, and capacitors C1, C2, and C3. One end of the inductor L1 is connected to the first port 2. One end of the capacitor C1 is connected to the other end of the inductor L1. One end of the capacitor C10 is connected to the other end of the capacitor C1.

[0022] One end of the capacitor C2 is connected to the other end of the capacitor C10. One end of the inductor L2 is connected to the other end of the capacitor C2. The other end of the inductor L2 is connected to the second port 3.

[0023] One end of the capacitor C3 is connected to the first port 2. The other end of the capacitor C3 is connected to the second port 3.

[0024] One end of each of inductor L11 and capacitor C11 is connected to the connection point between capacitor C1 and capacitor C10. One end of each of inductor L12 and capacitor C12 is connected to the connection point between capacitor C2 and capacitor C10. The other end of each of inductors L11 and L12 is connected to one end of inductor L3. The other end of each of capacitors C11 and C12 is connected to one end of inductor L4. The other end of each of inductors L3 and L4 is connected to ground.

[0025] The connection order of inductor L1 and capacitor C1 may be reversed from that shown in Fig. 1. That is, one end of capacitor C1 may be connected to first port 2, one end of inductor L1 may be connected to the other end of capacitor C1, and one end of capacitor C10 may be connected to the other end of inductor L1. In this case, the same characteristics as those of the configuration shown in Fig. 1 can be obtained.

[0026] Similarly, the connection order of inductor L2 and capacitor C2 may be reversed from that shown in Fig. 1. That is, one end of inductor L2 may be connected to the other end of capacitor C10, one end of capacitor C2 may be connected to the other end of inductor L2, and the other end of capacitor C2 may be connected to second port 3. In this case, the same characteristics as those of the configuration shown in Fig. 1 can be obtained.

[0027] Next, other configurations of the electronic component 1 will be described with reference to Fig. 2. Fig. 2 is a perspective view showing the appearance of the electronic component 1.

[0028] The electronic component 1 further includes a laminate 50 including a plurality of laminated dielectric layers and a plurality of laminated conductor layers. The first port 2, the second port 3, the LC resonators 11 and 12, the inductors L1 to L4, and the capacitors C1 to C3 and C10 are integrated into the laminate 50.

[0029] The laminate 50 has a bottom surface 50A and a top surface 50B located at both ends in the stacking direction T of the multiple dielectric layers, and four side surfaces 50C to 50F connecting the bottom surface 50A and the top surface 50B. The side surfaces 50C and 50D face in opposite directions from each other, and the side surfaces 50E and 50F also face in opposite directions from each other. The side surfaces 50C to 50F are perpendicular to the top surface 50B and the bottom surface 50A.

[0030] Here, the X direction, Y direction, and Z direction are defined as shown in FIG. 2. The X direction, Y direction, and Z direction are perpendicular to each other. In this embodiment, a direction parallel to the stacking direction T is defined as the Z direction. Furthermore, the direction opposite to the X direction is defined as the −X direction, the direction opposite to the Y direction is defined as the −Y direction, and the direction opposite to the Z direction is defined as the −Z direction.

[0031] As shown in FIG. 2, the bottom surface 50A is located at the end of the laminate 50 in the -Z direction. The top surface 50B is located at the end of the laminate 50 in the Z direction. The bottom surface 50A and the top surface 50B each have a rectangular shape that is long in the X direction. The side surface 50C is located at the end of the laminate 50 in the -X direction. The side surface 50D is located at the end of the laminate 50 in the X direction. The side surface 50E is located at the end of the laminate 50 in the -Y direction. The side surface 50F is located at the end of the laminate 50 in the Y direction.

[0032] The bottom surface 50A faces a substrate or other object to be mounted (not shown). The bottom surface 50A corresponds to the "first surface" in the present invention. The top surface 50B of the laminate 50 is located on the opposite side to the bottom surface 50A. The top surface 50B corresponds to the "second surface" in the present invention.

[0033] Electronic component 1 further includes terminals 111, 112, 113, 114, 115, and 116 provided on bottom surface 50A of laminate 50. Terminals 111, 112, and 113 are aligned in this order in the X direction at positions closer to side surface 50E than to side surface 50F. Terminals 114, 115, and 116 are aligned in this order in the -X direction at positions closer to side surface 50F than to side surface 50E.

[0034] Terminal 114 corresponds to second port 3, and terminal 116 corresponds to first port 2. Therefore, the first and second ports 2 and 3 are provided on the bottom surface 50A of the laminate 50. Each of terminals 111 to 113, and 115 is connected to ground. Each of terminals 111 to 113, and 115 corresponds to a "ground terminal" in the present invention.

[0035] The electronic component 1 further includes a ground conductor layer 611 that is integrated with the laminate 50 and connected to ground. The ground conductor layer 611 is disposed closer to the top surface 50B than to the bottom surface 50A. As will be described later, the LC resonators 11 and 12 are present between the bottom surface 50A and the ground conductor layer 611 in the stacking direction T, but are not present between the top surface 50B and the ground conductor layer 611.

[0036] Next, an example of the plurality of dielectric layers and the plurality of conductor layers constituting the laminate 50 will be described with reference to Figures 3(a) to 6(c). In this example, the laminate 50 has 12 laminated dielectric layers. Hereinafter, these 12 dielectric layers will be referred to as the first to 12th dielectric layers, in order from the bottom up. The first to 12th dielectric layers will be denoted by reference numerals 51 to 62.

[0037] In Figures 3(a) to 6(a), multiple circles represent multiple through holes. Multiple through holes are formed in each of the dielectric layers 51 to 60. The multiple through holes are formed by filling holes for the through holes with conductive paste. Each of the multiple through holes is connected to a terminal, a conductive layer, or another through hole.

[0038] Fig. 3(a) shows the pattern-formed surface of the first dielectric layer 51. Terminals 111 to 116 are formed on the pattern-formed surface of the dielectric layer 51. In Fig. 3(a), a specific through-hole connected to the terminal 114 is indicated by reference numeral 51T7, and a specific through-hole connected to the terminal 116 is indicated by reference numeral 51T6.

[0039] Fig. 3(b) shows the pattern-formed surface of the second dielectric layer 52. Conductor layers 521 and 522 are formed on the pattern-formed surface of the dielectric layer 52. In Fig. 3(b), two specific through-holes connected to two specific through-holes 51T6 and 51T7 formed in the dielectric layer 51 are indicated by the reference numerals 52T6 and 52T7, respectively.

[0040] 3(c) shows the pattern formation surface of the third dielectric layer 53. Conductor layers 531 and 532 are formed on the pattern formation surface of the dielectric layer 53. A specific through-hole 52T6 formed in the dielectric layer 52 is connected to the conductor layer 531. A specific through-hole 52T7 formed in the dielectric layer 52 is connected to the conductor layer 532.

[0041] In addition, in FIG. 3(c), two specific through holes connected to the conductor layer 531 are indicated by reference numeral 53T6, and two specific through holes connected to the conductor layer 532 are indicated by reference numeral 53T7.

[0042] 4(a) shows the pattern-formed surface of the fourth dielectric layer 54. In FIG. 4(a), two specific through holes connected to two specific through holes 53T6 formed in the dielectric layer 53 are indicated by reference numeral 54T6, and two specific through holes connected to two specific through holes 53T7 formed in the dielectric layer 53 are indicated by reference numeral 54T7.

[0043] 4(b) shows the pattern formation surface of the fifth dielectric layer 55. Inductor conductor layers 551 and 552 are formed on the pattern formation surface of the dielectric layer 55. Each of the conductor layers 551 and 552 has a first end and a second end located opposite to each other.

[0044] 4(b), a specific through hole connected to a first end of the conductor layer 551 is indicated by reference numeral 55T1, a specific through hole connected to a second end of the conductor layer 551 is indicated by reference numeral 55T2, a specific through hole connected to a first end of the conductor layer 552 is indicated by reference numeral 55T3, and a specific through hole connected to a second end of the conductor layer 552 is indicated by reference numeral 55T4. Also, two specific through holes connected to two specific through holes 54T6 formed in the dielectric layer 54 are indicated by reference numeral 55T6, and two specific through holes connected to two specific through holes 54T7 formed in the dielectric layer 54 are indicated by reference numeral 55T7.

[0045] 4(c) shows the pattern-formed surface of the sixth dielectric layer 56. In FIG. 4(c), four specific through holes connected to four specific through holes 55T1, 55T2, 55T3, and 55T4 formed in the dielectric layer 55 are indicated by reference numerals 56T1, 56T2, 56T3, and 56T4, respectively. In addition, two specific through holes connected to two specific through holes 55T6 formed in the dielectric layer 55 are indicated by reference numeral 56T6, and two specific through holes connected to two specific through holes 55T7 formed in the dielectric layer 55 are indicated by reference numeral 56T7.

[0046] 5(a) shows the pattern-formed surface of the seventh dielectric layer 57. A conductor layer 571 is formed on the pattern-formed surface of the dielectric layer 57. Specific through-holes 56T2 and 56T4 formed in the dielectric layer 56 are connected to the conductor layer 571.

[0047] 5(a), two specific through holes connected to two specific through holes 56T1 and 56T3 formed in the dielectric layer 56 are indicated by reference numerals 57T1 and 57T3, respectively. Also, a specific through hole connected to the conductor layer 571 is indicated by reference numeral 57T5. Also, two specific through holes connected to two specific through holes 56T6 formed in the dielectric layer 56 are indicated by reference numeral 57T6, and two specific through holes connected to two specific through holes 56T7 formed in the dielectric layer 56 are indicated by reference numeral 57T7.

[0048] 5(b) shows the pattern-formed surface of the eighth dielectric layer 58. Conductor layers 581 and 582 are formed on the pattern-formed surface of the dielectric layer 58. Two specific through-holes 57T6 formed in the dielectric layer 57 are connected to the conductor layer 581. Two specific through-holes 57T7 formed in the dielectric layer 57 are connected to the conductor layer 582.

[0049] 5(b), three specific through holes connected to the three specific through holes 57T1, 57T3, and 57T5 formed in the dielectric layer 57 are indicated by reference numerals 58T1, 58T3, and 58T5, respectively. Also, the specific through hole connected to the conductor layer 581 is indicated by reference numeral 58T6, and the specific through hole connected to the conductor layer 582 is indicated by reference numeral 58T7.

[0050] 5(c) shows the pattern-formed surface of the ninth dielectric layer 59. Capacitor conductor layers 591, 592, and 593 and conductor layers 594 and 595 are formed on the pattern-formed surface of the dielectric layer 59. Two specific through-holes 58T1 and 58T3 formed in the dielectric layer 58 are connected to the conductor layers 594 and 595, respectively. Two specific through-holes 58T6 and 58T7 formed in the dielectric layer 58 are connected to the conductor layers 591 and 592, respectively.

[0051] Also, in Figure 5(c), a specific through hole connected to conductor layer 594 is indicated by symbol 59T1, a specific through hole connected to conductor layer 595 is indicated by symbol 59T3, and a specific through hole connected to a specific through hole 58T5 formed in dielectric layer 58 is indicated by symbol 59T5.

[0052] 6(a) shows the pattern-formed surface of the tenth dielectric layer 60. Capacitor conductor layers 601 and 602 are formed on the pattern-formed surface of the dielectric layer 60. Two specific through-holes 59T1 and 59T3 formed in the dielectric layer 59 are connected to the conductor layers 601 and 602, respectively. Also in FIG. 6(a), the specific through-hole connected to the specific through-hole 59T5 formed in the dielectric layer 59 is indicated by the symbol 60T5.

[0053] 6(b) shows the pattern formation surface of the eleventh dielectric layer 61. A ground conductor layer 611 is formed on the pattern formation surface of the dielectric layer 61. A specific through-hole 60T5 formed in the dielectric layer 60 is connected to the ground conductor layer 611.

[0054] 6(c) shows the pattern-formed surface of the twelfth dielectric layer 62. On the pattern-formed surface of the dielectric layer 62, marks 621 made of a conductor layer are formed.

[0055] The laminate 50 shown in Figure 2 is constructed by stacking the first to twelfth dielectric layers 51 to 62 so that the pattern-forming surface of the first dielectric layer 51 becomes the bottom surface 50A of the laminate 50, and the surface opposite the pattern-forming surface of the twelfth dielectric layer 62 becomes the top surface 50B of the laminate 50.

[0056] Each of the plurality of through holes shown in Figures 3(a) to 6(a), excluding the plurality of specific through holes with reference numerals, is connected to a conductor layer that overlaps it in the stacking direction T or to another through hole that overlaps it in the stacking direction T when the first to twelfth dielectric layers 51 to 62 are stacked. Furthermore, of the plurality of through holes shown in Figures 3(a) to 6(a), excluding the plurality of specific through holes, a through hole that is located within a terminal or a conductor layer is connected to that terminal or that conductor layer.

[0057] Fig. 7 shows the inside of a laminate 50 formed by stacking first to twelfth dielectric layers 51 to 62. As shown in Fig. 7, the inside of the laminate 50 has a plurality of conductor layers and a plurality of through holes as shown in Figs. 3(a) to 6(c) stacked. Note that the mark 621 is omitted in Fig. 7.

[0058] The following describes the correspondence between the circuit components of the electronic component 1 shown in FIG. 1 and the internal components of the laminate 50 shown in FIGS. 3(a) to 6(c). The inductor L11 of the LC resonator 11 is composed of an inductor conductor layer 551 and specific through-holes 55T1, 55T2, 56T1, 56T2, 57T1, and 58T1. The capacitor C11 of the LC resonator 11 is composed of a capacitor conductor layer 601, a ground conductor layer 611, and a dielectric layer 60 between these conductor layers. The capacitor conductor layer 601 is connected to the specific through-hole 58T1 that constitutes the inductor L11 via a conductor layer 594 and a specific through-hole 59T1.

[0059] The inductor L12 of the LC resonator 12 is composed of the inductor conductor layer 552 and specific through holes 55T3, 55T4, 56T3, 56T4, 57T3, and 58T3. 12The capacitor C12 is composed of a capacitor conductor layer 602, a ground conductor layer 611, and a dielectric layer 60 between these conductor layers. The capacitor conductor layer 602 is connected to a specific through-hole 58T3 that constitutes the inductor L12 via a conductor layer 595 and a specific through-hole 59T3.

[0060] The capacitor C10 is composed of capacitor conductor layers 593, 601, and 602, and a dielectric layer 59 between these conductor layers.

[0061] The inductor L1 is formed by specific through holes 53T6, 54T6, 55T6, 56T6, and 57T6. The inductor L2 is formed by specific through holes 53T7, 54T7, 55T7, 56T7, and 57T7.

[0062] Capacitor C1 is composed of capacitor conductor layers 591 and 601 and a dielectric layer 59 between these conductor layers. Capacitor C2 is composed of capacitor conductor layers 592 and 602 and a dielectric layer 59 between these conductor layers. Capacitor C3 is composed of conductor layers 521, 531, and 532 and a dielectric layer 52 between these conductor layers.

[0063] 2 to 7, structural features of the electronic component 1 according to this embodiment will be described. The LC resonators 11 and 12 are located between the bottom surface 50A and the ground conductor layer 611 in the stacking direction T, but are not located between the top surface 50B and the ground conductor layer 611. That is, the inductors L11 and L12 and the capacitors C11 and C12 are located between the bottom surface 50A and the ground conductor layer 611 in the stacking direction T, but are not located between the top surface 50B and the ground conductor layer 611. When the laminate 50 is viewed from a position further away in the Z direction from the laminate 50, the ground conductor layer 611 covers the LC resonators 11 and 12.

[0064] The inductors L11 and L12 are disposed between the bottom surface 50A and the capacitors C11 and C12 in the stacking direction T. That is, the inductors L11 and L12 are disposed ahead of the capacitors C11 and C12 in the -Z direction. The -Z direction is also the direction from the ground conductor layer 611 toward the bottom surface 50A.

[0065] The capacitors C1, C2, and C10 are arranged in the stacking direction T between the inductors L11 and L12 and the capacitors C11 and C12.

[0066] Between the bottom surface 50A and the inductors L11 and L12, there is a capacitor C3 that is not connected to the inductors L11 and L12, but there is no capacitor that is connected to the inductors L11 and L12.

[0067] The capacitor conductor layer 601 faces the ground conductor layer 611. The dielectric layer 60 is interposed between the capacitor conductor layer 601 and the ground conductor layer 611. As described above, the capacitor C11 is composed of the capacitor conductor layer 601, the ground conductor layer 611, and the dielectric layer 60.

[0068] The capacitor conductor layer 602 faces the ground conductor layer 611. The dielectric layer 60 is interposed between the capacitor conductor layer 602 and the ground conductor layer 611. As described above, the capacitor C12 is composed of the capacitor conductor layer 602, the ground conductor layer 611, and the dielectric layer 60.

[0069] The ground conductor layer 611 is connected to the terminal 115 via some of the through holes excluding the specific through holes marked with reference numerals, and is also connected to the terminals 111 to 113 via other parts of the through holes excluding the specific through holes and the conductor layer 522. In this embodiment, no conductor layers for connecting the ground conductor layer 611 to the terminals 111 to 113, 115 are provided on the side surfaces 50C to 50F of the laminate 50.

[0070] Here, a structure formed by connecting two or more through holes in series is referred to as a through-hole row. The laminate 50 includes a through-hole row T1 formed by through holes 55T1, 56T1, 57T1, and 58T1, a through-hole row T2 formed by through holes 55T2 and 56T2, a through-hole row T3 formed by through holes 55T3, 56T3, 57T3, and 58T3, and a through-hole row T4 formed by through holes 55T4 and 56T4. The through-hole rows T1 and T3 correspond to the "first through-hole row" of the present invention, and the through-hole rows T2 and T4 correspond to the "second through-hole row" of the present invention.

[0071] The inductor conductive layer 551 connects the through-hole rows T1 and T2. The inductor conductive layer 551 is disposed between the bottom surface 50A and the through-hole rows T1 and T2 in the stacking direction T. The inductor L11 includes the through-hole rows T1 and T2 and the inductor conductive layer 551.

[0072] The inductor conductor layer 551 includes a portion 551A extending non-parallel to the short-side direction of each of the plurality of dielectric layers 51-62 (the same as the short-side direction of the bottom surface 50A and the top surface 50B) and the long-side direction of each of the plurality of dielectric layers 51-62 (the same as the long-side direction of the bottom surface 50A and the top surface 50B). The inductor conductor layer 551 further includes a portion 551B extending in the short-side direction of each of the plurality of dielectric layers 51-62 (the same as the short-side direction of the bottom surface 50A and the top surface 50B). In this embodiment, the portion 551A extends in a direction parallel to a direction tilted from the Y direction toward the −X direction. The portion 551B extends in a direction parallel to the Y direction.

[0073] The inductor conductive layer 552 connects the through-hole rows T3 and T4. The inductor conductive layer 552 is disposed between the bottom surface 50A and the through-hole rows T3 and T4 in the stacking direction T. The inductor L12 includes the through-hole rows T3 and T4 and the inductor conductive layer 552.

[0074] The inductor conductor layer 552 includes a portion 552A extending non-parallel to the short-side direction of each of the plurality of dielectric layers 51-62 (the same as the short-side direction of the bottom surface 50A and the top surface 50B) and the long-side direction of each of the plurality of dielectric layers 51-62 (the same as the long-side direction of the bottom surface 50A and the top surface 50B). The inductor conductor layer 552 further includes a portion 552B extending in the short-side direction of each of the plurality of dielectric layers 51-62 (the same as the short-side direction of the bottom surface 50A and the top surface 50B). In this embodiment in particular, the portion 552A extends in a direction parallel to a direction tilted from the Y direction toward the X direction. The portion 552B extends in a direction parallel to the Y direction.

[0075] Next, the operation and effect of the electronic component 1 according to this embodiment will be described. In this embodiment, the ground conductor layer 611 covers the LC resonators 11 and 12, i.e., the inductors L11 and L12 and the capacitors C11 and C12. If the inductor is disposed between the capacitor and the ground conductor layer in the stacking direction T, and the distance between the inductor and the ground conductor layer becomes small, stray capacitance may occur between the inductor and the ground conductor layer, making it difficult to obtain desired characteristics. To prevent this, it is necessary to intentionally increase the distance between the inductor and the ground conductor layer.

[0076] In contrast, in the present embodiment, the inductors L11 and L12 are disposed between the bottom surface 50A and the capacitors C11 and C12 in the stacking direction T. As a result, in this embodiment, the distance between the ground conductor layer 611 and the inductors L11 and L12 can be increased compared to the above case. As a result, in this embodiment, it is not necessary to intentionally increase the distance between the ground conductor layer 611 and the inductors L11 and L12. As a result, in this embodiment, the height of the electronic component 1 can be reduced.

[0077] Furthermore, in the present embodiment, no circuit components of the electronic component 1, including the LC resonators 11 and 12, exist between the top surface 50B and the ground conductor layer 611. Therefore, in the present embodiment, no through-holes exist in the dielectric layer 61 on which the ground conductor layer 611 is formed. As a result, according to the present embodiment, the area of ​​the ground conductor layer 611 can be made larger than when the ground conductor layer 611 is formed on another dielectric layer in which a through-hole exists.

[0078] Furthermore, in this embodiment, the capacitors C11 and C12 are configured by the capacitor conductor layers 601 and 602 facing the ground conductor layer 611. As described above, the area of ​​the ground conductor layer 611 can be increased, which in turn allows the area of ​​each of the capacitor conductor layers 601 and 602 to be increased. As a result, this embodiment allows a wider range of designable capacitances for the capacitors C11 and C12, thereby increasing the degree of freedom in designing the electronic component 1.

[0079] Furthermore, as in the electronic component of a comparative example described later, three or more capacitor conductor layers arranged at different positions in the stacking direction T may be provided to increase capacitance. In contrast, in this embodiment, the areas of the capacitor conductor layers 601 and 602 are increased, thereby widening the range over which the capacitance of the capacitors C11 and C12 can be increased compared to conventional cases. This also enables the electronic component 1 to be made thinner according to this embodiment.

[0080] Furthermore, in this embodiment, the inductor conductor layer 551 of the inductor L11 and the inductor conductor layer 552 of the inductor L12 are disposed at a position relatively far from the ground conductor layer 611, so that stray capacitance is unlikely to occur between them and the ground conductor layer 611. Therefore, according to this embodiment, the width and length of the inductor conductor layers 551 and 552 can be increased without causing or increasing stray capacitance. In this way, according to this embodiment, the degree of freedom in designing the inductors L11 and L12 is increased. Enhance For example, by lengthening the inductor conductive layer 551, the space surrounded by the inductor conductive layer 551, the through-hole rows T1, and the through-hole rows T2, i.e., the opening of inductor L11, can be enlarged. Similarly, by lengthening the inductor conductive layer 552, the space surrounded by the inductor conductive layer 552, the through-hole rows T3, and the through-hole rows T4, i.e., the opening of inductor L12, can be enlarged.

[0081] In particular, in this embodiment, each of the inductor conductive layers 551, 552 includes a portion extending in a direction inclined from the Y direction. As a result, according to this embodiment, the length of the inductor conductive layers 551, 552 can be increased compared to when each of the inductor conductive layers 551, 552 is composed only of a portion extending in a direction parallel to the Y direction (the short-side direction of the dielectric layer 55).

[0082] Next, the effects of this embodiment will be described with reference to the results of a simulation. In the simulation, a model of an example and a model of a comparative example were used. The model of the example is a model of the electronic component 1 according to this embodiment. The model of the comparative example is a model of the electronic component of the comparative example. The circuit configuration of the electronic component of the comparative example is the same as the circuit configuration of the electronic component 1 according to this embodiment shown in FIG. 1.

[0083] First, the configuration of an electronic component 101 of a comparative example will be described with reference to Figs. 8(a) to 12. The electronic component 101 includes a laminate 70 including first to twelfth dielectric layers 71 to 82 stacked one on the other. The circuit components of the electronic component 101 are integrated into the laminate 70. In Figs. 8(a) to 11(a), multiple circles represent multiple through holes. Multiple through holes are formed in each of the dielectric layers 71 to 80.

[0084] 8(a) shows the patterned surface of the first dielectric layer 71. Terminals 211, 212, 213, 214, 215, and 216 are formed on the patterned surface of the dielectric layer 71. Terminal 214 corresponds to the second port 3, and terminal 216 corresponds to the first port 2.

[0085] Figure 8(b) shows the pattern formation surface of the second dielectric layer 72. Capacitor conductor layers 721 and 722 are formed on the pattern formation surface of the dielectric layer 72. Figure 8(c) shows the pattern formation surface of the third dielectric layer 73. Capacitor conductor layers 731 and 732 are formed on the pattern formation surface of the dielectric layer 73.

[0086] FIG. 9(a) shows the pattern formation surface of the fourth dielectric layer 74. Capacitor conductor layers 741 and 742 are formed on the pattern formation surface of the dielectric layer 74. FIG. 9(b) shows the pattern formation surface of the fifth dielectric layer 75. Capacitor conductor layers 751, 752, and 753 and conductor layers 754, 755, 756, and 757 are formed on the pattern formation surface of the dielectric layer 75. FIG. 9(c) shows the pattern formation surface of the sixth dielectric layer 76. Capacitor conductor layer 761 is formed on the pattern formation surface of the dielectric layer 76.

[0087] Fig. 10(a) shows the pattern-forming surface of the seventh dielectric layer 77. A conductor layer 771 is formed on the pattern-forming surface of the dielectric layer 77. Fig. 10(b) shows the pattern-forming surface of the eighth dielectric layer 78. No conductor layer is formed on the pattern-forming surface of the dielectric layer 78.

[0088] 10(c) shows the pattern formation surface of the ninth dielectric layer 79. Inductor conductor layers 791 and 792 are formed on the pattern formation surface of the dielectric layer 79. The shapes of the inductor conductor layers 791 and 792 are approximately the same as the shapes of the inductor conductor layers 551 and 552 in this embodiment.

[0089] FIG. 11(a) shows the pattern-forming surface of the tenth dielectric layer 80. No conductor layer is formed on the pattern-forming surface of the dielectric layer 80. FIG. 11(b) shows the pattern-forming surface of the eleventh dielectric layer 81. A ground conductor layer 811 is formed on the pattern-forming surface of the dielectric layer 81. FIG. 11(c) shows the pattern-forming surface of the twelfth dielectric layer 82. A mark 821 made of a conductor layer is formed on the pattern-forming surface of the dielectric layer 82.

[0090] The laminate 70 of the comparative electronic component 101 is constructed by stacking the first to twelfth dielectric layers 71 to 82 so that the pattern-forming surface of the first dielectric layer 71 becomes the bottom surface of the laminate 70 and the surface opposite the pattern-forming surface of the twelfth dielectric layer 82 becomes the top surface of the laminate 70.

[0091] When the first to twelfth dielectric layers 71 to 82 are stacked, each of the plurality of through holes is connected to a conductor layer that overlaps it in the stacking direction T or to another through hole that overlaps it in the stacking direction T. Furthermore, of the plurality of through holes, a through hole located within a terminal or a conductor layer is connected to that terminal or that conductor layer.

[0092] Fig. 12 shows the inside of the laminate 70, which is formed by stacking the first to twelfth dielectric layers 71 to 82. As shown in Fig. 12, the multiple conductor layers and multiple through holes shown in Figs. 8(a) to 11(c) are stacked inside the laminate 70. Note that the mark 821 is omitted in Fig. 12.

[0093] The following describes the correspondence between the circuit components of electronic component 101 (the same as the circuit components of electronic component 1 shown in FIG. 1) and the internal components of laminate 70 shown in FIGS. 8(a) to 11(c). Inductor L11 of LC resonator 11 is composed of an inductor conductor layer 791, a plurality of through holes connecting inductor conductor layer 791 and conductor layer 756, and a plurality of through holes connecting inductor conductor layer 791 and conductor layer 771. Capacitor C11 of LC resonator 11 is composed of capacitor conductor layers 721, 731, and 741, and dielectric layers 72 and 73 between these conductor layers.

[0094] The inductor L12 of the LC resonator 12 is composed of an inductor conductor layer 792, a plurality of through holes connecting the inductor conductor layer 792 to the conductor layer 757, and a plurality of through holes connecting the inductor conductor layer 792 to the conductor layer 771. 12 The capacitor C12 is composed of capacitor conductor layers 722, 732, and 742, and dielectric layers 72 and 73 between these conductor layers.

[0095] The capacitor C10 is composed of capacitor conductor layers 741, 742, and 753, and a dielectric layer 74 between these conductor layers.

[0096] The inductor L1 is formed by a plurality of through holes that connect the terminal 216 and the conductor layer 751 for the capacitor. The inductor L2 is formed by a plurality of through holes that connect the terminal 214 and the conductor layer 752 for the capacitor.

[0097] Capacitor C1 is composed of capacitor conductor layers 741 and 751 and a dielectric layer 74 between these conductor layers. Capacitor C2 is composed of capacitor conductor layers 742 and 752 and a dielectric layer 74 between these conductor layers. Capacitor C3 is composed of capacitor conductor layers 751, 752, and 761 and a dielectric layer 75 between these conductor layers.

[0098] In the electronic component 101 of the comparative example, the inductors L11 and L12 are arranged between the capacitors C11 and C12 and the ground conductor layer 811 in the stacking direction T. The inductor conductor layers 791 and 792 face the ground conductor layer 811. No capacitors are present between the inductor conductor layers 791 and 792 and the ground conductor layer 811.

[0099] Next, the results of the simulation will be described. In the simulation, the model of the example and the model of the comparative example were designed so that the pass bands of electronic component 1 and electronic component 101 would be approximately the same, and the attenuation characteristics in the frequency range on the low side of the pass bands of electronic component 1 and electronic component 101 would be approximately the same.

[0100] Fig. 13 is a characteristic diagram showing the pass attenuation characteristics and return attenuation characteristics of the comparative example model. In Fig. 13, the horizontal axis represents frequency, and the vertical axis represents attenuation. In Fig. 13, the curve labeled 91 represents the pass attenuation characteristics of electronic component 101. In addition, the curve labeled 92 represents the return attenuation characteristics at first port 2 of electronic component 101.

[0101] Figure 14 shows Example 14 is a characteristic diagram showing the pass attenuation characteristics and return attenuation characteristics of the model. In Fig. 14, the horizontal axis represents frequency and the vertical axis represents attenuation. In Fig. 14, the curve labeled 93 represents the pass attenuation characteristics of the electronic component 1. In addition, the curve labeled 94 represents the return attenuation characteristics at the first port 2 of the electronic component 1.

[0102] In a bandpass filter, it is sometimes required to increase the band attenuation, which is expressed as the absolute value of the attenuation, in the frequency range higher than the passband. Figures 13 and 14 show that the model of the example has a larger band attenuation in a wide frequency range higher than the passband compared to the model of the comparative example. As can be seen from the simulation results, according to this embodiment, by arranging inductors L11 and L12 between the bottom surface 50A and capacitors C11 and C12, the band attenuation can be increased in a wide frequency range higher than the passband.

[0103] The present invention is not limited to the above-described embodiment and various modifications are possible. For example, the electronic component of the present invention may include only one LC resonator, or may include three or more LC resonators. [Explanation of symbols]

[0104] 1...electronic component, 2...first port, 3...second port, 11, 12...resonator, 50...laminated body, 50A...bottom surface, 50B...top surface, 50C to 50F...side surface, 611... For ground Conductor layer, C1 to C3, C10 to C12... capacitors, L1 to L4, L11, L12... inductors.

Claims

1. a ground conductor layer connected to the ground; at least one inductor; A plurality of capacitors; a laminate including a plurality of laminated dielectric layers, having a first surface facing an object to be mounted and a second surface opposite to the first surface, and for integrating the ground conductor layer, the at least one inductor, and the plurality of capacitors; the at least one inductor and the plurality of capacitors are used to configure at least one LC resonator; the at least one LC resonator is present between the first surface and the ground conductor layer in a stacking direction of the plurality of dielectric layers, but is not present between the second surface and the ground conductor layer; the at least one inductor is disposed between the first surface and the plurality of capacitors in the stacking direction; the at least one inductor includes a first row of through holes, a second row of through holes, and an inductor conductor layer connecting the first row of through holes and the second row of through holes; each of the first through-hole row and the second through-hole row is configured by connecting two or more through-holes in series; the inductor conductor layer is disposed between the first surface and the first and second rows of through holes in the stacking direction; a multilayer electronic component characterized in that, between the inductor conductor layer and the ground conductor layer, there is no other conductor layer constituting the at least one inductor and extending in a direction perpendicular to the stacking direction.

2. 2. The multilayer electronic component according to claim 1, wherein the ground conductor layer is disposed in a position closer to the second surface than to the first surface within the multilayer body.

3. The laminate further includes a plurality of capacitor conductor layers each integrated with the laminate and facing the ground conductor layer, the plurality of dielectric layers includes at least one dielectric layer interposed between the ground conductor layer and the plurality of capacitor conductor layers, 3. The multilayer electronic component according to claim 1, wherein the plurality of capacitors are formed by the ground conductor layer, the plurality of capacitor conductor layers, and the at least one dielectric layer.

4. the at least one LC resonator is a plurality of LC resonators; 4. The multilayer electronic component according to claim 1, wherein the at least one inductor is a plurality of inductors.

5. 5. The multilayer electronic component according to claim 4, wherein each of the plurality of LC resonators is configured by at least one inductor from the plurality of inductors and at least one capacitor from the plurality of capacitors.

6. 6. The multilayer electronic component according to claim 1, wherein the inductor conductor layer includes a portion that extends non-parallel to both the short-side direction and the long-side direction of each of the plurality of dielectric layers.

7. 7. The multilayer electronic component according to claim 6, wherein the inductor conductor layers include a portion extending in a first direction perpendicular to the stacking direction, and a portion extending in a second direction perpendicular to the stacking direction and intersecting the first direction.

8. Furthermore, a ground terminal disposed on the first surface; 8. The multilayer electronic component according to claim 1, further comprising a plurality of through holes in the multilayer body for connecting the ground conductor layer to the ground.

9. 9. The multilayer electronic component according to claim 1, wherein no capacitor connected to the at least one inductor is present between the first surface and the at least one inductor.

Images