Solar cell and solar cell manufacturing method

Abstract

Provided is a solar cell that can prevent leaks between electrodes. A solar cell according to one embodiment of the present invention is provided with: a semiconductor substrate 11; a plurality of band-shaped first semiconductor layers 13 and a plurality of second semiconductor layers 14 that are disposed alternately on a back surface side of the semiconductor substrate 11; band-shaped first electrodes 15 that are layered onto the first semiconductor layers 13 and band-shaped second electrodes 16 that are layered onto the second semiconductor layers; and band-shaped or linear insulating bodies 17 that are layered onto regions of back surfaces of the first semiconductor layers 13 so as to be separated from end edges on the second semiconductor layer 14 side and from the first electrodes 15.

Description

[Technical Field]

[0001] The present invention relates to a solar cell and a method for manufacturing a solar cell. [Background technology]

[0002] Back-contact solar cells are known in which strip-shaped p-type and n-type semiconductor layers are alternately formed on the back side of a semiconductor substrate with an intrinsic semiconductor layer interposed therebetween, and electrodes are laminated on each of the p-type and n-type semiconductor layers. In such back-contact solar cells, a known configuration is one in which a strip-shaped insulating material is disposed on the back side of one of the semiconductor layers to prevent leakage between the electrode on the p-type semiconductor layer and the electrode on the n-type semiconductor layer.

[0003] As an example, Patent Document 1 describes a process for forming an intrinsic first amorphous semiconductor film on one surface of the back surface of a semiconductor substrate of one conductivity type having a light-receiving surface and a back surface; forming a second amorphous semiconductor film containing impurities that exhibit a conductivity type on one surface of the first amorphous semiconductor film; forming a first etching mask layer having electrical insulation properties on the second amorphous semiconductor film so that the first and second amorphous semiconductor films remain in a comb shape, and then etching the first and second amorphous semiconductor films; forming an intrinsic third amorphous semiconductor film on the back surface of the semiconductor substrate exposed by etching and on the first etching mask layer; forming a fourth amorphous semiconductor film containing impurities that exhibit a conductivity type different from that of the first amorphous semiconductor film; forming a second etching mask layer in the short direction from an end of the first etching mask layer so that a comb-shaped overlap with the first etching mask layer, the third amorphous semiconductor film, and the fourth amorphous semiconductor film remains, and then etching the first etching mask layer and the third and fourth amorphous semiconductor films; forming a first electrode in an area on the second amorphous semiconductor layer where there is no first etching mask layer; and forming a second electrode on the fourth amorphous semiconductor layer in an area where there is no overlap.

[0004] In the manufacturing method described in Patent Document 1, a part of the first etching mask layer is used as an insulating layer that prevents leakage between electrodes, thereby omitting the step of forming the insulating layer and reducing the manufacturing cost of the solar cell. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Publication No. 2018-164057 Summary of the Invention [Problem to be solved by the invention]

[0006] However, after studying the solar cell manufacturing method described in Patent Document 1, it was found that damage occurs in the boundary region between the first semiconductor layer (first amorphous semiconductor film) and the second semiconductor layer (second amorphous semiconductor film) during the process, resulting in a deterioration of the solar cell characteristics. An object of the present invention is to provide a solar cell and a solar cell manufacturing method that can prevent leakage between electrodes while suppressing the deterioration of the solar cell characteristics in the boundary region between the first semiconductor layer and the second semiconductor layer. [Means for solving the problem]

[0007] A solar cell according to one embodiment of the present invention comprises a semiconductor substrate, a plurality of strip-shaped first semiconductor layers and a plurality of second semiconductor layers alternately arranged on the back surface side of the semiconductor substrate, a strip-shaped first electrode stacked on the first semiconductor layer and a strip-shaped second electrode stacked on the second semiconductor layer, and a strip-shaped or linear insulator stacked on the back surface of the first semiconductor layer at the edge on the second semiconductor layer side and in a region spaced from the first electrode.

[0008] In the solar cell according to the above aspect of the present invention, the second semiconductor layer may be laminated on a back surface side of the insulator.

[0009] The solar cell according to the above aspect of the present invention may further include an intrinsic semiconductor layer interposed between the insulator and the second semiconductor layer.

[0010] In the solar cell according to the above aspect of the present invention, the intrinsic semiconductor layer may be stacked so as to extend from between the semiconductor substrate and the first semiconductor layer and the second semiconductor layer, through the gap between the first semiconductor layer and the second semiconductor layer and the back surface side of the first semiconductor layer to the back surface side of the insulator, and the second semiconductor layer may be stacked so as to cover substantially the entire area of ​​the intrinsic semiconductor layer stacked on the back surface side of the first semiconductor layer.

[0011] In the solar cell according to the above aspect of the present invention, the second electrode may be laminated so as to cover at least a part of an area of ​​the second semiconductor layer that is laminated on the back surface side of the first semiconductor layer.

[0012] In the solar cell according to the above aspect of the present invention, the second semiconductor layer may be stacked continuously up to the back surface side of the first semiconductor layer, and the second electrode may have a planar shape substantially the same as that of the second semiconductor layer.

[0013] Another aspect of the present invention provides a solar cell manufacturing method comprising the steps of: stacking a first semiconductor layer on the back surface of a semiconductor substrate; stacking a lift-off layer on the back surface of the first semiconductor layer; removing the first semiconductor layer and the lift-off layer in stripes by etching to form a striped etching mask on the back surface of the lift-off layer; stacking a second semiconductor layer on the back surface of the stack of the semiconductor substrate, the first semiconductor layer, and the lift-off layer; removing a central portion of the lift-off layer and the second semiconductor layer stacked there under conditions such that the widthwise ends of the lift-off layer remain in stripes or lines; and stacking a first electrode on the back surface of the first semiconductor layer and a second electrode on the back surface of the second semiconductor layer. [Effects of the Invention]

[0014] According to the present invention, it is possible to provide a solar cell and a method for manufacturing a solar cell that can prevent leakage between electrodes. [Brief explanation of the drawings]

[0015] [Figure 1] 1 is a cross-sectional view showing the configuration of a solar cell according to a first embodiment of the present invention. [Figure 2] 2 is a flowchart showing the steps of a method for manufacturing the solar cell of FIG. [Figure 3] 3 is a cross-sectional view showing one step in the solar cell manufacturing method of FIG. 2. [Figure 4] 2. FIG. 4 is a cross-sectional view showing a step subsequent to FIG. 3 in the solar cell manufacturing method of FIG. [Figure 5]5 is a cross-sectional view showing a step subsequent to FIG. 4 in the solar cell manufacturing method of FIG. 2. [Figure 6] 6 is a cross-sectional view showing a step subsequent to FIG. 5 in the solar cell manufacturing method of FIG. [Figure 7] FIG. 3 is a cross-sectional view showing the configuration of a solar cell according to a second embodiment of the present invention. [Figure 8] FIG. 4 is a cross-sectional view showing the configuration of a solar cell according to a third embodiment of the present invention. [Figure 9] FIG. 10 is a cross-sectional view showing the configuration of a solar cell according to a fourth embodiment of the present invention. [Figure 10] FIG. 10 is a cross-sectional view showing the configuration of a solar cell according to a fifth embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0016] Hereinafter, each embodiment of the present invention will be described with reference to the drawings. For convenience, hatching and component reference numerals may be omitted. In such cases, other drawings should be referenced. Also, the dimensions of various components in the drawings have been adjusted for clarity. Furthermore, in the following description, components similar to those in the previously described embodiments are designated by the same reference numerals, and redundant description will be omitted.

[0017] First Embodiment 1 is a cross-sectional view showing the configuration of a solar cell 1 according to a first embodiment of the present invention. Solar cell 1 includes a semiconductor substrate 11, an intrinsic semiconductor layer 12 stacked on the back surface of semiconductor substrate 11, a plurality of first semiconductor layers 13 and a plurality of second semiconductor layers 14 alternately provided on the back surface side of the semiconductor substrate with intrinsic semiconductor layer 12 interposed therebetween, a strip-shaped first electrode 15 stacked on the back surface side of first semiconductor layer 13 and a strip-shaped second electrode 16 stacked on second semiconductor layer 14, and strip-shaped or linear insulators 17 stacked on the edge of the back surface of first semiconductor layer 13 on the second semiconductor layer side and in a region spaced from the first electrode.

[0018] The semiconductor substrate 11 can be made of a crystalline silicon material such as single crystal silicon or polycrystalline silicon. It may also be made of other semiconductor materials such as gallium arsenide (GaAs). The semiconductor substrate 11 is, for example, an n-type semiconductor substrate in which a crystalline silicon material is doped with an n-type dopant. An example of an n-type dopant is phosphorus (P). The semiconductor substrate 11 functions as a photoelectric conversion substrate that absorbs incident light from the light-receiving surface side and generates photocarriers (electrons and holes). Crystalline silicon is used as the material for the semiconductor substrate 11. This makes it possible to obtain a relatively high output (stable output regardless of illuminance) even when the dark current is relatively small and the intensity of incident light is low.

[0019] The intrinsic semiconductor layer 12 forms a depletion layer to suppress carrier recombination. The intrinsic semiconductor layer 12 can be made of so-called i-type amorphous silicon, which has a sufficiently low impurity content.

[0020] Intrinsic semiconductor layer 12 is laminated so as to extend from between semiconductor substrate 11 and first and second semiconductor layers 13 and 14, through between first and second semiconductor layers 13 and 14 and via the back surface side of first semiconductor layer 13, to the back surface side of insulator 17. That is, intrinsic semiconductor layer 12 branches between first and second semiconductor layer 13 and 14, extends to the back surface side of first semiconductor layer 13, and has extension portion 121 laminated on the back surface of insulator 17 and the back surface of a region of first semiconductor layer 13 that protrudes further toward second semiconductor layer 14 than insulator 17.

[0021] The extension portion 121 of the intrinsic semiconductor layer 12 provides insulation between the first semiconductor layer 13 and the second semiconductor layer 14 and improves the characteristics of the edge of the first semiconductor layer 13. More specifically, in the manufacturing process of the solar cell 1 described below, damage to the surface of the edge of the first semiconductor layer 13 caused by exposure to an etching solution due to side etching during etching to define the edge of the first semiconductor layer 13 can be repaired by forming the extension portion 121. Note that during etching, the surface of the first semiconductor layer 13 in the portion where the insulator 17 is stacked may also be damaged by side etching, and this damage may remain even after the extension portion 121 is formed. However, because the first semiconductor layer 13 has undamaged portions on both sides of the portion where the insulator 17 is stacked, carriers that should be collected in the damaged portion can be dispersed and collected in the undamaged portions on both sides. Therefore, by stacking the extension portion 121 on the back surface of the edge of the first semiconductor layer 13, performance degradation due to etching damage is suppressed for the entire first semiconductor layer 13.

[0022] The first semiconductor layer 13 and the second semiconductor layer 14 are each formed in a strip shape extending in the same direction. The second semiconductor layer 14 is laminated so as to cover the region of the intrinsic semiconductor layer 12 laminated on the back surface side of the first semiconductor layer 13, i.e., substantially the entire surface of the extension portion 121. Therefore, the second semiconductor layer 14 is also laminated on the back surface side of the insulator 17, and the intrinsic semiconductor layer 12 is interposed between the insulator 17 and the second semiconductor layer. Note that the ends of the multiple first semiconductor layers 13 and the multiple second semiconductor layers 14 may be connected to form a comb shape. Also, in FIG. 1, the thickness of each component is greatly exaggerated, so the laminated portion appears to be stepped, but in reality, the thickness of each component is very small and each component may be formed flat.

[0023] The first semiconductor layer 13 and the second semiconductor layer 14 have different conductivity types. The first semiconductor layer 13 and the second semiconductor layer 14 generate a large number of carriers different from each other, thereby forming an electric field that attracts the carriers generated in the semiconductor substrate 11.

[0024] Specifically, the first semiconductor layer 13 may be formed of a p-type semiconductor, and the second semiconductor layer 14 may be formed of an n-type semiconductor. The first semiconductor layer 13 and the second semiconductor layer 14 may be formed of, for example, an amorphous silicon material containing a dopant that imparts the desired conductivity type. An example of a p-type dopant is boron (B), and an example of an n-type dopant is the aforementioned phosphorus (P).

[0025] The first electrode 15 and the second electrode 16 are provided to extract charges from the first semiconductor layer 13 and the second semiconductor layer 14. The first electrode 15 and the second electrode 16 may also be formed into a comb shape, similar to the first semiconductor layer 13 and the second semiconductor layer 14. The first electrode 15 and the second electrode 16 can be formed from a conductive paste containing conductive particles and a binder. A typical example of a conductive paste is silver paste. By using a conductive paste, the first electrode 15 and the second electrode 16 can be formed relatively inexpensively with a sufficient thickness to reduce electrical resistance.

[0026] When a solar cell module is formed by sealing the solar cell 1 with a sealing material whose main component is, for example, ethylene vinyl acetate copolymer (EVA), the insulator 17 prevents leakage caused by charge migration along the interface between the sealing material and the first semiconductor layer 13 and the second semiconductor layer 14. Specifically, when moisture penetrates the sealing material, the moisture that penetrates tends to accumulate at the interface between the sealing material, which is made of different materials (an inorganic material and an organic material), and the first semiconductor layer 13 and the second semiconductor layer 14, and charge can migrate through this moisture layer. However, the sealing material and the insulator 17, which are made of the same material (both organic materials), have high adhesion and moisture is unlikely to accumulate at the interface, so they can act as a barrier that prevents charge migration.

[0027] The lower limit of the distance between the insulator 17 and the edge of the first semiconductor layer 13, i.e., the extension length of the first semiconductor layer 13 from the insulator 17, is preferably 10 μm, more preferably 20 μm, in order to recover from damage. On the other hand, the upper limit of the distance between the insulator 17 and the edge of the first semiconductor layer 13 is preferably 300 μm, more preferably 200 μm, in order to facilitate the arrangement of the insulator 17.

[0028] The lower limit of the width of the insulator 17 is preferably 5 μm, more preferably 8 μm, in order to obtain a good leak prevention effect, while the upper limit of the width of the insulator 17 is preferably 100 μm, more preferably 50 μm, in order to optimize the widths of the first semiconductor layer 13, the second semiconductor layer 14, the first electrode 15, and the second electrode 16.

[0029] The lower limit of the distance between the insulator 17 and the first electrode 15 is preferably 50 μm, more preferably 100 μm, in order to prevent a short circuit between the first electrode 15 and the second semiconductor layer 14. On the other hand, the upper limit of the distance between the insulator 17 and the first electrode 15 is preferably 300 μm, more preferably 200 μm, in order to ensure appropriate widths of the first semiconductor layer 13, the second semiconductor layer 14, the first electrode 15, and the second electrode 16.

[0030] <Solar cell manufacturing method> The solar cell 1 can be manufactured by the solar cell manufacturing method shown in Fig. 2. The solar cell manufacturing method shown in Fig. 2 is one embodiment of the solar cell manufacturing method according to the present invention.

[0031] The solar cell manufacturing method according to this embodiment includes a primary intrinsic semiconductor layer lamination process (step S1), a first semiconductor layer lamination process (step S2), a lift-off layer lamination process (step S3), an etching process (step S4), a secondary intrinsic semiconductor layer lamination process (step S5), a second semiconductor layer lamination process (step S6), a lift-off process (step S7), and an electrode lamination process (step S8).

[0032] In the primary intrinsic semiconductor layer lamination step of step S1, an intrinsic semiconductor layer 12 is laminated over the entire back surface of the semiconductor substrate 11. The intrinsic semiconductor layer 12 can be laminated by, for example, plasma CVD.

[0033] In the first semiconductor layer lamination step of step S2, a first semiconductor layer 13 is laminated on the back surface side of the semiconductor substrate 11 on which the intrinsic semiconductor layer 12 is laminated, i.e., on the entire back surface side of the intrinsic semiconductor layer 12. Like the intrinsic semiconductor layer 12, the first semiconductor layer 13 can be laminated by, for example, plasma CVD.

[0034] In the lift-off layer deposition step of step S3, as shown in FIG. 3, a lift-off layer L is deposited on the entire back surface of the first semiconductor layer 13. The lift-off layer L is partially left to form an insulator 17. The lift-off layer L can be formed from a material such as silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), or a material containing a combination of these materials. The lift-off layer L can be deposited by CVD, for example.

[0035] In the etching process of step S4, a striped etching mask M is formed on the back surface of the lift-off layer L, and the intrinsic semiconductor layer 12, the first semiconductor layer 13, and the lift-off layer L are removed in stripes by etching. More specifically, the etching process includes a step of forming an etching mask, a step of removing the intrinsic semiconductor layer 12, the first semiconductor layer 13, and the lift-off layer L with an etching solution, and a step of removing the etching mask with a mask remover.

[0036] The etching mask M is formed into a planar shape that matches the desired shape of the first semiconductor layer 13 using, for example, printing technology, photolithography technology, etc. As an etching solution, for example, a mixture of hydrofluoric acid (HF) and nitric acid (HNO3) can be used. As a mask remover, for example, an organic solvent such as acetone can be used.

[0037] By increasing the solubility of the lift-off layer L in the etching solution compared to the intrinsic semiconductor layer 12 and the first semiconductor layer 13, only the edges of the lift-off layer L are recessed from the edges of the etching mask M by side etching, as shown in FIG. 4 . This separates the insulator 17 from the edges of the first semiconductor layer 13. At this time, the first semiconductor layer 13 in the portion where the lift-off layer L has recessed and the first semiconductor layer 13 directly below the edge of the remaining lift-off layer L that has not been completely removed but has soaked in the etching solution are exposed to the etching solution, albeit for a relatively short time. As a result, the surface of the edge of the first semiconductor layer 13 is damaged by the etching solution.

[0038] 5, in the secondary intrinsic semiconductor layer lamination process of step S5, the intrinsic semiconductor layer 12 is laminated over the entire back surface of the laminate of the semiconductor substrate 11, the intrinsic semiconductor layer 12, the first semiconductor layer 13, and the lift-off layer L. The lamination of the intrinsic semiconductor layer 12 in the secondary intrinsic semiconductor layer lamination process can also be performed by, for example, plasma CVD, as in the primary intrinsic semiconductor layer lamination process.

[0039] In this secondary intrinsic semiconductor layer deposition step, a material similar to that of the first semiconductor layer deposition step is deposited using a process similar to that of the first semiconductor layer 13, except that it does not contain a trace amount of dopant. Therefore, by filling scratches formed on the surface of the first semiconductor layer 13 in the etching step with the same material, it is possible to repair damage caused by etching in the edge region of the first semiconductor layer 13 where there is no lift-off layer L. Damage may remain in the first semiconductor layer 13 directly below the edge of the lift-off layer L, but if the area of ​​the damaged region is the same, having damage inside the first semiconductor layer 13 will result in less degradation in performance than having damage at the edge of the first semiconductor layer 13.

[0040] In the second semiconductor layer lamination step of step S6, a second semiconductor layer 14 is laminated over the entire back surface of the laminate of the semiconductor substrate 11, the intrinsic semiconductor layer 12, the first semiconductor layer 13, and the lift-off layer L, i.e., over the back surface of the intrinsic semiconductor layer 12 laminated in the second intrinsic semiconductor layer lamination step. The second semiconductor layer 14 can be laminated by, for example, plasma CVD.

[0041] In the lift-off process of step S7, as shown in FIG. 6, the central portion of the lift-off layer M and the intrinsic semiconductor layer 12 and second semiconductor layer 14 stacked thereon are removed under conditions that leave the widthwise edges of the lift-off layer L in a strip-like or linear shape. For example, the lift-off layer M can be removed sequentially from the widthwise center by forming, for example, scratches or openings in the intrinsic semiconductor layer 12 and second semiconductor layer 14 stacked in the widthwise center of the lift-off layer L, forming areas that are easily penetrated by a dissolving solution that dissolves the lift-off layer. By adjusting the immersion time in the dissolving solution, an insulator 17 can be formed while leaving the widthwise edges of the lift-off layer L. An acidic solution such as hydrofluoric acid can be used as the dissolving solution that dissolves the lift-off layer L.

[0042] In the electrode lamination process of step S8, a first electrode 15 is laminated on the back surface of the first semiconductor layer 13, and a second electrode 16 is laminated on the back surface of the second semiconductor layer 14. The first electrode 15 and the second electrode 16 can be formed by printing and firing a conductive paste. Screen printing, for example, can be used as a method for printing the conductive paste.

[0043] As described above, in the solar cell manufacturing method of this embodiment, by leaving the end of the lift-off layer M to form an insulator 17, a solar cell 1 that can prevent leakage between the first electrode 15 and the second electrode 16 can be manufactured relatively inexpensively.

[0044] Second Embodiment 7 is a cross-sectional view showing the configuration of a solar cell 1A according to a second embodiment of the present invention. Solar cell 1A includes a semiconductor substrate 11, an intrinsic semiconductor layer 12A stacked on the back surface of semiconductor substrate 11, a plurality of first semiconductor layers 13 and a plurality of second semiconductor layers 14A alternately provided on the back surface side of the semiconductor substrate with intrinsic semiconductor layer 12A interposed therebetween, a strip-shaped first electrode 15 stacked on the back surface side of first semiconductor layer 13 and a strip-shaped second electrode 16 stacked on second semiconductor layer 14A, and strip-shaped or linear insulators 17 stacked on the edge of the back surface of first semiconductor layer 13 on the second semiconductor layer 14A side and in a region spaced from first electrode 15.

[0045] 7, intrinsic semiconductor layer 12A and second semiconductor layer 14A do not extend to the back surface side of first semiconductor layer 13. In other words, intrinsic semiconductor layer 12A is a single layer laminated on the back surface of semiconductor substrate 11, and second semiconductor layer 14A is laminated only in the non-laminated region of first semiconductor layer 13. Therefore, the back surface side of insulator 17 is not covered by other components.

[0046] Solar cell 1A in FIG. 7 can be manufactured by forming and patterning first semiconductor layer 13, second semiconductor layer 14A, and insulator 17 using dedicated resist patterns, respectively.

[0047] In solar cell 1A of FIG. 7, second semiconductor layer 14A is particularly separated from insulator 17, and therefore, the occurrence of leakage current between first electrode 15 and second semiconductor layer 14A can be suppressed.

[0048] Third Embodiment 8 is a cross-sectional view showing the configuration of a solar cell 1B according to a third embodiment of the present invention. Solar cell 1B includes a semiconductor substrate 11, an intrinsic semiconductor layer 12A stacked on the back surface of semiconductor substrate 11, a plurality of first semiconductor layers 13 and a plurality of second semiconductor layers 14A alternately provided on the back surface of the semiconductor substrate with intrinsic semiconductor layer 12A interposed therebetween, a strip-shaped first electrode 15 stacked on the back surface of first semiconductor layer 13 and a strip-shaped second electrode 16 stacked on second semiconductor layer 14A, strip-shaped or linear insulator 17 stacked on an edge of the back surface of first semiconductor layer 13 on the second semiconductor layer 14A side and in a region spaced from first electrode 15, an intrinsic semiconductor cap portion 18 stacked on the back surface of insulator 17, and a second semiconductor cap portion 19 stacked on the back surface of intrinsic semiconductor cap portion 18.

[0049] For example, the solar cell 1B of Figure 8 can be manufactured by forming the first semiconductor layer 13 and the second semiconductor layer 14A, then forming a lift-off layer that opens the area where the insulator 17 will be formed, sequentially stacking the material that forms the insulator 17, the material that forms the intrinsic semiconductor cap portion 18, and the material that forms the second semiconductor cap portion 19, and dissolving the lift-off layer to remove it together with the material stacked on its back side.

[0050] <Fourth embodiment> 9 is a cross-sectional view showing the configuration of a solar cell 1C according to a fourth embodiment of the present invention. Solar cell 1C includes a semiconductor substrate 11, an intrinsic semiconductor layer 12 stacked on the back surface of semiconductor substrate 11, a plurality of first semiconductor layers 13 and a plurality of second semiconductor layers 14 alternately provided on the back surface side of the semiconductor substrate with intrinsic semiconductor layer 12 interposed therebetween, a strip-shaped first electrode 15 stacked on the back surface side of first semiconductor layer 13 and a strip-shaped second electrode 16C stacked on second semiconductor layer 14, and strip-shaped or linear insulators 17 stacked on the edge of the back surface of first semiconductor layer 13 on the second semiconductor layer 14 side and in a region spaced from first electrode 15.

[0051] 9, second electrode 16C is laminated so as to cover at least a portion of the region of second semiconductor layer 14 that is laminated on the back surface side of first semiconductor layer 13. In this way, by increasing the width of second electrode 16C, it is possible to improve the efficiency of current collection from second semiconductor layer 14.

[0052] Fifth Embodiment 10 is a cross-sectional view showing the configuration of a solar cell 1D according to a fifth embodiment of the present invention. Solar cell 1D includes a semiconductor substrate 11, an intrinsic semiconductor layer 12D stacked on the back surface of semiconductor substrate 11, a plurality of first semiconductor layers 13 and a plurality of second semiconductor layers 14D alternately provided on the back surface side of the semiconductor substrate with intrinsic semiconductor layer 12D interposed therebetween, strip-shaped first electrodes 15 stacked on the back surface side of first semiconductor layers 13 and strip-shaped second electrodes 16C stacked on second semiconductor layers 14D, and strip-shaped or linear insulators 17 stacked on the edge of the back surface of first semiconductor layer 13 on the second semiconductor layer 14D side and in a region spaced from first electrode 15.

[0053] 10, intrinsic semiconductor layer 12D has extending portion 121D that branches between first semiconductor layer 13 and second semiconductor layer 14D, extends toward the back surface side of first semiconductor layer 13, and terminates at a position away from insulator 17. Second semiconductor layer 14D terminates at the same position as extending portion 121D of intrinsic semiconductor layer 12D. In other words, second semiconductor layer 14D is continuously stacked up to the back surface side of first semiconductor layer 13 via intrinsic semiconductor layer 12D.

[0054] Solar cell 1D in Fig. 10 can be manufactured by etching solar cell 1C in Fig. 9 using second electrode 16C as a mask to remove the portions of intrinsic semiconductor layer 12 and second semiconductor layer 14 that are exposed from second electrode 16C. Therefore, in solar cell 1D of this embodiment, second electrode 16C has substantially the same planar shape as intrinsic semiconductor layer 12D and second semiconductor layer 14D.

[0055] In this way, by removing the portions of the intrinsic semiconductor layer 12 and the second semiconductor layer 14 exposed from the second electrode 16C, leakage current between the first electrode 15 and the second semiconductor layer 14D can be more reliably suppressed.

[0056] Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments and various modifications and variations are possible. For example, the solar cell according to the present invention may not include an intrinsic semiconductor layer, and may include additional components such as a passivation layer, an anti-reflection film, and a protective film in addition to the components described above. [Explanation of symbols]

[0057] 1,1A,1B,1C,1D solar cell 11 Semiconductor substrate 12, 12A, 12D Intrinsic semiconductor layer 13 First semiconductor layer 14, 14A, 14D Second semiconductor layer 15 1st electrode 16,16C 2nd electrode 17 Insulators 18 Intrinsic semiconductor cap 19 Second semiconductor cap part 121,121D Extension L lift-off layer M Etching Mask

Claims

1. a semiconductor substrate; a plurality of strip-shaped first semiconductor layers and a plurality of strip-shaped second semiconductor layers alternately provided on the back surface side of the semiconductor substrate; a strip-shaped first electrode laminated on the first semiconductor layer and a strip-shaped second electrode laminated on the second semiconductor layer; a strip-shaped or linear insulator laminated on an edge of the back surface of the first semiconductor layer on the side of the second semiconductor layer and in a region spaced from the first electrode; Equipped with The width of the insulator is 5 μm or more and 100 μm or less, the distance between the insulator and the first electrode is 50 μm or more and 300 μm or less; the second semiconductor layer is stacked on the back surface side of the insulator, an intrinsic semiconductor layer interposed between the insulator and the second semiconductor layer; the intrinsic semiconductor layer is laminated so as to extend from between the semiconductor substrate and the first semiconductor layer and the second semiconductor layer, through between the first semiconductor layer and the second semiconductor layer and via the back surface side of the first semiconductor layer to the back surface side of the insulator, The second semiconductor layer is laminated so as to cover substantially the entire area of ​​the intrinsic semiconductor layer that is laminated on the back surface side of the first semiconductor layer.

2. The solar cell according to claim 1 , wherein the second electrode is laminated so as to cover at least a part of an area of ​​the second semiconductor layer laminated on the back surface side of the first semiconductor layer.

3. the second semiconductor layer is laminated continuously up to the back surface side of the first semiconductor layer, The solar cell according to claim 1 , wherein the second electrode has a planar shape substantially equal to that of the second semiconductor layer.

4. a step of depositing a first semiconductor layer on a back surface side of the semiconductor substrate; depositing a lift-off layer on the back surface side of the first semiconductor layer; removing the first semiconductor layer and the lift-off layer in stripes by etching to form a striped etching mask on the back surface of the lift-off layer; a step of stacking an intrinsic semiconductor layer and a second semiconductor layer in this order on a back surface of a stack of a semiconductor substrate, the first semiconductor layer, and the lift-off layer; forming scratches or openings in widthwise central portions of the intrinsic semiconductor layer and the second semiconductor layer, and sequentially removing the lift-off layer from the widthwise central portion under conditions such that widthwise ends of the lift-off layer are left in a strip-like or linear shape, thereby expanding the scratches or openings in the intrinsic semiconductor layer and the second semiconductor layer in the widthwise direction; a step of stacking a first electrode on a rear surface of the first semiconductor layer and a second electrode on a rear surface of the second semiconductor layer; A solar cell manufacturing method comprising:

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