Memory System

Abstract

To provide a memory system capable of addressing a fine access granularity while keeping the amount of increase in size of an address conversion table to minimum.SOLUTION: A controller of a memory system manages 2N banks which are obtained by dividing a logical address space, and 2N regions which are contained in a physical storage area of a non-volatile memory and correspond to the 2N banks one-to-one. The controller stores an address conversion table in a random access memory, the address conversion table containing a plurality of entries respectively corresponding to a plurality of logical addresses which are continuous in units of a first size corresponding to granularity of data to be read / write-accessed by a host, and the address conversion table managing mapping between each of the plurality of logical addresses and each of a plurality of physical addresses. The controller assigns 2N write buffers corresponding to the 2N banks one-to-one to the random access memory.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] FIELD OF THE INVENTION Embodiments of the present invention relate to techniques for controlling non-volatile memory. [Background technology]

[0002] In recent years, memory systems equipped with nonvolatile memories have become widespread. In these memory systems, an address translation table is used to manage mapping between each logical address and each physical address of the nonvolatile memory in units of a predetermined management size.

[0003] When controlling flash memory in solid-state drives (SSDs), a management size of 4K bytes (4KB) is often used. When applying a 4KB management size flash memory to a memory system with 64-byte (64B) accessibility, rewriting only 64B of data, which is a portion of the 4KB data already written, requires a read-modify-write operation that includes reading the already written 4KB data from nonvolatile memory, modifying the read 4KB data with the 64B data, and writing the modified 4KB data to nonvolatile memory. This read-modify-write operation increases the write amplification of the memory system.

[0004] Furthermore, simply applying a technique of reducing the address translation unit of the address translation table to accommodate finer access granularity would result in an increase in the size of the address translation table.

[0005] For this reason, there is a need to realize a new technology that can accommodate finer access granularity while minimizing the increase in the size of the address translation table. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] U.S. Patent Application Publication No. 2020 / 0250090 [Patent Document 2] U.S. Patent Application Publication No. 2021 / 0109666 [Patent Document 3] US Patent Application Publication No. 2020 / 0334169 Summary of the Invention [Problem to be solved by the invention]

[0007] A problem to be solved by one embodiment of the present invention is to provide a memory system that can accommodate fine access granularity while minimizing the increase in size of the address translation table. [Means for solving the problem]

[0008] According to an embodiment, a memory system connectable to a host via a memory bus includes a random access memory, a non-volatile memory, and a controller, the controller being configured to access two memory locations obtained by dividing a logical address space used by the host to access the memory system. N 2 small logical address spaces N banks and 2 N Two physical memory areas of the nonvolatile memory, each corresponding to one of the banks, are included. N The controller stores in the random access memory an address translation table that includes a plurality of entries corresponding to a plurality of consecutive logical addresses in units of a first size corresponding to the granularity of data accessed for read / write by the host, and that manages mapping between each of the plurality of logical addresses and each of a plurality of physical addresses in the physical storage area. The controller manages the two N two banks each having at least a first capacity corresponding to a write size of the nonvolatile memory; NIn response to receiving a write access request and first write data from the host, the controller identifies a bank to which a logical address of the first write data specified by the write access request belongs, and allocates the two write buffers to the random access memory. N The controller writes the first write data to the write buffer corresponding to the specified bank among the write buffers. After the total size of the write data including the first write data stored in the write buffers reaches or exceeds a predetermined size, the controller writes the write data including the first write data to the second write buffer. N The logical address is written to an area corresponding to the specified bank among the areas. Each of the plurality of entries holds, as a physical address, location information indicating one of a plurality of storage locations included in one area corresponding to one bank to which the corresponding logical address belongs, but does not hold location information for identifying the one area. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a block diagram showing an example of the configuration of an information processing system including a memory system according to an embodiment. [Figure 2] FIG. 2 is a block diagram showing the relationship between a media control unit and multiple flash dies provided in the memory system according to the embodiment. [Figure 3] FIG. 2 is a block diagram showing an example of the configuration of a flash die in a NAND flash memory included in the memory system according to the embodiment. [Figure 4] 1 is a diagram showing the correspondence between each logical address and each physical address managed by an address translation table used in a memory system according to an embodiment. [Figure 5] 1 is a diagram showing components provided in a memory system according to an embodiment, and a write-back operation, a refill operation, and a garbage collection operation executed in the memory system. [Figure 6]FIG. 2 is a diagram showing the relationship between components provided in the memory system according to the embodiment and a plurality of banks. [Figure 7] FIG. 2 is a diagram showing the relationship between components provided in a memory system according to an embodiment and a plurality of banks and a plurality of sub-regions. [Figure 8] FIG. 2 is a diagram showing a group of logical addresses belonging to each bank used in the memory system according to the embodiment. [Figure 9] FIG. 2 is a diagram showing an example of the configuration of a cache included in the memory system according to the embodiment. [Figure 10] FIG. 2 is a diagram showing a state in which data is stored in a cache included in the memory system according to the embodiment. [Figure 11] FIG. 10 is a diagram showing a state in which additional data is stored in a cache included in the memory system according to the embodiment. [Figure 12] FIG. 10 is a diagram showing a write-back operation executed in the memory system according to the embodiment. [Figure 13] 10A and 10B are diagrams showing a refill operation executed in the memory system according to the embodiment; [Figure 14] 10A and 10B are diagrams showing first position information of 16 bits wide applied to 64-byte data and second position information of 32 bits wide applied to 128-byte data used in a memory system according to an embodiment; [Figure 15] 10 is a flowchart showing the procedure of a preparation process executed in the memory system according to the embodiment. [Figure 16] 10 is a flowchart showing the procedure of a process executed in the memory system according to the embodiment to write data to a region via a write buffer. [Figure 17] 10 is a flowchart showing the procedure of a write process executed in the memory system according to the embodiment. [Figure 18] 10 is a flowchart showing the procedure of an eviction process executed in the memory system according to the embodiment. [Figure 19] 10 is a flowchart showing the procedure of a read process executed in the memory system according to the embodiment. [Figure 20] 10 is a flowchart showing the procedure of a refill operation executed in the memory system according to the embodiment. [Figure 21] 1 is a diagram showing various management sizes used in a memory system according to an embodiment; DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, an embodiment will be described with reference to the drawings. 1 is a block diagram showing an example of the configuration of an information processing system 1 including a memory system according to an embodiment. The information processing system 1 includes a host (host device) 2 and a memory system 3. The host 2 and the memory system 3 can be connected via a memory bus 4. The memory bus 4 may be, for example, a Compute Express Link TM (CXL TM ) standard compliant CXL TM Bus, bus conforming to the OpenCAPI (Open Coherent Accelerator Processor Interface) standard, or PCI Express TM (PCIe TM ) standard compliant PCIe TM It's a bus.

[0011] The host 2 is an information processing device. The host 2 is, for example, a server computer or a personal computer. The host 2 accesses the memory system 3 via the memory bus 4. Specifically, the host 2 transmits a store command, which is a write access request for writing data, to the memory system 3 via the memory bus 4. The host 2 also transmits a load command, which is a read access request for reading data, to the memory system 3 via the memory bus 4.

[0012] The memory system 3 is a memory device equipped with a nonvolatile memory. The memory system 3 can be connected to the host 2 via a memory bus 4.

[0013] Next, we will explain the internal configuration of the host 2. The host 2 includes a processor 21 and a memory 22.

[0014] The processor 21 is a central processing unit (CPU). The processor 21 executes software (host software) loaded into the memory 22. The host software is loaded into the memory 22 from the memory system 3 or a storage device (not shown) connected to the host 2. The host software includes an operating system, a file system, a device driver, an application program, etc. The processor 21 has a virtual memory function. A memory management unit of the processor 21 converts virtual memory addresses used by application programs into physical memory addresses. The processor 21 accesses the memory 22 using the physical memory addresses. The processor 21 also accesses the memory system 3 via the memory bus 4 using the physical memory addresses. Read / write access to the memory system 3 via the memory bus 4 is performed at a predetermined data granularity. The data granularity is, for example, 64 bytes (64B), 128 bytes (128B), or 256 bytes (256B). The data granularity has a size corresponding to the bus width of the memory bus 4. 1 shows an example in which the processor 21 executes read / write access to the memory system 3 at a granularity of 64 B. Hereinafter, the granularity of data accessed for read / write by the host 2 via the memory bus 4 will be referred to as "access granularity."

[0015] Next, we will explain the internal configuration of the memory system 3. The memory system 3 includes a controller 5, a NAND flash memory 6, and a dynamic random access memory (DRAM) 7.

[0016] The controller 5 is a memory controller. The controller 5 is a control circuit such as a System-on-a-Chip (SoC). The controller 5 controls writing and reading of data to and from the NAND flash memory 6. The controller 5 also controls writing and reading of data to and from the DRAM 7. The controller 5 also communicates with the processor 21 of the host 2 via the memory bus 4. The controller 5 is configured to be able to handle fine access granularity such as 64B.

[0017] The NAND flash memory 6 is a nonvolatile memory. The NAND flash memory 6 is, for example, a flash memory with a three-dimensional structure. The memory cell array of the NAND flash memory 6 is divided into multiple planes. The NAND flash memory 6 includes multiple blocks in each plane. Each of the multiple blocks is a unit of data erase operation. Each of the multiple blocks includes multiple physical pages. Each of the multiple physical pages includes multiple memory cells connected to the same word line. Each of the multiple physical pages is a unit of data program operation and data read operation. In an intra-page read operation, the NAND flash memory 6 can output only a portion of the data of one physical page size read from one physical page to the controller 5.

[0018] The DRAM 7 is a random access memory. The DRAM 7 is a volatile memory that can be accessed faster than the NAND flash memory 6.

[0019] Next, we will explain the functions executed by the controller 5. The controller 5 manages the data stored in the NAND flash memory 6 and the blocks included in the NAND flash memory 6.

[0020] The data management includes management of mapping information indicating the correspondence between each logical address and each physical address of the NAND flash memory 6. The controller 5 uses an address conversion table to manage the mapping between each logical address and each physical address in a predetermined management size unit. The address conversion table is also called a logical-to-physical address conversion table (L2P table) or a page table. A logical address is an address used by the host 2 (processor 21) to access the memory system 3. A physical address is an address indicating a storage location (physical storage location) included in a physical storage area included in the NAND flash memory 6. In this embodiment, the physical memory address output from the processor 21 to the memory bus 7 is used as the logical address for accessing the memory system 3. In other words, the address conversion table converts the physical memory address output from the processor 21 into a physical address of the NAND flash memory 6.

[0021] In the NAND flash memory 6, data can be written to a physical page of a block only once per program / erase cycle of the block. In other words, new data cannot be directly overwritten to a physical storage area in a block to which data has already been written. Therefore, when updating data already written to a physical storage area, the controller 5 writes the new data to an unwritten area in that block (or another block) and treats the previous data as invalid data. In other words, the controller 5 writes updated data corresponding to a logical address to a different storage location rather than to the storage location where the previous data corresponding to that logical address is stored. The controller 5 then updates the address translation table to associate this logical address with a physical address indicating this different storage location.

[0022] Management of the blocks contained in the NAND flash memory 6 includes management of defective blocks (bad blocks), wear leveling, and garbage collection (GC).

[0023] GC is an operation for increasing the number of free blocks. A free block is a block that does not contain valid data. In a GC operation, the controller 5 selects several blocks containing a mixture of valid and invalid data as GC source blocks. The GC source blocks are also referred to as copy source blocks or move source blocks. The controller 5 copies the valid data contained in the GC source blocks to GC destination blocks (e.g., free blocks). The GC destination blocks are also referred to as copy destination blocks or move destination blocks. Here, valid data refers to data associated with a logical address. Data associated with a logical address as the latest data is valid data and may be read by the host 2 later. Invalid data refers to data that is not associated with any logical address. Data that is not associated with any logical address is data that may no longer be read by the host 2. After copying valid data from a GC source block to a GC destination block, the controller 5 updates the address translation table to map the physical address of the copy destination to each logical address of the copied valid data. A block that contains only invalid data as a result of valid data being copied to another block is released as a free block, which makes it possible to reuse the block for writing data after a data erase operation is performed on the block.

[0024] Next, a description will be given of the internal configuration of the controller 5. The controller 5 includes a cache 51 and a media control unit 52.

[0025] The cache 51 is hardware that stores frequently accessed data. The data storage area of ​​the cache 51 is realized using the DRAM 7. Cache control logic that controls the cache 51 is implemented in the controller 5.

[0026] The media control unit 52 is a circuit that controls the NAND flash memory 6 .

[0027] Next, a description will be given of an example of the configuration of the NAND flash memory 6. Fig. 2 is a block diagram showing the relationship between a media control unit 52 and multiple flash dies provided in the memory system 3 according to the embodiment.

[0028] The NAND flash memory 6 includes, for example, 32 NAND flash memory dies (flash dies #0 to #31). The flash dies #0 to #31 can operate independently of one another. The flash dies #0 to #31 are connected to 32 channels ch.0 to ch.31, respectively. The media control unit 52 can access the flash dies #0 to #31 in parallel via the channels ch.0 to ch.31. Therefore, the media control unit 52 can write data to a maximum of 32 flash dies simultaneously (number of parallel writes = 32). Note that a configuration in which two or more flash dies are connected to each of the channels ch.0 to ch.31 may also be used.

[0029] Next, a configuration example of a flash die will be described. Fig. 3 is a block diagram showing a configuration example of a flash die in a NAND flash memory 6 included in a memory system 3 according to the embodiment.

[0030] Flash die #0 has a multi-plane configuration including multiple planes. For example, the memory cell array of flash die #0 is divided into 16 planes (planes #0 to #15). Each of planes #0 to #15 includes multiple blocks BLK#0 to BLK#x-1. Each of blocks BLK#0 to BLK#x-1 includes multiple physical pages (P#0 to P#y-1). The size (physical page size) of each of physical pages P#0 to P#y-1 is, for example, 4 KB. Flash die #0 can operate in a multi-plane mode in which data is simultaneously written to eight planes. Therefore, data can be written to flash die #0 in units of 32 KB (= 4 KB × 8 planes). Each of the other flash dies #1 to #31 has the same configuration as flash die #0.

[0031] Next, the address conversion table will be described. Fig. 4 is a diagram showing the correspondence between each logical address and each physical address managed by the address conversion table used in the memory system 3 according to the embodiment.

[0032] The page table 71 is an address translation table (L2P table) for managing mapping between each logical address included in the logical address space and each physical address included in the physical address space. The logical address space is a memory address space used by the host 2 to access the memory system 3. The physical address space is an address space indicating multiple storage locations (physical storage locations) in the physical storage area of ​​the NAND flash memory 6.

[0033] In this embodiment, the page table 71 manages the mapping between each logical address included in the logical address space and each physical address included in the physical address space in units of a first size corresponding to the granularity (access granularity) of data accessed for read / write by the host. The following mainly describes a case where the access granularity is 64B and the page table 71 manages the mapping between each logical address and each physical address in units of 64B. When the page table 71 manages the mapping between each logical address and each physical address in units of 64B, the address translation unit of the page table 71 is 64B. The address translation unit of the page table 71 is also referred to as a page.

[0034] The page table 71 includes a plurality of entries corresponding to a plurality of consecutive logical addresses in units of 64B, such as logical address "0", logical address "64", and logical address "128". Generally, a configuration is used in which only a portion of the address translation table is stored as a cache in the DRAM 7, but in this embodiment, all of the entries included in the page table 71 are stored in the DRAM 7 so that the page table 71 can be referenced and updated with low latency. Note that the configuration may also be such that most of the entries in the page table 71 (for example, 80% or more of the entries) are stored in the DRAM 7.

[0035] 4, "64B-addr0" to "64B-addr12" indicate consecutive logical addresses in 64B units. Each entry in the page table 71 holds a physical address where the data at the corresponding logical address is stored. The physical address is location information that indicates a storage location within the physical storage area of ​​the NAND flash memory 6.

[0036] FIG. 4 illustrates a case in which 64B data (page 0 data) corresponding to logical address "64B-addr0" is stored at a location in the physical storage area indicated by physical address 0, 64B data (page 1 data) corresponding to logical address "64B-addr1" is stored at a location in the physical storage area indicated by physical address 2, 64B data (page 2 data) corresponding to logical address "64B-addr2" is stored at a location in the physical storage area indicated by physical address 1, 64B data (page 5 data) corresponding to logical address "64B-addr5" is stored at a location in the physical storage area indicated by physical address 3, 64B data (page 6 data) corresponding to logical address "64B-addr6" is stored at a location in the physical storage area indicated by physical address 4, and 64B data (page 7 data) corresponding to logical address "64B-addr7" is stored at a location in the physical storage area indicated by physical address 5.

[0037] In this case, the entry corresponding to logical address "64B-addr0" holds physical address 0, the entry corresponding to logical address "64B-addr1" holds physical address 2, and the entry corresponding to logical address "64B-addr2" holds physical address 1. The entry corresponding to logical address "64B-addr5" holds physical address 3, the entry corresponding to logical address "64B-addr6" holds physical address 4, and the entry in page table 71 corresponding to "64B-addr7" holds physical address 5.

[0038] In this state, when a read access request to read data corresponding to logical address "64B-addr2" (page 2) is received from the host 2 via the memory bus 4, physical address 1 is obtained from the entry corresponding to logical address "64B-addr2" (page 2). Then, the 64B data stored in the obtained physical address 1 is read from the NAND flash memory 6. The read 64B data is sent to the host 2 via the memory bus 4.

[0039] Generally, an address translation table often manages the mapping between each logical address and each physical address in units of 4 KB. In this case, when rewriting only 64 B of data, which is a portion of the 4 KB data already written, it is necessary to execute a read-modify-write operation including the operation of reading the already written 4 KB data from the NAND flash memory 6, the operation of correcting the read 4 KB data with 64 B of data, and the operation of writing the corrected 4 KB data to another storage area in the NAND flash memory 6. In response to a write access request for 64 B of data from the host 2, 4 KB of data is written to the NAND flash memory 6, resulting in a write amount 64 times the amount written by the host, i.e., a write amplification of 64 (= 4K / 64).

[0040] In this embodiment, the page table 71 manages the mapping between each logical address and each physical address in 64B units. Therefore, regardless of the order of logical addresses in which a write access request requesting the writing of 64B data is received from the host 2, each 64B data can be written sequentially to the physical storage area of ​​the NAND flash memory 6. Furthermore, the page table 71 can be used to manage location information (physical addresses) indicating the storage location in the physical storage area where each 64B data is written. Therefore, when already written 64B data is rewritten, only the updated 64B data is written to a different storage location in the physical storage area of ​​the NAND flash memory 6. Then, the page table 71 is updated, and the logical address corresponding to this 64B data is associated with a physical address indicating a different storage location in the physical storage area where the updated 64B data is written. Therefore, even when the host 2 executes 64B random write access, it is possible to maintain a small write amplification value.

[0041] When managing mappings in 64B increments, the number of page table entries required is 64 times the number of page table entries required to manage mappings in 4KB increments. The bit width of the physical address per page table entry also increases because the physical address stored in each page table entry needs to indicate memory locations in granularity finer than 4KB increments.

[0042] Therefore, this embodiment provides a controller 5 having a new configuration that can manage mapping between each logical address and each physical address with a fine access granularity such as 64B while minimizing an increase in the size of the page table 71. Specifically, the controller 5 uses (1) a bank configuration for reducing the size of the page table 71, and (2) a write buffer provided for each bank. Furthermore, this embodiment implements (3) a cache that can consolidate multiple 64B write data associated with multiple 64B random write accesses from the host 2 at different times into data having a size of 128B to 512B corresponding to multiple consecutive logical addresses, in order to achieve low latency.

[0043] Here, an outline of the bank configuration will be explained. The controller 5 divides the logical address space into two N Divide into 2 banks. N The banks are obtained by dividing the logical address space into two N The controller 5 has 2 small logical address spaces. N is a natural number. N banks and 2 N 2 banks, which correspond one-to-one to the physical storage area of ​​the NAND flash memory. N Manage individual regions. N This region is 2 bytes long and is contained in the physical storage area. N The physical storage area of ​​the NAND flash memory 6 is 2 NIt may contain more than two regions. N Regions are 2 N For example, of the physical storage capacity of the NAND flash memory 6, 2 N If the capacity allocated to each bank is 512 GB, N Each of the regions is 512GB / 2 N It has a capacity of

[0044] And controller 5 is 2 N Data corresponding to a logical address belonging to a certain bank among the banks is written to a region corresponding to this bank. As a result, in the page table 71, an entry corresponding to a certain logical address only needs to hold location information indicating one of multiple storage locations included in one region corresponding to the bank to which this logical address belongs, and does not need to hold location information for identifying this one region. In other words, the storage location to which data corresponding to a certain logical address is written is represented by the region corresponding to the bank to which this logical address belongs and the location information held in the page table 71 entry corresponding to this logical address. As a result, compared to a normal configuration in which the logical address space is not divided, the bit width of the physical address required to be held per entry in the page table 71 can be reduced by N bits. N can be set to, for example, a natural number equal to or greater than 10. When N is equal to or greater than 10, the number of bits of the physical address required to be held per entry in the page table 71 can be reduced by 10 bits or more.

[0045] Furthermore, the controller 5 divides each region into 2 M The controller 5 divides the logical address into two sub-regions (sub-regions), where M is a natural number. The controller 5 divides the logical address into two sub-regions (sub-regions) included in the region corresponding to the bank to which the logical address specified by the read / write access request received from the host 2 belongs. MOf these subregions, one subregion determined by this logical address is determined as the subregion to be read / written. For example, consider the case where M=1. In this case, the region corresponding to the bank to which the logical address specified by the read / write access request belongs includes two subregions. Of these two subregions, one subregion determined by the value of a specific one bit of the logical address is determined as the subregion to be read / written. Furthermore, when M=4, the region corresponding to the bank to which the logical address specified by the read / write access request belongs includes 16 subregions. Of these 16 subregions, one subregion determined by the value of specific four bits of the logical address is determined as the subregion to be read / written. A specific bit of a value obtained by converting the logical address using a hash function may be used to determine the subregion.

[0046] Each of the multiple entries in the page table 71 only needs to hold location information indicating one of the multiple storage locations included in one sub-region. The number of storage locations included in one sub-region is fewer than the number of storage locations included in one region. Therefore, compared to a configuration in which the regions are not divided, the number of physical address bits that need to be held per entry in the page table 71 can be further reduced by M bits.

[0047] Next, an outline of the write buffer prepared for each bank will be explained. Data is written to the NAND flash memory 6 in units of the write size of the NAND flash memory 6. For example, if the physical page size of the NAND flash memory 6 is 4 KB and writing is performed simultaneously on 8 planes, the write size is 32 KB (= 4 KB × 8 planes). In this embodiment, basically, write data from the host 2 corresponding to a logical address belonging to a certain bank is written in 32 KB increments to the region corresponding to this bank. Therefore, the controller 5 waits until about 32 KB of write data for the same bank has been accumulated, and after about 32 KB of write data for the same bank has been accumulated, writing to the region corresponding to this bank is started. In addition, N To accommodate 64 random write accesses across two banks, N It is necessary to separately store the write data from the host 2 for each of the two banks. N 2 banks, each with a one-to-one correspondence N write buffers are allocated to the DRAM 7.

[0048] where 2 NThe following describes a write process performed using a write buffer. When a write access request and 64B write data are received from the host 2 via the memory bus 4, the controller 5 identifies the bank to which the logical address of the 64B write data specified in the received write access request belongs. The controller 5 writes the 64B write data to the write buffer corresponding to the identified bank. In this way, multiple pieces of write data corresponding to logical addresses belonging to a certain bank are accumulated in the write buffer corresponding to that bank. When the total size of the write data stored in this write buffer reaches the write size (here, 32 KB), the controller 5 writes the 32 KB write data stored in this write buffer to the region corresponding to that bank. Note that a configuration may be applied that allows writing to a region to begin as needed even if the total size of the write data stored in the write buffer has not yet reached 32 KB. In this case, a configuration may be used in which padding is added to the write data stored in the write buffer. In other words, writing to a region only needs to be performed after the total size of the write data stored in the write buffer reaches a predetermined size or greater.

[0049] In this way, 2 N 2 banks, each with a one-to-one correspondence N By allocating write buffers to DRAM7, 2 N This makes it possible to handle random write access across multiple banks.

[0050] Next, an overview of the cache will be described. The cache 51 includes multiple cache lines. Since the access granularity is 64B, the cache line size should normally be 64B. In this embodiment, the cache line size is set to a size larger than 64B, for example, 512B. The controller 5 stores multiple 64B write data corresponding to multiple consecutive logical addresses in one of the multiple cache lines. For example, consider a case where another 64B write data belonging to the same 512B logical address range as the logical address of the received 64B write data is already stored in a certain cache line. In this case, the controller 5 stores the received 64B write data in this cache line. This allows multiple 64B write data associated with multiple 64B random write accesses from the host 2 at different times to be combined into a single write data piece having a size of 128B to 512B corresponding to consecutive logical addresses. For example, if four 64B write data pieces corresponding to four consecutive logical addresses are stored in the same cache line, these four 64B write data pieces are combined into a single write data piece having a size of 256B on the cache line.

[0051] When a cache line is selected as a cache line to be written back or evicted, the controller 5 executes a write-back operation. The write-back operation is a process of writing dirty data, i.e., write data that has not yet been reflected in the NAND flash memory 6, from the cache 51 to the NAND flash memory 6 via a write buffer.

[0052] Here, consider a case where a cache line in which four 64B write data corresponding to four consecutive logical addresses are stored is selected as a cache line to be written back or evicted. In this case, the controller 5 executes a write-back operation for the four 64B write data (i.e., write data having a size of 256B). Specifically, the controller 5 executes a write-back operation for the four 64B write data corresponding to four consecutive logical addresses. N Four 64B write data are stored in two regions so that they are sequentially arranged in physically consecutive memory locations within one of the regions. N Through one of the write buffers, N The four 64B write data are written to one of the regions. This region corresponds to one bank to which the four logical addresses of the four 64B write data belong together. This allows the four 64B write data associated with the four 64B random write accesses from the host 2 at different times to be sequentially arranged in multiple physically consecutive memory locations within one region.

[0053] When the write-back operation for the data stored in the cache line to be evicted is completed, the cache line is initialized.

[0054] On the other hand, when the write-back operation for the data stored in the cache line to be written back is completed, the data stored in the cache line to be written back is maintained in the cache line as valid data. Specifically, after the write-back, the dirty flag corresponding to each piece of written-back data is reset, but each piece of written-back data continues to be maintained in the cache line as valid data.

[0055] Next, consider the case where a cache line in which eight 64B write data corresponding to eight consecutive logical addresses is stored is selected as the cache line to be evicted. In this case, the controller 5 executes a write-back operation for the eight 64B write data (i.e., write data having a size of 512B). Specifically, the controller 5 executes a write-back operation for the eight 64B write data corresponding to eight consecutive logical addresses in a manner similar to the case where the eight 64B write data are stored in two consecutive logical addresses. N Eight 64B write data are stored in two regions so that they are sequentially arranged in physically consecutive memory locations within one of the regions. N Through one of the write buffers, N The eight 64B write data items are written to one of the eight regions. This region corresponds to one bank to which the eight logical addresses of the eight 64B write data items belong together. This allows the eight 64B write data items associated with the eight 64B random write accesses from the host 2 at different times to be sequentially arranged in multiple physically consecutive memory locations within one region.

[0056] Next, consider the case where a cache line storing only one 64B write data is selected as the cache line to be written back or evicted. In this case, the controller 5 writes this 64B write data to the cache line 2 N Through one of the write buffers, N The 64B write data is written to one of the regions. This region corresponds to the bank to which the logical address of the 64B write data belongs.

[0057] In this way, write-back operations of write data of a variety of sizes from 64B to 512B are executed.

[0058] Next, an overview of the refill operation of the cache 51 will be explained. The refill operation is executed when the 64B read target data specified by a read access request received from the host 2 is not present in the cache 51. The refill operation is an operation in which the 64B read target data is read from the NAND flash memory 6 and stored in the cache 51. The refill operation can also accommodate data of multiple sizes from 64B to 512B. In other words, the controller 5 determines whether multiple 64B data items corresponding to multiple consecutive logical addresses, including the 64B read target data, are sequentially arranged in multiple physically consecutive storage locations within a region. This region is a region corresponding to the bank to which the logical address of the 64B read target data belongs.

[0059] For example, if four 64B data items corresponding to four consecutive logical addresses, including the 64B read target data, are sequentially arranged in multiple physically consecutive storage locations, the controller 5 reads the four 64B data items from the NAND flash memory 6 and stores them in one cache line of the cache 51. This allows 256B data to be refilled with one read access to the NAND flash memory 6.

[0060] Furthermore, for example, if eight 64B data items corresponding to eight consecutive logical addresses including the 64B read target data are sequentially arranged in multiple physically consecutive storage locations, the controller 5 reads the eight 64B data items from the NAND flash memory 6 and stores them in one cache line of the cache 51. This allows 512B data to be refilled with one read access to the NAND flash memory 6.

[0061] If multiple 64B data corresponding to multiple consecutive logical addresses, including the 64B read target data, are not sequentially arranged in multiple physically consecutive storage locations, the controller 5 reads only the 64B read target data from the NAND flash memory 6 and stores it in one cache line of the cache 51.

[0062] In this way, refill operations for data of a variety of sizes from 64B to 512B are performed.

[0063] Next, a description will be given of the components provided in the memory system 3, and the write-back operation, refill operation, and garbage collection operation. Fig. 5 is a diagram showing the components provided in the memory system 3 according to the embodiment, and the write-back operation, refill operation, and garbage collection operation executed in the memory system 3.

[0064] 5, cache control logic 511 is a component of the cache 51. The cache control logic 511 is a circuit that controls the cache 51. The data storage area of ​​the cache 51 is arranged on the DRAM 7, and the cache control logic 511 is implemented in the controller 5.

[0065] The write controller 521, read controller 522, and GC controller 523 are components of the media control unit 52. The write controller 521 is hardware that executes write-back operations. The read controller 522 is hardware that executes refill operations. The GC controller 523 is hardware that executes GC operations.

[0066] The page table 71, the write buffer 72, and the program buffer 73 are arranged on the DRAM 7. The write buffer 72 is N 2 corresponding to banks N A set of 2 write buffers. NEach of the write buffers contains at least the capacity of the write size (32KB). When N=13, the number of banks is 8K (=2 13 ) Therefore, since the write buffer 72 includes 8K write buffers, the capacity of the entire write buffer 72 is expressed as 8K x 32KB. The program buffer 73 is, for example, a set of 32 program buffers corresponding to the 32 channels, respectively. Each of the 32 program buffers is used to store the write size (32KB) of data to be written to the flash die connected to the corresponding channel. The capacity of each of the 32 program buffers, that is, the capacity of the program buffer 73 per channel, is 32KB.

[0067] Next, the operation of the cache control logic 511 will be described. When a write access request and 64B write data are received from the host 2 via the memory bus 4, the cache control logic 511 stores the received 64B write data in one of multiple cache lines in the cache 51. The size of each of the multiple cache lines is 512B. If there is a cache line in which 64B write data having a logical address belonging to the same 512B logical address range as the logical address of the received 64B write data is already stored, the cache control logic 511 stores the received 64B write data in this cache line. If there is no cache line in which 64B write data having a logical address belonging to the same 512B logical address range as the logical address of the received 64B write data is already stored, the cache control logic 511 stores the received 64B write data in a free cache line. If there is no free cache line, the cache control logic 511 selects a cache line to be evicted. If dirty data exists in the cache line to be evicted, a write-back operation is executed by the write controller 521.

[0068] When a read access request is received from the host 2 via the memory bus 4, the cache control logic 511 executes a cache hit determination process. The cache hit determination process is a process for determining whether or not the data to be read is stored in the cache 51. The data to be read is 64B data having a logical address specified by the read access request.

[0069] If the read target data exists in the cache 51, the cache control logic 511 reads the read target data from the cache 51. Then, the cache control logic 511 transmits the read target data that has been read to the host 2 via the memory bus 4.

[0070] If the data to be read does not exist in the cache 51, the cache control logic 511 sends a read request requesting reading of the data to the read controller 522. Upon receiving this read request, the read controller 522 executes a refill operation.

[0071] Next, the write-back operation executed by the write controller 521 will be described. Here, it is assumed that 64B write data is written to a write-destination region among 8K regions included in the physical storage area of ​​the NAND flash memory. The write-destination region is a region corresponding to the bank to which the logical address of the 64B write data belongs. In the write-back operation, the 64B write data stored in the cache line to be evicted is written to the write-destination region of the NAND flash memory 6 via one of the 8K 32KB write buffers included in the write buffer 72 and one of the 32 32KB program buffers included in the program buffer 73.

[0072] In a write-back operation, the write controller 521 identifies one of the 8K banks to which the logical address of the write data belongs. The 64B write data is then written to the 32KB write buffer corresponding to the identified bank. When write data of a predetermined size or more accumulates in the 32KB write buffer—for example, when the total size of the multiple write data, including the 64B write data, accumulated in the 32KB write buffer reaches 32KB (write size)—the multiple write data, including the 64B write data, are written to a single 32KB program buffer. If the NAND flash memory 6 includes multiple flash dies, each of the 8K regions may be included in one of the multiple flash dies. For example, if the write-destination region is included in flash die #0 connected to channel ch.0, the multiple write data, including the 64B write data, is written to the program buffer corresponding to channel ch.0. The multiple write data, including the 64B write data, written to the program buffer is then written to the write-destination region. Then, the page table 71 is updated by the write controller 521, and the physical address indicating the storage location in the write destination region to which the 64B write data has been written is stored in the entry corresponding to the logical address of the 64B write data. Note that the process of storing the physical address in the entry corresponding to the logical address of the 64B write data may be executed when the cache control logic 511 requests write-back of the 64B write data.

[0073] Next, a refill operation executed by the read controller 522 will be described. In the refill operation, the read controller 522 identifies the bank to which the logical address of the 64B data to be read belongs. The read controller 522 also obtains from the page table 71 a physical address corresponding to the logical address of the 64B data to be read. Then, based on the identified bank and the obtained physical address, the 64B data to be read is read from the region of the NAND flash memory 6 corresponding to the identified bank. The read 64B data to be read is stored in one cache line and then transmitted to the host 2. Note that if the 64B data to be read is stored in the write buffer 72, the 64B data to be read is read from the write buffer 72. The read 64B data to be read is stored in one cache line and then transmitted to the host 2.

[0074] Next, we will explain the garbage collection operation executed by the GC controller 523. In the garbage collection operation, valid data stored in the GC source block is read by the GC controller 523. The read valid data is sent to the write controller 521. The write controller 521 executes a process of writing the received valid data to the GC destination block.

[0075] Next, the multiple banks will be described. Fig. 6 is a diagram showing the relationship between the components provided in the memory system 3 according to the embodiment and the multiple banks.

[0076] Multiple banks can be used in two N Banks 1 to 8K in FIG. 6 are small logical address spaces. The entire logical address space is divided into 8K (=2 13 ) banks. When a 256 GB logical address space is divided into 8K banks, each bank has a capacity of 32 MB. The 8K banks 1 to 8K are created by dividing the physical storage area of ​​the NAND flash memory 6 into 8K (=213 ) regions 1 to 8K correspond one-to-one to the 8K (=2 13 ) entries in the write buffer 72. 13 ) 32KB write buffers (w-buffer 1 to w-buffer 8K) in a one-to-one correspondence.

[0077] Each of the 8K regions 1 to 8K is a non-overlapping storage area. Therefore, if the capacity of the NAND flash memory 6 is 512 GB, the storage area corresponding to each region, i.e., each bank, has a capacity of 64 MB. The page table 71 includes a group of entries corresponding to each bank. Furthermore, there is a one-to-one correspondence between the 8K banks and the 8K regions. Therefore, the physical address stored in each entry of the page table 71 only needs to specify a storage location within the corresponding region, and does not need to include information specifying the region. This allows the bit width of the physical address stored in each entry of the page table 71 to be reduced according to the number of divided banks.

[0078] In this way, the 8K banks 1 to 8K correspond to the 8K regions 1 to 8K, respectively. Therefore, data having a logical address belonging to a certain bank is written only to the region corresponding to that bank. Furthermore, writing to each region cannot begin until data of a size corresponding to the write size is available. Therefore, a write buffer having a capacity corresponding to the write size (here, 32 KB) is required for each bank. In this embodiment, 8K 32 KB write buffers (w-buffer1 to w-buffer8K) included in the write buffer 72 correspond to the 8K banks 1 to 8K, respectively. Data output from the cache 51 is stored in the 32 KB write buffer (w-buffer) corresponding to the bank containing the logical address corresponding to that data. Then, when data of a size corresponding to the write size is stored in that 32 KB write buffer (w-buffer), the data is written to the region corresponding to the bank to which those logical addresses belong.

[0079] Here, the capacity of the write buffer and the capacity of the page table in a normal configuration in which the logical address space is not divided, and the capacity of the write buffer and the capacity of the page table in this embodiment will be described.

[0080] In a normal configuration in which the logical address space is not divided, the required capacity of the write buffer is expressed by the following formula. Write buffer capacity = "write size" x "number of parallel writes" In the case where the physical page size is 4 KB and a multi-plane mode is used in which data is written to eight planes simultaneously, the write size is 32 KB (= 4 KB × 8). When data is written in parallel to 32 flash dies connected to 32 channels, the number of parallel writes is 32. Therefore, the required write buffer capacity (total capacity) is 1 MB (= 32 KB × 32). This write buffer capacity corresponds to the total capacity of the program buffer 73 in this embodiment.

[0081] In this embodiment, the required capacity of the write buffer 72 is expressed by the following formula. Write buffer capacity = write size x number of banks The write size is 32KB (=4KB x 8) and the number of banks (2 N ) is 8K, the required capacity of the write buffer 72 is expressed by the following formula: Write buffer capacity = 32KB x 8K = 256MB Therefore, the required capacity (total capacity) of the write buffer 72 is several hundred times the "write size x number of parallel writes," that is, at least 10 times the "write size x number of parallel writes."

[0082] Next, the size of the page table 71 will be described. 38 Consider the case of B). The capacity of the logical address space is the capacity (user capacity) of the memory system 3 that is visible to the host 2.

[0083] The address translation unit of the page table 71 is 64B (=2 6 B). Therefore, the number of entries included in the page table 71 is 256 GB (entire logical address space) ÷ 64 B (address translation unit) = 2 38-6 = 4G, so it is a 4G entry. The bit width of the logical address corresponding to the 4G entry is 32 bits.

[0084] The NAND flash memory 6 has a capacity equal to or greater than the capacity of the logical address space. For example, if the capacity of the NAND flash memory 6 is 512 GB (=2 39 The address translation unit of the page table 71 is 64B (=2 6 B), the bit width of the physical address that can address the 512G physical address space in 64B units is 512GB (the capacity of the storage area of ​​the NAND flash memory 6) ÷ 64B (address translation unit) = 2 39-6 =2 33 Therefore, it is 33 bits.

[0085] In this embodiment, the logical address space is 2 N It is divided into 2 banks. N banks and 2 N There is a one-to-one correspondence between the page table 71 and each region. Therefore, each entry in the page table 71 only needs to hold location information indicating one of the multiple storage locations contained in one region as a physical address. The number of storage locations contained in one region is half the number of storage locations contained in the entire physical storage area of ​​the NAND flash memory 6. N Therefore, the bit width of the physical address stored in each entry can be reduced by N bits. When N=13, that is, when the logical address space is divided into 8K banks, the bit width of the physical address that needs to be stored in each entry is 20 bits (=33 bits - 13 bits).

[0086] The capacity of the page table 71 is 20 bits x 4 GB entries = 10 GB, which is 10 GB. On the other hand, if the logical address space is not divided, the capacity of the page table 71 is 33 bits x 4 GB entries = 16.5 GB, which is 16.5 GB. Therefore, it is possible to reduce the capacity of the page table 71 by 6.5 GB, since 16.5 GB - 10 GB = 6.5 GB.

[0087] In this embodiment, the sum of the capacity of the page table 71 and the total capacity of the write buffer 72 is 10 GB + 256 MB. On the other hand, in the case where the logical address space is not divided, the sum of the capacity of the page table and the total capacity of the write buffer is 16.5 GB + 1 MB. Therefore, when the logical address space is divided into two, N By dividing the memory area into four banks, the overall capacity of the DRAM 7 required to store the page table 71 and the write buffer 72 can be reduced.

[0088] Here, N=13, that is, the logical address space is 8K (=2 13), the number of banks (i.e., the value of N) can be set to any value. N may be set to a natural number equal to or greater than 10. When N is equal to or greater than 10, the capacity of the page table 71 can be reduced by 5 GB or more. A reduction of 5 GB is 10 times the reduction of the page table 71, 0.5 GB, when N is 1. Furthermore, when N is 10, the number of banks is 1024, and the total capacity of the write buffer 72 is 32 MB (= 32 KB × 1024). The total capacity of the write buffer 72, 32 MB, is approximately 30 times the "write size × number of parallel writes." Therefore, by setting N to 10 or greater, the overall capacity of the DRAM 7 required to store the page table 71 and the write buffer 72 can be significantly reduced compared to when the logical address space is not divided.

[0089] Next, the subregions will be described. Fig. 7 is a diagram showing the relationship between the components provided in the memory system 3 according to the embodiment and the multiple banks and multiple subregions.

[0090] Each of the 8K regions is 2 MThe region is divided into subregions, where M is a natural number. In FIG. 7, each region is divided into two subregions (M=1). Each entry group in the page table 71 corresponds to a region. The media control unit 52 references a logical address specified by a read / write access request from the host 2 to identify one of the subregions included in the region corresponding to the bank containing the logical address as the subregion to be read / written. For example, the media control unit 52 determines whether the logical address is even or odd. If the logical address is even, the media control unit 52 identifies subregion 1 as the subregion to be read / written from among the subregions included in the region corresponding to the bank containing the logical address. If the logical address is odd, the media control unit 52 identifies subregion 2 as the subregion to be read / written from among the subregions included in the region corresponding to the bank containing the logical address. The physical address stored in each entry in the page table 71 specifies one of the storage locations included in one subregion. That is, the physical address of each entry in the page table 71 only needs to specify a storage location within a subregion, which is an area smaller than a region, and therefore the bit width of the physical address is reduced by M bits.

[0091] Specifically, the capacity of the NAND flash memory 6 is 512 GB, and the logical address space is 8 K (= 2 13 ) and 8K(=2 13 ) regions each of which has 2(=2 1 ) sub-regions, the bit width of the physical address stored in each entry of the page table 71 is 512 GB (storage area of ​​the NAND flash memory 6) ÷ 8 K (number of banks) ÷ 2 (number of sub-regions in each region) ÷ 64 B (address translation unit) = 2 38-13-1-6 =2 19Therefore, the total is 19 bits. In other words, by dividing each region into two sub-regions, the bit width of the physical address per entry can be reduced by 1 bit. By reducing the bit width of the physical address per entry by 1 bit, a reduction effect of 1 bit (number of bits reduced in the address width of the physical address by dividing the sub-regions) x 4G (number of entries in the page table 71) = 0.5GB can be achieved in the page table 71 having 4G entries. When combined with the reduction effect achieved by dividing the entire logical address space into 8K banks, the reduction effect is 7.0GB (=0.5GB + 6.5GB).

[0092] When M=4, the bit width of the physical address per entry can be reduced by 4 bits. By reducing the bit width of the physical address per entry by 4 bits, a reduction effect of 4 bits x 4G = 2GB can be obtained. When combined with the reduction effect achieved by dividing the entire logical address space into 8K banks, the reduction effect is 8.5GB (=2GB + 6.5GB).

[0093] When N is set to 14, the required capacity of the write buffer 72 is 512 MB, twice the 256 MB capacity of the write buffer 72 when N is 13. On the other hand, the reduction effect of dividing the entire logical address space into 16K banks is 0.5 GB more than when N is 13. Therefore, the sum of the capacity of the page table 71 and the capacity of the write buffer 72 is smaller with 16K banks than with 8K banks.

[0094] Next, the logical addresses belonging to each bank will be described. Figure 8 is a diagram showing the logical addresses belonging to each bank used in the memory system 3 according to the embodiment. Here, the case where each bank has a logical address space of 32 MB and the address translation unit is 64 B is shown.

[0095] Bank 1 contains 0.5M consecutive logical addresses in 64B units. Specifically, Bank 1 contains logical address "64B-addr0", logical address "64B-addr1", ..., logical address "64B-addr(0.5M-1)". Logical address "64B-addr0", logical address "64B-addr1", ..., logical address "64B-addr(0.5M-1)" correspond to page 0, page 1, ..., page (0.5M-1).

[0096] Furthermore, eight 64B data items belonging to a 512B logical address range including eight consecutive logical addresses in 64B units are stored in the same cache line in the cache 51. For example, eight 64B data items belonging to the 512B logical address range corresponding to page 0 to page 7 are data items that should be stored in the same cache line. Similarly, eight 64B data items belonging to the 512B logical address range corresponding to page 8 to page 15 are data items that should be stored in the same cache line, and eight 64B data items belonging to the 512B logical address range corresponding to page (0.5M-8) to page (0.5M-1) are also data items that should be stored in the same cache line.

[0097] Bank 2 contains 0.5M consecutive logical addresses in 64B units. Specifically, logical address "64B-addr0.5M", logical address "64B-addr(0.5M+1)", ..., logical address "64B-addr(1M-1)" belong to Bank 2. Logical address "64B-addr0.5M", logical address "64B-addr(0.5M+1)", ..., logical address "64B-addr(1M-1)" correspond to page 0.5M, page (0.5M+1), ..., page (1M-1).

[0098] Next, an example of the configuration of a cache will be described. Fig. 9 is a diagram showing an example of the configuration of a cache 51 included in the memory system 3 according to the embodiment.

[0099] The cache 51 includes a cache body that stores data, and a cache management table that holds information for managing the data stored in the cache 51.

[0100] The cache body is a memory area for storing data. The cache body includes n cache lines L1 to Ln. Each cache line has a size of 512B. Therefore, each cache line has eight memory areas that can store eight 64B data items each.

[0101] The cache management table holds eight valid flags, a tag, and eight dirty flags for each cache line. The eight valid flags correspond to eight storage areas in the corresponding cache line. Each of the eight valid flags is a flag indicating whether the corresponding storage area is valid. A valid storage area is an area that stores 64B write data from the host 2 or 64B read data read from the NAND flash memory 6. The tag indicates which 512B logical address range the data belonging to is stored in the corresponding cache line. The eight dirty flags correspond to eight storage areas in the corresponding cache line. Each of the eight dirty flags is a flag indicating whether the corresponding 64B data is updated data (dirty data) that needs to be written to the NAND flash memory 6.

[0102] 10 is a diagram showing a cache in which data is stored in a memory system according to an embodiment. Four 64B write data items and one 64B write data item are stored in cache line L1 and cache line L2, respectively.

[0103] Cache line L1 stores four 64B write data items corresponding to page 4, page 5, page 6, and page 7, respectively. Because the latter four storage areas of cache line L1 hold data, valid flags V4, V5, V6, V7, and V8 of cache line L1 are set to the value "1" indicating valid. Furthermore, the tag corresponding to cache line L1 indicates the first logical address "64B-addr0" of the 512B address range that includes pages 0 to 7. Because the four 64B write data items corresponding to page 4, page 5, page 6, and page 7, respectively, are data that need to be written to the NAND flash memory 6, dirty flags D5, D6, D7, and D8 are set to the value "1" indicating dirty.

[0104] Furthermore, cache line L2 stores one 64B write data item corresponding to page 0.5M. Because the first storage area of ​​cache line L2 holds data, the valid flag V1 corresponding to cache line L2 is set to the value "1" indicating valid. Furthermore, the tag of cache line L2 indicates the first logical address "64B-addr0.5M" of the 512B address range including page 0.5M. Because the one 64B write data item corresponding to page 0.5M is data that needs to be written to the NAND flash memory 6, the dirty flag D1 is set to the value "1" indicating dirty.

[0105] Since no data has been stored in the cache line L3 yet, each of the valid flags V1 to V8 corresponding to the cache line L3 is set to the value "0" indicating invalidity.

[0106] 11 is a diagram showing a state in which further data has been stored in the cache 51 in the memory system 3 according to the embodiment. Here, a case will be described in which, in response to writing from the host 2, four pieces of 64B write data corresponding to pages 12 to 15, one piece of 64B write data corresponding to page (0.5M+7), and four pieces of 64B write data corresponding to pages 0 to 3 have been stored in this order in the cache 51 described in FIG.

[0107] First, the four 64B write data corresponding to pages 12 to 15 are stored in the last four storage areas of cache line L3, which is an empty cache line. In response to the data being written to the last four storage areas of cache line L3, the valid flags V5, V6, V7, and V8 corresponding to cache line L3 are set to values ​​indicating valid. Then, the tag corresponding to cache line L3 indicates the first logical address "64B-addr8" of the 512B logical address range corresponding to pages 8 to 15. Then, the dirty flags D5, D6, D7, and D8 corresponding to pages 12 to 15 are set to values ​​indicating dirty.

[0108] Next, one 64B write data item corresponding to page (0.5M+7) is stored in the memory area at the end of cache line L2. As a result, the valid flag V8 of cache line L2 is set to a value indicating valid. Also, the dirty flag D8 of cache line L2 is set to a value indicating dirty.

[0109] Then, the four 64B write data corresponding to pages 0 to 3 are stored in the first four storage areas of cache line L1, respectively. As a result, the valid flags V1, V2, V3, and V4 of cache line L2 are set to values ​​indicating valid. Also, the dirty flags D1, D2, D3, and D4 of cache line L1 are set to values ​​indicating dirty.

[0110] Next, the write-back operation will be described. Fig. 12 is a diagram showing the write-back operation executed in the memory system 3 according to the embodiment. Here, a case will be described in which four 64B write data corresponding to pages 12 to 15 stored in cache line L3 in Fig. 11 are written back.

[0111] The cache line L3 is selected as the cache line to be written back or evicted. In this case, since the dirty flags D4 to D7 of the cache line L3 are 1, the controller 5 recognizes that four 64B write data items corresponding to pages 12 to 15 stored in the cache line L3 need to be written to the NAND flash memory 6.

[0112] The four 64B write data corresponding to pages 12 to 15 are 256B data corresponding to four consecutive logical addresses. These four logical addresses all belong to Bank 1. Therefore, the controller 5 reserves a contiguous area having a size of 256B in the 32KB write buffer w-buffer1 corresponding to Bank 1. The controller then writes the four 64B write data corresponding to pages 12 to 15 (i.e., the four 64B write data corresponding to four consecutive logical addresses) to the 256B contiguous area reserved in the 32KB write buffer w-buffer1. Then, cache line L3 is initialized, and the eight valid flags, tag, and eight dirty flags corresponding to cache line L3 are reset. As a result, cache line L3 becomes a free cache line.

[0113] After the total size of the data stored in the write buffer w-buffer1 reaches a predetermined size or more, for example, after the total size of the data stored in the write buffer w-buffer1 reaches 32 KB (write size), the 32 KB data stored in the write buffer w-buffer1 is written to region 1, which is the storage area of ​​the NAND flash memory 6 corresponding to bank 1. The 32 KB data stored in the write buffer w-buffer1 is sequentially arranged in physically contiguous storage locations within region 1. Therefore, the four 64 B write data corresponding to pages 12 to 15, i.e., the four 64 B write data corresponding to four consecutive logical addresses, are physically contiguous in the storage area of ​​region 1. At this time, the write operation of the 32 KB data to region 1 can be executed by a parallel write operation of 8 planes x physical pages.

[0114] Next, the refill operation will be described. Fig. 13 is a diagram showing the refill operation executed in the memory system according to the embodiment. Here, a case will be described in which four 64B data corresponding to pages 12 to 15 written in region 1 in Fig. 12 are refilled together.

[0115] The controller 5 searches the cache 51 based on the read access request received from the host 2 that specifies the logical address "64B-addr12" (page 12).

[0116] If the read target data having the logical address "64B-addr12" (page 12) specified by the read access request is not present in the cache 51, the controller 5 executes a refill process. The controller 5 selects one cache line as the cache line to be refilled. For example, if there is a cache that stores data belonging to the same 512B logical address range as the read target data, this cache line is selected as the cache line to be refilled. If there is no cache that stores data belonging to the same 512B logical address range as the read target data, an empty cache line is selected as the cache line to be refilled. If there is no empty cache line, an eviction process is executed to generate an empty cache line. After selecting the cache line to be refilled, the controller 5 refers to the page table 71 to obtain a physical address indicating the storage location in the NAND flash memory 6 where the read target data is stored. The controller 5 then determines whether the data to be stored in the same cache line as the read target data is sequentially arranged in multiple physically contiguous storage locations within the storage area of ​​the NAND flash memory 6. This determination can be made by referring to the page table 71. Here, four 64B data items corresponding to pages 12 to 15 are sequentially arranged in a plurality of physically consecutive storage locations within region 1. Therefore, the controller 5 collectively reads the four 64B data items corresponding to pages 12 to 15 from the NAND flash memory 6, and stores the four read 64B data items in the cache line to be refilled. In the cache line to be refilled, four valid flags corresponding to the four 64B data items are set to values ​​indicating validity.

[0117] Next, an operation of writing two 64-byte data (i.e., 128-byte data) corresponding to two consecutive logical addresses to an arbitrary region will be described. Fig. 14 is a diagram showing 16-bit first location information applied to 64-byte data and 32-bit second location information applied to 128-byte data, which are used in the memory system 3 according to the embodiment.

[0118] Each entry in the page table 71 holds a physical address that indicates the storage location in the NAND flash memory 6 where the data corresponding to each logical address is stored.

[0119] Here, for example, when N=13 and M=4, the bit width of the physical address per entry is 16 bits.

[0120] For example, when 64B data corresponding to entry #1 and 64B data corresponding to entry #2 are written to consecutive storage areas, the page table 71 uses the combined 32 bits of entry #1 and entry #2 to manage the storage location of the 128B data written to the consecutive storage areas. The page table 71 may also manage a flag indicating that the two entries have been combined. In this case, by combining the two entries, the available bit width is increased, and the physical addresses stored in the combined two entries can specify not only storage locations within the region corresponding to this bank, but also storage locations included in any region. Therefore, 2 N Based on the amount of writes in each region, N From these regions, it is possible to select the region to which 128B of data should be written. This prevents writing from concentrating on only a few regions, preventing differences in the amount of data written among multiple regions. Also, page table 71 may combine three or more entries.

[0121] Next, we will explain the write-back process when evicting 64B write data from the cache line to be evicted, and the write-back process when writing back or evicting two 64B write data (i.e., 128B write data) corresponding to two consecutive logical addresses from the cache line to be evicted.

[0122] When evicting 64B of write data from the cache line to be evicted, the controller 5 N The controller 5 identifies the bank to which the logical address of the 64B write data belongs among the banks. The controller 5 writes the 64B write data to one region corresponding to the identified bank via the write buffer 73 (one of w-buffer1 to w-buffer8K) corresponding to the identified bank. The controller 5 stores in the page table 71 location information having a first bit width (16 bits width) that indicates the storage location within the region to which the 64B write data has been written, by using one entry in the page table 71 that corresponds to the logical address of the 64B write data. In this way, the 64B write data is written only to the region corresponding to the bank to which the logical address belongs.

[0123] When two 64B write data (i.e., 128B write data) corresponding to two consecutive logical addresses are evicted from the cache line to be evicted, the controller 5 N Based on the amount of writes in each region, NThe controller 5 selects one of these regions into which the two 64B write data should be written. The controller 5 writes the two 64B write data to the selected region via the write buffer 73 (one of w-buffer1 to w-buffer8K) corresponding to the selected region so that the two 64B write data are sequentially arranged in two physically consecutive memory locations within the selected region. The controller 5 uses two entries in the page table 71 corresponding to the two logical addresses of the two 64B write data to store second position information having a second bit width (32 bits wide) in the page table 71, which indicates both the selected region and the memory locations within the selected region into which the two 64B write data have been written.

[0124] In this way, by using two entries to manage the physical address of the 128B write data, N By taking into account the amount of data written to each region, 128B of write data can be written to the region with the least amount of data written. N This allows the amount of writing to each of the regions to be equalized, thereby maximizing the lifespan of the memory system 3 and improving the write performance. N The write amount for each region is not limited to the amount of data written to each region, and any predetermined criteria may be used. For example, a configuration may be used in which a region other than the region currently being accessed is selected to temporarily avoid a concentration of read / write accesses. While the write-back process for evicting data from a cache line to be evicted has been described above, the write-back process for writing back data from a cache line to be written back is also performed in a similar manner.

[0125] It is also possible to write two 64B data items (i.e., 128B data items) corresponding to two consecutive logical addresses to any subregion. In this case, the write-back process when evicting 64B write data from the cache line to be evicted and the write-back process when evicting two 64B write data items (i.e., 128B write data items) corresponding to two consecutive logical addresses from the cache line to be evicted are executed as follows:

[0126] When evicting 64B of write data from the cache line to be evicted, the controller 5 N The controller 5 identifies the bank to which the logical address of the 64B write data belongs. The controller 5 writes the 64B write data to two banks included in one region corresponding to the identified bank. M The controller 5 writes the 64B write data to one of the sub-regions determined by the logical address of the 64B write data. By using one entry in the page table 71 corresponding to the logical address of the 64B write data, the controller 5 stores in the page table 71 first position information having a first bit width (16 bits width) that indicates the storage location in one sub-region to which the 64B write data has been written. In other words, the 64B write data is written to one of the two entries in the page table 71 that corresponds to the logical address of the 64B write data. M The data is written into one of the subregions determined by the logical address.

[0127] When two 64B write data (i.e., 128B write data) corresponding to two consecutive logical addresses are evicted from the cache line to be evicted, the controller 5 N The controller 5 identifies the bank to which the two logical addresses of the two 64B write data belong. M Based on the amount of writing in each of these subregions, MThe controller 5 selects a subregion into which the two 64B write data are to be written from the subregions. The controller 5 writes the two 64B write data to the selected subregion such that the two 64B write data are sequentially arranged in two physically consecutive memory locations within the selected subregion. The controller 5 uses two entries in the page table 71 corresponding to the two logical addresses of the two 64B write data to store in the page table 71 second location information having a second bit width (32 bits wide) that indicates both the selected subregion and the memory locations within the selected subregion into which the two 64B write data have been written. Note that the criteria used to select a subregion are also two M The write amount of each sub-region is not limited to the write amount of each sub-region, and any predetermined standard may be used. Also, although the write-back process when evicting data from a cache line that is the target of eviction has been described, the write-back process when writing back data from a cache line that is the target of write-back is also performed in a similar manner.

[0128] Next, a description will be given of the preparation process of the memory system 3. Fig. 15 is a flowchart showing the procedure of the preparation process executed in the memory system 3 according to the embodiment.

[0129] The controller 5 manages 8K banks obtained by dividing the entire logical address space and 8K regions obtained by dividing the entire physical storage area of ​​the NAND flash memory 6 (step S101).

[0130] The controller 5 stores in the DRAM 7 a page table 71 for managing, in units of 64 B, mapping between each logical address belonging to the logical address space and each piece of location information indicating a location on the physical storage area of ​​the NAND flash memory 6 (step S102). In this case, all entries of the page table 71 are stored in the DRAM 7.

[0131] The controller 5 allocates 8K write buffers 72 (w-buffer1 to w-buffer8K) that correspond one-to-one to the 8K banks to the DRAM 7 (step S103).

[0132] Next, a description will be given of the operation of writing data to the NAND flash memory 6. Fig. 16 is a flowchart showing the procedure of a process of writing data to a region via the write buffer 72, which is executed in the memory system 3 according to the embodiment.

[0133] The controller 5 receives a write access request from the host 2 (step S201).

[0134] The controller 5 identifies the bank that contains the logical address corresponding to the received write data from among the 8K banks obtained by dividing the entire logical address space (step S202).

[0135] The controller 5 stores the received write data in the write buffer 72 (one of w-buffer1 to w-buffer8K) corresponding to the bank identified in step S202 (step S203).

[0136] The controller 5 determines whether the total size of the write data stored in the write buffer 72 (one of w-buffer1 to w-buffer8K) corresponding to the identified bank has reached the write size (step S204).

[0137] If the total size of the write data stored in the write buffer 72 (one of w-buffer1 to w-buffer8K) corresponding to the identified bank reaches the write size (Yes in step S204), the controller 5 writes the write data stored in the write buffer 72 (one of w-buffer1 to w-buffer8K) corresponding to the identified bank to the region corresponding to the identified bank (step S205).

[0138] If the total size of the write data stored in the write buffer 72 (one of w-buffer1 to w-buffer8K) corresponding to the identified bank has not reached the write size (No in step S204), the controller 5 waits until it receives the next write access request.

[0139] Here, we have explained an example in which writing to a region begins when the total size of the write data stored in the write buffer 72 (one of w-buffer1 to w-buffer8K) corresponding to the identified bank reaches the write size, but writing to a region can be performed only after the total size of the write data stored in the write buffer 72 (one of w-buffer1 to w-buffer8K) reaches a predetermined size or greater.

[0140] Next, a description will be given of a write process using the cache 51. Fig. 17 is a flowchart showing the procedure of a write process executed in the memory system 3 according to the embodiment.

[0141] The controller 5 determines whether or not there is a cache line in which data belonging to the same 512B logical address range as the write data corresponding to the received write access request is stored (step S301). That is, the controller 5 determines whether or not there is a cache line in which data that should be stored in the same cache line as the write data corresponding to the received write access request is already stored.

[0142] If there is a cache line storing data that belongs to the same 512B logical address range as the write data (Yes in step S301), the controller 5 stores the write data in the corresponding cache line (step S302).

[0143] The controller 5 sets the dirty flag corresponding to the write data stored in the relevant cache line to a value indicating dirty (step S303).

[0144] The controller 5 sets the valid flag corresponding to the write data stored in the relevant cache line to a value indicating validity (step S304).

[0145] If there is no cache line storing data belonging to the same 512B logical address range as the write data (No in step S301), the controller 5 determines whether or not there is an empty cache line among the cache lines included in the cache 51 (step S305). The controller 5 identifies whether or not there is a cache line among the multiple cache lines in which all eight valid flags are set to values ​​indicating invalid.

[0146] If there is a free cache line (Yes in step S305), the controller 5 stores the write data in the free cache line (step S306).

[0147] The controller 5 sets the dirty flag corresponding to the stored write data to a value indicating dirty (step S307).

[0148] The controller 5 sets the valid flag corresponding to the stored write data to a value indicating validity (step S308).

[0149] If there are no free cache lines (No in step S305), the controller 5 executes an eviction process (step S309), which includes selecting any one cache line as the cache line to be evicted and writing back the dirty data stored in the cache line to be evicted.

[0150] The controller 5 stores the write data in the free cache line created by the eviction process in step S309 (step S306).

[0151] The controller 5 sets the dirty flag corresponding to the stored write data to a value indicating dirty (step S307).

[0152] The controller 5 sets the valid flag corresponding to the stored write data to a value indicating validity (step S308).

[0153] Next, the eviction process will be described with reference to a flowchart of FIG 18, which is executed in the memory system 3 according to the embodiment.

[0154] The controller 5 selects a cache line to be evicted (step S401). The controller 5 can select the cache line to be evicted using any algorithm.

[0155] The controller 5 determines whether dirty data is stored in the cache line selected in step S401 (step S402). The controller 5 determines whether data corresponding to a dirty flag set to a value indicating dirty exists by referring to a plurality of dirty flags corresponding to the selected cache line.

[0156] If dirty data is stored in the selected cache line (Yes in step S402), the controller 5 writes back dirty data having a size of 64 B to 512 B (step S403). The controller 5 writes dirty data corresponding to each dirty flag set to a value indicating dirty to the physical storage area of ​​the NAND flash memory 6. Note that the data to be written back may include valid data other than dirty data. For example, if the 8-bit valid flag in a certain cache line is "11110000" and the 8-bit dirty flag is "10110000", the first four 64 B data of this cache line (i.e., 256 B data) may be written to the physical storage area of ​​the NAND flash memory 6.

[0157] After writing back the dirty data, the controller 5 initializes the selected cache line to be evicted (step S404). In this case, the controller 5 resets all valid bits of the selected cache line to be evicted, and also resets all dirty bits of the selected cache line to be evicted.

[0158] If dirty data is not stored in the cache line selected as the cache line to be evicted (No in step S402), the controller 5 initializes the selected cache line to be evicted (step S404).

[0159] Next, the read process will be described with reference to a flowchart of FIG 19, which shows the procedure of the read process executed in the memory system 3 according to the embodiment.

[0160] The controller 5 determines whether the read target data is stored in the cache 51 (step S501). The controller 5 determines whether the read target data specified by the read access request received from the host 2 is stored in the cache 51. In this case, the controller 5 refers to the cache management table of the cache 51 and searches for a cache line having a tag that matches the logical address of the read target data specified by the read access request. If there is no cache line having a tag that matches the logical address of the read target data, the read target data is not stored in the cache 51. If there is a cache line having a tag that matches the logical address of the read target data, the controller 5 further refers to one valid flag determined from the logical address of the read target data, out of the eight valid flags of this cache line. Depending on whether this valid flag is set to a value indicating valid, the controller 5 can determine whether the read target data is stored in this cache line.

[0161] If the read target data is stored in the cache 51 (Yes in step S501), the controller 5 reads the read target data from the cache 51 (step S502).

[0162] If the read target data is not stored in the cache 51 (No in step S501), the controller 5 reads the read target data from the storage area of ​​the NAND flash memory 6 and executes a refill process to store the read target data in the cache 51 (step S503). Furthermore, if the read target data is stored in the write buffer 72, the controller 5 may read the read target data from the write buffer 72.

[0163] Then, the controller 5 reads the read target data stored in the cache by the refill process from the cache 51 (step S502).

[0164] Next, the refill process will be described with reference to a flowchart of FIG 20, which shows the procedure of the refill process executed in the memory system 3 according to the embodiment.

[0165] The controller 5 determines whether there is a cache line storing data belonging to the same 512B logical address space as the data to be read (step S601). If there is a cache line storing data belonging to the same 512B logical address space as the data to be read (Yes in step S601), the controller 5 selects this cache line as the cache line to be refilled (step S602).

[0166] If there is no cache line storing data belonging to the same 512B logical address space as the data to be read (No in step S601), the controller 5 determines whether or not there is an empty cache line in the cache 51 (step S603). The controller 5 refers to the cache management table of the cache 51 and determines whether or not there is a cache line in which all valid flags are set to values ​​indicating invalid.

[0167] If there is no free cache line in the cache 51 (No in step S603), the controller 5 selects any one cache line and executes an eviction process to create a free cache line (step S604).

[0168] If there is a free cache line in the cache 51 (Yes in step S603), the controller 5 skips the eviction process in step S604.

[0169] The controller 5 selects an empty cache line as a cache line to be refilled (step S605).The controller 5 then refers to the page table 71 and acquires the physical address of the data to be read (step S606).

[0170] The controller 5 determines whether data belonging to the logical address range to be stored in the same cache line as the read target data is sequentially arranged at consecutive physical addresses including the acquired physical address (step S607).

[0171] If data belonging to the logical address range that should be stored in the same cache line as the data to be read is sequentially arranged at consecutive physical addresses including the acquired physical address (Yes in step S607), the controller 5 reads the sequentially arranged data having a size of 128B to 512B from the NAND flash memory 6 (step S608).

[0172] The controller 5 stores the data read in step S608 in the cache line to be refilled (step S609).

[0173] The controller 5 sets the valid flag corresponding to each 64B data (each refilled data) stored in the cache line to be refilled in step S609 to a value indicating validity (step S610).

[0174] If dirty 64B data already exists in the cache line to be refilled, the controller 5 stores data having a size of 128B to 512B read from the NAND flash memory 6 in the cache line to be refilled, avoiding the dirty 64B data. This prevents the dirty 64B data from being overwritten by the refill process. Furthermore, the controller 5 does not necessarily need to store all of the multiple data read from one region in a cache line; it may store only at least a portion of the read multiple data, including the read data, in a cache line. For example, if 512B of data including the read data is sequentially allocated in multiple physically contiguous storage locations, the controller 5 may read the 512B data from the region and store only the 256B of data including the read data in the cache line from the read 512B data. Furthermore, for example, when a cache configuration having a variable cache line size is used, in addition to a configuration in which data having a size of 128B to 512B read from the NAND flash memory 6 is stored in one cache line, a configuration in which the data is stored using two or more cache lines can also be used.

[0175] If data belonging to the logical address range that should be stored in the same cache line as the data to be read is not sequentially located at consecutive physical addresses including the acquired physical address (No in step S607), the controller 5 reads only the data to be read from the NAND flash memory 6 (step S611).

[0176] Then, the controller 5 stores the data read in step S611 in the cache line to be refilled (step S609).

[0177] The controller 5 sets the valid flag corresponding to the data read in step S611 to a value indicating validity (step S610).

[0178] Although the refill process that is executed when the read target data specified by a read access request from the host 2 does not exist in the cache 51 has been described above, the refill process can also be executed due to other factors. For example, when 64B of data in a cache line is write-accessed or read-accessed by the host 2, the controller 5 can internally execute a refill process (prefetch) to transfer (512B - 64B) of data excluding the accessed 64B of data from the NAND flash memory 6 to this cache line.

[0179] The data to be stored in the cache 51 by the refill process is data that needs to be read from the NAND flash memory 5. Therefore, the data to be stored in the cache 51 by the refill process is called read data to be stored in the cache 51. Examples of the read data to be stored in the cache 51 include data to be read specified by a read access request from the host 2 and data to be prefetched.

[0180] Next, the access size and the address translation unit will be explained. Fig. 21 is a diagram showing various management sizes used in the memory system 3 according to the embodiment.

[0181] The access size is the data size (data granularity) of the read data or write data corresponding to the read access request or write access request sent from the host 2. The access request sent from the host 2 specifies a logical address indicating a multiple of 64. If a logical address indicating a value other than a multiple of 64 (for example, Addr96) is received from the host 2, the controller 5 notifies the host 2 of an error. The logical address (Addr320) indicates five times 64. Therefore, the logical address (Addr320) is treated as the sixth logical address "64B-addr5" of six consecutive logical addresses "64B-addr0" to "64B-addr5" in 64B units.

[0182] Furthermore, the address translation unit of the page table 71 may be an integer multiple of 64B (for example, 64B, 128B, or 256B). The address translation unit is the same as the access size or an integer multiple of the access size. In other words, if the size (granularity) of data accessed for read / write by the host 2 is 64B, the address translation unit is either 64B, 128B, or 256B. If the size (granularity) of data accessed for read / write by the host 2 is 128B, the address translation unit is either 128B or 256B.

[0183] As described above, according to this embodiment, the controller 5 divides the logical address space used by the host 2 into two N The controller 5 manages two banks. N The physical storage area of ​​the NAND flash memory 6 is divided into two banks, each of which corresponds one-to-one to the other. N In addition, the controller 5 manages two regions. N 2 banks, each with a one-to-one correspondence. N Manages two write buffers 72. N Write data having a logical address belonging to a certain bank among the banks is written to one region corresponding to this bank. Therefore, each entry of the page table 71 only needs to hold location information indicating one of multiple storage locations included in the region as a physical address, and does not need to hold location information for identifying the region to which the write data is written. Furthermore, the number of storage locations included in each region is fewer than the number of storage locations included in the entire NAND flash memory 6. Therefore, the bit width of the physical address that needs to be stored in each entry of the page table 71 is reduced, and the capacity of the page table 71 can be reduced.

[0184] Furthermore, in the memory system 3 in which the increase in write amplification is suppressed by narrowing the access granularity, the number of entries in the page table 71 increases in accordance with the reduction in the address translation size. However, in this embodiment, a configuration is adopted in which the bit width of the physical address per entry is reduced, so that the increase in the size of the page table 71 can be kept to a minimum. Therefore, it becomes possible to store all entries of the page table 71 in the DRAM 7.

[0185] Therefore, it is possible to realize a memory system 3 that can accommodate fine access granularity while minimizing the increase in size of the page table 71.

[0186] Furthermore, when a write access request and write data are received from the host 2, the controller 5 identifies the bank that includes the logical address specified by the write access request. The controller 5 stores the received write data in the write buffer 72 that corresponds to the identified bank.

[0187] When the total size of the write data stored in any one of the write buffers 72 reaches the write size, the controller 5 writes the write data stored in this write buffer 72 to the region corresponding to the bank corresponding to this write buffer 72.

[0188] This allows the controller 5 to prevent write data corresponding to logical addresses belonging to different banks from being mixed in the same write buffer 72. Therefore, the controller 5 can also handle 64B random write access to a wide logical address range spanning all banks.

[0189] While the present embodiment has been described with a focus on an example in which a logical address is directly converted into a physical address by using the page table 71, it is also possible to use a configuration in which a logical address is converted into virtual location information such as an intra-region offset by a first-stage address conversion using the page table 71, and then the virtual location information such as an intra-region offset is converted into an actual physical address by a second-stage address conversion using a separate address conversion table. In this case, each entry in the page table 71 only needs to hold an intra-region offset, i.e., location information indicating the offset from the beginning of the corresponding region to the location within that region where data is written. The separate address conversion table may be stored, for example, in an SRAM in the controller 5.

[0190] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0191] 1...information processing system, 2...host, 3...memory system, 4...memory bus, 5...control, 6...NAND flash memory, 7...DRAM, 21...processor, 22...memory, 51...cache, 52...media control unit, 71...page table, 72...write buffer, 73...program buffer, 511...cache control logic, 521...write controller, 522...read controller, 523...GC controller

Claims

1. 1. A memory system connectable to a host via a memory bus, comprising: A random access memory, a non-volatile memory, and a controller, The controller The two resulting from dividing the logical address space used by the host to access the memory system Ｎ 2 small logical address spaces Ｎ banks and 2 Ｎ Two physical memory areas of the nonvolatile memory, each of which corresponds to one of the banks. Ｎ N is a natural number, an address translation table that includes a plurality of entries corresponding to a plurality of consecutive logical addresses in units of a first size corresponding to a granularity of data read / write accessed by the host, and that manages mapping between each of the plurality of logical addresses and each of a plurality of physical addresses in the physical storage area, is stored in the random access memory; 2. Ｎ two memory cells each having at least a first capacity corresponding to a write size of the nonvolatile memory; Ｎ allocate write buffers in said random access memory; In response to receiving a write access request and first write data from the host, a bank to which a logical address of the first write data specified by the write access request belongs is identified, and the second write data is stored. Ｎ writing the first write data into a write buffer corresponding to the specified bank among the write buffers; After the total size of the write data including the first write data stored in the write buffer reaches a predetermined size or more, the write data including the first write data is transferred to the second write buffer. Ｎ the area corresponding to the specified bank is written into the area; each of the plurality of entries holds, as a physical address, location information indicating any one of a plurality of storage locations included in one area corresponding to one bank to which the corresponding logical address belongs, and does not hold location information for identifying the one area; Memory system.

2. The controller In response to receiving a read access request from the host, ２Ｎ the read access request specifies a bank among the banks to which a logical address of the data to be read specified by the read access request belongs, acquires location information stored in an entry of the address translation table corresponding to the logical address of the data to be read, and reads the data to be read from an area corresponding to the specified bank based on the specified bank and the acquired location information.

10. The memory system of claim 1.

3. The N is a natural number of 10 or more.

10. The memory system of claim 1.

4. the non-volatile memory includes a plurality of dies; 2. Ｎ the total capacity of the write buffers is 30 times or more the size represented by the product of the write size and the number of parallel writes, The parallel write number indicates the number of dies on which the write operation is performed in parallel.

4. The memory system of claim 3.

5. The granularity and the first size of data accessed for read / write by the host have a size corresponding to the bus width of the memory bus.

10. The memory system of claim 1.

6. The granularity of data read / write accessed by the host is 64 bytes, and the first size is 64 bytes.

10. The memory system of claim 1.

7. the granularity of data read / write accessed by the host is 64 bytes, and the first size is any one of 64 bytes, 128 bytes, or 256 bytes; 10. The memory system of claim 1.

8. the granularity of data read / write accessed by the host is 128 bytes, and the first size is either 128 bytes or 256 bytes; 10. The memory system of claim 1.

9. 2. Ｎ Each of the regions is Ｍ M is a natural number; The controller The two logical addresses included in the area corresponding to the bank to which the logical address specified by the read / write access request received from the host belongs. Ｍ one sub-area determined from the logical address is determined as a read / write target sub-area, Each of the plurality of entries holds location information indicating one of a plurality of storage locations included in one sub-area.

10. The memory system of claim 1.

10. a cache; The controller storing a plurality of write data corresponding to a plurality of consecutive logical addresses in one cache line among a plurality of cache lines included in the cache; When the one cache line is selected as a cache line to be written back or evicted, the plurality of write data corresponding to the plurality of consecutive logical addresses stored in the one cache line are written to the second cache line. Ｎ the plurality of write data corresponding to the plurality of consecutive logical addresses are stored in the two areas so as to be sequentially arranged in a plurality of physically consecutive storage positions in one of the areas; Ｎ The two write buffers are Ｎ Write to one of the areas, determining whether a plurality of data items corresponding to a plurality of consecutive logical addresses, including the first read data to be stored in the cache, are sequentially arranged in a plurality of physically consecutive memory locations within one area corresponding to the bank to which the logical address of the first read data belongs; when the plurality of data items corresponding to a plurality of consecutive logical addresses including the first read data are sequentially arranged in a plurality of physically consecutive storage locations within the one area, the plurality of data items including the first read data are read from the one area, and at least a portion of the read plurality of data items including the first read data is stored in one or more cache lines among the plurality of cache lines; 10. The memory system of claim 1.

11. The controller When one write data having the first size is written back or evicted from the cache line to be written back or evicted, Ｎ Among the banks, a bank to which the logical address of the one piece of write data belongs is identified, and the one piece of write data is transferred to the one of the two banks corresponding to the identified bank. Ｎ writing the write data to one of the areas, and using one entry of the address conversion table corresponding to the logical address of the write data, storing first position information having a first bit width in the address conversion table, the first position information indicating a storage location in the one area where the write data has been written; When two pieces of write data each having the first size and corresponding to two consecutive logical addresses are written back or evicted from the cache line to be written back or evicted, the two pieces of write data are written back or evicted based on a predetermined criterion. Ｎ the address conversion table is configured to select an area into which the two pieces of write data are to be written from among these areas, write the two pieces of write data into the selected area so that the two pieces of write data are sequentially arranged at a plurality of physically consecutive storage locations within the selected area, and store second position information having a second bit width greater than the first bit width, which indicates both the selected area and the storage locations within the selected area into which the two pieces of write data have been written, by using two entries of the address conversion table corresponding to two logical addresses of the two pieces of write data. The memory system of claim 10.

12. 2. Ｎ Each of the regions is Ｍ M is a natural number; The controller The two logical addresses included in the area corresponding to the bank to which the logical address specified by the read / write access request received from the host belongs. Ｍ one of the sub-areas determined by the logical address is determined as a sub-area to be read / written, and each of the plurality of entries holds location information indicating one of a plurality of storage locations included in one sub-area; When one write data having the first size is written back or evicted from the cache line to be written back or evicted, Ｎ The bank to which the logical address of the one write data belongs is identified among the banks, and the one write data is written to two areas included in one area corresponding to the identified bank. Ｍ writing the write data into one of the sub-areas determined by the logical address of the write data, and using one entry of the address conversion table corresponding to the logical address of the write data, storing first position information having a first bit width in the address conversion table, the first position information indicating a storage position within the one sub-area to which the write data has been written; When two pieces of write data each having the first size and corresponding to two consecutive logical addresses are written back or evicted from the cache line to be written back or evicted, Ｎ Among the banks, a bank to which the two logical addresses of the two write data belong is identified, and two logical addresses included in one area corresponding to the identified bank are identified based on a predetermined criterion. Ｍ the address conversion table is configured to store second position information having a second bit width greater than the first bit width, which indicates both the selected subarea and the storage locations in the selected subarea where the two write data have been written, by selecting a subarea into which the two write data should be written from among the subareas, writing the two write data into the selected subarea so that the two write data are sequentially arranged in a plurality of physically consecutive storage locations in the selected subarea, and using two entries in the address conversion table corresponding to two logical addresses of the two write data. The memory system of claim 10.

13. the controller is configured to store all of the plurality of entries included in the address translation table in the random access memory; 10. The memory system of claim 1.

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